JP4547958B2 - Manufacturing method of multilayer wiring board - Google Patents

Manufacturing method of multilayer wiring board Download PDF

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JP4547958B2
JP4547958B2 JP2004091156A JP2004091156A JP4547958B2 JP 4547958 B2 JP4547958 B2 JP 4547958B2 JP 2004091156 A JP2004091156 A JP 2004091156A JP 2004091156 A JP2004091156 A JP 2004091156A JP 4547958 B2 JP4547958 B2 JP 4547958B2
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layer
resist pattern
forming
conductive layer
via hole
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JP2005277258A (en
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浩希 小林
直人 大野
浩二 市川
正孝 前原
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Toppan Inc
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本発明は、絶縁基材に配線層、ビアが形成された多層配線基板の製造方法に関し、特に、めっきで形成された導体層を物理研磨、もしくは化学研磨して配線層及びビアを形成する多層配線基板の製造方法に関する。   The present invention relates to a method for manufacturing a multilayer wiring board in which a wiring layer and a via are formed on an insulating substrate, and in particular, a multilayer in which a conductor layer formed by plating is physically polished or chemically polished to form a wiring layer and a via. The present invention relates to a method for manufacturing a wiring board.

近年、半導体素子をプリント配線基板に実装するためのインターポーザとして、多層回路基板が広く採用されている。この多層回路基板は表面に所定パターンの導体回路が形成された単位回路基板を複数枚積層してなっており、各単位回路基板の間はスルーホールやビアホールで導通が取られている。   In recent years, multilayer circuit boards have been widely adopted as interposers for mounting semiconductor elements on printed wiring boards. This multilayer circuit board is formed by laminating a plurality of unit circuit boards each having a predetermined pattern of conductor circuits formed on the surface, and the unit circuit boards are electrically connected by through holes or via holes.

その一方で、半導体大規模集積回路（ＬＳＩ）等の半導体素子ではトランジスターの集積度が高まり、その動作速度はクロック周波数で１ＧＨｚに達するものが、また入出力端子数では１０００を越えるものが出現するに至っている。   On the other hand, in a semiconductor element such as a semiconductor large-scale integrated circuit (LSI), the degree of integration of transistors is increased, and the operation speed reaches 1 GHz at the clock frequency, and the number of input / output terminals exceeds 1000. Has reached.

このため、多層回路基板にも高密度、高精細の配線形成技術が求められている。
高密度、高精細配線形成の有効な手段として、めっきを用いたセミアディティブ法がある（例えば参考文献１参照）。セミアディティブ法では、主に次の工程を経て配線層及びビアを得る。 For this reason, a high-density, high-definition wiring formation technology is also required for multilayer circuit boards.
As an effective means for forming high-density and high-definition wiring, there is a semi-additive method using plating (for example, see Reference 1). In the semi-additive method, a wiring layer and a via are obtained mainly through the following steps.

セミアディティブ法にて、配線層及びビアを形成するプロセスについて説明する。
図８（ａ）〜（ｅ）及び図９（ｆ）〜（ｇ）に、配線層及びビアをセミアディティブ法にて形成するプロセスの一例を示す。 A process for forming wiring layers and vias by the semi-additive method will be described.
8A to 8E and FIGS. 9F to 9G show an example of a process for forming a wiring layer and a via by a semi-additive method.

まず、両面に配線層５１及び５２が形成されたコア基板３０の両面に樹脂フィルム等をラミネートする等の方法で所定厚の絶縁層６１を形成する。（図８（ａ）及び（ｂ）参照）。
次に、絶縁層６１の所定位置に、レーザー加工等によりビア用孔６２を形成する（図８（ｃ）参照）。 First, the insulating layer 61 having a predetermined thickness is formed by a method such as laminating a resin film or the like on both surfaces of the core substrate 30 on which the wiring layers 51 and 52 are formed on both surfaces. (See FIGS. 8A and 8B).
Next, a via hole 62 is formed at a predetermined position of the insulating layer 61 by laser processing or the like (see FIG. 8C).

次に、ビア用孔６２のデスミア処理を行って、絶縁層上及びビア用孔側壁に無電解銅めっき等によりめっき下地導電層７１を形成する（図８（ｄ）参照）。
次に、めっき下地導電層７１上の所定位置にパターめっき用のレジストパターン８１を形成する（図８（ｅ）参照）。 Next, a desmear process of the via hole 62 is performed, and a plating base conductive layer 71 is formed on the insulating layer and the via hole side wall by electroless copper plating or the like (see FIG. 8D).
Next, a resist pattern 81 for pattern plating is formed at a predetermined position on the plating base conductive layer 71 (see FIG. 8E).

次に、めっき下地導電層７１を給電層にして電解銅めっきを行い、フィルドビア５３及び所定厚の導体層５４を形成する（図９（ｆ）参照）。
最後に、レジストパターン８１を専用の剥離液で除去し、レジストパターン８１下部にあっためっき下地導電層７１をエッチングして、配線層５４ａを得る（図９（ｇ）参照）。
特開平７−１５１１３号公報 Next, electrolytic copper plating is performed using the plating base conductive layer 71 as a power feeding layer to form a filled via 53 and a conductor layer 54 having a predetermined thickness (see FIG. 9F).
Finally, the resist pattern 81 is removed with a dedicated stripping solution, and the plating base conductive layer 71 under the resist pattern 81 is etched to obtain a wiring layer 54a (see FIG. 9G).
JP-A-7-15113

しかし、従来のセミアディティブ工法では、配線層のパターンによっては、配線の高さ、断面形状にばらつきが生じることがある。また、フィルドビアと配線層形成を同時に行う場合、配線の断面形状が矩形とならずに不均一になることがある。配線層の高さや断面
形状が不均一になると、配線層の電気的特性にばらつきを生じ、配線基板としての使用に耐え得ないものとなってしまう。 However, in the conventional semi-additive method, the wiring height and cross-sectional shape may vary depending on the wiring layer pattern. In addition, when the filled via and the wiring layer formation are performed simultaneously, the cross-sectional shape of the wiring may not be rectangular but may be non-uniform. If the height and cross-sectional shape of the wiring layer are not uniform, the electrical characteristics of the wiring layer will vary, making it unusable for use as a wiring board.

本発明は上記問題点に鑑み考案されたもので、微細パターンからなる配線層領域で、配線層の高さや断面形状が不均一にならず、接続信頼性に優れたビアオンビア構造の配線基板を容易に得ることができる多層配線基板の製造方法及び多層配線基板を提供することを目的とする。   The present invention has been devised in view of the above problems, and in a wiring layer region having a fine pattern, the wiring layer height and cross-sectional shape are not uneven, and a wiring board having a via-on-via structure excellent in connection reliability can be easily obtained. An object of the present invention is to provide a method for manufacturing a multilayer wiring board and a multilayer wiring board that can be obtained.

本発明は、上記課題を達成するために、まず請求項１においては、多層配線基板の製造方法であって、少なくとも以下の工程を有することを特徴とする多層配線基板の製造方法としたものである。
（ａ）絶縁基材の両面に導体層が形成された積層基材の一方の面から導体層及び絶縁基材を貫通し他方の面の導体層に達するビア用孔を形成する工程。
（ｂ）両面に所定厚の感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｃ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｄ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｅ）物理研磨、または化学研磨により、レジストパターンの上部が露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｆ）レジストパターンを剥離液で剥離する工程。
（ｇ）レジストパターン下部にあった導体層をエッチングにより除去する工程。
（ｈ）絶縁層を形成する工程。
（ｉ）絶縁層の所定位置にビア用孔を形成する工程。
（ｊ）両面に所定厚のレジスト感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｋ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｌ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｍ）物理研磨、または化学研磨により、レジストパターンの上部が露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｎ）レジストパターンを剥離液で剥離する工程。
（ｐ）上記（ｈ）〜（ｎ）の工程を所望の回数繰り返す工程。
In order to achieve the above object, the present invention provides a method for manufacturing a multilayer wiring board according to claim 1, wherein the method includes at least the following steps. is there.
(A) The process of forming the via hole which penetrates a conductor layer and an insulation base material from one surface of the lamination base material in which the conductor layer was formed in both surfaces of the insulation base material, and reaches the conductor layer of the other surface.
(B) A step of forming a photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(C) A step of forming a plating base conductive layer on the entire surface including the via hole sidewall and the via hole bottom surface on the resist pattern.
(D) A step of performing electroplating using the plating base conductive layer as a power supply layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(E) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the upper portion of the resist pattern is exposed.
(F) A step of stripping the resist pattern with a stripping solution.
(G) A step of removing the conductor layer under the resist pattern by etching.
(H) A step of forming an insulating layer.
(I) A step of forming a via hole at a predetermined position of the insulating layer.
(J) A step of forming a resist photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(K) A step of forming a plating base conductive layer on the entire surface including the via hole side wall and the via hole bottom surface on the resist pattern.
(L) A step of performing electroplating using the plating base conductive layer as a power feeding layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(M) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the upper portion of the resist pattern is exposed.
(N) A step of stripping the resist pattern with a stripping solution.
(P) A step of repeating the steps (h) to (n) a desired number of times.

また、請求項２においては、多層配線基板の製造方法であって、少なくとも以下の工程を有することを特徴とする多層配線基板の製造方法としたものである。
（ａ）絶縁基材の片面に導体層が形成された積層基材の一方の面から絶縁基材を貫通し他方の面の導体層に達するビア用孔を形成する工程。
（ｂ）両面に所定厚の感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｃ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｄ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｅ）物理研磨、または化学研磨により、レジストパターンが露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｆ）レジストパターンを剥離液で剥離する工程。
（ｇ）レジストパターン下部にあった導体層をエッチングにより除去する工程。
（ｈ）絶縁層を形成する工程。
（ｉ）絶縁層の所定位置にビア用孔を形成する工程。
（ｊ）両面に所定厚のレジスト感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｋ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｌ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｍ）物理研磨、または化学研磨により、レジストパターンの上部が露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｎ）レジストパターンを剥離液で剥離する工程。
（ｐ）上記（ｈ）〜（ｎ）の工程を所望の回数繰り返す工程。
According to a second aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board, comprising at least the following steps.
(A) A step of forming a via hole penetrating the insulating base material from one side of the laminated base material on which the conductive layer is formed on one side of the insulating base material and reaching the conductive layer on the other side.
(B) A step of forming a photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(C) A step of forming a plating base conductive layer on the entire surface including the via hole sidewall and the via hole bottom surface on the resist pattern.
(D) A step of performing electroplating using the plating base conductive layer as a power supply layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(E) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the resist pattern is exposed.
(F) A step of stripping the resist pattern with a stripping solution.
(G) A step of removing the conductor layer under the resist pattern by etching.
(H) A step of forming an insulating layer.
(I) A step of forming a via hole at a predetermined position of the insulating layer.
(J) A step of forming a resist photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(K) A step of forming a plating base conductive layer on the entire surface including the via hole side wall and the via hole bottom surface on the resist pattern.
(L) A step of performing electroplating using the plating base conductive layer as a power feeding layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(M) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the upper portion of the resist pattern is exposed.
(N) A step of stripping the resist pattern with a stripping solution.
(P) A step of repeating the steps (h) to (n) a desired number of times.

本発明の多層配線基板の製造方法よれば、配線層の幅、高さ及び形状が均一でパターン再現性に優れ、且つ接続信頼性に優れたビアオンビア構造の多層配線基板を容易に得ることができる。   According to the method for manufacturing a multilayer wiring board of the present invention, a multilayer wiring board having a via-on-via structure in which the width, height and shape of the wiring layer are uniform, the pattern reproducibility is excellent, and the connection reliability is easily obtained. .

以下、本発明の実施の形態につき説明する。
図１（ａ）は、本発明の請求項１に係る多層配線基板の製造方法で作製された多層配線基板の一実施例を示す模式構成断面図を、図１（ｂ）は、本発明の請求項２に係る多層配線基板の製造方法で作製された多層配線基板の一実施例を示す模式構成断面をそれぞれ示す。図１（ａ）の多層配線基板１００は、絶縁基材１１の両面に導体層２１を有する積層基材１０を用いて多層配線基板を、図１（ｂ）の多層配線基板２００は、絶縁基材１１の片面に導体層２１を有する積層基材２０を用いて多層配線基板をそれぞれ作製したものである。
本発明の多層配線基板の製造方法では、めっきで形成された導体層を物理研磨、もしくは化学研磨して配線層及びビアを形成するので、表面が平滑な形状再現性に優れた配線層及び接続信頼性に優れたビアオンビア構造の多層配線基板を容易に得ることができる。 Hereinafter, embodiments of the present invention will be described.
FIG. 1 (a) is a schematic cross-sectional view showing an embodiment of a multilayer wiring board manufactured by the method for manufacturing a multilayer wiring board according to claim 1 of the present invention, and FIG. The schematic structure cross section which shows one Example of the multilayer wiring board produced with the manufacturing method of the multilayer wiring board which concerns on Claim 2 is shown, respectively. A multilayer wiring board 100 in FIG. 1A is a multilayer wiring board using a laminated base material 10 having conductor layers 21 on both sides of an insulating base material 11, and a multilayer wiring board 200 in FIG. A multilayer wiring board is produced using a laminated base material 20 having a conductor layer 21 on one side of the material 11.
In the method for producing a multilayer wiring board according to the present invention, the conductor layer formed by plating is physically polished or chemically polished to form the wiring layer and the via, so that the wiring layer and connection having a smooth surface and excellent shape reproducibility are formed. A multilayer wiring board having a via-on-via structure with excellent reliability can be easily obtained.

以下、本発明の多層配線基板の製造方法について説明する。
図２（ａ）〜（ｅ）、図３（ｆ）〜（ｉ）及び図４（ｊ）〜（ｎ）は、本発明の請求項１に係る多層配線基板の製造方法の一実施例を工程順に示す模式構成断面図である。
まず、絶縁基材１１の両面に極薄銅箔を積層して導体層２１を形成した積層基材１０を準備する（図２（ａ）参照）。
次に、ＣＯ2レーザー、ＵＶレーザー等を用いたレーザー加工により、積層基材１０の一方の面から導体層２１及び絶縁基材１１を貫通し他方の面の導体層２１に達するビア用孔１２を形成し、ビア用孔１２底及び内壁に付着した樹脂残渣を、ドライデスミア又は、ウェットデスミア処理にて除去する（図２（ｂ）参照）。 Hereinafter, the manufacturing method of the multilayer wiring board of this invention is demonstrated.
2 (a) to 2 (e), FIGS. 3 (f) to (i) and FIGS. 4 (j) to (n) show an embodiment of a method for manufacturing a multilayer wiring board according to claim 1 of the present invention. It is a schematic structure sectional view shown in process order.
First, a laminated base material 10 is prepared in which ultrathin copper foils are laminated on both surfaces of an insulating base material 11 to form a conductor layer 21 (see FIG. 2A).
Next, via holes 12 that penetrate the conductor layer 21 and the insulating substrate 11 from one surface of the laminated substrate 10 and reach the conductor layer 21 on the other surface by laser processing using a CO 2 laser, a UV laser, or the like. The resin residue adhering to the bottom of the via hole 12 and the inner wall is removed by dry desmear or wet desmear treatment (see FIG. 2B).

次に、感光性のドライフィルムをラミネートする等の方法で感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３１を形成する（図２（ｃ）参照）。   Next, a photosensitive layer is formed by a method such as laminating a photosensitive dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 31 (see FIG. 2C).

次に、スパッタ又は、ＤＰＳ、無電解銅めっき等によりレジストパターン３１上、導体層２１上及びビア用孔１２内に所定厚の銅薄膜層からなるめっき下地導電層４１を形成する（図２（ｄ）参照）。   Next, a plating base conductive layer 41 made of a copper thin film layer having a predetermined thickness is formed on the resist pattern 31, the conductor layer 21, and the via hole 12 by sputtering, DPS, electroless copper plating, or the like (FIG. 2 ( d)).

次に、めっき下地導電層４１を給電層にしてフィルドビア用銅めっき液を用いて、電解銅めっきを行い、レジストパターン３１を覆いつくすような厚みまでめっき銅を析出させ、導体層２２を形成する（図２（ｅ）参照）。   Next, electrolytic copper plating is performed using a filled via copper plating solution using the plating base conductive layer 41 as a power feeding layer, and the plated copper is deposited to a thickness that covers the resist pattern 31, thereby forming the conductor layer 22. (See FIG. 2 (e)).

次に、基板両面をバフ研磨等の物理研磨、またはエッチング等の化学研磨により、レジストパターン３１の上部が露出するまで導体層２１及びレジストパターン３１上部のめっき下地導電層４１を研磨処理し、研磨処理された配線層２２ａ、ランド２２ｂ及びフィルドビア２２ｃを形成する（図３（ｆ）参照）。   Next, by polishing the both surfaces of the substrate by physical polishing such as buffing or chemical polishing such as etching, the conductive layer 21 and the plating base conductive layer 41 above the resist pattern 31 are polished and polished until the upper portion of the resist pattern 31 is exposed. The processed wiring layer 22a, land 22b, and filled via 22c are formed (see FIG. 3F).

次に、レジストパターン３１を専用の剥離液で除去し、レジストパターン３１の下部にあった導体層２１をエッチングで除去して配線層及びランド間の絶縁性を確保し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２２ａ及びランド２２ｂが形成され、配線層２２ａとランド２２ｂがフィルドビア２２ｃにて電気的に接続された２層の配線基板を得る（図３（ｇ）参照）。
 Next, the resist pattern 31 is removed with a special stripping solution, and the conductor layer 21 under the resist pattern 31 is removed by etching to ensure insulation between the wiring layer and the land. A wiring layer 22a and a land 22b having a smooth surface and excellent shape reproducibility are formed, and a two-layer wiring board in which the wiring layer 22a and the land 22b are electrically connected by a filled via 22c is obtained (FIG. 3G )reference).

次に、両面に樹脂フィルムをラミネートする等の方法で、絶縁層１３を形成する（図３（ｈ）参照）。
次に、ＣＯ2レーザー、ＵＶレーザー等を用いたレーザー加工により、絶縁層１３の所定位置にビア用孔１４を形成し、、ビア用孔１４底及び内壁に付着した樹脂残渣を、ドライデスミア又は、ウェットデスミア処理にて除去する（図３（ｉ）参照）。 Next, the insulating layer 13 is formed by a method such as laminating resin films on both surfaces (see FIG. 3H).
Next, a via hole 14 is formed at a predetermined position of the insulating layer 13 by laser processing using a CO 2 laser, a UV laser, etc., and the resin residue attached to the bottom and inner wall of the via hole 14 is removed by dry desmear or Then, it is removed by wet desmear treatment (see FIG. 3 (i)).

次に、感光性のドライフィルムをラミネートする等の方法で感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３２を形成する（図４（ｊ）参照）。   Next, a photosensitive layer is formed by a method such as laminating a photosensitive dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 32 (see FIG. 4J).

次に、スパッタ又は、ＤＰＳ、無電解銅めっき等によりレジストパターン３２上、絶縁層１３上及びビア用孔１４内に所定厚の銅薄膜層からなるめっき下地導電層４２を形成する（図４（ｋ）参照）。   Next, a plating base conductive layer 42 made of a copper thin film layer having a predetermined thickness is formed on the resist pattern 32, the insulating layer 13 and the via hole 14 by sputtering, DPS, electroless copper plating or the like (FIG. 4 ( k)).

次に、めっき下地導電層４２を給電層にしてフィルドビア用銅めっき液を用いて、電解銅めっきを行い、レジストパターン３２を覆いつくすような厚みまでめっき銅を析出させ、導体層２３を形成する（図４（ｌ）参照）。   Next, electrolytic copper plating is performed using a filled via copper plating solution with the plating base conductive layer 42 as a power feeding layer, and the plated copper is deposited to a thickness that covers the resist pattern 32, thereby forming the conductor layer 23. (See FIG. 4 (l)).

次に、基板両面をバフ研磨等の物理研磨、またはエッチング等の化学研磨により、レジストパターン３２の上部が露出するまで導体層２３及びレジストパターン３２上部のめっき下地導電層４２を研磨処理し、研磨処理された配線層２３ａ、ランド２３ｂ及びフィルドビア２３ｃを形成する（図４（ｍ）参照）。   Next, by polishing the both surfaces of the substrate by physical polishing such as buffing or chemical polishing such as etching, the conductive layer 23 and the plating base conductive layer 42 on the resist pattern 32 are polished and polished until the upper portion of the resist pattern 32 is exposed. The processed wiring layer 23a, land 23b, and filled via 23c are formed (see FIG. 4M).

次に、レジストパターン３２を専用の剥離液で除去し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２３ａ及びランド２３ｂが形成され、配線層２２ａとランド２２ｂがフィルドビア２２ｃにて、ランド２２ｂとランド２３ｂとがフィルドビア２３ｃにて電気的に接続された接続信頼性に優れたビアオンビア構造の４層の配線基板１００を得る（図４（ｎ）参照）。
さらに、必用であれば上記絶縁層、レジストパターン、めっき下地導電層、めっきよる導体層形成及び研磨処理、レジストパターン剥離工程を繰り返すことにより、所望の多層配線基板を得ることができる。
 Next, the resist pattern 32 is removed with a special stripping solution, and the wiring layer 23a and the land 23b having a smooth surface and excellent shape reproducibility are formed on both surfaces of the insulating substrate 11, and the wiring layer 22a and the land 22b are filled vias. In 22c, a four-layer wiring board 100 having a via-on-via structure excellent in connection reliability in which the land 22b and the land 23b are electrically connected by the filled via 23c is obtained (see FIG. 4 (n)).
Furthermore, if necessary, a desired multilayer wiring board can be obtained by repeating the insulating layer, resist pattern, plating base conductive layer, conductor layer formation and polishing treatment by plating, and resist pattern peeling step.

図５（ａ）〜（ｅ）、図６（ｆ）〜（ｉ）及び図７（ｊ）〜（ｎ）には、本発明の請求項２に係る多層配線基板の製造方法の一実施例を工程順に示す模式構成断面図である。
まず、絶縁基材１１の片面に極薄銅箔を積層して導体層２１を形成した積層基材２０を準備する（図５（ａ）参照）。
次に、ＣＯ2レーザー、ＵＶレーザー等を用いたレーザー加工により、積層基材２０の一方の面から絶縁基材１１を貫通し導体層２１に達するビア用孔１５を形成し、ビア用孔１５底及び内壁に付着した樹脂残渣を、ドライデスミア又は、ウェットデスミア処理にて除去する（図５（ｂ）参照）。 5 (a) to (e), FIGS. 6 (f) to (i) and FIGS. 7 (j) to (n) show an embodiment of a method for manufacturing a multilayer wiring board according to claim 2 of the present invention. FIG.
First, a laminated base material 20 is prepared in which an extremely thin copper foil is laminated on one side of the insulating base material 11 to form a conductor layer 21 (see FIG. 5A).
Next, via holes 15 that penetrate the insulating base material 11 from one surface of the laminated base material 20 and reach the conductor layer 21 are formed by laser processing using a CO 2 laser, a UV laser, or the like. Resin residues adhering to the bottom and the inner wall are removed by dry desmear or wet desmear treatment (see FIG. 5B).

次に、感光性のドライフィルムをラミネートする等の方法で感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３３を形成する（図５（ｃ）参照）。   Next, a photosensitive layer is formed by a method such as laminating a photosensitive dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 33 (see FIG. 5C).

次に、スパッタ又は、ＤＰＳ、無電解銅めっき等により、一方の面のレジストパターン３３上、絶縁基材１１上及びビア用孔１２内に、他方の面のレジストパターン３３上及び導体層２１上に所定厚の銅薄膜層からなるめっき下地導電層４３を形成する（図５（ｄ）参照）。   Next, by sputtering, DPS, electroless copper plating or the like, on the resist pattern 33 on one side, on the insulating base material 11 and in the via hole 12, on the resist pattern 33 on the other side and on the conductor layer 21 Then, a plating base conductive layer 43 made of a copper thin film layer having a predetermined thickness is formed (see FIG. 5D).

次に、めっき下地導電層４３を給電層にしてフィルドビア用銅めっき液を用いて、電解銅めっきを行い、レジストパターン３３を覆いつくすような厚みまでめっき銅を析出させ、導体層２４を形成する（図５（ｅ）参照）。   Next, electrolytic copper plating is performed using a filled via copper plating solution with the plating base conductive layer 43 as a power feeding layer, and the plated copper is deposited to a thickness that covers the resist pattern 33, thereby forming the conductor layer 24. (See FIG. 5 (e)).

次に、基板両面をバフ研磨等の物理研磨、またはエッチング等の化学研磨により、レジストパターン３３の上部が露出するまで導体層２４及びレジストパターン３３上部のめっき下地導電層４３を研磨処理し、研磨処理された配線層２４ａ、ランド２４ｂ及びフィルドビア２４ｃを形成する（図６（ｆ）参照）。   Next, the conductive layer 24 and the plating base conductive layer 43 above the resist pattern 33 are polished and polished by physical polishing such as buffing or chemical polishing such as etching on both surfaces of the substrate until the upper portion of the resist pattern 33 is exposed. The processed wiring layer 24a, land 24b, and filled via 24c are formed (see FIG. 6F).

次に、レジストパターン３３を専用の剥離液で除去し、レジストパターン３３の下部にあった導体層２１をエッチングで除去して配線層及びランド間の絶縁性を確保し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２４ａ及びランド２４ｂが形成され、配線層２４ａとランド２４ｂがフィルドビア２４ｃにて電気的に接続された２層の配線基板を得る（図６（ｇ）参照）。
 Next, the resist pattern 33 is removed with a special stripping solution, and the conductor layer 21 under the resist pattern 33 is removed by etching to ensure insulation between the wiring layer and the land. A wiring layer 24a and a land 24b having a smooth surface and excellent shape reproducibility are formed, and a two-layer wiring board is obtained in which the wiring layer 24a and the land 24b are electrically connected by a filled via 24c (FIG. 6G )reference).

次に、両面に樹脂フィルムをラミネートする等の方法で、絶縁層１６を形成する（図６（ｈ）参照）。
次に、ＣＯ2レーザー、ＵＶレーザー等を用いたレーザー加工により、絶縁層１６の所定位置にビア用孔１７を形成し、、ビア用孔１７底及び内壁に付着した樹脂残渣を、ドライデスミア、又はウェットデスミア処理にて除去する（図６（ｉ）参照）。 Next, the insulating layer 16 is formed by a method such as laminating a resin film on both surfaces (see FIG. 6H).
Next, a via hole 17 is formed at a predetermined position of the insulating layer 16 by laser processing using a CO 2 laser, a UV laser, etc., and the resin residue adhering to the bottom and inner wall of the via hole 17 is dry desmear, Or it removes by a wet desmear process (refer FIG.6 (i)).

次に、感光性のドライフィルムをラミネートする等の方法で感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３４を形成する（図７（ｊ）参照）。   Next, a photosensitive layer is formed by a method such as laminating a photosensitive dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 34 (see FIG. 7J).

次に、スパッタ、ＤＰＳ、無電解銅めっき等によりレジストパターン３４上、絶縁層１６上及びビア用孔１７内に所定厚の銅薄膜層からなるめっき下地導電層４４を形成する（図７（ｋ）参照）。   Next, a plating base conductive layer 44 made of a copper thin film layer having a predetermined thickness is formed on the resist pattern 34, the insulating layer 16 and the via hole 17 by sputtering, DPS, electroless copper plating, or the like (FIG. 7 (k)). )reference).

次に、めっき下地導電層４４を給電層にしてフィルドビア用銅めっき液を用いて、電解銅めっきを行い、レジストパターン３４を覆いつくすような厚みまでめっき銅を析出させ、導体層２５を形成する（図７（ｌ）参照）。   Next, electrolytic copper plating is performed using a filled via copper plating solution with the plating base conductive layer 44 as a power feeding layer, and the plated copper is deposited to a thickness that covers the resist pattern 34, thereby forming the conductor layer 25. (See FIG. 7 (l)).

次に、基板両面をバフ研磨等の物理研磨、またはエッチング等の化学研磨により、レジストパターン３４の上部が露出するまで導体層２５及びレジストパターン３４上部のめっき下地導電層４４を研磨処理し、研磨処理された配線層２５ａ、ランド２５ｂ及びフィルドビア２５ｃを形成する（図７（ｍ）参照）。   Next, by polishing the both surfaces of the substrate by physical polishing such as buffing or chemical polishing such as etching, the conductive layer 25 and the plating base conductive layer 44 on the resist pattern 34 are polished and polished until the upper portion of the resist pattern 34 is exposed. The processed wiring layer 25a, land 25b, and filled via 25c are formed (see FIG. 7M).

次に、レジストパターン３４を専用の剥離液で除去し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２５ａ及びランド２５ｂが形成され、配線層２４ａとランド２４ｂがフィルドビア２４ｃにて、ランド２４ｂとランド２５ｂとがフィルドビア２５ｃにて電気的に接続された接続信頼性に優れたビアオンビア構造の４層の配線基板２００を得る（図７（ｎ）参照）。
さらに、必用であれば上記絶縁層、レジストパターン、めっき下地導電層、めっきよる導体層形成及び研磨処理、レジストパターン剥離工程を繰り返すことにより、所望の多層配線基板を得ることができる。
 Next, the resist pattern 34 is removed with a special stripping solution, and the wiring layer 25a and the land 25b having a smooth surface and excellent shape reproducibility are formed on both surfaces of the insulating substrate 11, and the wiring layer 24a and the land 24b are filled vias. In 24c, the land 24b and the land 25b are electrically connected by the filled via 25c to obtain a four-layer wiring board 200 having a via-on-via structure excellent in connection reliability (see FIG. 7 (n)).
Furthermore, if necessary, a desired multilayer wiring board can be obtained by repeating the insulating layer, resist pattern, plating base conductive layer, conductor layer formation and polishing treatment by plating, and resist pattern peeling step.

まず、２５μｍ厚のポリイミドテープからなる絶縁基材１１の両面に銅箔が積層された両面銅箔付きポリイミドテープの銅箔をエッチングして３μｍ厚の銅箔からなる導体層２１を形成した積層基材１０を準備した（図２（ａ）参照）。
次に、ＵＶレーザーを用いたレーザー加工により、積層基材１０の一方の面から導体層２１及び絶縁基材１１を貫通し他方の面の導体層２１に達する１００μｍ径のビア用孔１２を形成し、ビア用孔１２底及び内壁に付着した樹脂残渣を５０℃に加熱された過マンガン酸カリウム水溶液によるデスミア処理にて除去した（図２（ｂ）参照）。 First, a laminated base formed by etching a copper foil of a polyimide tape with double-sided copper foil in which copper foil is laminated on both sides of an insulating base material 11 made of polyimide tape having a thickness of 25 μm to form a conductor layer 21 made of copper foil having a thickness of 3 μm. A material 10 was prepared (see FIG. 2A).
Next, via holes 12 having a diameter of 100 μm are formed by laser processing using a UV laser so as to penetrate the conductor layer 21 and the insulating substrate 11 from one surface of the laminated substrate 10 and reach the conductor layer 21 on the other surface. The resin residue adhering to the bottom and inner wall of the via hole 12 was removed by desmear treatment with an aqueous potassium permanganate solution heated to 50 ° C. (see FIG. 2B).

次に、感光性のドライフィルムをラミネートして感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３１を形成した（図２（ｃ）参照）。   Next, a photosensitive dry film was laminated to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development were performed to form a resist pattern 31 (see FIG. 2C).

次に、無電解銅めっきによりレジストパターン３１上、導体層２１上及びビア用孔１２内に０．５〜１．０μｍ厚の銅薄膜層からなるめっき下地導電層４１を形成した（図２（ｄ）参照）。   Next, a plating base conductive layer 41 made of a copper thin film layer having a thickness of 0.5 to 1.0 μm was formed on the resist pattern 31, the conductor layer 21, and the via hole 12 by electroless copper plating (FIG. 2 ( d)).

次に、めっき下地導電層４１を給電層にして、硫酸銅５水和物濃度が２３０ｇ／Ｌ、硫酸濃度が７０ｇ／Ｌ、塩素イオン濃度が６０ｍｇ／Ｌの硫酸銅水溶液にエバラユージライト製キューブライトＶＦ−ＭＵを２０ｍｌ／Ｌを加えた銅めっき液を用いて電解銅めっきを行い、レジストパターン３１を覆いつくすような厚みまでめっき銅を析出させ、導体層２２を形成した（図２（ｅ）参照）。
ここで、電流密度は、はじめの１５分間で１．５ＡＳＤ、続く２５分間で２．０ＡＳＤとした。 Next, using the plating base conductive layer 41 as a power feeding layer, a copper sulfate aqueous solution having a copper sulfate pentahydrate concentration of 230 g / L, a sulfuric acid concentration of 70 g / L, and a chlorine ion concentration of 60 mg / L is prepared by an Ebara Eugilite cube. Electrolytic copper plating was performed using a copper plating solution to which 20 ml / L of light VF-MU was added, and the plated copper was deposited to such a thickness as to cover the resist pattern 31 to form a conductor layer 22 (FIG. 2 (e )reference).
Here, the current density was 1.5 ASD for the first 15 minutes and 2.0 ASD for the next 25 minutes.

次に、過酸化水素水と硫酸の混合液からなるエッチング液を用いた化学研磨により、レ
ジストパターン３１の上部が露出するまで導体層２１及びレジストパターン３１上部のめっき下地導電層４１をエッチングし、５〜１０μｍの配線層２２ａ、ランド２２ｂ及びフィルドビア２２ｃを形成した（図３（ｆ）参照）。 Next, the conductive underlayer 21 and the plating base conductive layer 41 above the resist pattern 31 are etched by chemical polishing using an etching solution composed of a mixed solution of hydrogen peroxide and sulfuric acid until the upper portion of the resist pattern 31 is exposed, A wiring layer 22a, a land 22b, and a filled via 22c of 5 to 10 μm were formed (see FIG. 3F).

次に、レジストパターン３１を専用の剥離液で除去し、レジストパターン３１の下部にあった導体層２１をエッチングで除去し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２２ａ及びランド２２ｂが形成され、配線層２２ａとランド２２ｂがフィルドビア２２ｃにて電気的に接続された２層の配線基板を得た（図３（ｇ）参照）。
 Next, the resist pattern 31 is removed with a special stripping solution, and the conductor layer 21 located under the resist pattern 31 is removed by etching . The wiring having excellent surface reproducibility with smooth surfaces on both surfaces of the insulating base 11 A layer 22a and a land 22b were formed, and a two-layer wiring board in which the wiring layer 22a and the land 22b were electrically connected by a filled via 22c was obtained (see FIG. 3G).

次に、両面に樹脂フィルムをラミネートし絶縁層１３を形成した（図３（ｈ）参照）。次に、ＵＶレーザーを用いたレーザー加工により、絶縁層１３の所定位置に５０μｍ径のビア用孔１４を形成し、ビア用孔１４底及び内壁に付着した樹脂残渣を５０℃に加熱された過マンガン酸カリウム水溶液によるデスミア処理にて除去した（図３（ｉ）参照）。   Next, a resin film was laminated on both surfaces to form an insulating layer 13 (see FIG. 3 (h)). Next, a via hole 14 having a diameter of 50 μm is formed at a predetermined position of the insulating layer 13 by laser processing using a UV laser, and the resin residue adhering to the bottom and inner wall of the via hole 14 is heated to 50 ° C. It removed by the desmear process by potassium manganate aqueous solution (refer FIG.3 (i)).

次に、感光性のドライフィルムをラミネートして感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３２を形成した（図４（ｊ）参照）。   Next, a photosensitive dry film was laminated to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development were performed to form a resist pattern 32 (see FIG. 4J).

次に、無電解銅めっきによりレジストパターン３２上、絶縁層１３上及びビア用孔１４内に０．５〜１．０μｍ厚の銅薄膜層からなるめっき下地導電層４２を形成した図４（ｋ）参照）。   Next, FIG. 4 (k) in which a plating base conductive layer 42 composed of a copper thin film layer having a thickness of 0.5 to 1.0 μm is formed on the resist pattern 32, the insulating layer 13 and the via hole 14 by electroless copper plating. )reference).

次に、めっき下地導電層４１を給電層にして、硫酸銅５水和物濃度が２３０ｇ／Ｌ、硫酸濃度が７０ｇ／Ｌ、塩素イオン濃度が６０ｍｇ／Ｌの硫酸銅水溶液にエバラユージライト製キューブライトＶＦ−ＭＵを２０ｍｌ／Ｌを加えた銅めっき液を用いて電解銅めっきを行い、レジストパターン３１を覆いつくすような厚みまでめっき銅を析出させ、導体層２３を形成した（図４（ｌ）参照）。
ここで、電流密度は、はじめの１５分間で１．５ＡＳＤ、続く２５分間で２．０ＡＳＤとした。 Next, using the plating base conductive layer 41 as a power feeding layer, a copper sulfate aqueous solution having a copper sulfate pentahydrate concentration of 230 g / L, a sulfuric acid concentration of 70 g / L, and a chlorine ion concentration of 60 mg / L is prepared by an Ebara Eugilite cube. Electrolytic copper plating was performed using a copper plating solution to which 20 ml / L of light VF-MU was added, and plated copper was deposited to such a thickness as to cover the resist pattern 31 to form a conductor layer 23 (FIG. 4 (l )reference).
Here, the current density was 1.5 ASD for the first 15 minutes and 2.0 ASD for the next 25 minutes.

次に、過酸化水素水と硫酸の混合液からなるエッチング液を用いた化学研磨により、レジストパターン３２の上部が露出するまで導体層２１及びレジストパターン３１上部のめっき下地導電層４１をエッチングし、５〜１０μｍの配線層２２ａ、ランド２２ｂ及びフィルドビア２２ｃを形成した（図４（ｍ）参照）。   Next, the conductive conductive layer 21 and the plating base conductive layer 41 above the resist pattern 31 are etched by chemical polishing using an etchant composed of a mixed solution of hydrogen peroxide and sulfuric acid until the upper portion of the resist pattern 32 is exposed, A wiring layer 22a, a land 22b, and a filled via 22c of 5 to 10 μm were formed (see FIG. 4M).

次に、レジストパターン３２を専用の剥離液で除去し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２３ａ及びランド２３ｂが形成され、配線層２２ａとランド２２ｂがフィルドビア２２ｃにて、ランド２２ｂとランド２３ｂとがフィルドビア２３ｃにて電気的に接続された接続信頼性に優れたビアオンビア構造の４層の配線基板１００を得た（図４（ｎ）参照）。
 Next, the resist pattern 32 is removed with a special stripping solution, and the wiring layer 23a and the land 23b having a smooth surface and excellent shape reproducibility are formed on both surfaces of the insulating substrate 11, and the wiring layer 22a and the land 22b are filled vias. In 22c, a four-layer wiring board 100 having a via-on-via structure excellent in connection reliability in which the land 22b and the land 23b were electrically connected by the filled via 23c was obtained (see FIG. 4 (n)).

まず、２５μｍ厚のポリイミドテープからなる絶縁基材１１の片面に銅箔が積層された片面銅箔付きポリイミドテープの銅箔をエッチングして３μｍ厚の銅箔からなる導体層２１を形成した積層基材２０を準備した（図５（ａ）参照）。
次に、ＵＶレーザーを用いたレーザー加工により、積層基材２０の一方の面から絶縁基材１１を貫通し他方の面の導体層２１に達する１００μｍ径のビア用孔１５を形成し、ビア用孔１５底及び内壁に付着した樹脂残渣を５０℃に加熱された過マンガン酸カリウム水溶
液によるデスミア処理にて除去した（図５（ｂ）参照）。 First, a laminated base formed by etching a copper foil of a polyimide tape with a single-sided copper foil in which a copper foil is laminated on one side of an insulating substrate 11 made of a polyimide tape having a thickness of 25 μm to form a conductor layer 21 made of a copper foil having a thickness of 3 μm. A material 20 was prepared (see FIG. 5A).
Next, by via laser processing using a UV laser, a via hole 15 having a diameter of 100 μm that penetrates the insulating base material 11 from one side of the laminated base material 20 and reaches the conductor layer 21 on the other side is formed. Resin residues adhering to the bottoms and inner walls of the holes 15 were removed by desmear treatment with an aqueous potassium permanganate solution heated to 50 ° C. (see FIG. 5B).

次に、感光性のドライフィルムをラミネートして感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３３を形成した（図５（ｃ）参照）。   Next, a photosensitive dry film was laminated to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development were performed to form a resist pattern 33 (see FIG. 5C).

次に、無電解銅めっきにより一方の面のレジストパターン３３上及びビア用孔１２内に、他方の面のレジストパターン３３上及び導体層２１上に０．５〜１．０μｍ厚の銅薄膜層からなるめっき下地導電層４３を形成した（図５（ｄ）参照）。   Next, a copper thin film layer having a thickness of 0.5 to 1.0 μm is formed on the resist pattern 33 on one side and in the via hole 12 by electroless copper plating, on the resist pattern 33 on the other side and on the conductor layer 21 A plating base conductive layer 43 made of (see FIG. 5D) was formed.

次に、めっき下地導電層４３を給電層にして、硫酸銅５水和物濃度が２３０ｇ／Ｌ、硫酸濃度が７０ｇ／Ｌ、塩素イオン濃度が６０ｍｇ／Ｌの硫酸銅水溶液にエバラユージライト製キューブライトＶＦ−ＭＵを２０ｍｌ／Ｌを加えた銅めっき液を用いて電解銅めっきを行い、レジストパターン３３を覆いつくすような厚みまでめっき銅を析出させ、導体層２４を形成した（図５（ｅ）参照）。
ここで、電流密度は、はじめの１５分間で１．５ＡＳＤ、続く２５分間で２．０ＡＳＤとした。 Next, using the plating base conductive layer 43 as a power feeding layer, a copper sulfate aqueous solution having a copper sulfate pentahydrate concentration of 230 g / L, a sulfuric acid concentration of 70 g / L, and a chlorine ion concentration of 60 mg / L is prepared by Ebara Eugilite Cube. Electrolytic copper plating was performed using a copper plating solution to which 20 ml / L of light VF-MU was added, and the plated copper was deposited to such a thickness as to cover the resist pattern 33, thereby forming a conductor layer 24 (FIG. 5 (e )reference).
Here, the current density was 1.5 ASD for the first 15 minutes and 2.0 ASD for the next 25 minutes.

次に、過酸化水素水と硫酸の混合液からなるエッチング液を用いた化学研磨により、レジストパターン３１の上部が露出するまで導体層２４及びレジストパターン３３上部のめっき下地導電層４３をエッチングし、５〜１０μｍの配線層２４ａ、ランド２４ｂ及びフィルドビア２４ｃを形成した（図６（ｆ）参照）。   Next, the plating underlying conductive layer 43 on the conductor layer 24 and the resist pattern 33 is etched by chemical polishing using an etchant composed of a mixed solution of hydrogen peroxide and sulfuric acid until the upper portion of the resist pattern 31 is exposed, A wiring layer 24a, a land 24b, and a filled via 24c of 5 to 10 μm were formed (see FIG. 6F).

次に、レジストパターン３１を専用の剥離液で除去し、レジストパターン３１の下部にあった導体層２１をエッチングで除去し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２４ａ及びランド２４ｂが形成され、配線層２４ａとランド２４ｂがフィルドビア２４ｃにて電気的に接続された２層の配線基板を得た（図６（ｇ）参照）。
 Next, the resist pattern 31 is removed with a special stripping solution, and the conductor layer 21 located under the resist pattern 31 is removed by etching . The wiring having excellent surface reproducibility with smooth surfaces on both surfaces of the insulating base 11 A layer 24a and a land 24b were formed, and a two-layer wiring board in which the wiring layer 24a and the land 24b were electrically connected by a filled via 24c was obtained (see FIG. 6G).

次に、両面に樹脂フィルムをラミネートし絶縁層１３を形成した（図６（ｈ）参照）。次に、ＵＶレーザーを用いたレーザー加工により、絶縁層１６の所定位置に５０μｍ径のビア用孔１７を形成し、ビア用孔１７底及び内壁に付着した樹脂残渣を５０℃に加熱された過マンガン酸カリウム水溶液によるデスミア処理にて除去した（図６（ｉ）参照）。   Next, a resin film was laminated on both surfaces to form an insulating layer 13 (see FIG. 6H). Next, a via hole 17 having a diameter of 50 μm is formed at a predetermined position of the insulating layer 16 by laser processing using a UV laser, and the resin residue adhering to the bottom and inner wall of the via hole 17 is heated to 50 ° C. It removed by the desmear process by potassium manganate aqueous solution (refer FIG.6 (i)).

次に、感光性のドライフィルムをラミネートして感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターン３４を形成した（図７（ｊ）参照）。   Next, a photosensitive dry film was laminated to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development were performed to form a resist pattern 34 (see FIG. 7J).

次に、無電解銅めっきによりレジストパターン３４上、絶縁層１３上及びビア用孔１７内に０．５〜１．０μｍ厚の銅薄膜層からなるめっき下地導電層４４を形成した図７（ｋ）参照）。   Next, FIG. 7 (k) in which a plating base conductive layer 44 made of a copper thin film layer having a thickness of 0.5 to 1.0 μm is formed on the resist pattern 34, the insulating layer 13, and the via hole 17 by electroless copper plating. )reference).

次に、めっき下地導電層４４を給電層にして、硫酸銅５水和物濃度が２３０ｇ／Ｌ、硫酸濃度が７０ｇ／Ｌ、塩素イオン濃度が６０ｍｇ／Ｌの硫酸銅水溶液にエバラユージライト製キューブライトＶＦ−ＭＵを２０ｍｌ／Ｌを加えた銅めっき液を用いて電解銅めっきを行い、レジストパターン３４を覆いつくすような厚みまでめっき銅を析出させ、導体層２５を形成した（図７（ｌ）参照）。
ここで、電流密度は、はじめの１５分間で１．５ＡＳＤ、続く２５分間で２．０ＡＳＤとした。 Next, using the plating base conductive layer 44 as a power feeding layer, a copper sulfate aqueous solution having a copper sulfate pentahydrate concentration of 230 g / L, a sulfuric acid concentration of 70 g / L, and a chlorine ion concentration of 60 mg / L is prepared by an Ebara Eugilite cube. Electrolytic copper plating was performed using a copper plating solution to which 20 ml / L of light VF-MU was added, and the plated copper was deposited to such a thickness as to cover the resist pattern 34, thereby forming the conductor layer 25 (FIG. 7 (l )reference).
Here, the current density was 1.5 ASD for the first 15 minutes and 2.0 ASD for the next 25 minutes.

次に、過酸化水素水と硫酸の混合液からなるエッチング液を用いた化学研磨により、レジストパターン３４の上部が露出するまで導体層２５及びレジストパターン３４上部のめっき下地導電層４４をエッチングし、５〜１０μｍ厚の配線層２５ａ、ランド２５ｂ及びフィルドビア２５ｃを形成した（図７（ｍ）参照）。   Next, the conductor layer 25 and the plating base conductive layer 44 on the resist pattern 34 are etched by chemical polishing using an etchant composed of a mixed solution of hydrogen peroxide and sulfuric acid until the upper portion of the resist pattern 34 is exposed, A wiring layer 25a, a land 25b, and a filled via 25c having a thickness of 5 to 10 μm were formed (see FIG. 7 (m)).

次に、レジストパターン３４を専用の剥離液で除去し、絶縁基材１１の両面に表面が平滑な形状再現性に優れた配線層２５ａ及びランド２５ｂが形成され、配線層２２ａとランド２２ｂがフィルドビア２２ｃにて、ランド２４ｂとランド２５ｂとがフィルドビア２５３ｃにて電気的に接続された接続信頼性に優れたビアオンビア構造の４層の配線基板２００を得た（図７（ｏ）参照）。 Next, the resist pattern 34 is removed with a special stripping solution, and the wiring layer 25a and the land 25b having a smooth surface and excellent shape reproducibility are formed on both surfaces of the insulating substrate 11, and the wiring layer 22a and the land 22b are filled vias. In 22c, a four-layer wiring board 200 having a via on via structure excellent in connection reliability in which the land 24b and the land 25b were electrically connected by the filled via 253c was obtained (see FIG. 7 (o)).

（ａ）は、本発明の請求項１に係る多層配線基板の製造方法で作製された多層配線基板の一実施例を示す模式構成断面図である。(A) is a schematic cross-sectional view showing an example of a multilayer wiring board manufactured by the method for manufacturing a multilayer wiring board according to claim 1 of the present invention.

（ｂ）は、本発明の請求項２に係る多層配線基板の製造方法で作製された多層配線基板の一実施例を示す模式構成断面図である。
（ａ）〜（ｅ）は、本発明の請求項１に係る多層配線基板の製造方法における工程の一部を模式的に示す構成断面図である。 （ｆ）〜（ｉ）は、本発明の請求項１に係る多層配線基板の製造方法における工程の一部を模式的に示す構成断面図である。 （ｊ）〜（ｎ）は、本発明の請求項１に係る多層配線基板の製造方法における工程の一部を模式的に示す構成断面図である。 （ａ）〜（ｅ）は、本発明の請求項２に係る多層配線基板の製造方法における工程の一部を模式的に示す構成断面図である。 （ｆ）〜（ｉ）は、本発明の請求項２に係る多層配線基板の製造方法における工程の一部を模式的に示す構成断面図である。 （ｊ）〜（ｎ）は、本発明の請求項２に係る多層配線基板の製造方法における工程の一部を模式的に示す構成断面図である。 （ａ）〜（ｅ）は、セミアディティブプロセスによる配線層、ビア形成における工程の一部を模式的に示す構成断面図である。 （ｆ）〜（ｇ）は、セミアディティブプロセスによる配線層、ビア形成における工程の一部を模式的に示す構成断面図である。 (B) is a schematic cross-sectional view showing an example of a multilayer wiring board produced by the method for manufacturing a multilayer wiring board according to claim 2 of the present invention.
(A)-(e) is a structure sectional drawing which shows typically a part of process in the manufacturing method of the multilayer wiring board based on Claim 1 of this invention. (F)-(i) is a structure sectional view showing typically a part of process in a manufacturing method of a multilayer wiring board concerning claim 1 of the present invention. (J)-(n) is a structure sectional view showing typically a part of process in a manufacturing method of a multilayer wiring board concerning claim 1 of the present invention. (A)-(e) is a structure sectional drawing which shows typically a part of process in the manufacturing method of the multilayer wiring board based on Claim 2 of this invention. (F)-(i) is a structure sectional drawing which shows typically a part of process in the manufacturing method of the multilayer wiring board based on Claim 2 of this invention. (J)-(n) is a structure sectional view showing typically a part of process in a manufacturing method of a multilayer wiring board concerning claim 2 of the present invention. (A)-(e) is a structure sectional drawing which shows typically a part of process in the wiring layer by a semi-additive process, and via | veer formation. (F)-(g) is a structure sectional drawing which shows typically a part of process in the wiring layer by a semi-additive process, and via | veer formation.

符号の説明Explanation of symbols

１０、２０……積層基材
１１……絶縁基材
１２、１４、１５、１７、６２……ビア用孔
１３、１６、６１……絶縁層
１５……デバイスホール
２１……導体層
３０……コア基板
３１、３２、３３、３４、８１……レジストパターン
４１、４２、４３、４４、７１……めっき下地導電層
２２、２３、２４、２５……導体層
２２ａ、２３ａ、２４ａ、２５ａ、５１、５２、５４ａ……配線層
２２ｂ、２３ｂ、２４ｂ、２５ｂ……ランド
２２ｃ、２３ｃ、２４ｃ、２５ｃ、５３……フィルドビア
５４……導体層 10, 20 ... Laminated base material 11 ... Insulating base material 12, 14, 15, 17, 62 ... Via holes 13, 16, 61 ... Insulating layer 15 ... Device hole 21 ... Conductor layer 30 ... Core substrate 31, 32, 33, 34, 81... Resist pattern 41, 42, 43, 44, 71... Plating underlayer conductive layer 22, 23, 24, 25 ...... conductor layer 22 a, 23 a, 24 a, 25 a, 51 , 52, 54a... Wiring layers 22b, 23b, 24b, 25b... Land 22c, 23c, 24c, 25c, 53... Filled via 54.

Claims (2)

多層配線基板の製造方法であって、少なくとも以下の工程を有することを特徴とする多層配線基板の製造方法。
（ａ）絶縁基材の両面に導体層が形成された積層基材の一方の面から導体層及び絶縁基材を貫通し他方の面の導体層に達するビア用孔を形成する工程。
（ｂ）両面に所定厚の感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｃ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｄ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｅ）物理研磨、または化学研磨により、レジストパターンの上部が露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｆ）レジストパターンを剥離液で剥離する工程。
（ｇ）レジストパターン下部にあった導体層をエッチングにより除去する工程。
（ｈ）絶縁層を形成する工程。
（ｉ）絶縁層の所定位置にビア用孔を形成する工程。
（ｊ）両面に所定厚のレジスト感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｋ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｌ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｍ）物理研磨、または化学研磨により、レジストパターンの上部が露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｎ）レジストパターンを剥離液で剥離する工程。
（ｐ）上記（ｈ）〜（ｎ）の工程を所望の回数繰り返す工程。 A method for manufacturing a multilayer wiring board, comprising at least the following steps.
(A) The process of forming the via hole which penetrates a conductor layer and an insulation base material from one surface of the lamination base material in which the conductor layer was formed in both surfaces of the insulation base material, and reaches the conductor layer of the other surface.
(B) A step of forming a photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(C) A step of forming a plating base conductive layer on the entire surface including the via hole sidewall and the via hole bottom surface on the resist pattern.
(D) A step of performing electroplating using the plating base conductive layer as a power supply layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(E) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the upper portion of the resist pattern is exposed.
(F) A step of stripping the resist pattern with a stripping solution.
(G) A step of removing the conductor layer under the resist pattern by etching.
(H) A step of forming an insulating layer.
(I) A step of forming a via hole at a predetermined position of the insulating layer.
(J) A step of forming a resist photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(K) A step of forming a plating base conductive layer on the entire surface including the via hole side wall and the via hole bottom surface on the resist pattern.
(L) A step of performing electroplating using the plating base conductive layer as a power feeding layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(M) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the upper portion of the resist pattern is exposed.
(N) A step of stripping the resist pattern with a stripping solution.
(P) A step of repeating the steps (h) to (n) a desired number of times. 多層配線基板の製造方法であって、少なくとも以下の工程を有することを特徴とする多層配線基板の製造方法。
（ａ）絶縁基材の片面に導体層が形成された積層基材の一方の面から絶縁基材を貫通し他方の面の導体層に達するビア用孔を形成する工程。
（ｂ）両面に所定厚の感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｃ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｄ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｅ）物理研磨、または化学研磨により、レジストパターンが露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｆ）レジストパターンを剥離液で剥離する工程。
（ｇ）レジストパターン下部にあった導体層をエッチングにより除去する工程。
（ｈ）絶縁層を形成する工程。
（ｉ）絶縁層の所定位置にビア用孔を形成する工程。
（ｊ）両面に所定厚のレジスト感光層を形成し、パターン露光、現像等のパターニング処理によりレジストパターンを形成する工程。
（ｋ）レジストパターン上、ビア用孔側壁及びビア用孔底面を含む全面にめっき下地導電層を形成する工程。
（ｌ）めっき下地導電層を給電層にして電解めっきを行い、レジストパターンの高さ以上にめっき金属を析出させて導体層を形成する工程。
（ｍ）物理研磨、または化学研磨により、レジストパターンの上部が露出するまで導体層及びめっき下地導電層を研磨する工程。
（ｎ）レジストパターンを剥離液で剥離する工程。
（ｐ）上記（ｈ）〜（ｎ）の工程を所望の回数繰り返す工程。
A method for manufacturing a multilayer wiring board, comprising at least the following steps.
(A) A step of forming a via hole penetrating the insulating base material from one side of the laminated base material on which the conductive layer is formed on one side of the insulating base material and reaching the conductive layer on the other side.
(B) A step of forming a photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(C) A step of forming a plating base conductive layer on the entire surface including the via hole sidewall and the via hole bottom surface on the resist pattern.
(D) A step of performing electroplating using the plating base conductive layer as a power supply layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(E) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the resist pattern is exposed.
(F) A step of stripping the resist pattern with a stripping solution.
(G) A step of removing the conductor layer under the resist pattern by etching.
(H) A step of forming an insulating layer.
(I) A step of forming a via hole at a predetermined position of the insulating layer.
(J) A step of forming a resist photosensitive layer having a predetermined thickness on both surfaces and forming a resist pattern by patterning processing such as pattern exposure and development.
(K) A step of forming a plating base conductive layer on the entire surface including the via hole side wall and the via hole bottom surface on the resist pattern.
(L) A step of performing electroplating using the plating base conductive layer as a power feeding layer and depositing a plating metal at a height higher than the resist pattern to form a conductor layer.
(M) A step of polishing the conductor layer and the plating base conductive layer by physical polishing or chemical polishing until the upper portion of the resist pattern is exposed.
(N) A step of stripping the resist pattern with a stripping solution.
(P) A step of repeating the steps (h) to (n) a desired number of times.
JP2004091156A 2004-03-26 2004-03-26 Manufacturing method of multilayer wiring board Expired - Fee Related JP4547958B2 (en)

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Publication number Priority date Publication date Assignee Title
CN102256453B (en) * 2010-05-21 2013-12-25 富葵精密组件(深圳)有限公司 Multilayer circuit board manufacturing method
CN107094349B (en) * 2017-06-20 2019-08-27 广州兴森快捷电路科技有限公司 Printed circuit board and preparation method thereof
WO2022191180A1 (en) * 2021-03-10 2022-09-15 凸版印刷株式会社 Multilayer wiring board

Citations (6)

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Publication number Priority date Publication date Assignee Title
JPS5655099A (en) * 1979-10-12 1981-05-15 Fujitsu Ltd Method of manufacturing printed board
JPH06132630A (en) * 1992-10-20 1994-05-13 Matsushita Electric Ind Co Ltd Manufacture of flexible circuit board
JPH07231146A (en) * 1994-02-15 1995-08-29 Ibiden Co Ltd Board for mounting semiconductor, and its manufacture
JP2002076620A (en) * 2000-08-31 2002-03-15 Fujitsu Ltd Multilayer circuit board and its manufacturing method
JP2003101221A (en) * 2001-09-20 2003-04-04 Ibiden Co Ltd Method for manufacturing multilayer printed wiring board
JP2004096007A (en) * 2002-09-03 2004-03-25 Furukawa Electric Co Ltd:The Multilayer substrate manufacturing method

Patent Citations (6)

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Publication number Priority date Publication date Assignee Title
JPS5655099A (en) * 1979-10-12 1981-05-15 Fujitsu Ltd Method of manufacturing printed board
JPH06132630A (en) * 1992-10-20 1994-05-13 Matsushita Electric Ind Co Ltd Manufacture of flexible circuit board
JPH07231146A (en) * 1994-02-15 1995-08-29 Ibiden Co Ltd Board for mounting semiconductor, and its manufacture
JP2002076620A (en) * 2000-08-31 2002-03-15 Fujitsu Ltd Multilayer circuit board and its manufacturing method
JP2003101221A (en) * 2001-09-20 2003-04-04 Ibiden Co Ltd Method for manufacturing multilayer printed wiring board
JP2004096007A (en) * 2002-09-03 2004-03-25 Furukawa Electric Co Ltd:The Multilayer substrate manufacturing method

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