JP2005093774A - Semiconductor device and micro power converting device, and their manufacturing method - Google Patents

Semiconductor device and micro power converting device, and their manufacturing method Download PDF

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JP2005093774A
JP2005093774A JP2003325948A JP2003325948A JP2005093774A JP 2005093774 A JP2005093774 A JP 2005093774A JP 2003325948 A JP2003325948 A JP 2003325948A JP 2003325948 A JP2003325948 A JP 2003325948A JP 2005093774 A JP2005093774 A JP 2005093774A
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semiconductor chip
thin film
bump
bump electrode
insulating
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Yoshitomo Hayashi
善智 林
Tetsuya Kawashima
鉄也 川島
Akira Amano
彰 天野
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a micro power converting device hard to cause damages such as metal fatigue, crack, or the like in an Al electrode film on a semiconductor chip or a semiconductor chip with a structure having a high bonding strength and a high bonding reliability and to provide a method for manufacturing them. <P>SOLUTION: The semiconductor device comprises a semiconductor chip 1, a stud bump 3 formed on the chip 1, an insulative resist film 4 as an insulative supporting thin film formed on the chip 1 so as to surround the bump 3, and a ceramic substrate 5 with a metal terminal 6 fixed to the chip 1 through the bump 3 by a ultrasonic bonding. Determining the film thickness of the film 4 1/2 to 1/3 of a height of the bump 3 makes the fixing strength of the bump 3 satisfactorily strong to improve the bonding strength. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は，半導体チップをバンプ電極を介して超音波接合で導電パターン付き絶縁基板と固着した半導体装置や半導体チップとバンプ電極を介して超音波振動で薄膜磁気誘導素子とを固着した超小型電力変換装置およびそれらの製造方法に関する。   The present invention relates to a semiconductor device in which a semiconductor chip is fixed to an insulating substrate with a conductive pattern by ultrasonic bonding via a bump electrode, or a micro power having a thin film magnetic induction element fixed by ultrasonic vibration via a semiconductor chip and a bump electrode. The present invention relates to conversion devices and methods for manufacturing them.

近年、携帯電話などの携帯機器やパソコンなどのＯＡ機器の小型、軽量化を一層促進するために、これらの機器に搭載する半導体装置の超小型化と低背化やスイッチング電源として用いられるＤＣ−ＤＣコンバータなどの電力変換装置の超小型化と低背化が求められている。   In recent years, in order to further promote the reduction in size and weight of portable devices such as mobile phones and OA devices such as personal computers, the size of semiconductor devices mounted on these devices is reduced in size and height, and DC- used as a switching power source. There is a demand for ultra-miniaturization and low-profile power conversion devices such as DC converters.

図１７は、ＤＣ−ＤＣコンバータの回路図である。このＤＣ−ＤＣコンバータは、直流の入力電圧を任意の出力電圧に変換する降圧型の電力変換装置である。図中のＶｉは入力電圧、Ｃｉ、ＣＴ、Ｃｏはコンデンサ、Ｌは薄膜磁気誘導素子であるインダクタ、Ｖｏは出力電圧である。ＬとＣｏは出力電圧電流を平滑化するフィルタである。   FIG. 17 is a circuit diagram of a DC-DC converter. This DC-DC converter is a step-down power converter that converts a DC input voltage into an arbitrary output voltage. In the figure, Vi is an input voltage, Ci, CT and Co are capacitors, L is an inductor which is a thin film magnetic induction element, and Vo is an output voltage. L and Co are filters that smooth the output voltage current.

図１８は、超小型化と低背化された従来の半導体装置の要部断面図である。セラミック基板５に形成された金属端子６（導電パターン）と半導体チップ１に形成されたスタッドバンプ３が超音波接合で直接固着している。このセラミック基板５の金属端子６が点線で示すプリント基板３１の導電パターン３２とはんだ３３などで面実装される。また、このセラミック基板５はガラスエポキシのプリント基板の場合もある。また、このセラミック基板５に固着した半導体チップ１が単体で樹脂ケース（モールド）や樹脂パッケージに収納されて半導体装置となる場合もある。   FIG. 18 is a cross-sectional view of a main part of a conventional semiconductor device that is ultra-small and low-profile. The metal terminals 6 (conductive pattern) formed on the ceramic substrate 5 and the stud bumps 3 formed on the semiconductor chip 1 are directly fixed by ultrasonic bonding. The metal terminals 6 of the ceramic substrate 5 are surface-mounted with the conductive pattern 32 of the printed circuit board 31 and the solder 33 indicated by dotted lines. The ceramic substrate 5 may be a glass epoxy printed circuit board. In some cases, the semiconductor chip 1 fixed to the ceramic substrate 5 is housed alone in a resin case (mold) or resin package to form a semiconductor device.

図１９は、薄膜磁気誘導素子と半導体チップを一体化したＤＣ−ＤＣコンバータなどを超小型化と低背化した従来の超小型電力変換装置の要部断面図である。これは図１７の電源用ＩＣとインダクタとＣｉ、ＣＴ、Ｃｏなどのコンデンサ（セラミックコンデンサアレイ３５）を固着した図である。   FIG. 19 is a cross-sectional view of a main part of a conventional micro power converter in which a DC-DC converter or the like in which a thin film magnetic induction element and a semiconductor chip are integrated is miniaturized and reduced in height. This is a diagram in which the power supply IC, inductor, and capacitor (ceramic capacitor array 35) such as Ci, CT, and Co are fixedly attached.

フェライト基板１１上にコイル導体１２が形成された薄膜磁気誘導素子１０の金属端子６と半導体チップ１に形成されたスタッドバンプ３が超音波接合で直接固着されている。このフェライト基板１１の金属端子６に、点線で示したセラミックコンデンサアレイ３５などが接続されて超小型半導体装置となる。   The metal terminal 6 of the thin film magnetic induction element 10 having the coil conductor 12 formed on the ferrite substrate 11 and the stud bump 3 formed on the semiconductor chip 1 are directly fixed by ultrasonic bonding. A ceramic capacitor array 35 or the like indicated by a dotted line is connected to the metal terminal 6 of the ferrite substrate 11 to form a microminiature semiconductor device.

この超音波接合により直接固着する接合構造は、フリップチップボンディング（以下ＦＣＢと略す）構造と呼ばれ、この構造を用いた半導体装置（例えば、特許文献１、特許文献２）および超小型電力変換装置（例えば、特許文献３）が報告されている。   This bonding structure directly fixed by ultrasonic bonding is called a flip chip bonding (hereinafter abbreviated as FCB) structure, and a semiconductor device (for example, Patent Document 1 and Patent Document 2) and an ultra-small power converter using this structure are used. (For example, Patent Document 3) has been reported.

また、バンプと半導体チップを異方性導電膜を介して圧接するとき、押圧で半導体チップにダメージが導入されるのを防止し、その接合強度を増すために樹脂層でバンプを補強した例がある（例えば、特許文献４）。
特開２００２−２５２２５２号公報 特開２００１−１２７１１０号公報 特開２００２−２３３１４０号公報 特開２００３−３１７３７号公報 In addition, when the bump and the semiconductor chip are pressed through the anisotropic conductive film, an example in which the bump is reinforced with a resin layer in order to prevent damage to the semiconductor chip due to pressing and to increase the bonding strength. Yes (for example, Patent Document 4).
JP 2002-252252 A JP 2001-127110 A JP 2002-233140 A JP 2003-31737 A

これらの半導体装置および超小型電力変換装置においては，絶縁基板５やフェライト基板１１への半導体チップ１のＦＣＢが、超音波振動と圧着させるための加圧でのみで行われるため生産性が良いという利点がある。しかしその反面、はんだ接合に比べると接合の強度が弱く、ヒートサイクル等の熱ストレスに対する信頼性が低いという問題点があった。   In these semiconductor devices and micro power converters, productivity is good because the FCB of the semiconductor chip 1 to the insulating substrate 5 and the ferrite substrate 11 is performed only by ultrasonic vibration and pressurization for pressure bonding. There are advantages. On the other hand, however, there is a problem that the strength of bonding is weaker than that of solder bonding, and the reliability against heat stress such as heat cycle is low.

図２０は、半導体チップを超音波によるＦＣＢを行っている様子を示す概念図である。半導体チップ１のＡｌパット２に形成したＡｕのスタッドバンプ３をセラミック基板５の金属端子６に超音波でＦＣＢして直接固着する場合、まず、半導体チップ１をボンディングツール５１に真空吸着させ、このボンディングツール５１でセラミック基板５の金属端子６にスタッドバンプ３を押圧し、超音波発振器５２で発生させた超音波振動を超音波伝達部５３を介してボンディングスール５１に伝達し、この超音波振動が半導体チップ１に伝達し、半導体チップ１が横方向に強制的に揺すられて、スタッドバンプ３とセラミック基板５の金属端子６との接合が進行する。超音波接合が終了するとセラミック基板５を移動させてこの動作を繰り返す。   FIG. 20 is a conceptual diagram showing a state in which the semiconductor chip is subjected to FCB using ultrasonic waves. When the Au stud bump 3 formed on the Al pad 2 of the semiconductor chip 1 is directly fixed to the metal terminal 6 of the ceramic substrate 5 by ultrasonic FCB, first, the semiconductor chip 1 is vacuum-adsorbed to the bonding tool 51. The stud bump 3 is pressed against the metal terminal 6 of the ceramic substrate 5 by the bonding tool 51, and the ultrasonic vibration generated by the ultrasonic oscillator 52 is transmitted to the bonding suit 51 via the ultrasonic transmission unit 53. Is transmitted to the semiconductor chip 1 and the semiconductor chip 1 is forcibly shaken in the lateral direction, and the joining of the stud bump 3 and the metal terminal 6 of the ceramic substrate 5 proceeds. When the ultrasonic bonding is completed, the ceramic substrate 5 is moved and this operation is repeated.

この超音波接合の進行を早めるために、セラミック基板５が乗っているステージ５４をヒータ５５で加熱する。セラミック基板５の金属端子６とスタッドバンプ３の接合強度を一定の限界値以上に無理に高めようとすると、超音波振動によるストレスが、半導体チップ１上のＡｌパッド２とＡｕのスタッドバンプ３の接合部付近に集中し、超音波振動の横方向に働く力（半導体チップの表面と平行する力）により半導体チップ１からスタッドバンプ３がむしり取られる力が作用して、その近傍のＡｌパッド２やその下の半導体チップ１（母材）に金属疲労やクラック等のダメージが発生するという問題がある。   In order to accelerate the progress of this ultrasonic bonding, the stage 54 on which the ceramic substrate 5 is placed is heated by the heater 55. If the bonding strength between the metal terminal 6 of the ceramic substrate 5 and the stud bump 3 is forcibly increased beyond a certain limit value, the stress due to ultrasonic vibration causes stress between the Al pad 2 on the semiconductor chip 1 and the stud bump 3 of Au. A force concentrated in the vicinity of the joint and acting in the lateral direction of the ultrasonic vibration (a force parallel to the surface of the semiconductor chip) acts to peel off the stud bump 3 from the semiconductor chip 1, and the Al pad 2 and There is a problem that damage such as metal fatigue and cracks occurs in the semiconductor chip 1 (base material) therebelow.

尚、前記の特許文献４では異方性導電膜を圧接する力（半導体チップに対して縦方向の力）で半導体チップのバンプと導電パターンを固着しており、この縦方向の力で半導体チップにダメージが発生することに対する対策は示されているが、本発明では、超音波接合で半導体チップのバンプと導電パターン（または金属端子）を固着しており、この超音波接合での横方向に働く力（超音波振動）でダメージが発生することに対する対策は特許文献４では示されていない。   In Patent Document 4, the bumps of the semiconductor chip and the conductive pattern are fixed with a force that presses the anisotropic conductive film (force in the vertical direction with respect to the semiconductor chip), and the semiconductor chip is applied with this vertical force. However, in the present invention, the bumps of the semiconductor chip and the conductive pattern (or metal terminal) are fixed by ultrasonic bonding, and the horizontal direction in this ultrasonic bonding is shown. A countermeasure against the occurrence of damage due to working force (ultrasonic vibration) is not disclosed in Patent Document 4.

この発明の目的は、前記の課題を解決して、超音波接合での接合強度および接合の信頼性が高い半導体装置と超小型電力変換装置およびそれらの製造方法を提供することにある。   An object of the present invention is to solve the above-described problems and provide a semiconductor device and a micro power converter having high bonding strength and bonding reliability in ultrasonic bonding, and methods for manufacturing the same.

前記の目的を達成するために、半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた導電パターン付き絶縁基板とを有する半導体装置において、半導体チップ上にバンプ電極の先端が露出するように形成した該バンプ電極の剥離強度を補強すると共に超音波振動による応力を和らげる働きをする絶縁性支持薄膜を有する構成とする。   In order to achieve the above object, a semiconductor chip having a semiconductor chip and an insulating substrate with a conductive pattern in which the semiconductor chip is fixed by ultrasonic bonding via bump electrodes formed on the semiconductor chip. An insulating support thin film that reinforces the peel strength of the bump electrode formed so that the tip of the bump electrode is exposed and functions to relieve stress due to ultrasonic vibration is provided.

また、前記絶縁性支持薄膜の厚さが、バンプ電極高さの半分以下であるとよい。   Further, the thickness of the insulating support thin film is preferably not more than half the height of the bump electrode.

また、前記バンプ電極が，Ａｕのスタッドバンプであるとよい。   The bump electrode may be an Au stud bump.

また、前記絶縁基板が、ガラスエポキシ基板もしくはセラミック基板であるとよい。   The insulating substrate may be a glass epoxy substrate or a ceramic substrate.

また、半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた導電パターン付き絶縁基板とを有する半導体装置の製造方法において、半導体チップ上にバンプが埋没する厚さでバンプ電極の剥離強度を補強する絶縁性支持薄膜を形成し、該絶縁性支持薄膜をエッチバックによりバンプ電極先端が露出するまで薄くする製造方法とする。   Further, in a method of manufacturing a semiconductor device having a semiconductor chip and an insulating substrate with a conductive pattern in which the semiconductor chip is fixed by ultrasonic bonding via a bump electrode formed on the semiconductor chip, bumps are formed on the semiconductor chip. An insulating support thin film that reinforces the peeling strength of the bump electrode with the thickness to be buried is formed, and the insulating support thin film is thinned by etch back until the bump electrode tip is exposed.

また、前記絶縁性支持薄膜が、絶縁性レジスト、ポリイミドおよびエポキシの有機系絶縁物もしくはＣＶＤ法により４５０℃以下の温度で低温形成されたＳｉＯ2 、ＳｉＮ、ＰＳＧ等およびＳＯＧ（スピンオングラス）の無機系絶縁物もしくは蒸着またはスパッタ法で堆積させたＡｌ膜を陽極酸化により形成したＡｌ2 Ｏ3 であるとよい。 Further, the insulating support thin film is made of an insulating resist, an organic insulator of polyimide and epoxy, or SiO 2 , SiN, PSG, etc. formed at a low temperature by a CVD method at a temperature of 450 ° C. or less, and SOG (spin-on-glass) inorganic. It is preferable to use Al 2 O 3 formed by anodic oxidation of a system insulator or an Al film deposited by vapor deposition or sputtering.

また、半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた薄膜磁気誘導素子とを有する超小型電力変換装置において、半導体チップ上にバンプ電極の先端が露出するように形成した該バンプ電極の剥離強度を補強すると共に超音波振動による応力を和らげる働きをする絶縁性支持薄膜を有する構成とする。   Further, in a micro power converter having a semiconductor chip and a thin film magnetic induction element in which the semiconductor chip is fixed by ultrasonic bonding via a bump electrode formed on the semiconductor chip, a bump electrode is formed on the semiconductor chip. The insulating film is provided with an insulating support thin film that reinforces the peel strength of the bump electrode formed so that the tip is exposed, and that reduces the stress caused by ultrasonic vibration.

また、前記絶縁性支持薄膜の厚さが、バンプ電極高さの半分以下であるとよい。   Further, the thickness of the insulating support thin film is preferably not more than half the height of the bump electrode.

また、前記バンプ電極が、Ａｕのスタッドバンプであるとよい。   The bump electrode may be an Au stud bump.

また、前記薄膜磁気誘導素子の基板が、フェライト基板であるとよい。   The substrate of the thin film magnetic induction element may be a ferrite substrate.

また、半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた薄膜磁気誘導素子とを有する超小型電力変換装置の製造方法において、半導体チップ上にバンプが埋没する厚さでバンプ電極の剥離強度を補強する絶縁性支持薄膜を形成し、該絶縁性支持薄膜をエッチバックによりバンプ電極先端が露出するまで薄くする製造方法とする。   Further, in a method of manufacturing a micro power converter having a semiconductor chip and a thin film magnetic induction element in which the semiconductor chip is fixed by ultrasonic bonding via a bump electrode formed on the semiconductor chip, An insulating support thin film that reinforces the peeling strength of the bump electrode with a thickness at which the bump is buried is formed, and the insulating support thin film is thinned by etching back until the bump electrode tip is exposed.

また、前記絶縁性支持薄膜が、絶縁性レジスト、ポリイミドおよびエポキシの有機系絶縁物もしくはＣＶＤ法により４５０℃以下の温度で低温形成されたＳｉＯ2 、ＳｉＮ、ＰＳＧ等およびＳＯＧ（スピンオングラス）の無機系絶縁物もしくは蒸着またはスパッタ法で堆積させたＡｌ膜を陽極酸化により形成したＡｌ2 Ｏ3 であるとよい。
〔作用〕
バンプ電極を支える絶縁性支持薄膜を、半導体チップの金属パッドおよびバンプ電極下部を被覆するように厚く形成することで、ＦＣＢ時の超音波振動によるバンプ電極の揺れを低減し、パッドや半導体チップに金属疲労やクラック等のダメージが発生することを防止する。 Further, the insulating support thin film is made of an insulating resist, an organic insulator of polyimide and epoxy, or SiO 2 , SiN, PSG, etc. formed at a low temperature by a CVD method at a temperature of 450 ° C. or less, and SOG (spin-on-glass) inorganic. It is preferable to use Al 2 O 3 formed by anodic oxidation of a system insulator or an Al film deposited by vapor deposition or sputtering.
[Action]
The insulating support thin film that supports the bump electrode is formed thick so as to cover the metal pad of the semiconductor chip and the lower part of the bump electrode, thereby reducing the vibration of the bump electrode due to ultrasonic vibration during FCB, and to the pad and the semiconductor chip. Prevents damage such as metal fatigue and cracks.

この発明によれば、バンプ電極を絶縁性支持薄膜で固定補強し、超音波接合時のバンプ電極の横揺れを防止することで、半導体チップにダメージを発生させることなく、バンプ電極と導電パターン（金属端子）との接合強度を従来の１．５倍程度に高めることができる。   According to the present invention, the bump electrode is fixed and reinforced with the insulating support thin film, and the bump electrode is prevented from rolling during the ultrasonic bonding, so that the bump electrode and the conductive pattern ( The bonding strength with the metal terminal can be increased to about 1.5 times the conventional strength.

超音波接合での接合強度を高めることで、接合信頼性の高い半導体装置および超小型電力変換装置を実現することができる。   By increasing the bonding strength in ultrasonic bonding, it is possible to realize a semiconductor device and an ultra-small power conversion device with high bonding reliability.

この発明の実施の形態は、半導体チップに形成されたバンプ電極を導電パターン（金属端子）付き絶縁基板やフェライト基板に超音波接合で固着するときに、超音波振動でバンプ電極が横揺れするのを防止するために、バンプ電極の固定補強と超音波振動による応力緩和を目的に絶縁性支持薄膜を半導体チップ上にバンプ電極を取り囲むように形成したことである。   In the embodiment of the present invention, when a bump electrode formed on a semiconductor chip is fixed to an insulating substrate with a conductive pattern (metal terminal) or a ferrite substrate by ultrasonic bonding, the bump electrode rolls by ultrasonic vibration. In order to prevent this, an insulating support thin film is formed on the semiconductor chip so as to surround the bump electrode in order to fix and reinforce the bump electrode and relieve stress by ultrasonic vibration.

図１は、この発明の第１実施例の半導体装置の要部断面図である。図１８と同一部位には同一の符号を付した。   FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. The same parts as those in FIG. 18 are denoted by the same reference numerals.

この半導体装置は、半導体チップ１と、半導体チップ１に形成されたスタッドバンプ３と、このスタッドバンプ３を取り囲むように、半導体チップ１上に形成した絶縁性支持薄膜である絶縁性レジスト膜４と、スタットバンプ３を介して半導体チップ１と超音波接合で固着された金属端子６付きセラミック基板５と、これらを収納する図示しないパッケージで構成される。   This semiconductor device includes a semiconductor chip 1, a stud bump 3 formed on the semiconductor chip 1, and an insulating resist film 4 that is an insulating support thin film formed on the semiconductor chip 1 so as to surround the stud bump 3. The ceramic substrate 5 with the metal terminals 6 fixed by ultrasonic bonding to the semiconductor chip 1 via the stat bumps 3 and a package (not shown) for storing them.

絶縁性レジスト膜４の膜厚はスタッドパンプ３の高さの１／２から１／３程度にする。この絶縁性レジスト膜６の厚さが厚すぎて絶縁性レジスト膜４とセラミック基板１５の隙間が１０μｍ程度となると、アンダーフィル充填が良好に行われない。また、絶縁性レジスト膜４の厚さが薄くなり過ぎるとスタッドパンブ３の固定補強が不十分になり、接合強度が低下する。   The thickness of the insulating resist film 4 is set to about ½ to ３ of the height of the stud pump 3. If the thickness of the insulating resist film 6 is too thick and the gap between the insulating resist film 4 and the ceramic substrate 15 is about 10 μm, the underfill is not satisfactorily performed. Further, if the thickness of the insulating resist film 4 becomes too thin, the fixing and reinforcement of the stud pan 3 is insufficient, and the bonding strength is lowered.

この絶縁性レジスト膜４の代わりに、ポリイミド、エポキシ等の有機系絶縁膜、ＳｉＯ2 （酸化シリコン）、ＳｉＮ（窒化シリコン）、ＰＳＧ（リンガラス）およびＳＯＧ（スピンオングラス）などの無機系絶縁膜およびＡｌ2 Ｏ3 （アルミナ）などを絶縁性支持薄膜として用いてもよい。また、セラミック基板５の代わりにガラスエポキシ基板を絶縁基板として用いてもよい。 Instead of the insulating resist film 4, an organic insulating film such as polyimide or epoxy, an inorganic insulating film such as SiO 2 (silicon oxide), SiN (silicon nitride), PSG (phosphorus glass), and SOG (spin on glass). Al 2 O 3 (alumina) or the like may be used as the insulating support thin film. Further, a glass epoxy substrate may be used as an insulating substrate instead of the ceramic substrate 5.

セラミック基板５など半導体チップ１との熱膨張係数の違いが大きい絶縁基板を用いる場合には、スタッドバンプ３とセラミック基板５の隙間にアンダーフィル７を充填して、熱膨張による応力を緩和するとよい。   When an insulating substrate having a large difference in thermal expansion coefficient from the semiconductor chip 1 such as the ceramic substrate 5 is used, the underfill 7 is filled in the gap between the stud bump 3 and the ceramic substrate 5 to relieve stress due to thermal expansion. .

このように絶縁性レジスト膜６などの絶縁性支持薄膜を半導体チップ１上に形成することで、スタッドバンプ３が超音波接合で揺さぶられることが抑制され、スタッドバンプ３と金属端子６との接合強度を従来の１．５倍程度に高めることができる。接合強度が高まることで接合信頼性の高い半導体装置とすることができる。   By forming an insulating support thin film such as the insulating resist film 6 on the semiconductor chip 1 in this manner, the stud bump 3 is suppressed from being shaken by ultrasonic bonding, and the stud bump 3 and the metal terminal 6 are bonded. The strength can be increased to about 1.5 times the conventional level. By increasing the bonding strength, a semiconductor device with high bonding reliability can be obtained.

尚、金属端子６は、端子パターン金属膜６ａと表面側、裏面側の最表面金属膜６ｂ、６ｃで形成される。また、半導体チップ１は集積回路を形成したＩＣチップなどである。   The metal terminal 6 is formed of the terminal pattern metal film 6a and the outermost surface metal films 6b and 6c on the front surface side and the back surface side. The semiconductor chip 1 is an IC chip or the like on which an integrated circuit is formed.

図２から図８は、この発明の第２実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。この半導体装置は図１に示したものである。   FIGS. 2 to 8 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method of manufacturing the semiconductor device according to the second embodiment of the present invention. This semiconductor device is shown in FIG.

半導体チップ１の外周部にＡｌ（アルミニウム）パッド２を形成する（図２）。つぎに、このＡｌパッド２上にＡｕワイヤのボールボンディングにより高さ７０μｍのスタッドバンプ３を形成する（図３）。つぎに、絶縁性支持薄膜となる液状の保護レジスト剤をコーティングし熱硬化して絶縁性レジスト膜４を形成する（図４）。この場合、絶縁性レジスト膜４の厚さは１００μｍ程度が望ましい。この絶縁性レジスト膜４は、フイルム状のレジストをラミネータで貼付け、熱硬化させて形成してもよい。つぎに、酸素プラズマエッチングによりエッチバックして、スタッドバンプ３を露出させる（図５）。この場合、前記したように残す絶縁性レジスト膜４の厚さは、スタッドバンプ３の高さの１／２から１／３程度が望ましい。   An Al (aluminum) pad 2 is formed on the outer periphery of the semiconductor chip 1 (FIG. 2). Next, a stud bump 3 having a height of 70 μm is formed on the Al pad 2 by ball bonding of an Au wire (FIG. 3). Next, a liquid protective resist agent to be an insulating support thin film is coated and thermally cured to form an insulating resist film 4 (FIG. 4). In this case, the thickness of the insulating resist film 4 is desirably about 100 μm. The insulating resist film 4 may be formed by pasting a film resist with a laminator and thermosetting it. Next, the stud bump 3 is exposed by etching back by oxygen plasma etching (FIG. 5). In this case, the thickness of the insulating resist film 4 to be left as described above is preferably about 1/2 to 1/3 of the height of the stud bump 3.

つぎに、セラミック基板５に形成した金属端子６の位置と半導体チップ１に形成したスタッドバンプ３の位置を合わせ、セラミック基板５と半導体チップ１を配置する（図６）。つぎに、半導体チップ１を超音波ＦＣＢにより、スタットバンプ３をセラミック基板５に形成した金属端子６に直接固着する。この固着した後、セラミック基板５を移動させ、再び半導体チップ１を超音波ＦＣＢにより固着する（図７）。このとき、金属端子６として、端子パターン金属膜６ａは厚み５μｍのＮｉが、また表面側、裏面側の最表面金属膜６ｂ、６ｃは厚み１μｍのＡｕがそれぞれめっきにより形成されていることが望ましい。つぎに、アンダーフィル７を半導体チップ１とセラミック基板５の間に充填し、Ｙ−Ｙ線で切断して、セラミック基板５と半導体チップ１がスタットバンプ３で固着したチップ型の半導体素子となる（図８）。つぎに、図示しない樹脂やキャンパッケージに収納するして半導体装置が完成する。   Next, the position of the metal terminal 6 formed on the ceramic substrate 5 and the position of the stud bump 3 formed on the semiconductor chip 1 are aligned, and the ceramic substrate 5 and the semiconductor chip 1 are arranged (FIG. 6). Next, the semiconductor chip 1 is directly fixed to the metal terminal 6 formed on the ceramic substrate 5 by the ultrasonic FCB. After the fixing, the ceramic substrate 5 is moved, and the semiconductor chip 1 is again fixed by the ultrasonic FCB (FIG. 7). At this time, as the metal terminal 6, it is desirable that the terminal pattern metal film 6a is formed by plating with 5 μm thick Ni, and the outermost surface metal films 6b and 6c on the front and back surfaces are formed by plating with 1 μm thick Au, respectively. . Next, the underfill 7 is filled between the semiconductor chip 1 and the ceramic substrate 5 and cut along the Y-Y line, so that a chip-type semiconductor element in which the ceramic substrate 5 and the semiconductor chip 1 are fixed by the stat bump 3 is obtained. (FIG. 8). Next, the semiconductor device is completed by being housed in a resin or can package (not shown).

絶縁性支持薄膜として絶縁性レジスト膜７の代わりに用いられるＳｉＯ2 、ＳｉＮ、ＰＳＧおよびＳＯＧなどの無機系絶縁膜は、ＣＶＤ法により４５０℃以下の温度で低温形成する。また、Ａｌ2 Ｏ3 は、蒸着またはスパッタ法で堆積させたＡｌ膜を陽極酸化して形成する。 An inorganic insulating film such as SiO 2 , SiN, PSG, and SOG used as the insulating support thin film instead of the insulating resist film 7 is formed at a low temperature of 450 ° C. or less by the CVD method. Al 2 O 3 is formed by anodizing an Al film deposited by vapor deposition or sputtering.

図９は、この発明の第３実施例の超小型電力変換装置の要部断面図である。図１９と同一部位には同一の符号を付した。   FIG. 9 is a cross-sectional view of an essential part of a micro power converter according to a third embodiment of the present invention. The same parts as those in FIG. 19 are denoted by the same reference numerals.

この超小型電力変換装置は、半導体チップ１と、半導体チップ１に形成されたスタッドバンプ３と、このスタッドバンプ３を取り囲むように、半導体チップ１上に形成した絶縁性支持膜である絶縁性レジスト膜４と、スタットバンプ３を介して半導体チップ１と超音波接合で固着された金属端子６付きフェライト基板１１（薄膜磁気誘導素子１０）とで構成される。   This micro power conversion device includes a semiconductor chip 1, a stud bump 3 formed on the semiconductor chip 1, and an insulating resist that is an insulating support film formed on the semiconductor chip 1 so as to surround the stud bump 3. A film 4 and a ferrite substrate 11 (thin film magnetic induction element 10) with a metal terminal 6 fixed to the semiconductor chip 1 by ultrasonic bonding via a stat bump 3 are formed.

絶縁性レジスト膜４の膜厚はスタッドパンプ３の高さの１／２から１／３にすることが望ましい。この絶縁性レジスト膜４の厚さが厚すぎて、絶縁性レジスト膜４とフェライト基板１１との隙間が１０μｍ程度となるとアンダーフィル７の充填が良好に行われない。また絶縁性レジスト膜４の厚さが薄くなり過ぎるとスタッドパンブ３の固定補強が不十分になり、接合強度が低下する。   The film thickness of the insulating resist film 4 is preferably set to 1/2 to 1/3 of the height of the stud pump 3. If the insulating resist film 4 is too thick and the gap between the insulating resist film 4 and the ferrite substrate 11 is about 10 μm, the underfill 7 is not satisfactorily filled. On the other hand, if the thickness of the insulating resist film 4 becomes too thin, the fixing of the stud pan 3 is insufficient and the bonding strength is lowered.

この絶縁性レジスト膜４の代わりに、ポリイミド、エポキシ等の有機系絶縁膜、ＳｉＯ2 、ＳｉＮ、ＰＳＧおよびＳＯＧなどの無機系絶縁膜およびＡｌ2 Ｏ3 などを用いてもよい。 Instead of the insulating resist film 4, an organic insulating film such as polyimide or epoxy, an inorganic insulating film such as SiO 2 , SiN, PSG and SOG, Al 2 O 3 or the like may be used.

このように絶縁性レジスト膜４などの絶縁性支持薄膜を半導体チップ上に形成することで、スタッドバンプが超音波接合で揺さぶられることが抑制され、スタッドバンプと金属端子との接合強度を従来の１．５倍程度に高めることができる。接合強度が高まることで接合信頼性の高い超小型電力変換装置とすることができる。   By forming an insulating support thin film such as the insulating resist film 4 on the semiconductor chip in this way, the stud bumps are suppressed from being shaken by ultrasonic bonding, and the bonding strength between the stud bumps and the metal terminals can be reduced. It can be increased to about 1.5 times. By increasing the bonding strength, an ultra-compact power conversion device with high bonding reliability can be obtained.

前記のアンダーフィル７の充填は、半導体チップ１とフィライト基板１１との密着性を増大される働きと、半導体チップ１とフィライト基板１１の線熱膨張係数の違いにより発生する応力を緩和する働きがある。そのため、半導体チップ１が大きい場合は特に有効であり、小さい場合は不要とすることができる。   The filling of the underfill 7 serves to increase the adhesion between the semiconductor chip 1 and the philite substrate 11 and to relieve stress generated due to the difference in linear thermal expansion coefficient between the semiconductor chip 1 and the philite substrate 11. is there. Therefore, it is particularly effective when the semiconductor chip 1 is large, and can be made unnecessary when the semiconductor chip 1 is small.

図１０から図１６は、この発明の第４実施例の超小型電力変換装置の製造方法であり、工程順に示した要部製造工程断面図である。この超小型電力変換装置は図９に示したものである。   FIGS. 10 to 16 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method for manufacturing the micro power converter according to the fourth embodiment of the present invention. This micro power converter is shown in FIG.

半導体チップ１の外周部にＡｌ（アルミニウム）パッド２を形成する（図１０）。つぎに、このＡｌパッド２上にＡｕワイヤのボールボンディングにより高さ７０μｍのスタッドバンプ３を形成する（図１１）。つぎに、絶縁性支持薄膜となる液状の保護レジスト剤をコーティングし熱硬化して絶縁性レジスト膜４を形成する（図１２）。この場合、絶縁性レジスト膜４の厚さは１００μｍ程度が望ましい。この絶縁性レジスト膜４は、フイルム状のレジストをラミネータで貼付け、熱硬化させて形成してもよい。つぎに、酸素プラズマエッチングによりエッチバックして、スタッドバンプ３を露出させる（図１３）。この場合、前記したように残す絶縁性レジスト膜４の厚さは、スタッドバンプ３の高さの１／２から１／３程度が望ましい。ここまでは、図２から図５と同じである。   Al (aluminum) pads 2 are formed on the outer periphery of the semiconductor chip 1 (FIG. 10). Next, a stud bump 3 having a height of 70 μm is formed on the Al pad 2 by ball bonding of an Au wire (FIG. 11). Next, a liquid protective resist agent to be an insulating support thin film is coated and thermally cured to form an insulating resist film 4 (FIG. 12). In this case, the thickness of the insulating resist film 4 is desirably about 100 μm. The insulating resist film 4 may be formed by pasting a film resist with a laminator and thermosetting it. Next, the stud bump 3 is exposed by etching back by oxygen plasma etching (FIG. 13). In this case, the thickness of the insulating resist film 4 to be left as described above is preferably about 1/2 to 1/3 of the height of the stud bump 3. Up to this point, the process is the same as that shown in FIGS.

つぎに、フェライト基板５にコイル導体１２を形成し、その表面を表面保護膜１３で被覆した薄膜磁気誘導素子１０を複数個形成する。このフェライト基板１１に形成した金属端子６の位置と半導体チップ１に形成したスタッドバンプ３の位置を合わせ、フェライト基板１１と半導体チップ１を配置する（図１４）。つぎに、半導体チップ１を超音波ＦＣＢにより、スタットバンプ３をフェライト基板１１に形成した金属端子６に直接固着する。この固着した後、フェライト基板１１を移動させ、再び半導体チップ１を超音波ＦＣＢにより固着する（図１５）。このとき、金属端子６として、端子パターン金属膜６ａの表面にはは厚み５μｍのＮｉが、また表面側、裏面側の最表面金属膜６ｂ、６ｃは厚み１μｍのＡｕがそれぞれめっきにより形成されていることが望ましい。つぎに、アンダーフィル７を半導体チップ１とフェライト基板１１の間に充填し、Ｙ−Ｙ線で切断して、フェライト基板１１と半導体チップ１がスタットバンプ３で固着したチップ型の超小型電力変換装置となる（図１６）。   Next, the coil conductor 12 is formed on the ferrite substrate 5, and a plurality of thin film magnetic induction elements 10 whose surfaces are covered with the surface protective film 13 are formed. The position of the metal terminal 6 formed on the ferrite substrate 11 and the position of the stud bump 3 formed on the semiconductor chip 1 are aligned, and the ferrite substrate 11 and the semiconductor chip 1 are arranged (FIG. 14). Next, the semiconductor chip 1 is directly fixed to the metal terminals 6 formed on the ferrite substrate 11 by the ultrasonic FCB. After the fixing, the ferrite substrate 11 is moved, and the semiconductor chip 1 is again fixed by the ultrasonic FCB (FIG. 15). At this time, as the metal terminal 6, Ni having a thickness of 5 μm is formed on the surface of the terminal pattern metal film 6a, and Au having a thickness of 1 μm is formed on each of the outermost metal films 6b and 6c on the front side and the back side. It is desirable that Next, the underfill 7 is filled between the semiconductor chip 1 and the ferrite substrate 11, cut along the Y-Y line, and the chip-type micro power conversion in which the ferrite substrate 11 and the semiconductor chip 1 are fixed by the stat bump 3. It becomes a device (FIG. 16).

尚、図１５の工程で複数個の半導体チップ１とそれに対応する数の薄膜磁気誘導素子１０を含むように切断すると、多出力の超小型電力変換装置とすることができる。   In addition, if it cut | disconnects so that the some semiconductor chip 1 and the corresponding number of thin film magnetic induction elements 10 may be included in the process of FIG. 15, it can be set as a multi-output microminiature power converter.

また、絶縁性支持薄膜として絶縁性レジスト膜７の代わりに用いられるＳｉＯ2 、ＳｉＮ、ＰＳＧおよびＳＯＧなどの無機系絶縁膜は、ＣＶＤ法により４５０℃以下の温度で低温形成する。また、Ａｌ2 Ｏ3 は、蒸着またはスパッタ法で堆積させたＡｌ膜を陽極酸化して形成する。 Further, an inorganic insulating film such as SiO 2 , SiN, PSG and SOG used as an insulating support thin film instead of the insulating resist film 7 is formed at a low temperature of 450 ° C. or less by the CVD method. Al 2 O 3 is formed by anodizing an Al film deposited by vapor deposition or sputtering.

この発明は、半導体チップに形成したバンプと導電パターン（金属端子）付き絶縁基板（セラミック基板やフェライト基板）を超音波接合で直接固着する場合に、バンプの固定を補強するために絶縁性支持薄膜を半導体チップ上にバンプ電極を取り囲むように形成するものであり、半導体装置や超小型電力変換装置に限らず半導体チップとそれを支持する基板とをバンプ電極を介して超音波接合する場合に有効に利用できる。   The present invention provides an insulating support thin film for reinforcing the fixing of bumps when directly bonding a bump formed on a semiconductor chip and an insulating substrate (ceramic substrate or ferrite substrate) with a conductive pattern (metal terminal) by ultrasonic bonding. Is formed so as to surround the bump electrode on the semiconductor chip, and is effective not only for semiconductor devices and ultra-small power converters, but also for ultrasonic bonding of the semiconductor chip and the substrate supporting it via the bump electrode. Available to:

この発明の第１実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. この発明の第２実施例の半導体装置の要部製造工程断面図Sectional view of manufacturing process of main part of semiconductor device according to second embodiment of this invention. 図２に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 2 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図３に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 3 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図４に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 4 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図５に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 5 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図６に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 6 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図７に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 7 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the second embodiment of the present invention, continued from FIG. この発明の第３実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. この発明の第４実施例の半導体装置の要部製造工程断面図Sectional view of manufacturing process of main part of semiconductor device according to fourth embodiment of this invention. 図１０に続く、この発明の第４実施例の半導体装置の要部製造工程断面図FIG. 10 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the fourth embodiment of the present invention continued from FIG. 図１１に続く、この発明の第４実施例の半導体装置の要部製造工程断面図FIG. 11 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 図１２に続く、この発明の第４実施例の半導体装置の要部製造工程断面図FIG. 12 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 図１３に続く、この発明の第４実施例の半導体装置の要部製造工程断面図FIG. 13 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 図１４に続く、この発明の第４実施例の半導体装置の要部製造工程断面図FIG. 14 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 図１５に続く、この発明の第４実施例の半導体装置の要部製造工程断面図FIG. 15 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. ＤＣ−ＤＣコンバータの回路図Circuit diagram of DC-DC converter 超小型化と低背化された従来の半導体装置の要部断面図Cross-sectional view of the main parts of a conventional semiconductor device that has been reduced in size and height 超小型化と低背化された従来の超小型電力変換装置の要部断面図Cross-sectional view of the main part of a conventional ultra-compact power converter with ultra-compact and low profile 超音波接合の概念図Conceptual diagram of ultrasonic bonding

符号の説明Explanation of symbols

１ 半導体チップ
２ Ａｌパッド
３ スタッドバンプ
４ 絶縁性支持基板
５ セラミック基板
６ 金属端子
６ａ 端子パターン金属膜
６ｂ 表面側の最表面金属膜
６ｃ 裏面側の最表面金属膜
７ アンダーフィル
１０ 薄膜磁気誘導素子
１１ フェライト基板
１２ コイル導体
１３ 絶縁保護膜 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Al pad 3 Stud bump 4 Insulating support board 5 Ceramic substrate 6 Metal terminal 6a Terminal pattern metal film 6b Outermost surface metal film 6c Outermost surface metal film 7 Underfill 10 Thin film magnetic induction element 11 Ferrite substrate 12 Coil conductor 13 Insulating protective film

Claims (12)

半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた導電パターン付き絶縁基板とを有する半導体装置において、
半導体チップ上にバンプ電極が露出するように形成した絶縁性支持薄膜を有することを特徴とする半導体装置。 In a semiconductor device having a semiconductor chip and an insulating substrate with a conductive pattern in which the semiconductor chip is fixed by ultrasonic bonding via a bump electrode formed on the semiconductor chip.
A semiconductor device comprising: an insulating support thin film formed on a semiconductor chip so that bump electrodes are exposed. 前記絶縁性支持薄膜の厚さが、バンプ電極高さの半分以下であることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the thickness of the insulating support thin film is not more than half of the height of the bump electrode. 前記バンプ電極が，Ａｕのスタッドバンプであることを特徴とする請求項１または２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the bump electrode is an Au stud bump. 前記絶縁基板が、ガラスエポキシ基板もしくはセラミック基板であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating substrate is a glass epoxy substrate or a ceramic substrate. 半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた導電パターン付き絶縁基板とを有する半導体装置の製造方法において、
半導体チップ上にバンプ電極が埋没する厚さで絶縁性支持薄膜を形成する工程と、該絶縁性支持薄膜をエッチバックによりバンプ電極が露出するまで薄くする工程を有することを特徴とする半導体装置の製造方法。 In a method of manufacturing a semiconductor device having a semiconductor chip and an insulating substrate with a conductive pattern in which the semiconductor chip is fixed by ultrasonic bonding via a bump electrode formed on the semiconductor chip.
A semiconductor device comprising: a step of forming an insulating support thin film with a thickness at which a bump electrode is buried on a semiconductor chip; and a step of thinning the insulating support thin film until the bump electrode is exposed by etch back. Production method. 前記絶縁性支持薄膜が、絶縁性レジスト、ポリイミドおよびエポキシの有機系絶縁物もしくはＣＶＤ法により４５０℃以下の温度で低温形成されたＳｉＯ2 、ＳｉＮ、ＰＳＧ等およびＳＯＧ（スピンオングラス）の無機系絶縁物もしくは蒸着またはスパッタ法で堆積させたＡｌ膜を陽極酸化により形成したＡｌ2 Ｏ3 であることを特徴とする請求項５に記載の半導体装置の製造方法。 The insulating support thin film is made of an organic resist such as an insulating resist, polyimide and epoxy, or an inorganic insulating material such as SiO 2 , SiN, PSG and SOG (spin-on-glass) formed at a low temperature of 450 ° C. or less by a CVD method. the method of manufacturing a semiconductor device according to claim 5, characterized in that the object or Al films deposited by evaporation or sputtering a Al 2 O 3 formed by anodic oxidation. 半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた薄膜磁気誘導素子とを有する超小型電力変換装置において、
半導体チップ上にバンプ電極が露出するように形成した絶縁性支持薄膜を有することを特徴とする超小型電力変換装置。 In a micro power converter having a semiconductor chip and a thin film magnetic induction element in which the semiconductor chip is fixed by ultrasonic bonding via a bump electrode formed on the semiconductor chip,
An ultra-compact power conversion device comprising an insulating support thin film formed so that a bump electrode is exposed on a semiconductor chip. 前記絶縁性支持薄膜の厚さが、バンプ電極高さの半分以下であることを特徴とする請求項７に記載の超小型電力変換装置。 The ultra-compact power converter according to claim 7, wherein the thickness of the insulating support thin film is not more than half of the height of the bump electrode. 前記バンプ電極が、Ａｕのスタッドバンプであることを特徴とする請求項７または８に記載の超小型電力変換装置。 The micro power converter according to claim 7 or 8, wherein the bump electrode is an Au stud bump. 前記薄膜磁気誘導素子の基板が、フェライト基板であることを特徴とする請求項７に記載の超小型電力変換装置。 The micro power converter according to claim 7, wherein the substrate of the thin film magnetic induction element is a ferrite substrate. 半導体チップと、該半導体チップを該半導体チップに形成されたバンプ電極を介して超音波接合で固着させた薄膜磁気誘導素子とを有する超小型電力変換装置の製造方法において、
半導体チップ上にバンプが埋没する厚さで絶縁性支持薄膜を形成する工程と、該絶縁性支持薄膜をエッチバックによりバンプ電極が露出するまで薄くする工程を有することを特徴とする超小型電力変換装置の製造方法。 In a method for manufacturing a microminiature power conversion device having a semiconductor chip and a thin film magnetic induction element in which the semiconductor chip is fixed by ultrasonic bonding via a bump electrode formed on the semiconductor chip,
An ultra-compact power conversion comprising: forming an insulating support thin film with a thickness at which a bump is buried on a semiconductor chip; and thinning the insulating support thin film until the bump electrode is exposed by etch back. Device manufacturing method. 前記絶縁性支持薄膜が、絶縁性レジスト、ポリイミドおよびエポキシの有機系絶縁物もしくはＣＶＤ法により４５０℃以下の温度で低温形成されたＳｉＯ2 、ＳｉＮ、ＰＳＧ等およびＳＯＧ（スピンオングラス）の無機系絶縁物もしくは蒸着またはスパッタ法で堆積させたＡｌ膜を陽極酸化により形成したＡｌ2 Ｏ3 であることを特徴とする請求項１１に記載の超小型電力変換装置の製造方法。 The insulating support thin film is made of an organic resist such as an insulating resist, polyimide and epoxy, or an inorganic insulating material such as SiO 2 , SiN, PSG and SOG (spin-on-glass) formed at a low temperature of 450 ° C. or less by a CVD method. 12. The method for manufacturing a micro power converter according to claim 11, wherein the Al film is Al 2 O 3 formed by anodic oxidation of an Al film deposited by an object or vapor deposition or sputtering.
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JP2007089316A (en) * 2005-09-22 2007-04-05 Fuji Electric Device Technology Co Ltd Microminiature power conversion device and manufacturing method therefor
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