JP2005057253A5

JP2005057253A5 -

Info

Publication number: JP2005057253A5
Application number: JP2004206753A
Authority: JP
Filing date: 2004-07-14
Publication date: 2007-08-09
Anticipated expiration: 2024-07-14

Claims

チャネル形成領域、前記チャネル形成領域を挟んでいる一対の第１の領域、及び前記チャネル形成領域と前記一対の第１の領域を挟んでいる一対の第２の領域を含む活性層と、ゲート絶縁膜を間に挟んで前記チャネル形成領域及び前記一対の第１の領域と重なっているゲート電極とを有するトランジスタが設けられ、
前記活性層の表面に対して斜めに交差する方向から不純物を注入することで、前記一対の第１の領域と前記一対の第２の領域に前記不純物を添加し、
前記一対の第２の領域は、前記一対の第１の領域よりも前記不純物の注入方向寄りに設けられていることを特徴とする半導体装置の作製方法。 An active layer including a channel formation region, the channel forming a pair sandwiching a region first region, and a pair of second regions and the channel forming region and across the pair of first regions, Gate A transistor having a gate electrode overlapping with the channel formation region and the pair of first regions with an insulating film interposed therebetween,
Wherein by injecting an impurity from a direction intersecting obliquely to the surface of the active layer, the impurity is added to the second realm the pair of first regions and the pair,
Second region before Symbol pair, a method for manufacturing a semiconductor device, characterized in that provided in the injection direction toward said impurities than said pair of first regions.

請求項１において、In claim 1,
前記活性層と重なる前記ゲート電極の端部は、前記不純物の注入方向側に向けられていることを特徴とする半導体装置の作製方法。A manufacturing method of a semiconductor device, wherein an end portion of the gate electrode overlapping with the active layer is directed to the impurity implantation direction side.

チャネル形成領域、前記チャネル形成領域を挟んでいる一対の第１の領域、及び前記一対の第１の領域の一方と前記チャネル形成領域との間に設けられている第２の領域を含む活性層と、ゲート絶縁膜を間に挟んで前記チャネル形成領域及び前記第２の領域と重なっているゲート電極とを有するトランジスタが設けられ、An active layer including a channel formation region, a pair of first regions sandwiching the channel formation region, and a second region provided between one of the pair of first regions and the channel formation region And a transistor having a gate electrode overlapping with the channel formation region and the second region with a gate insulating film interposed therebetween,
前記活性層の表面に対して斜めに交差する方向から不純物を注入することで、前記一対の第１の領域と前記第２の領域に前記不純物を添加し、By injecting impurities from a direction obliquely intersecting the surface of the active layer, the impurities are added to the pair of first regions and the second regions,
前記一対の第１の領域の一方は、前記第２の領域よりも前記不純物の注入方向寄りに設けられており、One of the pair of first regions is provided closer to the impurity implantation direction than the second region,
前記チャネル形成領域と前記一対の第１の領域の他方は、前記注入方向に沿って接していることを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the channel formation region and the other of the pair of first regions are in contact with each other along the implantation direction.

請求項３において、In claim 3,
前記活性層と重なる前記ゲート電極の複数の端部の一つは、前記不純物の注入方向側に向けられていることを特徴とする半導体装置の作製方法。One of the plurality of end portions of the gate electrode overlapping with the active layer is directed to the impurity implantation direction side.

チャネル形成領域、前記チャネル形成領域を挟んでいる一対の第１の領域、及び前記チャネル形成領域と前記一対の第１の領域を挟んでいる一対の第２の領域を含む活性層と、ゲート絶縁膜を間に挟んで前記チャネル形成領域と重なっているゲート電極とを有するトランジスタが設けられ、An active layer including a channel formation region, a pair of first regions sandwiching the channel formation region, and a pair of second regions sandwiching the channel formation region and the pair of first regions, and gate insulation A transistor having a gate electrode overlapping with the channel formation region with a film interposed therebetween;
前記活性層の表面に対して斜めに交差する方向から不純物を注入することで、前記一対の第２の領域に前記不純物を添加し、By injecting impurities from a direction obliquely intersecting the surface of the active layer, the impurities are added to the pair of second regions,
前記一対の第１の領域は、前記一対の第２の領域よりも前記不純物の注入方向寄りに設けられていることを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the pair of first regions is provided closer to the impurity implantation direction than the pair of second regions.

請求項５において、In claim 5,
前記活性層と重なる前記ゲート電極の端部は、前記不純物の注入方向とは反対の側に向けられていることを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, wherein an end portion of the gate electrode overlapping with the active layer is directed to a side opposite to the impurity implantation direction.

請求項１乃至請求項６のいずれか一項において、
第１の基板に、前記トランジスタを有する複数の集積回路を形成し、
前記第１の基板を分断することで、前記複数の集積回路のうちの一の集積回路が形成された第２の基板を形成し、
前記第２の基板を、半導体素子または表示素子が形成された第３の基板に貼り合わせ、前記一の集積回路と前記半導体素子または表示素子とを電気的に接続することを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 6,
A first substrate, forming a plurality of integrated circuits with the transistors,
The first by cutting the substrate, forming a second substrate in which one of the integrated circuits of the plurality of integrated circuits have been formed,
The second substrate is bonded to a third substrate on which a semiconductor element or a display element is formed, and the one integrated circuit and the semiconductor element or the display element are electrically connected to each other. Manufacturing method.

第１のチャネル形成領域、前記第１のチャネル形成領域を挟んでいる一対の第１の領域、及び前記第１のチャネル形成領域と前記一対の第１の領域を挟んでいる一対の第２の領域を含む第１の活性層と、第１のゲート絶縁膜を間に挟んで前記第１のチャネル形成領域及び前記一対の第１の領域と重なっている第１のゲート電極とを有する第１のトランジスタと、第２のチャネル形成領域及び第３の領域を含む第２の活性層と、第２のゲート絶縁膜を間に挟んで前記第２のチャネル形成領域と重なっている第２のゲート電極とを有する第２のトランジスタとが設けられ、
前記第１の活性層の表面及び前記第２の活性層の表面に対して斜めに交差する方向から不純物を注入することで、前記一対の第１の領域、前記一対の第２の領域、及び前記第３の領域に前記不純物を添加し、
前記一対の第２の領域は、前記一対の第１の領域よりも前記不純物の注入方向寄りに設けられており、
前記第２のチャネル形成領域と前記第３の領域は、前記注入方向に沿って接していることを特徴とする半導体装置の作製方法。 A first channel formation region, a pair of first regions sandwiching the first channel formation region, and a pair of second regions sandwiching the first channel formation region and the pair of first regions the has a first active layer including a region, a first gate electrode that is sandwiched therebetween overlap the first channel formation region and the pair of first region between the first gate insulating film 1 A second active layer including a second channel formation region and a third region, and a second gate overlapping the second channel formation region with a second gate insulating film interposed therebetween And a second transistor having an electrode ,
By implanting an impurity from a direction intersecting obliquely with respect to the surface and the surface of the second active layer before Symbol first active layer, the pair of first regions, the pair of second regions, And adding the impurity to the third region ,
Second region before Symbol pair is provided in the injection direction toward said impurities than said pair of first regions,
Before Symbol wherein the second channel formation region third region, the method for manufacturing a semiconductor device, characterized in that contact I along with the injection direction.

第１のチャネル形成領域、前記第１のチャネル形成領域を挟んでいる一対の第１の領域、及び前記第１のチャネル形成領域と前記一対の第１の領域を挟んでいる一対の第２の領域を含む第１の活性層と、第１のゲート絶縁膜を間に挟んで前記第１のチャネル形成領域及び前記一対の第１の領域と重なっている第１のゲート電極とを有する第１のトランジスタと、第２のチャネル形成領域、前記第２のチャネル形成領域を挟んでいる一対の第３の領域、及び前記第２のチャネル形成領域と前記一対の第３の領域を挟んでいる一対の第４の領域を含む第２の活性層と、第２のゲート絶縁膜を間に挟んで前記第２のチャネル形成領域と重なっている第２のゲート電極とを有する第２のトランジスタとが設けられ、
前記第１の活性層の表面及び前記第２の活性層の表面に対して斜めに交差する方向から不純物を注入することで、前記一対の第１の領域、前記一対の第２の領域、及び前記一対の第４の領域に前記不純物を添加し、
前記一対の第２の領域は、前記一対の第１の領域よりも前記不純物の注入方向寄りに設けられており、
前記一対の第３の領域は、前記一対の第４の領域よりも前記不純物の注入方向寄りに設けられていることを特徴とする半導体装置の作製方法。 A first channel formation region, a pair of first regions sandwiching the first channel formation region, and a pair of second regions sandwiching the first channel formation region and the pair of first regions the has a first active layer including a region, a first gate electrode that is sandwiched therebetween overlap the first channel formation region and the pair of first region between the first gate insulating film 1 and transistor, a second channel formation region, the second third pair sandwiching a channel formation region of the region, and a pair sandwiching the second third channel forming region and the pair of areas A second transistor having a second active layer including the fourth region and a second gate electrode overlapping with the second channel formation region with the second gate insulating film interposed therebetween. Provided ,
By implanting an impurity from a direction intersecting obliquely with respect to the surface and the surface of the second active layer before Symbol first active layer, the pair of first regions, the pair of second regions, And adding the impurity to the pair of fourth regions ,
Second region before Symbol pair is provided in the injection direction toward said impurities than said pair of first regions,
The third region before Symbol pair, a method for manufacturing a semiconductor device, characterized in that provided in the injection direction toward said impurities than said pair of fourth regions.

請求項９において、In claim 9,
前記第２の活性層と重なる前記第２のゲート電極の端部は、前記不純物の注入方向とは反対の側に向けられていることを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, wherein an end portion of the second gate electrode overlapping with the second active layer is directed to a side opposite to an impurity implantation direction.

請求項８乃至請求項１０のいずれか一項において、In any one of Claims 8 to 10,
前記第１の活性層と重なる前記第１のゲート電極の端部は、前記不純物の注入方向側に向けられていることを特徴とする半導体装置の作製方法。A manufacturing method of a semiconductor device, wherein an end portion of the first gate electrode overlapping with the first active layer is directed to the impurity implantation direction side.

第１のチャネル形成領域、前記第１のチャネル形成領域を挟んでいる一対の第１の領域、及び前記第１のチャネル形成領域と前記一対の第１の領域を挟んでいる一対の第２の領域を含む第１の活性層と、第１のゲート絶縁膜を間に挟んで前記第１のチャネル形成領域及び前記一対の第１の領域と重なっている第１のゲート電極とを有する第１のトランジスタと、第２のチャネル形成領域、第３の領域、及び前記第２のチャネル形成領域と前記第３の領域に挟まれた第４の領域を含む第２の活性層と、第２のゲート絶縁膜を間に挟んで前記第２のチャネル形成領域と重なっている第２のゲート電極とを有する第２のトランジスタとが設けられ、
前記一対の第２の領域、前記第３の領域、及び前記第４の領域に第１の不純物を添加し、
前記第２のトランジスタの前記第２のチャネル形成領域及び前記第４の領域を覆うようにマスクを形成し、
前記第１の活性層の表面及び前記第２の活性層の表面に対して斜めに交差する方向から第２の不純物を注入することで、前記一対の第１の領域、前記一対の第２の領域、及び前記第３の領域に前記第２の不純物を添加し、
前記一対の第２の領域は、前記一対の第１の領域よりも前記第２の不純物の注入方向寄りに設けられており、
前記第３の領域と前記第４の領域は、前記注入方向に沿って接していることを特徴とする半導体装置の作製方法。 A first channel formation region, a pair of first regions sandwiching the first channel formation region, and a pair of second regions sandwiching the first channel formation region and the pair of first regions the has a first active layer including a region, a first gate electrode that is sandwiched therebetween overlap the first channel formation region and the pair of first region between the first gate insulating film 1 A second active layer including a second channel formation region, a third region, and a fourth region sandwiched between the second channel formation region and the third region; A second transistor having a second gate electrode overlapping with the second channel formation region with a gate insulating film interposed therebetween ,
Adding a first impurity to the pair of second regions, the third region, and the fourth region;
The mask is formed to cover the second channel forming region and the fourth region of the second transistor,
By implanting a second impurity from a direction obliquely intersecting the surface of the first active layer and the surface of the second active layer , the pair of first regions and the pair of second regions Adding the second impurity to the region and the third region ;
Second region before Symbol pair is provided in the injection direction toward the second impurity than the pair of first regions,
The third region and the fourth region, a method for manufacturing a semiconductor device according to claim Tei Rukoto contact me along the injection direction.

請求項１２において、In claim 12,
前記第１の活性層と重なる前記第１のゲート電極の端部は、前記第２の不純物の注入方向側に向けられていることを特徴とする半導体装置の作製方法。A manufacturing method of a semiconductor device, wherein an end portion of the first gate electrode overlapping with the first active layer is directed to the second impurity implantation direction side.

請求項８乃至請求項１３のいずれか一項において、
第１の基板に、前記第１のトランジスタ及び前記第２のトランジスタを有する複数の集積回路を形成し、
前記第１の基板を分断することで、前記複数の集積回路のうちの一の集積回路が形成された第２の基板を形成し、
前記第２の基板を、半導体素子または表示素子が形成された第３の基板に貼り合わせ、前記一の集積回路と前記半導体素子または表示素子とを電気的に接続することを特徴とする半導体装置の作製方法。 In any one of Claims 8 to 13,
A first substrate, forming a plurality of integrated circuits having the first and second transistors,
The first by cutting the substrate, forming a second substrate in which one of the integrated circuits of the plurality of integrated circuits have been formed,
The second substrate is bonded to a third substrate on which a semiconductor element or a display element is formed, and the one integrated circuit and the semiconductor element or the display element are electrically connected to each other. Manufacturing method.