JP2005005312A - Method and structure for packaging semiconductor chip and semiconductor chip - Google Patents

Method and structure for packaging semiconductor chip and semiconductor chip Download PDF

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Publication number
JP2005005312A
JP2005005312A JP2003163977A JP2003163977A JP2005005312A JP 2005005312 A JP2005005312 A JP 2005005312A JP 2003163977 A JP2003163977 A JP 2003163977A JP 2003163977 A JP2003163977 A JP 2003163977A JP 2005005312 A JP2005005312 A JP 2005005312A
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Japan
Prior art keywords
semiconductor chip
substrate
resin layer
synthetic resin
rod
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Pending
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JP2003163977A
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Japanese (ja)
Inventor
Yasuo Yamazaki
康男 山▲崎▼
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2003163977A priority Critical patent/JP2005005312A/en
Publication of JP2005005312A publication Critical patent/JP2005005312A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of connecting a semiconductor chip and a substrate stably while eliminating a sealing step. <P>SOLUTION: On the connecting surface of a semiconductor chip 1 and a substrate 5, a synthetic resin layer 20 is formed while including a rod-like electrode 4 extending vertically from the connecting surface. While a planar electrode 6 formed on the substrate 5 is facing the rod-like electrode 4 of the synthetic resin layer 20, a pressing force is imparted between the substrate 5 and the semiconductor chip 1. Consequently, the synthetic resin layer 20 is deformed and the rod-like electrode 4 is thrust into the planar electrode 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、半導体チップの実装方法に関する。
【0002】
【従来の技術】
従来より、半導体チップを基板上に取り付けて電気的に接続する(実装する)方法として、「バンプ」と称される突起状電極を用いた方法が行われている。この方法では、例えば、半導体チップ上の電極(ボンディングパッド)にバンプを形成し、このバンプと基板側の電極とが対向するように、基板上に半導体チップを配置した後、バンプを熱圧着している。これにより、バンプが基板側の電極に接着固定されて、半導体チップと基板が電気的に接続される。
【0003】
そして、この接続工程の後に、前記半導体チップと基板との間に、両者間の側部から液状樹脂を流し入れて硬化させること等により、前記樹脂の硬化物(絶縁材料)で両者間を封止する工程が行われている。
このようなバンプを用いた接続工程と封止工程とからなる実装方法では、バンプの高さが不均一に形成されたり、バンプの熱圧着時に半導体チップと基板との熱膨張差に伴って位置ずれが生じたりすることで、良好な接続がなされない場合がある。また、接続工程の後に上述の封止工程を行うことは煩雑であり、しかも上述の方法で完全な封止を行うことは困難である。
【0004】
下記の特許文献1には、基板側の電極上にピンを形成し、このピンを半導体チップに設けられたバンプに突き刺すことで、半導体チップを基板に実装することが記載されている。この実装方法は、バンプの高さが不均一に形成されたり、バンプの熱圧着時に半導体チップと基板との熱膨張差に伴って位置ずれが生じたりすることを防止することを目的としたものである。
【0005】
【特許文献1】
特開平6−188289号公報
【0006】
【発明が解決しようとする課題】
しかしながら、上記特許文献1に記載の方法では、ピンの先端部分のみをバンプに突き刺しているため、例えばピンの挿入部分のバンプを熱で変形させたりはしているが、安定的な電気的接続を得ることが困難である。また、ピンが露出した状態となっているため、別工程による封止を行わないと接続の信頼性が不十分となる。
【0007】
本発明は、従来技術の未解決な課題を解決するためになされたものであり、特許文献1に記載の方法よりも安定的に半導体チップと基板との接続が行われ、しかも接続工程の後の封止工程を省略できるようにすることを目的とする。
【0008】
【課題を解決するための手段】
上記課題を解決するために、本発明は、半導体チップの基板との接続面に、この接続面から垂直に延びる棒状電極を含有する合成樹脂層を形成し、基板に形成された板状電極と前記合成樹脂層の棒状電極を対向させた状態で前記基板と半導体チップとの間に押圧力を付与し、前記合成樹脂層を変形させながら前記棒状電極を前記板状電極に突き刺すことにより、前記半導体チップと基板とを接続することを特徴とする半導体チップの実装方法を提供する。
【0009】
本発明の実装方法によれば、半導体チップの基板との接続面に、この接続面から垂直に延びる棒状電極を含有する合成樹脂層が形成され、基板に形成された板状電極に前記棒状電極が突き刺さり、この棒状電極が形成されている部分の合成樹脂層が変形し、この合成樹脂層により半導体チップと基板との間が塞がれた状態で、前記半導体チップと基板とが接続されている半導体チップの実装構造が得られる。
【0010】
すなわち、本発明の実装方法によれば、合成樹脂層内の棒状電極を板状電極に突き刺すことにより半導体チップと基板が接続され、この合成樹脂層により半導体チップと基板との間を塞ぐことができるため、特許文献1に記載の方法よりも安定的に半導体チップと基板との接続が行われ、接続工程後の封止工程も省略することができるようになる。
【0011】
本発明の実装方法において、前記板状電極は金からなり、前記棒状電極はニッケル−リン化合物からなると、ニッケル−リン化合物は金より硬い(ビッカース硬度(Hv)が一桁程度大きい)ため、棒状電極を板状電極に容易に突き刺すことができる。
本発明の実装方法においては、前記棒状電極を含有する合成樹脂層の形成を、半導体チップの基板との接続用の各電極面に棒状電極用の穴を複数個有するように合成樹脂層を形成した後、前記穴に無電解ニッケルメッキ法でニッケル−リン化合物を析出させることにより行うことが好ましい。
【0012】
本発明はまた、本発明の実装方法に使用する半導体チップとして、素子形成面(基板との接続面)に合成樹脂層が形成され、この合成樹脂層内に前記面から垂直に延びる棒状電極を有することを特徴とする半導体チップを提供する。
【0013】
【発明の実施の形態】
図1および図2を用いて、本発明の一例(一実施形態)に相当する半導体チップの実装方法について説明する。
図1は、この実施形態で用いる半導体チップの作製方法を説明する断面図である。図2は、この半導体チップの実装方法を説明する断面図である。
【0014】
先ず、図1(a)に示すように、半導体チップ1の素子形成面に紫外線硬化型樹脂組成物からなる層(未硬化の合成樹脂層)2を形成した。次に、この樹脂組成物層2に対して、所定パターンの紫外線遮蔽部31を有するマスク3を介して紫外線を照射した。
なお、この例では、図1(d)に示すように、半導体チップ1の正方形の各電極11面に、断面が正方形の棒状電極4を3行3列の行列状に配置する。そのため、この棒状電極4と同じパターンで紫外線遮蔽部31が形成されたマスク3を使用した。
【0015】
これにより、樹脂組成物層2の紫外線遮蔽部31の真下の部分は硬化されず、それ以外の部分は硬化されて合成樹脂層20となる。その結果、図1(b)に示すように、半導体チップ1の各電極11上に、棒状電極用の穴21を複数個有する状態の合成樹脂層20が形成された。
次に、この状態で、リンを10質量%程度含有する無電解ニッケルメッキ液に浸漬することにより、合成樹脂層20の各穴21にニッケル−リン化合物を析出させた。これにより、図1(c)に示すように、半導体チップ1の各電極11から垂直に延びる棒状電極4が合成樹脂層20内に形成された。この棒状電極4の硬さはHv800程度であった。
【0016】
次に、この半導体チップ1を、図2(a)に示すように、合成樹脂層20を下側にして基板5上に載せ、基板5に形成された板状電極6と合成樹脂層20の棒状電極4を対向させた。ここで、板状電極6は金からなり、基板5は所定のステージ上に固定されている。この状態で半導体チップ1の上から荷重を付加することにより、基板5と半導体チップ1との間に押圧力を付与した。
【0017】
その結果、図2(b)に示すように、合成樹脂層20が変形して、棒状電極4が板状電極6に突き刺さった状態となった。そして、棒状電極4が形成されている部分の合成樹脂層20が変形し、この合成樹脂層20により半導体チップ1と基板5との間が塞がれた状態となった。
したがって、この実施形態の実装方法によれば、特許文献1に記載の方法よりも安定的に半導体チップと基板との接続が行われ、接続工程後の封止工程も省略することができる。また、板状電極6が金からなり、棒状電極4が金よりビッカース硬度(Hv)が一桁程度大きいニッケル−リン化合物からなるため、小さな荷重で板状電極6を破壊することなく、棒状電極4を板状電極6に容易に突き刺すことができる。
【図面の簡単な説明】
【図1】半導体チップの作製方法を説明する断面図。
【図2】半導体チップの実装方法を説明する断面図。
【符号の説明】
1…半導体チップ、11…半導体チップの電極、20…合成樹脂層、21…棒状電極用の穴、3…マスク、31…紫外線遮蔽部、4…棒状電極、5…基板、6…板状電極(基板側の電極)。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip mounting method.
[0002]
[Prior art]
Conventionally, as a method for attaching and electrically connecting (mounting) a semiconductor chip on a substrate, a method using protruding electrodes called “bumps” has been performed. In this method, for example, a bump is formed on an electrode (bonding pad) on a semiconductor chip, and after placing the semiconductor chip on the substrate so that the bump and the electrode on the substrate face each other, the bump is thermocompression bonded. ing. Thereby, the bump is bonded and fixed to the electrode on the substrate side, and the semiconductor chip and the substrate are electrically connected.
[0003]
Then, after this connection step, between the semiconductor chip and the substrate, a liquid resin is poured from the side portion between the two and cured to seal the two with a cured product (insulating material) of the resin. The process to do is performed.
In the mounting method consisting of a connection process and a sealing process using such bumps, the bump height is unevenly formed, or the bump is thermocompression-bonded and positioned with the difference in thermal expansion between the semiconductor chip and the substrate. There may be a case where a good connection is not made due to a shift. Further, it is complicated to perform the above-described sealing step after the connecting step, and it is difficult to perform complete sealing by the above-described method.
[0004]
Patent Document 1 below describes mounting a semiconductor chip on a substrate by forming a pin on an electrode on the substrate side and piercing this pin into a bump provided on the semiconductor chip. The purpose of this mounting method is to prevent bumps from being formed unevenly or from being displaced due to thermal expansion differences between the semiconductor chip and the substrate during the thermocompression bonding of the bumps. It is.
[0005]
[Patent Document 1]
JP-A-6-188289 [0006]
[Problems to be solved by the invention]
However, in the method described in Patent Document 1, since only the tip portion of the pin is pierced into the bump, for example, the bump at the insertion portion of the pin is deformed by heat, but stable electrical connection is possible. Is difficult to get. In addition, since the pins are exposed, the connection reliability becomes insufficient unless sealing is performed in a separate process.
[0007]
The present invention has been made to solve the unsolved problems of the prior art, and the semiconductor chip and the substrate can be connected more stably than the method described in Patent Document 1, and after the connection step. It is an object of the present invention to be able to omit the sealing step.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a plate-like electrode formed on a substrate by forming a synthetic resin layer containing a rod-like electrode extending perpendicularly from the connection surface on a connection surface of the semiconductor chip with the substrate. By applying a pressing force between the substrate and the semiconductor chip with the rod-shaped electrodes of the synthetic resin layer facing each other, the rod-shaped electrode is pierced into the plate electrode while deforming the synthetic resin layer, Provided is a semiconductor chip mounting method comprising connecting a semiconductor chip and a substrate.
[0009]
According to the mounting method of the present invention, the synthetic resin layer containing the rod-shaped electrode extending perpendicularly from the connection surface is formed on the connection surface of the semiconductor chip with the substrate, and the rod-shaped electrode is formed on the plate-shaped electrode formed on the substrate. The synthetic resin layer of the portion where the rod-shaped electrode is formed is deformed, and the semiconductor chip and the substrate are connected in a state where the gap between the semiconductor chip and the substrate is blocked by the synthetic resin layer. A semiconductor chip mounting structure can be obtained.
[0010]
That is, according to the mounting method of the present invention, the semiconductor chip and the substrate are connected by piercing the rod-like electrode in the synthetic resin layer into the plate-like electrode, and the gap between the semiconductor chip and the substrate can be blocked by this synthetic resin layer. Therefore, the semiconductor chip and the substrate can be connected more stably than the method described in Patent Document 1, and the sealing step after the connecting step can be omitted.
[0011]
In the mounting method of the present invention, if the plate electrode is made of gold and the rod-like electrode is made of a nickel-phosphorus compound, the nickel-phosphorus compound is harder than gold (Vickers hardness (Hv) is about one digit larger). The electrode can be easily pierced into the plate electrode.
In the mounting method of the present invention, the synthetic resin layer containing the rod-shaped electrode is formed by forming a synthetic resin layer so as to have a plurality of holes for the rod-shaped electrode on each electrode surface for connection to the substrate of the semiconductor chip. After that, it is preferable to deposit a nickel-phosphorus compound in the hole by electroless nickel plating.
[0012]
According to the present invention, a synthetic resin layer is formed on an element forming surface (surface connected to a substrate) as a semiconductor chip used in the mounting method of the present invention, and a rod-like electrode extending vertically from the surface is formed in the synthetic resin layer. A semiconductor chip is provided.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor chip mounting method corresponding to an example (one embodiment) of the present invention will be described with reference to FIGS.
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor chip used in this embodiment. FIG. 2 is a cross-sectional view for explaining the semiconductor chip mounting method.
[0014]
First, as shown in FIG. 1A, a layer (uncured synthetic resin layer) 2 made of an ultraviolet curable resin composition was formed on the element forming surface of the semiconductor chip 1. Next, the resin composition layer 2 was irradiated with ultraviolet rays through a mask 3 having an ultraviolet shielding part 31 having a predetermined pattern.
In this example, as shown in FIG. 1D, the rod-like electrodes 4 having a square cross section are arranged in a matrix of 3 rows and 3 columns on each square electrode 11 surface of the semiconductor chip 1. Therefore, the mask 3 in which the ultraviolet shielding part 31 was formed in the same pattern as the rod-like electrode 4 was used.
[0015]
Thereby, the part directly under the ultraviolet shielding part 31 of the resin composition layer 2 is not cured, and the other part is cured to become the synthetic resin layer 20. As a result, as shown in FIG. 1B, a synthetic resin layer 20 having a plurality of rod-shaped electrode holes 21 was formed on each electrode 11 of the semiconductor chip 1.
Next, in this state, a nickel-phosphorus compound was deposited in each hole 21 of the synthetic resin layer 20 by dipping in an electroless nickel plating solution containing about 10% by mass of phosphorus. As a result, as shown in FIG. 1C, rod-like electrodes 4 extending vertically from the respective electrodes 11 of the semiconductor chip 1 were formed in the synthetic resin layer 20. The bar electrode 4 had a hardness of about Hv800.
[0016]
Next, as shown in FIG. 2A, the semiconductor chip 1 is placed on the substrate 5 with the synthetic resin layer 20 facing down, and the plate-like electrode 6 and the synthetic resin layer 20 formed on the substrate 5 are placed. The rod-shaped electrode 4 was made to oppose. Here, the plate electrode 6 is made of gold, and the substrate 5 is fixed on a predetermined stage. A pressing force was applied between the substrate 5 and the semiconductor chip 1 by applying a load from above the semiconductor chip 1 in this state.
[0017]
As a result, as shown in FIG. 2B, the synthetic resin layer 20 was deformed and the rod-like electrode 4 was stuck into the plate-like electrode 6. And the synthetic resin layer 20 of the part in which the rod-shaped electrode 4 is formed deform | transformed, and the state between the semiconductor chip 1 and the board | substrate 5 was obstruct | occluded by this synthetic resin layer 20. FIG.
Therefore, according to the mounting method of this embodiment, the semiconductor chip and the substrate can be connected more stably than the method described in Patent Document 1, and the sealing step after the connecting step can be omitted. Further, since the plate-like electrode 6 is made of gold and the rod-like electrode 4 is made of a nickel-phosphorus compound whose Vickers hardness (Hv) is about an order of magnitude higher than that of gold, the rod-like electrode is not destroyed by a small load. 4 can be easily inserted into the plate electrode 6.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor chip.
FIG. 2 is a cross-sectional view illustrating a semiconductor chip mounting method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 11 ... Semiconductor chip electrode, 20 ... Synthetic resin layer, 21 ... Hole for rod-shaped electrode, 3 ... Mask, 31 ... Ultraviolet shielding part, 4 ... Rod-shaped electrode, 5 ... Substrate, 6 ... Plate-shaped electrode (Electrode on substrate side).

Claims (5)

半導体チップの基板との接続面に、この接続面から垂直に延びる棒状電極を含有する合成樹脂層を形成し、
基板に形成された板状電極と前記合成樹脂層の棒状電極を対向させた状態で前記基板と半導体チップとの間に押圧力を付与し、前記合成樹脂層を変形させながら前記棒状電極を前記板状電極に突き刺すことにより、前記半導体チップと基板とを接続することを特徴とする半導体チップの実装方法。
On the connection surface with the substrate of the semiconductor chip, a synthetic resin layer containing a rod-shaped electrode extending perpendicularly from the connection surface is formed,
A pressing force is applied between the substrate and the semiconductor chip in a state where the plate-shaped electrode formed on the substrate and the rod-shaped electrode of the synthetic resin layer are opposed to each other, and the rod-shaped electrode is moved while the synthetic resin layer is deformed. A semiconductor chip mounting method comprising connecting the semiconductor chip and a substrate by piercing a plate-like electrode.
前記板状電極は金からなり、前記棒状電極はニッケル−リン化合物からなる請求項1記載の半導体チップの実装方法。2. The method of mounting a semiconductor chip according to claim 1, wherein the plate electrode is made of gold and the rod electrode is made of a nickel-phosphorus compound. 前記棒状電極を含有する合成樹脂層の形成は、半導体チップの基板との接続用の各電極面に棒状電極用の穴を複数個有するように合成樹脂層を形成した後、前記穴に無電解ニッケルメッキ法でニッケル−リン化合物を析出させることにより行う請求項2記載の半導体チップの実装方法。The synthetic resin layer containing the rod-shaped electrode is formed by forming a synthetic resin layer so as to have a plurality of rod-shaped electrode holes on each electrode surface for connection to the substrate of the semiconductor chip, and then electrolessly forming the holes. 3. The semiconductor chip mounting method according to claim 2, wherein the nickel-phosphorus compound is deposited by a nickel plating method. 半導体チップの基板との接続面に、この接続面から垂直に延びる棒状電極を含有する合成樹脂層が形成され、
基板に形成された板状電極に前記棒状電極が突き刺さり、この棒状電極が形成されている部分の合成樹脂層が変形し、この合成樹脂層により半導体チップと基板との間が塞がれた状態で、前記半導体チップと基板とが接続されていることを特徴とする半導体チップの実装構造。
A synthetic resin layer containing a rod-shaped electrode extending perpendicularly from the connection surface is formed on the connection surface with the substrate of the semiconductor chip,
A state in which the rod-shaped electrode is pierced into the plate-shaped electrode formed on the substrate, the synthetic resin layer in the portion where the rod-shaped electrode is formed is deformed, and the gap between the semiconductor chip and the substrate is blocked by the synthetic resin layer A mounting structure of a semiconductor chip, wherein the semiconductor chip and the substrate are connected.
素子形成面に合成樹脂層が形成され、この合成樹脂層内に前記面から垂直に延びる棒状電極を有することを特徴とする半導体チップ。A semiconductor chip, wherein a synthetic resin layer is formed on an element forming surface, and a bar-shaped electrode extending perpendicularly from the surface is provided in the synthetic resin layer.
JP2003163977A 2003-06-09 2003-06-09 Method and structure for packaging semiconductor chip and semiconductor chip Pending JP2005005312A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013098408A (en) * 2011-11-02 2013-05-20 Lintec Corp Dicing sheet and manufacturing method of semiconductor chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013098408A (en) * 2011-11-02 2013-05-20 Lintec Corp Dicing sheet and manufacturing method of semiconductor chip
US9312162B2 (en) 2011-11-02 2016-04-12 Lintec Corporation Dicing sheet and a production method of a semiconductor chip

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