JP2004343055A - Pattern and member for evaluation of fine connection resistance, manufacturing method thereof, and evaluating method using same, and multilayered board - Google Patents
Pattern and member for evaluation of fine connection resistance, manufacturing method thereof, and evaluating method using same, and multilayered board Download PDFInfo
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本発明は、接続基板を用いた多層配線板の製造において、接続抵抗の信頼性を評価する評価方法に関する。 The present invention relates to an evaluation method for evaluating the reliability of connection resistance in manufacturing a multilayer wiring board using a connection substrate.
近年、我々を取り巻く社会環境は、情報通信網の進展と共に大きく変化している。その中に、携帯機器の成長があり、小型・高機能化と共にその市場は拡大している。このため、半導体パッケージの更なる小型化と、それらを高密度に実装できる多層配線基板が要求され、高密度配線が可能な層間接続、すなわち高密度多層化技術が重要となっている。 In recent years, the social environment surrounding us has changed drastically with the development of information and communication networks. Among them, there is the growth of portable devices, and the market is expanding along with miniaturization and high functionality. For this reason, further miniaturization of semiconductor packages and a multilayer wiring board capable of mounting them at high density are required, and an interlayer connection capable of high-density wiring, that is, a high-density multilayer technology is important.
主な多層化方法としては、ドリル穴明けとめっきプロセスを組み合わせたスルーホール接続があり、広く一般に知られているが、全ての層にわたって穴があくので、配線収容量に限界がある。 As a main multilayering method, there is a through-hole connection combining a drilling and a plating process, which is widely and generally known. However, since holes are formed in all layers, there is a limit in the wiring capacity.
そこで、接続部の穴体積を減らすため、絶縁樹脂組成物層の形成−穴あけ−回路形成を繰り返すビルドアップ技術が主流となりつつある。このビルドアップ技術は、大別して、レーザ法とフォトリソ法があり、レーザ法は、絶縁樹脂組成物層に穴をあけるのにレーザ照射を行うものであり、一方、フォトリソ法は、絶縁樹脂組成物層に感光性の硬化剤(光開始剤)を用い、フォトマスクを重ねて、露光・現像して穴を形成する。 Therefore, in order to reduce the volume of the hole in the connection portion, a build-up technique in which formation of an insulating resin composition layer, drilling, and circuit formation are repeated is becoming mainstream. This build-up technology is roughly classified into a laser method and a photolithography method.The laser method is a method in which laser irradiation is performed to make a hole in the insulating resin composition layer, while the photolithography method uses an insulating resin composition. Using a photosensitive hardener (photoinitiator) for the layer, a photomask is overlaid, and exposure and development are performed to form holes.
一方、ますます進展する情報・電子機器の小型・高機能化に対応し、半導体パッケージでは、高密度実装技術の開発が加速されている。このため、多層基板のみならず、半導体実装用基板にも、薄型化とともに高密度配線形成技術が要求されている。その一つに、直上ビア構造形成の要求がある。これは、フリップチップ実装に対応した配線設計の自由度を改善したり、ビルドアップ層へのワイヤボンディング性を向上するなどを目的としている。(非特許文献1参照)
これらの要求から、新規な基板製造方法として、一括積層技術が注目されている。一括積層技術は、絶縁樹脂層上には配線層が形成され、絶縁樹脂層内には導電接続部が形成された部材を準備し、それら部材を位置合わせして、熱プレスにより一括で成型加工と同時に層間を導通接続するものである。この技術により、直上ビア構造形成の実現だけでなく、コアレスによる薄型化が図れると考えられる。製造面では、大幅な納期短縮も期待できる。このため、各社から、一括積層技術が発表されている。(非特許文献2〜10参照)
主だった工法を見ると、絶縁樹脂には、熱硬化系樹脂または熱可塑系樹脂が用いられ、導電接続部には導電ペーストもしくは、めっき銅にはんだをめっきしたものが用いられている。配線層は、あらかじめ絶縁層に設けた金属層からエッチングで形成するもの、導電部上に配線を転写する方法が開発されている。従来の技術では、絶縁樹脂にあらかじめ微細な接続用導体をなんらかの方法で埋設しておく必要がある。そして、実際に多層化して双方向の接続信頼性を評価することが重要になる。
From these demands, a batch laminating technique has attracted attention as a novel substrate manufacturing method. In the batch lamination technology, a wiring layer is formed on an insulating resin layer, and a member having a conductive connection portion formed in the insulating resin layer is prepared, and the members are aligned and molded at a time by hot pressing. At the same time, the layers are electrically connected. It is considered that this technique can realize not only the formation of the via structure directly above but also the coreless thinning. In terms of manufacturing, it can be expected that delivery times will be significantly reduced. For this reason, the collective lamination technology has been announced by each company. (See Non-Patent
Looking at the main methods, a thermosetting resin or a thermoplastic resin is used for the insulating resin, and a conductive paste or plated copper is used for the conductive connection part. The wiring layer is formed by etching a metal layer provided in advance on an insulating layer, and a method of transferring a wiring on a conductive portion has been developed. In the conventional technology, it is necessary to previously bury a fine connection conductor in an insulating resin by some method. It is important to evaluate the bidirectional connection reliability by actually multi-layering.
従来の技術では、実際に多層化して層方向の接続信頼性を評価する必要がある。接続の経路を断面で見ると、図1に示すように、配線(〜11)間を絶縁樹脂(〜12)に埋設された接続用導体(〜13)で直上に接続したり、クランク形状で接続させたり、その断面パターンは、(〜14)で示す直上部と(〜15)で示すクランク形状部の接続形態の2種類に大別される。また、この2種類の接続部において、これらを構成する配線材料、接続用導体、絶縁材料、厚さやプロセス条件は多種・多様であり、このような、経路に存在する接続部の信頼性を評価する場合、例えばわずかの条件変更に対してわざわざ全工程を得て基板を試作していたのでは、開発時間が非常にかかる。また、すでに開発し市場に出した基板でも、コストの低減やさらなる微細化に対応した検討を要求されると開発時間が指数関数的に増大するという課題があった。 In the conventional technology, it is necessary to evaluate the connection reliability in the layer direction by actually forming a multilayer structure. Looking at the cross section of the connection path, as shown in FIG. 1, the wiring (〜11) is connected directly above with a connection conductor (〜13) embedded in an insulating resin (〜12), or is formed in a crank shape. The connection and the cross-sectional pattern are roughly classified into two types, that is, a connection form of an upper portion shown by ((14) and a crank-shaped portion shown by (〜15). In addition, the wiring materials, connecting conductors, insulating materials, thicknesses and process conditions that make up these two types of connection parts are diverse and varied, and the reliability of such connection parts existing in the path is evaluated. In such a case, for example, if a trial production of a substrate is performed by taking all steps for a slight change in conditions, development time is extremely long. Further, even with a substrate already developed and put on the market, there has been a problem that the development time increases exponentially if a study for cost reduction and further miniaturization is required.
本発明は、従来の接続基板における高多層化に必要な全工程を省略し、特にラフな位置精度でも、微細接続部や多層化プレスが可能な方法を提供するものである。 The present invention omits all the steps required for increasing the number of layers in a conventional connection board, and provides a method capable of performing a fine connection portion and a multi-layer press even with particularly rough positional accuracy.
(1)本発明は、絶縁樹脂と接続用導体からなる一対の部材であって、絶縁樹脂層が熱硬化樹脂およびまたは、熱可塑樹脂からなる微細接続抵抗評価用部材に関する。 (1) The present invention relates to a member for evaluating fine connection resistance, which is a pair of members made of an insulating resin and a connecting conductor, wherein the insulating resin layer is made of a thermosetting resin and / or a thermoplastic resin.
(2)また、本発明は、(1)に記載の一対からなる部材のうち、該部材の上側と該部材の下側の接続用導体のパターンが透視してみたときにラフな位置精度でも、線路長が変化しない微細接続抵抗評価用配線パターンに関する。 (2) In the present invention, among the pair of members described in (1), when the pattern of the connection conductor on the upper side of the member and the lower side of the member is seen through, even if the positional accuracy is rough. And a wiring pattern for evaluating fine connection resistance in which the line length does not change.
(3)また、本発明は、(2)のパターンを用いて、(1)の部材を製造する方法に関する。 (3) The present invention also relates to a method of manufacturing the member of (1) using the pattern of (2).
(4)また、本発明は、(3)で製造した部材を用いて、各種金属間の溶融または、固相金属拡散による接続抵抗および信頼性を評価する評価方法に関する。 (4) The present invention also relates to an evaluation method for evaluating connection resistance and reliability by melting between various metals or solid-phase metal diffusion using the member manufactured in (3).
(5)上記(4)の評価方法により接続信頼性を確認した接合めっきを用いて製造した多層板に関する。 (5) The present invention relates to a multilayer board manufactured using bonding plating whose connection reliability has been confirmed by the evaluation method of (4).
(6)接合めっきは、無電解ニッケル/金めっき、無電解ニッケル/パラジウム/金めっき、無電解ダイレクト金めっき、無電解錫めっき、無電解錫めっきにフッ化処理したもの、電解錫コバルト合金めっき、電解錫銀合金めっき、電解錫銅合金めっきからなる群から選択される同種もしくは異種のめっき同士の接合であるか、または、これらめっきとめっきをしない銅との接合である上記(5)に記載の多層板。 (6) Electroless nickel / gold plating, electroless nickel / palladium / gold plating, electroless direct gold plating, electroless tin plating, fluorinated electroless tin plating, electrolytic tin-cobalt alloy plating (5) above, wherein the same or different types of plating selected from the group consisting of electrolytic tin-silver alloy plating and electrolytic tin-copper alloy plating are joined together, or these platings are joined to unplated copper. The multilayer board as described.
本発明によって、接続基板の接続信頼性を開発前、若しくは製品条件で品質保証するために、多種多様な、これらを構成する配線材料、接続用導体、絶縁材料、厚さやプロセス条件で、かつ接続経路に存在する接続部の信頼性を評価する場合、わざわざ全工程をへて基板を試作する時間を大幅に削減でき、しかもラフな位置精度でも、微細接続部の多層化を評価可能とするものである。本発明は、1)プロセスの省略ができる。2)ラフな位置精度での微細接続が評価できる。3)各種接続用めっき種仕様の迅速な探索を可能とする。4)一括積層時の品質保証として使用できる。5)直上ビア構造部およびクランク形状部の接続抵抗および信頼性を容易に評価できる。という優れた効果のあるパターンおよび部材である。 According to the present invention, in order to guarantee the connection reliability of the connection board before development or under product conditions, a wide variety of wiring materials, connection conductors, insulating materials, thicknesses and process conditions, which constitute these, and connection. When evaluating the reliability of the connection part existing in the path, it is possible to drastically reduce the time required to prototype the board through all the steps, and to evaluate the multilayering of the fine connection part even with rough positional accuracy It is. In the present invention, 1) the process can be omitted. 2) Fine connection with rough positional accuracy can be evaluated. 3) Enables quick search for various kinds of plating specifications for connection. 4) Can be used as quality assurance during batch lamination. 5) The connection resistance and reliability of the via structure directly above and the crank-shaped portion can be easily evaluated. This is a pattern and a member having an excellent effect.
本発明の実施の形態は、絶縁樹脂と接続用導体からなる一対の部材であって、絶縁樹脂層が熱硬化樹脂およびまたは、熱可塑樹脂からなる微細接続抵抗評価用部材である。また、一対からなる部材のうち、該部材の上側と該部材の下側の接続用導体のパターンが透視してみたときにラフな位置精度でも、線路長が変化しないことを特徴とする微細接続抵抗評価用パターンを有するものであり、このパターンを有する部材を製造する方法、上記の部材をもちいて接続信頼性を評価する方法。上記部材をもちいた実装用基板が発明の実施の形態である。 The embodiment of the present invention is a member for evaluating fine connection resistance in which a pair of members made of an insulating resin and a connection conductor is used, and the insulating resin layer is made of a thermosetting resin and / or a thermoplastic resin. Further, among the pair of members, the line length does not change even with rough positional accuracy when the pattern of the connection conductor on the upper side of the member and the lower side of the member is seen through. A method for manufacturing a member having a pattern for resistance evaluation, and a method for evaluating connection reliability using the above member. A mounting board using the above-described member is an embodiment of the present invention.
また、本発明の実施の形態で用いられる微細接続抵抗評価用部材の基本構造、パターン、製造方法、評価方法、実装用基板の製造法を実施例に従って説明するが、本発明は、これらに限定されるわけではない。 Further, the basic structure, pattern, manufacturing method, evaluation method, and manufacturing method of the mounting substrate used in the member for evaluating fine connection resistance used in the embodiment of the present invention will be described according to Examples, but the present invention is not limited thereto. It is not done.
(実施例1)
図2(a)に示すように、第1の金属層(〜21)が厚さ70μmの銅であり、第3の金属層(〜23)が厚さ0.2μmのニッケルであり、第2の金属層(〜22)が厚さ25μmの銅からなる複合金属層(〜24)を一対準備した。それぞれの両面に、配線形成用レジストをラミネートし、図2(b)に示すように、上側および下側の複合金属層(〜24)の表面と裏面に、エッチングレジスト(〜25)を形成した。この時のエッチングレジスト(〜25)には、レジストNIT225(日本合成化学工業株式会社製、商品名)を用い、ロール温度110℃、ロール速度は0.6m/minの条件でレジストをラミネートし、積算露光量約80mJ/cm2の露光条件で上側および下側の複合金属箔(〜24)の第1の金属層(〜21)側は全面露光し、上側および下側の複合金属層(〜24)の第2の金属層(〜22)側は、埋設導体の形状を含むマスクパターンを焼き付け、炭酸ナトリウム溶液で両面を現像し、レジストの密着を確実なものとするために200mJ/cm2で後露光した。
(Example 1)
As shown in FIG. 2A, the first metal layer (.about.21) is copper having a thickness of 70 .mu.m, the third metal layer (.about.23) is nickel having a thickness of 0.2 .mu.m, and the second metal layer (.about.23) is nickel. A pair of composite metal layers (.about.24) having a thickness of 25 .mu.m made of copper was prepared. A wiring forming resist was laminated on each of both surfaces, and as shown in FIG. 2B, an etching resist (.about.25) was formed on the front and back surfaces of the upper and lower composite metal layers (.about.24). . At this time, a resist NIT 225 (trade name, manufactured by Nippon Synthetic Chemical Industry Co., Ltd.) was used for the etching resist (2525), and the resist was laminated at a roll temperature of 110 ° C. and a roll speed of 0.6 m / min. Under an exposure condition of an integrated exposure amount of about 80 mJ / cm 2 , the first metal layer (金属 21) side of the upper and lower composite metal foils (〜24) is entirely exposed, and the upper and lower composite metal layers (〜24) are exposed. the second metal layer (~ 22) side of 24), embedded in baking a mask pattern including a conductor shape, developed on both sides with sodium carbonate solution, 200 mJ / cm 2 to the adhesion of the resist made reliable Was post-exposed.
埋設導体の形状は、図2(c)に示すように、上側と下側により焼付けイメージが異なる。上側パターン(〜26)は、後述する測定用端子部(〜28)を有する。下側パターン(〜27)は、上側パターンと直交するように設計されている。この上下の焼付けイメージを透視したとき、交差する部分の面積が配線幅で変化させられることがわかる。また、このように上側と下側でラフに位置合わせしても、大きな回転がない限り、交差する面積も接続配線長さも変化しない。この様なパターンでは、埋設したときに、孤立パターンとなり、無電解めっきしか出来なくなるので、図面では省略するが、各孤立パターンから電気めっきリード線を引き出すこともできる。 As shown in FIG. 2 (c), the shape of the buried conductor has a different burning image between the upper side and the lower side. The upper pattern (〜26) has a measurement terminal portion (〜28) described later. The lower pattern (.about.27) is designed to be orthogonal to the upper pattern. When seeing through the upper and lower printed images, it can be seen that the area of the intersecting portion can be changed by the wiring width. Even if the upper and lower positions are roughly aligned as described above, neither the crossing area nor the connection wiring length changes unless there is a large rotation. In such a pattern, when buried, it becomes an isolated pattern and only electroless plating can be performed. Therefore, although omitted in the drawing, an electroplating lead wire can be drawn from each isolated pattern.
次に、埋設導体の形状を含むマスクパターンが形成された複合金属箔の作製手順を述べる。まず、ニッケルを浸食しないエッチング液であるアルカリエッチングAプロセス液(メルストリップ社製、商品名)をスプレー噴霧して、第2の金属層(〜22)を選択的にエッチング除去して、埋設導体形状を形成した。この後、水酸化ナトリウム溶液でエッチングレジスト(〜25)を剥離・除去した。次に、ニッケルのエッチング液であるメルストリップN950(メルテックス社製、商品名)を用いて、第3の金属層(〜23)をエッチング除去し、表面処理液CPE900(三菱ガス化学社製、商品名)をスプレー噴霧して、露出した銅表面の粗化処理を行った。これにより、図2(d)に示すように、埋設導体の形状を含むマスクパターンが形成された一対の複合金属箔(〜29)が得られた。また、上記ニッケルエッチングやニッケルエッチング後の粗化処理をしない場合でも、レジストラミネート前に一般に行う酸処理で第2の金属層(〜22)の表面は粗化されているので、絶縁樹脂との密着強度は低下するものの、同様に埋設導体が形成された複合箔が得られる。今回は、前者の方法で作製した複合金属箔(〜29)に対して、絶縁樹脂組成物層を形成した。この複合金属箔(〜29)の埋設導体の形状を含むパターンが形成された側に、絶縁樹脂組成物層(〜12)として液晶ポリマーBIAC(ジャパンゴアテックス社製、商品名)を50μm厚さのものを各面に載置した。さらに、それぞれの両面に、離型用として、ポリイミドフィルム(宇部興産製、商品名)を絶縁樹脂組成物層を覆うようにして載置して、少なくともこれら構成を含む様にして、その両側から加熱・加圧プレスを行った。4MPaの圧力を加えて、330℃の温度で5分加熱および加圧した。この後、離型用フィルムを手で剥離し、図2(e)に示す構造体を得た。 Next, a procedure for manufacturing a composite metal foil on which a mask pattern including the shape of a buried conductor is formed will be described. First, an alkali etching A process solution (trade name, manufactured by Merstrip), which is an etchant that does not corrode nickel, is spray-sprayed to selectively etch away the second metal layer (層 22) to remove the buried conductor. Shape was formed. Thereafter, the etching resist ((25) was peeled off and removed with a sodium hydroxide solution. Next, the third metal layer (〜23) was removed by etching using Melstrip N950 (trade name, manufactured by Meltex Co., Ltd.) which is a nickel etching solution, and the surface treatment solution CPE900 (manufactured by Mitsubishi Gas Chemical Co., Ltd .; (Trade name) was sprayed to roughen the exposed copper surface. As a result, as shown in FIG. 2D, a pair of composite metal foils (〜29) on which a mask pattern including the shape of the buried conductor was formed was obtained. Even when the nickel etching and the roughening treatment after the nickel etching are not performed, the surface of the second metal layer (up to 22) is roughened by the acid treatment generally performed before the resist lamination. Although the adhesion strength is reduced, a composite foil on which a buried conductor is similarly formed can be obtained. This time, an insulating resin composition layer was formed on the composite metal foil (-29) produced by the former method. On the side of the composite metal foil (~ 29) on which the pattern including the shape of the buried conductor was formed, a liquid crystal polymer BIAC (manufactured by Japan Gore-Tex Corporation, trade name) having a thickness of 50 µm was formed as an insulating resin composition layer (~ 12). Was placed on each side. Furthermore, a polyimide film (trade name, manufactured by Ube Industries, Ltd.) is placed on both sides of the insulating resin composition layer so as to cover the insulating resin composition layer. A heating / pressing press was performed. A pressure of 4 MPa was applied, and heating and pressurization were performed at a temperature of 330 ° C. for 5 minutes. Thereafter, the release film was peeled by hand to obtain a structure shown in FIG.
このあと、上側と下側の構造体の第1の金属層(〜21)と第3の金属層(〜23)を順次、まず、ニッケルを浸食しないエッチング液であるアルカリエッチングAプロセス液(メルストリップ社製、商品名)をスプレー噴霧して、第1の金属層(〜21)を選択的にエッチング除去して、次に、ニッケルのエッチング液であるメルストリップN950(メルテックス社製、商品名)を用いて、第3の金属層(〜23)をエッチング除去した。これにより、図2(f)に示すように、微細接続抵抗評価用部材を得ることができた。 Thereafter, the first metal layer (.about.21) and the third metal layer (.about.23) of the upper and lower structures are successively successively firstly treated with an alkaline etching A process solution (melting solution) which is an etching solution which does not attack nickel. The first metal layer (.about.21) is selectively etched off by spraying and spraying a strip (trade name, manufactured by Strip Co., Ltd.), and then Melstrip N950 (manufactured by Meltex Co., Ltd.) ), The third metal layer ((23) was removed by etching. As a result, as shown in FIG. 2F, a member for evaluating fine connection resistance could be obtained.
(実施例2)
実施例1の、微細接続抵抗評価用部材の表面に、無電解ニッケル、無電解パラジウム、無電解金めっきの順からなる金属層(〜31)を形成し、図3(a)に示す微細接続抵抗評価用部材を得た。この1対の微細接続抵抗評価用部材を外形で位置合わせし、またはパターン内にガイド穴あけをして、上下を位置合わせしした後、260℃に加熱したはんだ鏝で所定箇所を熱溶融により仮止めした。これらの両面に、離型用として、ポリイミドフィルム(宇部興産製、商品名)を絶縁樹脂組成物層を覆うようにして載置して、少なくともこれら構成を含む様にして、その両側から加熱・加圧プレスを行った。333℃の温度と、4MPaの圧力を、5分間加えて、加熱・加圧して積層一体化し、この後、離型用フィルムを手で剥離し、図3(b)に示す構造体を作製できた。このあと、図3(c)でしめすように四端子抵抗接続端子の箇所(〜28)をハンドドリルで座繰り出した。4端子抵抗測定により、導通接続を確認できた。また、接続基板への表面めっきには、無電解錫めっき(置換タイプ、還元タイプの何れでもよい)を用いた場合でも、同様に導通接続が確認できた。また、表面めっきが異なる一対の微細接続抵抗評価用部材を用いても良く、例えば、上側には、無電解ニッケル、無電解パラジウム、無電解金めっきを行い、下側には、無電解錫めっき(置換タイプ、還元タイプの何れでもよい)を用いることができ、同様に導通接続が確認できた。また、絶縁樹脂として熱硬化系樹脂をもちいてもよく、上側を、たとえばプリプレグGIA-671N(日立化成工業株式会社製、商品名)を用いた場合でも同様に導通接続が確認できた。
(Example 2)
On the surface of the member for evaluating fine connection resistance of Example 1, a metal layer (-31) composed of electroless nickel, electroless palladium, and electroless gold plating was formed in this order, and the fine connection shown in FIG. A member for resistance evaluation was obtained. The pair of fine connection resistance evaluation members are aligned with the outer shape, or a guide hole is formed in the pattern, and the upper and lower positions are aligned. Then, a predetermined location is temporarily melted with a soldering iron heated to 260 ° C. I stopped it. A polyimide film (trade name, manufactured by Ube Industries, Ltd.) is placed on both sides of the insulating resin composition layer so as to cover the insulating resin composition layer. A pressure press was performed. A temperature of 333 ° C. and a pressure of 4 MPa are applied for 5 minutes, and the laminate is integrated by heating and pressurizing. After that, the release film is manually peeled off to produce the structure shown in FIG. 3 (b). Was. Thereafter, as shown in FIG. 3 (c), the locations (.about.28) of the four-terminal resistance connection terminals were unraveled with a hand drill. Conductive connection was confirmed by four-terminal resistance measurement. In addition, even when electroless tin plating (either a substitution type or a reduction type) was used for the surface plating on the connection substrate, a continuity connection was similarly confirmed. Alternatively, a pair of fine connection resistance evaluation members having different surface platings may be used. For example, electroless nickel, electroless palladium, and electroless gold plating are performed on the upper side, and electroless tin plating is performed on the lower side. (Either the substitution type or the reduction type may be used), and the conductive connection was similarly confirmed. Further, a thermosetting resin may be used as the insulating resin, and a conductive connection can be similarly confirmed even when prepreg GIA-671N (trade name, manufactured by Hitachi Chemical Co., Ltd.) is used on the upper side.
(実施例3)
実施例1、2で示したように、上下の微細接続抵抗評価用部材はそれぞれ同じ厚さの絶縁層厚さであるが、図1の(〜15)で示すクランク部では、片側に絶縁層のみであり接続導体が存在しない箇所がある。この部分は、片側の微細接続抵抗評価部材の片側に、接続導体が存在しない箇所の絶縁樹脂層厚さ分を、重ねてプレスすることでシミュレートできる。実施例1、2では直上ビア部のシミュレートであり、そこで、片側に50μm厚さの液晶ポリマーを2枚追加し、プレスした。
(Example 3)
As shown in Examples 1 and 2, the upper and lower fine connection resistance evaluation members each have the same thickness of the insulating layer. However, in the crank portion shown in FIG. There is a portion where only the connection conductor does not exist. This part can be simulated by overlapping and pressing the insulating resin layer thickness at a portion where the connection conductor does not exist on one side of the fine connection resistance evaluation member on one side. In Examples 1 and 2, the via portion was simulated immediately above, and two liquid crystal polymers each having a thickness of 50 μm were added to one side and pressed.
その結果、図4に示すように、直上ビア構造の抵抗値(系列1〜4)、クランク部(クランク1、2)での抵抗値を評価することができた。ちなみに、各構造で、違いは無く、50μm角の接続面積でも、抵抗値は、等価配線抵抗1mm(30μm配線幅で7μm厚の銅配線)と充分に低い接続抵抗であることが分かった。さらに確認のため、実際に製造するパターンで、全プロセスを得て、高精度位置合わせをして接続面積と抵抗の関係を検証したが、直上部もクランク部も同様の結果となり、本部材の有効性が確かめられた。接合部分となる接合めっきは、接合するめっき同士の両方が同じ種類でも、異なる種類であってもよい。また、一方がめっきなしの銅であってもよい。接合するめっき同士の組み合わせとしては、例えば、表1の縦列のめっき種類と横列のめっき種類の組み合わせを挙げることができる。なお、表中、△が付いている組み合わせは、異物またはその他の原因で一途中抵抗上昇がみられたものであるが、非導通になったものではない。また、◎が付いている組み合わせは、−65℃15分放置、150℃15分放置を1サイクルとする熱衝撃試験において1000サイクルをクリアしたものであり、特に優れた熱衝撃性を有するものである。このことから表1に示す組み合わせ全てで良好な接続信頼性を得ることができる。また、図1に示すような多層板を作製しても同様の結果が得られた。
11:配線
12:絶縁層
13:接続用導体
14:直上部
15:クランク形状部
21:第1の金属層
22:第2の金属層
23:第3の金属層
24:複合金属層
25:エッチングレジスト
26:上側パターン
27:下側パターン
28:測定用端子部(上側パターンに含まれる)
29:埋設導体の形状を含むマスクパターンが形成された一対の複合金属箔
31:金属層
11: Wiring 12: Insulating layer 13: Connecting conductor 14: Immediately above 15: Crank-shaped portion 21: First metal layer 22: Second metal layer 23: Third metal layer 24: Composite metal layer 25: Etching Resist 26: Upper pattern 27: Lower pattern 28: Terminal for measurement (included in upper pattern)
29: A pair of composite metal foils 31 on which a mask pattern including the shape of a buried conductor is formed 31: Metal layer
Claims (6)
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WO2011081129A1 (en) * | 2009-12-28 | 2011-07-07 | 株式会社メイコー | Method for manufacturing printed circuit substrate and method for manufacturing probe substrate using the same |
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JPH07240582A (en) * | 1994-02-28 | 1995-09-12 | Hitachi Ltd | Multilayer interconnection board and method and device for manufacturing multilayer interconnection board |
JPH08316641A (en) * | 1995-05-12 | 1996-11-29 | Hitachi Ltd | Multilayer wiring board manufactured by collective connection method |
JPH11204943A (en) * | 1998-01-08 | 1999-07-30 | Hitachi Ltd | Electronic circuit board and manufacture thereof |
JP2000101248A (en) * | 1998-09-24 | 2000-04-07 | Ibiden Co Ltd | Multiple multilayer printed wiring board |
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JPH07240582A (en) * | 1994-02-28 | 1995-09-12 | Hitachi Ltd | Multilayer interconnection board and method and device for manufacturing multilayer interconnection board |
JPH08316641A (en) * | 1995-05-12 | 1996-11-29 | Hitachi Ltd | Multilayer wiring board manufactured by collective connection method |
JPH11204943A (en) * | 1998-01-08 | 1999-07-30 | Hitachi Ltd | Electronic circuit board and manufacture thereof |
JP2000101248A (en) * | 1998-09-24 | 2000-04-07 | Ibiden Co Ltd | Multiple multilayer printed wiring board |
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WO2011081129A1 (en) * | 2009-12-28 | 2011-07-07 | 株式会社メイコー | Method for manufacturing printed circuit substrate and method for manufacturing probe substrate using the same |
JP5582618B2 (en) * | 2009-12-28 | 2014-09-03 | 株式会社メイコー | Manufacturing method of probe substrate |
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