JP2004335629A - Chip-like electronic component and manufacturing method thereof, pseudo wafer used for manufacturing the same, and manufacturing method thereof - Google Patents

Chip-like electronic component and manufacturing method thereof, pseudo wafer used for manufacturing the same, and manufacturing method thereof Download PDF

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JP2004335629A
JP2004335629A JP2003127734A JP2003127734A JP2004335629A JP 2004335629 A JP2004335629 A JP 2004335629A JP 2003127734 A JP2003127734 A JP 2003127734A JP 2003127734 A JP2003127734 A JP 2003127734A JP 2004335629 A JP2004335629 A JP 2004335629A
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chip
conductive
electronic component
manufacturing
shaped electronic
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Japanese (ja)
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Nobuo Oshima
伸雄 大島
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Sony Corp
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Sony Corp
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Priority to JP2003127734A priority Critical patent/JP2004335629A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip-like electronic component capable of efficiently shielding a noise on the chip-like electronic component and easily realizing this with a simple structure and a manufacturing method thereof, and a pseudo wafer used for manufacturing thereof and a manufacturing method thereof. <P>SOLUTION: A protective substance layer 6 is coated on at least a side surface other than the surface of an electrode pad 5 of semiconductor chips 3, 4, and a metal plate 7 is formed on the layer 6 on the surface opposite to the surface of the layer 5 and is electrically grounded. The semiconductor chips 3, 4 are fixed in the opening 11 of a frame 12 fixed on a supporter 1, a protective substance is coated on at least the side surfaces of the semiconductor chips to form the layer 6, and the metal plate 7 is formed on the layer 6. After that, a pseudo wafer 14 integrally having the semiconductor chips 3, 4 is removed, and the wafer is cut after forming an interlayer insulating film 9, a connection hole 10 and wiring 15, thereby manufacturing a chip-like electronic component 19. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明が属する技術分野】
本発明は、半導体装置の製造に好適なチップ状電子部品及びその製造方法、その製造に用いる疑似ウェーハ及びその製造方法に関するものである。
【０００２】
【従来の技術】
従来、デジタルビデオカメラやデジタル携帯電話、更にノートＰＣ（Ｐｅｒｓｏｎａｌ Ｃｏｍｐｕｔｅｒ）等に代表される携帯用電子機器の、小型化や薄型化、軽量化に対する要求は強く、半導体部品の表面実装密度をいかに向上させるかが重要なポイントである。
【０００３】
この為、パッケージＩＣ（ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）等）に代る、より小型のＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）の開発や一部での採用が既に進められているが、究極の半導体高密度実装を考えると、ベアチップ実装でしかもフリップチップ方式による接続技術の普及が強く望まれる。
【０００４】
更には、近年の ＬＳＩ（Ｌａｒｇｅ Ｓｃａｌｅ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）の動作速度の向上及び低電圧化等に伴い、半導体チップとインターポーザ若しくはマザーボードとの接続については、配線経路の短縮及び配線抵抗の低減を目的として、上述のフリップチップ接続を用いることが増えている。
【０００５】
このような、フリップチップ実装におけるバンプ形成技術を用いたフリップチップ接続には、例えば、半導体チップの接続パッド上にはんだバンプを形成し、その後、熱により再度はんだを溶かしてマザーボードである実装基板と接続する方法や、Ａｌ電極パッド上にＡｕ−Ｓｔｕｄ Ｂｕｍｐ法や電解めっき法等によってＡｕバンプを形成し、その後、異方性導電フィルム等を用いてマザーボードと接続する方法や、電解めっき法や蒸着法等ではんだバンプを一括して形成する方法が代表的である。
【０００６】
しかし、民生用では、より低コストのフリップチップ実装の場合に、チップにしてからバンプを形成（Ａｕ−Ｓｔｕｄ Ｂｕｍｐ法がその代表例である）するのではなく、ウェーハ状態で一括してバンプを形成する方法が望ましい。
【０００７】
このようなウェーハ一括処理法は、近年のウェーハの大口径化（１５０ｍｍφ→２００ｍｍφ→３００ｍｍφ）と、ＬＳＩ（大規模集積回路）チップの接続ピン数の増加（多ピン化）傾向とを考えれば、当然の方向性である。
【０００８】
以下に、従来のバンプ形成方法を説明する。
【０００９】
図１４には、より低コストを目指して、Ｎｉ無電解めっきとはんだペーストの印刷とでウェーハ一括でバンプを形成する工程を示す。図１４（ａ）は、ＳｉＯ２膜が形成されたシリコン基板（ウェーハ）を示しており、同図（ｂ）はその電極を含むチップ部分を拡大したものである。図１４（ａ）、（ｂ）において、８５はシリコン基板（ウェーハ）、６５はＡｌ電極パッド、８４はＳｉＯ２膜、８３はＳｉ３Ｎ４、ＳｉＯ２膜やポリイミド膜等から成るパッシベーション膜である。
【００１０】
図１４（ｃ）では、Ｎｉ無電解めっき法により、開口されたＡｌ電極パッド６５の上面のみに、選択的にＮｉ無電解めっき層（ＵＢＭ：Ｕｎｄｅｒ Ｂｕｍｐ Ｍｅｔａｌ）７２が形成されている。このＮｉ無電解めっき層（ＵＢＭ）７２は、Ａｌ電極パッド６５面をリン酸系エッチ液で前処理した後に、Ｚｎ処理によりＺｎを置換析出させ、さらに、Ｎｉ−Ｐめっき槽に浸漬することによって容易に形成でき、Ａｌ電極パッド６５とはんだバンプとの接続を助けるＵＢＭとして作用する。
【００１１】
図１４（ｄ）は、印刷マスク７３（メタルスクリーン）を当てて、はんだペースト７４を印刷法によりＮｉ無電解めっき層（ＵＢＭ）７２上に転写した状態を示す。図１４（ｅ）は、ウエットバック（加熱溶融）法ではんだペースト７４を溶融して、はんだバンプ７５を形成したものである。このように、Ｎｉ無電解めっき法及びはんだペーストスクリーン印刷法等を用いることにより、フォトプロセスを用いずに、簡単にはんだバンプ７５を形成することができる。
【００１２】
他方、ＣＳＰは、１個１個のＬＳＩをいかに小さくして高密度で実装するかのアプローチであるが、デジタル機器の回路ブロックを見た場合、いくつかの共通回路ブロックで成り立っており、これらをマルチチップパッケージとしたり、モジュール化（ＭＣＭ：Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）する技術も登場している。デジタル携帯電話におけるＳＲＡＭ（スタティック・ラム）、フラッシュメモリー、マイコンの１パッケージ化等はその一例である。
【００１３】
このＭＣＭ技術は、最近の１チップシステムＬＳＩにおいても大きな利点を発揮するものと期待されている。即ち、メモリーやロジック、更にアナログＬＳＩを１チップ化する場合は、異なったＬＳＩ加工プロセスを同一ウェーハプロセスで処理することとなり、マスク数や工定数の著しい増加と開発ＴＡＴ（Ｔｕｒｎ ａｒｏｕｎｄ ｔｉｍｅ）の増加が問題となり、歩留りの低下も大きな懸念材料である。
【００１４】
このために、各ＬＳＩを個別に作り、ＭＣＭ化する方式が有力視されている。こうしたＭＣＭ化技術の例を図１５に示す。
【００１５】
図１５（ａ）及び（ｂ）はフリップチップ方式であって、配線基板（回路基板）７９上の電極７８に、フェイスダウンで半導体チップ５３及び５４を接続し、アンダーフィル材９５で固定している。ここで小型化、薄型化を考えた場合には、図１５のフリップチップが有利な方式である。今後の高速化での接続距離の縮小や各接続インピーダンスのバラツキ等を考えると、フリップチップ方式が主たる方法になるものと思われる。
【００１６】
このフリップチップ方式のＭＣＭとしては、例えば、複数の異種のＬＳＩについて、各々のＬＳＩのＡｌ電極パッド６５の面にＡｕ−Ｓｔｕｄ Ｂｕｍｐを形成し、異方性導電フィルム（ＡＣＦ：Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）を介して回路基板と接続する方法や、樹脂ペーストを用いて圧接する方法、更には、バンプとしてＡｕめっきバンプ、Ｎｉ無電解めっきバンプ及びはんだバンプを用いる方法等、種々のものが提案されている。
【００１７】
図１５（ｂ）は、はんだバンプ７５による配線基板７９との金属間接合で、より低抵抗で確実に接合できる例である。
【００１８】
上述のようなウェーハ一括のはんだバンプ形成法は、実装面でエリアパッド配置にも適用でき、一括リフローや両面実装が可能である等の利点がある。しかし、最先端の歩留まりが低いウェーハに対して処理をすると、良品チップ１個当たりのコストは極めて高くなる。
【００１９】
即ち、図１６には、従来のウェーハ一括処理における半導体ウェーハ９９を示すが、最先端ＬＳＩでは高歩留りが必要とされるにも拘らず、スクライブライン７１で仕切られたチップの内、×印で示す不良品ベアチップ９７の数が○印で示す良品ベアチップ９８の数より多くなるのが実情である。
【００２０】
また、チップをベアチップの形で他所から入手した場合のバンプ形成は極めて難しいという問題があった。即ち、上記した２種類のバンプ形成方法は各々特徴を持つが、全ての領域に使える技術ではなく、各々の特徴を活かした使い分けをされるのが現状である。ウェーハ一括バンプ処理法は、歩留まりが高く、ウェーハ１枚の中に占める端子数が多い場合（例えば５００００端子／ウェーハ）や、エリアパッド対応の低ダメージバンプ形成に特徴を発揮する。又、Ａｕスタッドバンプは、チップ単位で入手した場合のバンプ処理や、簡便なバンプ処理に特徴を発揮している。
【００２１】
なお、図１６に示した半導体ウェーハ９９をスクライブライン７１に沿って切断すると、切断の影響でチップにストレス、亀裂等のダメージが生じて、故障の原因になることがある。さらに、良品ベアチップ９８及び不良品ベアチップ９７を、共に半導体ウェーハ９９として一括ではんだバンプ形成まで工程を進行させると、不良品ベアチップ９７に施した工程が無駄になり、これもコストアップの原因となる。
【００２２】
更に、上述のはんだバンプを用いた接続法においては、半導体チップ上に予めはんだバンプを形成しておく必要があるために、以下に記した課題が挙げられる。
【００２３】
例えば、半導体チップを作製する工程からはんだバンプを形成する工程までの間の作製工程のリードタイムが、比較的長くなると共に作製コストも上昇する。このことは、特に複数の半導体チップからなるウェーハをそれぞれの半導体チップに分割したチップ状態においては、よりその傾向が顕著になる。
【００２４】
また、はんだバンプの形成においては、半導体チップ上の隣接するはんだバンプ同士が接触して短絡を起こさないために一定の間隔を設けねばならず、ある程度のスペースが必要であるために、これらのはんだバンプへの接続用の隣接する電極パッドのピッチが狭いタイプの半導体チップにおいては、比較的不向きな構造となってしまう。これは、近年の傾向である多ピン化とは相反するものであり、問題となっている。
【００２５】
そこで本出願人は、上述のような問題を解決した方法及び構造を特願２０００−１２２１１２（特開２００１−３０８１１６）として既に提起した（これを以下、先願発明（後記の特許文献１）と称する）。以下に、先願発明に基づく方法及び構造の一例を、図１７〜図２０について順を追って説明する。
【００２６】
図１７（ａ）は、仮の支持基板となる基板５１を示す。但し、基板への加熱プロセスは４００℃以下の為、より安価なガラス基板も使用できる。また、この基板５１は繰り返し使用できる。
【００２７】
次に、図１７（ｂ）に示すように、基板５１上に、ある温度以上に加熱されると粘着力が低下する、例えばアクリル系で所定の厚さの粘着シート５２を貼り付ける。
【００２８】
次に、図１７（ｃ）に示すように、良品と確認された複数の半導体（良品ベア）チップ５３及び５４を、電極パッド６５が露出している面を下にして配列して粘着シート５２上に貼り付ける。
【００２９】
なお、これらの良品の半導体チップ５３及び５４は、図１７に示した通常の半導体ウェーハ９９の工程でダイシングして、使用したダイシングシート（図示せず）の延伸状態から取り出してもよいし、チップトレイから移載してもよい。
【００３０】
ここで重要なことは、自社、他社製のチップに関わらず、良品の半導体チップ５３及び５４のみを基板５１上に再配列させることである。
【００３１】
次に、図１７（ｄ）に示すように、チップ５３及び５４上から例えば有機系絶縁性樹脂、例えばエポキシ系、アクリル系等の保護物質を均一に塗布して保護物質層５５を形成する。この塗布工程はスピンコート法や印刷法等で容易に実現できる。
【００３２】
次に、図１７（ｅ）に示すように、ある温度以上に加熱することにより、粘着シート５２の粘着力を弱くして、保護物質層５５で側面及び裏面が連続して固められた複数の良品の半導体チップ５３及び５４からなる疑似ウェーハ６７を、基板５１上から剥離する。
【００３３】
次に、図１７（ｆ）に示すように、基板５１上から剥離した疑似ウェーハ６７を上下方向で反転させて、半導体チップ５３及び５４の電極パッド６５が上面に来るようにする。
【００３４】
次に、図１７（ｇ）に示すように、疑似ウェーハ６７の上面に層間絶縁膜５６を形成する。
【００３５】
次に、図１７（ｈ）に示すように、層間絶縁膜５６に配線形成用の孔部５７を、それぞれの半導体チップ５３及び５４の電極パッド６５上に、電極パッド６５の上面の一部が露出するように設ける。
【００３６】
次に、層間絶縁膜５６上面及び孔部５７に配線材料を被着させた後に、図１８（ｉ）に示すように、フォトレジスト等を用いて所定の配線パターン５７に形成する。
【００３７】
次に、図１８（ｊ）に示すように、所定のパターンに形成された再配置用の配線５７を覆うようにして配線保護層５８を形成する。
【００３８】
次に、図１８（ｋ）に示すように、配線保護層５８に配線取り出し用のランド開口５９を、所定の位置に配線５７の上面の一部が露出するように複数箇所設ける。
【００３９】
次に、図１８（ｌ）に示すように、半導体チップ５３及び５４を保護物質層５５で保護して補強してなるチップ状電子部品６９の単位で、ブレード６８（又はレーザ）でスクライブライン７１に沿ってダイシング７０し、個々の個片とする。
【００４０】
図１９（ｍ）は、このチップ状電子部品６９の拡大図、及びこの拡大図中の、主に半導体チップ５４付近の詳細図であり、この半導体チップ５４（半導体チップ５３も同様）は、シリコン基板８５上にＳｉＯ２膜８４を介してＡｌ電極パッド６５及びパッシベーション膜８３が形成された構造のものである。
【００４１】
次に、図１９（ｎ）に示すように、Ｎｉ無電解めっき法によってランド開口５９内にＮｉ無電解めっき層（ＵＢＭ）７２を形成する。なお、このＮｉ無電解めっき層（ＵＢＭ）７２は、例えば、配線５７の上面をリン酸系エッチ液で前処理した後に、Ｚｎ処理によりＺｎを置換析出させ、さらにＮｉ−Ｐめっき槽に浸漬させることにより、容易に形成でき、Ａｌ電極パッド６５と後述するはんだバンプとの接続を助けるＵＢＭ（Ｕｎｄｅｒ Ｂｕｍｐ Ｍｅｔａｌ）として作用する。
【００４２】
更に、無電解めっき層７２上に、ランド１００をランド開口５９上のみならず配線保護層５８上にも連続して形成する。
【００４３】
次に、図１９（ｏ）に示すように、印刷マスク７３を当てて、はんだペースト７４を印刷法によりランド１００上に転写する。
【００４４】
次に、図２０（ｐ）に示すように、ウエットバック法ではんだペースト７４を溶融して、はんだバンプ７５を形成する。このように、Ｎｉ無電解めっき法及びはんだペーストスクリーン印刷法等を用いることにより、フォトプロセスを用いずに簡単にはんだバンプ７５を形成できる。
【００４５】
上記のようにして、低歩留まりの最先端のＬＳＩや他社から入手したチップであっても、良品の半導体チップ５３及び５４のみを基板５１に貼り付けて、あたかも１００％良品の半導体チップ５３及び５４のみで構成された疑似ウェーハ６７を作製できる。このため、図１８（ｋ）の状態でウェーハ一括の低コストのはんだバンプ形成も可能になる。
【００４６】
そして、図１８（ｉ）の状態において、プローブ検査による電気的特性の測定やバーンインを行って、図１７（ｃ）の工程前に良品の半導体チップ５３及び５４を選別したことに加えて、更により確実に良品チップのみを選別できる。
【００４７】
次に、図２０（ｑ）に示すように、基板７９上にソルダー（はんだ）レジスト７６で囲まれかつソルダー（はんだ）ペースト７７を被着した電極７８を設けた実装基板６０に、個片化されたチップ状電子部品６９をマウントする。
【００４８】
この際、チップ状電子部品６９の側面と裏面は保護物質層５５で覆われているため、実装基板６０への実装時のチップ状電子部品６９の吸着等のハンドリングにおいて、直接チップ５３、５４がダメージを受けることがないために、高い信頼性を持つフリップチップ実装を期待することができる。
【００４９】
なお、上記の記述は半導体チップのフリップチップ実装技術に関するものであるが、フリップチップ高密度実装における接続用はんだバンプの形成技術とその製造方法に関するものでもあり、良品の半導体チップ５３及び５４をその表面を下にして基板５１上に等間隔で並べて貼り付け、その後に保護物質層５５を裏面等に均一に塗布して、チップ５３及び５４同士を固定している。
【００５０】
しかる後に、貼着シート５２から剥がして、良品の半導体チップ５３及び５４のみが配列された疑似ウェーハ６７を作製し、このウェーハ６７に一括でバンプ形成をして、低コストでバンプチップを製造できる。このバンプチップは、小型・軽量の携帯用電子機器のみならず、全てのエレクトロニクス機器に利用され得る。
【００５１】
上述の工程によれば、半導体チップ５３及び５４等のチップ状電子部品（以下、半導体チップを代表例として説明する。）６９の電極パッド６５面以外（即ち、チップ５３及び５４の側面及び裏面）が連続した保護物質層５５によって保護されるので、チップ化後のハンドリングにおいてチップ５３及び５４が保護され、ハンドリングが容易となると共に、良好な実装信頼性が得られる。
【００５２】
又、上述の半導体ウェーハ９９から切出されて良品のみを選択した半導体チップ５３及び５４を基板５１に貼り付け、保護物質層５５を全面に被着した後に剥離することにより、あたかも全品が良品の半導体チップ５３及び５４のみからなる疑似ウェーハ６７を得るため、ウェーハ一括での配線形成やバンプ処理等も可能となる。
【００５３】
更に、チップ５３及び５４を疑似ウェーハ６７から切り出す際にチップ間の保護物質層５５の部分を切断することになるので、半導体チップ５３及び５４本体への悪影響（歪みやばり、亀裂等のダメージ）を抑えて容易に切断することができる。
【００５４】
しかも、保護物質層によってチップ５３及び５４の側面及び裏面が覆われていることから、Ｎｉ無電解めっき処理も可能である。そして、自社製ウェーハのみならず、他社から購入したベアチップでも、容易にはんだバンプ処理等が可能になる。
【００５５】
また、ＭＣＭに搭載される異種ＬＳＩチップを全て同一半導体メーカーから供給されるケースは少なく、最先端の半導体ラインの投資が大きくなってきているために、ＳＲＡＭ、フラッシュメモリーやマイコン、更にＣＰＵ（中央演算処理ユニット）を同一半導体メーカーで供給するのではなく、各々得意とする半導体メーカーから別々にチップで供給してもらい、これらをＭＣＭ化することもできる。
【００５６】
なお、上記の基板は繰り返し使用できて、バンプ形成のコストや環境面でも有利である。
【００５７】
更に、上述の工程においては、半導体チップ５３及び５４の作製工程を別工程として行い、既に良品と判定されたチップ５３及び５４のみを使用するために、例えば、半導体チップを作製する工程からはんだバンプを形成する工程までの間の、作製工程のリードタイムや検査時間等を比較的短くすることができると共に、作製コストの上昇を抑えることができる。
【００５８】
また、はんだバンプの形成においては、半導体チップ上の隣接するはんだバンプ同士が接触して短絡を起こさせないために一定の間隔を設けねばならず、ある程度のスペースが必要であるが、図１９（ｎ）に示すように、配線５７やランド１００等の配置形状によってはんだバンプの形成位置の自由度が増し、これらのはんだバンプへの接続用の隣接する電極パッド６５のピッチが狭いタイプの半導体チップにおいても、電極パッドのピッチをより短く高密度にすることができ、多ピン化を実現することができる。
【００５９】
【特許文献１】
特開２００１−３０８１１６公報明細書及び図面（第６〜１１欄、図１〜図３）
【００６０】
【発明が解決しようとする課題】
しかしながら、上述の先願発明は上記の如き優れた特徴を有しているものの、なお、改善すべき以下のような課題があることが判明した。
【００６１】
即ち、特にＲＦ（Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ）系のＬＳＩ用のチップ状電子部品６９を使用する場合、他のＬＳＩ用の電子部品との間に生じる電気的なノイズを遮断して誤動作等を防止するために、チップ状電子部品６９全体をシールドケースで覆うことが多い。
【００６２】
近年、小型化及び軽量化を目的として、ＣＳＰ等のＬＳＩパッケージの小型化が急速に進んでいるが、上記のようにシールドケースを後付けすることにより、小型化したＬＳＩパッケージでもその実装面積が大きくなってしまい、また、シールドケースの後付け等の工程が増えてコストアップにもなる。
【００６３】
そこで、本発明の目的は、上記した先願発明の特徴を生かしつつ、チップ状電子部品に対するノイズを効果的に遮断すると共に、これを簡易な構造により容易に実現できるチップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウェーハ及びその製造方法を提供することにある。
【００６４】
【課題を解決するための手段】
即ち、本発明は、
支持体上に複数個又は複数種のチップ部品を固定する工程と、
前記チップ部品の少なくとも側面に保護物質を被着させて保護物質層を形成する工程と、
前記保護物質層上に導電層を形成する工程と、
前記保護物質層が被着された前記チップ部品を前記支持体から剥離する工程と
を有する疑似ウェーハの製造方法に係わり、また、この方法に、
前記チップ部品の電極面上に層間絶縁膜及び接続孔を形成する工程と、
前記接続孔に導電性接続材を設ける工程と、
前記複数個又は複数種のチップ部品間を切断して、チップ状電子部品を得る工程と
を付加した、チップ状電子部品の製造方法に係わるものである。
【００６５】
本発明は又、複数個又は複数種のチップ部品が、電極面以外の少なくとも側面に被着された保護物質層によって一体化されていて、前記電極面とは反対側の面において前記保護物質層上に導電層が被着されている疑似ウェーハを提供し、また、この疑似ウェーハから得られ、前記チップ部品の電極面以外の少なくとも側面に前記保護物質層が被着されていて、前記電極面とは反対側の面において前記保護物質層上に前記導電層が形成されている、チップ状電子部品も提供するものである。
【００６６】
本発明によれば、前記電極面とは反対側の面において前記保護物質層上に導電層が形成されているために、前記チップ状電子部品に対する外部からのノイズを前記導電層を通して放出することができ、良好なシールド効果を得ることができると共に、チップ状電子部品とシールド手段とを一体化して小型化、薄型化することができ、しかもこれをシールド手段の後付け工程なしに簡易な構造で実現することができる。
【００６７】
また、先願発明と同様に、例えば、良品のチップ部品を再配列して疑似ウェーハとするので、あたかも全品が良品のチップからなるウェーハが得られるため、ウェーハ一括での配線形成及びはんだバンプ処理等も可能になり、低コストのフリップチップ用のチップ状電子部品を作製でき、自社製チップのみならず、他社から購入したベアチップでも容易に配線形成及びはんだバンプ処理等が可能になる。
【００６８】
そして、チップ状電子部品を疑似ウェーハから切り出す際に、前記チップ部品間（側面）を切断するので、チップ部品本体への悪影響（歪みやばり、亀裂等のダメージ）が抑えられる。
【００６９】
また、前記保護物質層によって少なくともチップ側面が覆われているので、Ｎｉ等の無電解めっき処理も可能であると共に、前記保護物質層によって少なくともチップ側面が保護されているので、個片化後のチップ状電子部品の実装ハンドリングにおいてもチップが保護され、良好な実装信頼性が得られる。
【００７０】
【発明の実施の形態】
本発明においては、前記保護物質層の形成時における前記保護物質層と前記チップ部品との熱膨張係数の差に起因する疑似ウェーハ（従ってチップ状電子部品）の変形を防ぐために、前記チップ部品を装入するための開口部を有する枠体を前記支持体上に固定した後、前記枠体の前記開口部内に前記チップ部品を装入して前記支持体上に固定し、この固定後に前記開口部内において前記チップ部品の少なくとも側面を覆うように前記保護物質を被着させるのが望ましい。
【００７１】
この場合、前記チップ状電子部品に対するシールド効果を向上させるために、前記枠体を導電性物質で形成し、前記導電層と接触させるのが望ましい。
【００７２】
また、前記保護物質の被着を印刷又は物理的蒸着によって行ってもよい。
【００７３】
また、前記導電性接続材を介して前記導電層を前記電極面上に電気的に取り出すのが望ましい。
【００７４】
また、前記接続孔を介して前記複数個又は複数種のチップ部品間を前記導電性接続材からなる配線によって接続するのが望ましい。
【００７５】
また、はんだバンプ等の外部接続端子を形成する上でその形成位置の選択の自由度を増すために、前記導電性接続材からなる配線上に第２の層間絶縁膜を形成し、この第２の層間絶縁膜に形成した第２の接続孔を介して前記配線を電気的に取り出すのが望ましい。
【００７６】
また、前記支持体上での前記チップ部品の位置決めを容易にかつ的確に行うために、前記開口部の近傍において前記枠体に前記チップ部品の位置決め手段を形成するのが望ましい。この位置決め手段は、前記チップ状電子部品において前記導電性物質層の表面に残されてよい。
【００７７】
また、前記導電層を接地してシールド効果を得るために、前記チップ部品の側面に被着された前記保護物質層の外面に前記導電性物質層が被着され、この導電性物質層が前記導電層に接触しているのが望ましい。
【００７８】
この場合、前記チップ部品の電極面上に層間絶縁膜が形成され、この層間絶縁膜に形成した接続孔に導電性接続材が設けられており、この導電性接続材を介して前記導電層が前記電極面上に電気的に取り出されてよい。
【００７９】
次に、本発明の好ましい実施の形態を図面の参照下に具体的に説明する。
【００８０】
第１の実施の形態
図１〜図６は、本実施の形態による疑似ウェーハ１４及びチップ状電子部品１９の作製工程、及びこのチップ状電子部品１９の実装工程を順次示すものである。
【００８１】
図１（ａ）は、仮の支持基板となる基板１を示す。但し、この基板１への加熱プロセスは４００℃以下で行えるため、安価なガラス基板も基板１として使用できる。また、この基板１は繰り返し使用することができる。
【００８２】
次に、図１（ｂ）に示すように、基板１上に、ある温度以上に加熱されると粘着力が低下する、例えばアクリル系で所定の厚さの粘着シート２を貼り付ける。
【００８３】
次に、図１（ｃ）に示すように、半導体チップ３及び４を装入する開口部１１を有する銅等の導電性材料からなるフレーム１２（詳細は後述）を、粘着シート２上に貼り付けて仮固定する。この際に、開口部１１の位置は半導体チップ３及び４の貼付け位置に概ね対応しており、フレーム１２は基板１の表面内に収まってさえいれば特に貼り付け精度は問わない。
【００８４】
ここで、フレーム１２の形状、大きさ、材質、貼付け方法及び貼付け位置等、並びに開口部１１の形状、大きさ及び個数等は、半導体チップ３及び４の貼付け位置等に対応して、任意に選択してよい。
【００８５】
次に、図１（ｄ）に示すように、良品と確認された複数の半導体（良品ベア）チップ３及び４を、電極パッド５が露出している面を下にしてフレーム１２の開口部１１内に装入し、この開口部１１内において粘着シート２上の所定の位置に貼り付ける。
【００８６】
なお、良品の半導体チップ３及び４は、図１６で述べたように通常の半導体ウェーハ９９を各半導体チップにダイシングして得てよいが、各良品半導体チップはダイシングシート（図示せず）の延伸状態から取り出してもよいし、チップトレイから移載してもよい。
【００８７】
このように、フレーム１２の開口部１１内に半導体チップ３及び４を指定した位置にマウント（仮固定）する際に、予めフレーム１２の上面に設けておいた位置合わせマーク（ここでは図示省略）を基準にして行うことによって、基板１上の全体の広範囲に亘って、半導体チップ３及び４の固定位置の精度を確保することが可能となる。
【００８８】
また、このことによって、図１７に示した先願発明では使用可能な専用の位置合わせマーク付きの基板５１を使用する必要がなくなるため、使用する基板１として汎用性のある安価な基板の採用が可能となり、コストダウンを図ることができる。
【００８９】
次に、図１（ｅ）に示すように、開口部１１からチップ３及び４上に例えば有機系絶縁性樹脂、例えばエポキシ系等からなる保護物質を流し込み、保護物質層６を各開口部毎に形成する。この保護物質層６は半導体チップ３及び４の側面、更には上面を覆う程度の量にし、また一般的にはディスペンス法（場合によっては印刷法等）によって形成する。保護物質層６の材質は、エポキシ樹脂とするのがよいが、アクリル系等でもよく、機械的な衝撃又は湿度等から半導体チップ３及び４を保護することができるものであれば、材質に制限はない。
【００９０】
ここで、図１７に示した先願発明においては、保護物質層５５には、半導体チップの固定機能に加えて、複数個又は複数種の半導体チップを連接した疑似ウェーハ６７全体の構造体としての機能も持たせていたが、本実施の形態においては、主にフレーム１２と半導体チップ３及び４との間の固定機能を果たすだけで十分であるため、保護物質６の使用量を必要最低限にすることが可能である。但し、各半導体チップ３と４との間にも保護物質が被着されているのが、チップの完全固定の上で望ましいが、必ずしもそのようにする必要はない。
【００９１】
このように、保護物質層６の量が激減するために、半導体チップと保護物質層との熱膨張係数の差により保護物質の流し込みによるチップ固定時に発生しがちであった内部応力が弱められ、後述のようにして疑似ウェーハ１４を基板１から剥離した後の疑似ウェーハ１４の反り量を大幅に低減することができ、疑似ウェーハ１４の平坦性を保つことができる。その結果、後工程での配線形成時の加工性及び歩留等を飛躍的に向上させることが可能となる。
【００９２】
次に、図２（ｆ）に示すように、フレーム１２上に平坦な銅等の金属板７を貼付ける。この際に、フレーム１２と金属板７との接合に導電性ペーストからなる接着剤（図示せず）を用いてよい。
【００９３】
ここで、金属板７の材質はフレーム１２の材質と同様に特に限定はされない。また、フレーム１２と金属板７とはシールド用として電気的に接続している必要があるため、図２（ｆ）においては導電性ペーストで接着する形態を記載したが、両者を電気的に接続可能であって接着力も得られるような接続方法であれば、特に限定されることはない。
【００９４】
また、金属板７に代えて、例えば、メタライジング法、めっき法、スパッタ法、蒸着法等により形成した金属層を用いてもよい。要は、金属板の貼り付け以外にも様々な方法で形成された導電層であればよい。この金属板７はべた付けであってよいが、所定パターンに形成してもよい。
【００９５】
次に、図２（ｇ）に示すように、ある温度以上に加熱することにより粘着シート２の粘着力を弱くした状態で、保護物質層６、更にはフレーム１２及び金属板７で側面及び裏面等が覆われた複数の良品の半導体チップ３及び４の一体化物からなる疑似ウェーハ１４を基板１から剥離し、疑似ウェーハ１４の作製工程を完了する。
【００９６】
この時に、上記したように保護物質層６の量が低減されていることによって疑似ウェーハ１４の反り量が大幅に低減するのに加えて、金属板７（又は金属層）がある程度の剛性を有しているために、疑似ウェーハ１４の反りを一層抑制することができる。
【００９７】
次に、図２（ｈ）に示すように、基板１から剥離した疑似ウェーハ１４を上下方向で反転させて、半導体チップ３及び４の電極パッド５の露出面が上側に来るようにする。
【００９８】
次に、図２（ｉ）に示すように、疑似ウェーハ１４の上面に塗布法や化学的気相成長法等によって層間絶縁膜９を形成する。ここで、層間絶縁膜９の厚さ、材質及び形成方法等は、任意に選択してよい。
【００９９】
次に、図２（ｊ）に示すように、フォトリソグラフィ技術によって層間絶縁膜９に配線形成用のビアホール１０を形成し、それぞれの半導体チップ３及び４の電極パッド５の上面の一部を露出させる。これと同時に、フレーム１２上にも層間絶縁膜９を貫通してビアホール１０を形成し、フレーム１２の上部の一部を露出させる。
【０１００】
ここで、ビアホール１０の大きさ、位置、数量及び形成方法等は、半導体チップ３及び４の配列等に対応して決定することができる。
【０１０１】
次に、図３（ｋ）に示すように、真空蒸着法又はスパッタ法等によって層間絶縁膜９の上面及びそれぞれのビアホール１０内に配線材料を被着した後に、フォトリソグラフィ技術によって所定パターンの配線１５を形成し、各チップ間を接続するＭＣＭ用配線としたり、外部端子形成用の配線とする。
【０１０２】
例えば、疑似ウェーハ１４上に層間絶縁膜９を塗布し、この層間絶縁膜９に電極パッド５上の必要箇所及びフレーム１２上の必要箇所にビアホール１０を開口した後に、例えば、セミアディティブ法等により配線１５を形成する。
【０１０３】
次に、図３（ｌ）に示すように、所定パターンに形成された再配置用の配線１５を覆うようにして、カバーコートである配線保護層１６を形成する。ここで、配線保護層１６の厚さ、材質及び形成方法等は、任意に選択してもよい。
【０１０４】
次に、図３（ｍ）に示すように、配線保護層１６に外部との接続に必要な配線取り出し用のランド開口１７を配線１５上の所定の位置に形成し、配線１５の上面の一部を露出させる。ここで、ランド開口１７の大きさ、数量及び形成方法等は、任意に選択してよい。
【０１０５】
こうして、半導体チップ３及び４の側面が保護物質層６を介してフレーム１２に接着されると共に、半導体チップ３及び４の裏面が保護物質層６及び金属板７で覆われた構造を形成する。
【０１０６】
次に、図４（ｎ）に示すように、フレーム１２の位置において、ブレード１８（又はレーザ等）でスクライブライン２１に沿って金属板７及びフレーム１２を切断してダイシング２０して、複数の半導体チップ３及び４が保護物質層６とフレーム１２及び金属板７で覆われてなる単位に個片化し、この個片をチップ状電子部品１９とする。
【０１０７】
こうして得られたチップ状電子部品１９は、後記のように、フレーム１２及び配線１５、この上のランド開口１７を介して金属板７を電気的にグランドに接続（接地）する。これによって、チップ状電子部品１９全体をフレーム１２及び金属板７からなるシールド層で囲む構造を形成し、チップ状電子部品１９をシールドケースで囲む場合と同様の構造及び効果を得ることができる。但し、フレーム１２及び金属板７からなるシールド構造は、シールドケースよりもはるかに薄型、小型化したものとなる。
【０１０８】
図４（ｏ）は、このチップ状電子部品１９の拡大図、及び主に半導体チップ４付近の詳細図であり、この半導体チップ４（半導体チップ３も同様）は、シリコン基板２４上にＳｉＯ２膜２３を介してＡｌ電極パッド５及びパッシベーション膜２２が形成された構造からなっている。
【０１０９】
次に、図５（ｐ）に示すように、Ｎｉ無電解めっき法によってランド開口１７内にＮｉ無電解めっき層（ＵＢＭ）２５を形成する。なお、このＮｉ無電解めっき層（ＵＢＭ）２５は、例えば、配線１５の上面をリン酸系エッチ液で前処理した後に、Ｚｎ処理によりＺｎを置換析出させ、さらにＮｉ−Ｐめっき槽に浸漬させることにより、容易に形成でき、Ａｌ電極パッド５と後述するはんだバンプとの接続を助けるＵＢＭ（Ｕｎｄｅｒ Ｂｕｍｐ Ｍｅｔａｌ）として作用する。
【０１１０】
更に、無電解めっき層２５と接続するように、ランド２６をランド開口１７上のみならず配線保護層１６上にも形成する。
【０１１１】
ここで、無電解めっき層２５やランド２６を含めた配線については、外部端子位置の再配置等に有用である。更に、配線１５も含めてランド２６は、いわゆるインターポーザー基板を用いることなしにインターポーザーをビルドアップした構造をなしているため、再配置用の配線構造を精度良く容易に形成することができ、また、これを基本的には、図３（ｍ）に示したウェーハレベルで一括処理により形成することができることは極めて有利である。
【０１１２】
次に、図５（ｑ）に示すように、印刷マスク２７を当てて、はんだペースト２８を印刷法によりランド２６上に転写する。
【０１１３】
次に、図６（ｒ）に示すように、ウエットバック法等ではんだペースト２８を溶融して、はんだバンプ２９を形成する。このように、Ｎｉ無電解めっき法及びはんだペーストスクリーン印刷法等を用いることにより、フォトプロセスを用いずに簡単にはんだバンプ２９を形成できる。
【０１１４】
上記のようにして、低歩留まりの最先端のＬＳＩや他社から入手したチップであっても、良品の半導体チップ３及び４のみを基板１に貼り付けて、あたかも１００％良品の半導体チップ３及び４のみで構成された疑似ウェーハ１４を作製できる。なお、図３（ｍ）の状態で、ウェーハ一括の低コストのはんだバンプ形成も可能になる。
【０１１５】
そして、図３（ｋ）の状態において、プローブ検査による電気的特性の測定やバーンインを行って、図１（ｄ）の工程前に良品の半導体チップ３及び４を選別したことに加えて、更により確実に良品チップのみを選別できる。
【０１１６】
次に、図６（ｓ）に示すように、基板３４上に、ソルダー（はんだ）レジスト３１で囲まれかつソルダー（はんだ）ペースト３２を被着した電極３３を設けた実装基板３０に、個片化されたチップ状電子部品１９をマウントする。なお、はんだペースト３２に代えてはんだバンプを形成すれば、チップ状電子部品１９に上記のはんだバンプ２９を形成することを要しない。
【０１１７】
上記のチップ状電子部品１９は、側面と裏面とがフレーム１２や金属板７等によって覆われて保護されているため、図４（ｎ）に示したダイシング時のみならず、図６（ｓ）に示した実装基板３０への実装時のチップ状電子部品１９の吸着等のハンドリングにおいても、チップ３及び４がダメージを受けることがなく、高い信頼性でダイシング及びフリップチップ実装が可能となる。
【０１１８】
図７には、図１（ｃ）に示した本実施の形態で使用するフレーム１２を詳しく説明するものである。ここで、図７（ａ）はフレーム１２の平面図を示し、図７（ｂ）はフレーム１２の断面図を示すが、概略図示した図１（ｃ）と比べて各部を詳細に図示している。
【０１１９】
図７に示すフレーム１２は、例えば、Ｃｕ等の金属を含む導電性物質からなる板材に、破線で示す半導体チップ３及び４が仮固定されるチップエリアより多少大きめの開口部１１をエッチング又はプレス加工法等により抜き加工したものである。
【０１２０】
フレーム１２の材質に関しては、上記のような加工に適用可能であれば特に限定されないが、導電性を有し、安価で大量加工に適した材質のものが望ましい。
【０１２１】
また、開口部１１の形成と同時に、開口部１１の近傍においてフレーム１２の片面（半導体チップ３及び４を装入する側の面）に対して、チップエリアへのチップマウント（仮固定）時にチップ位置合わせのために位置決めの手段として位置合わせマーク１３を形成しておくことが望ましい。この位置合わせマーク１３は、例えば円形のハーフエッチング等によって凹部として形成することができる。
【０１２２】
この場合、位置合わせマーク１３により、半導体チップ３及び４を組とするモジュール間でのチップ位置精度が決定されるので、位置合わせマーク１３は、マーク間のピッチが相対的に正確に保持されるような加工方法で形成するのが望ましい。
【０１２３】
そして、図１（ｄ）に示したように各半導体チップを開口部１１内の所定位置に装入、固定する際には、図８に示すように、フレーム１２に設けられた位置合わせマーク１３によって各半導体チップの装入位置を識別する。
【０１２４】
即ち、上部カメラ３５によって、真空チャック３７に吸着された半導体チップ４（又は３）の位置を検出すると共に、下部カメラ３６によって、基板１上に仮固定されたフレーム１２の位置合わせマーク１３の位置を検出しておく。
【０１２５】
例えば、これらの各カメラ３５及び３６によって位置合わせマーク１３と他の位置合わせマーク１３との距離や、位置合せマーク１３と半導体チップとの距離などを検出し、これらの検出による位置情報に基づいて、フレーム１２の開口部１１内の正規の位置に正規の向きで半導体チップ３及び４を装入し、破線で示すように粘着シート２上に仮固定することができる。
【０１２６】
なお、本実施の形態と比較して、図１７〜図２０に示した先願発明においては、以下のような問題点もある。
【０１２７】
即ち、得られたチップ状電子部品６９の半導体チップの裏面（電極パッド６５とは反対側の面）には、絶縁層である保護物質層５５が存在しているために、チップ状電子部品６９の表面側と裏面とは絶縁されており、その裏面に配線層等の導電層を設けて回路を構成することは何ら意図されていない。このため、チップ状電子部品６９の裏面側を含めてシールド層で覆うことは不可能である。
【０１２８】
また、粘着シート５２上に半導体チップ５３及び５４を仮固定する場合には、半導体チップ５３及び５４を基板５１上の広いエリアにおいて相対的に正確な位置精度で配置する必要があるが、このために半導体チップ５３及び５４をマウント（仮固定）する基板５１側に位置合わせマークを配置する。この位置合わせマークは、チップ状電子部品６９のサイズ毎に位置変更を行うことが必要となり、チップ状電子部品６９のサイズ毎に専用の基板５１を用意しなければならず、これに伴ってコストアップとなり易い。
【０１２９】
また、半導体チップ５３及び５４の材質（主としてシリコン）と、線膨張及び硬化時の収縮の大きい保護物質層５５の材質（主として例えばエポキシ樹脂）との熱膨張又は収縮量の差によって、保護物質層５５の被着後の基板５１からの剥離後に、疑似ウェーハ６７の反りが大きくなり、この反りがウェーハ上での配線形成やチップ状電子部品６９の実装に支障を生じ、搬送性及び歩留も阻害することがある。
【０１３０】
これに対し、本実施の形態では、チップ状電子部品１９の裏面に金属板７を設け、フレーム１２及び配線１５を介して電気的に接地しているので、チップ状電子部品１９の周囲をシールドでき、外部からのノイズ等による半導体チップ３及び４の誤動作等を十二分に防止することができる。
【０１３１】
この場合、シールド構造を形成する金属板７及びフレーム１２等とチップ状電子部品１９とを一体化しているために、シールドケースを後付けする場合に比べて、小型化、薄型化した構造となり、実装面積が小さくなり、作製工程も簡略化される。
【０１３２】
また、各半導体チップ３、４毎に専用の位置合わせマークを基板１に設けるのではなく、フレーム１２に設けられた位置合わせマーク１３よって、各半導体チップ３及び４間のマウント（仮固定）位置精度を確保できるため、基板１の汎用性の拡大及びそれによるコストダウンが可能となる。
【０１３３】
また、枠体であるフレーム１２によって各半導体チップ間が仕切られているために、各半導体チップ３及び４を固着するための保護物質層６の構成物質、例えばエポキシ樹脂の使用量を減らせるので、半導体チップ３及び４との熱膨張量又は収縮量の差を小さくして、疑似ウェーハ１４の変形を抑制することができる。これによって、疑似ウェーハ１４の反りを小さくでき、後工程の配線形成を行い易く、実装の信頼性が向上し、また搬送性及び歩留等も改善することができる。
【０１３４】
なお、本実施の形態においては、良品の半導体チップ３及び４のみが配列された疑似ウェーハ１４を作製し、このウェーハ１４に一括で配線形成（更に必要とあればバンプ形成）を行うことができる。これは、小型・軽量の携帯用電子機器のみならず、全てのエレクトロニクス機器に利用され得る。
【０１３５】
また、半導体チップ３及び４を有するチップ状電子部品１９の電極パッド５面以外（即ち、チップ３及び４の側面及び裏面）がフレーム１２及び金属板７等によって保護されるので、チップ化後のハンドリングにおいてチップ３及び４が保護され、ハンドリングが容易となると共に、良好な実装信頼性を得ることができる。
【０１３６】
また、チップ状電子部品１９を疑似ウェーハ１４から切り出す際に、チップ間のフレーム１２の部分を切断するので、半導体チップ３及び４本体への悪影響（歪みやばり、亀裂等のダメージ）を抑えて容易に切断することができる。
【０１３７】
しかも、フレーム１２や金属板７等によってチップ３及び４の側面及び裏面が覆われていることから、Ｎｉ無電解めっき処理も可能である。そして、自社製ウェーハのみならず、他社から購入したベアチップでも、容易にはんだバンプ処理等が可能になる。
【０１３８】
また、ＭＣＭに搭載される異種ＬＳＩチップを全て同一半導体メーカーから供給されるケースは少なく、最先端の半導体ラインの投資が大きくなってきているために、ＳＲＡＭ、フラッシュメモリーやマイコン、更にＣＰＵ（中央演算処理ユニット）を同一半導体メーカーで供給するのではなく、各々得意とする半導体メーカーから別々にチップで供給してもらい、これらをＭＣＭ化することもできる。
【０１３９】
また、上記の基板１は繰り返し使用でき、コストや環境面でも有利である。
【０１４０】
更に、上述の工程においては、半導体チップ３及び４の作製工程を別工程として行い、既に良品と判定されたチップ３及び４のみを使用するために、例えば、半導体チップを作製する工程からはんだバンプを形成する工程までの時間や検査時間等を短くすることができると共に、作製コストの上昇を抑えることができる。
【０１４１】
また、はんだバンプの形成においては、半導体チップ上の隣接するはんだバンプ同士が接触して短絡を起こさせないために一定の間隔を設けねばならず、ある程度のスペースが必要であるが、図５（ｐ）に示すように、配線１５やランド２６等の配置によってはんだバンプの形成位置の自由度が増し、隣接する電極パッド５のピッチが狭いタイプの半導体チップにおいても、ランド２６の数を増やして多ピン化を実現することができる。
【０１４２】
第２の実施の形態
本実施の形態は、図９〜図１１に示すように、半導体チップ３及び４の電極面以外を樹脂からなる保護物質のみで覆って保護物質層６を形成すると共に、金属層７の接地用の配線１５を保護物質層６を通して形成する以外は、第１の実施の形態と同様である。
【０１４３】
即ち、図９（ａ）〜図９（ｂ）に示すように、上記の図１（ａ）〜図１（ｂ）に示す工程と同様に、基板１上に粘着シート２を貼り付ける。
【０１４４】
次に、図９（ｃ）に示すように、良品の半導体チップ３及び４を粘着シート２上の所定の個所に貼り付けて仮固定する。
【０１４５】
次に、図９（ｄ）に示すように、半導体チップ３及び４を覆うように樹脂からなる保護物質を塗布して保護物質層６を形成する。
【０１４６】
その後、図９（ｅ）〜図１０（ｈ）に示すように、上記の図２（ｆ）〜図２（ｉ）に示す工程と同様に、保護物質層６上に金属板７を設けた後に、基板１から剥離して疑似ウェーハ１４とし、この疑似ウェーハ１４の電極パッド５の上に層間絶縁膜９を形成する。
【０１４７】
次に、図１０（ｉ）に示すように、フォトリソグラフィー技術によって配線用のビアホール１０を層間絶縁膜９又は保護物質層６に形成し、各電極パッド５の表面を一部露出させ、かつ接地（シールド）用の導電層となる金属板７の表面を一部露出させる。
【０１４８】
次に、図１０（ｊ）に示すように、それぞれのビアホール１０に配線材料を充填してパターニングし、配線１５を形成する。
【０１４９】
次に、図１０（ｋ）〜図１２（ｒ）に示すように、上記の図３（ｌ）〜図６（ｓ）の工程と同様に、配線１５等の施された疑似ウェーハ１４を個片化してチップ状電子部品１９とし、そのチップ状電子部品にはんだバンプ２９等を形成した後に、それを実装基板３０に実装する。
【０１５０】
本実施の形態によれば、第１の実施の形態におけるフレーム１２を用いないでも、保護物質層６を通して金属層７を配線１５によって接地することができると共に、半導体チップ３及び４間の保護物質層６を金属層７と共に切断してチップ状電子部品１９を形成しているため、疑似ウェーハ１４の切断が比較的容易になる。
【０１５１】
また、図９（ｆ）に示した疑似ウェーハ１４は、金属板７によって補強されていることから、これが存在しない場合に比べて、上記した反りを少なくすることができる。つまり、金属板７はシールドと共に反り防止作用も有している。
【０１５２】
その他、本実施の形態においては、上述の第１の実施の形態で述べたのと同様の作用及び効果が得られる。
【０１５３】
第３の実施の形態
本実施の形態は、図１３に示すように、フレーム４２の材質を保護物質層６の材質と同一として、このフレーム４２を粘着シート２上に仮固定し、更に、フレーム４２の開口部１１内に半導体チップ３及び４を装入した後に、加熱等でフレーム４２を溶解して各半導体チップ３及び４の側面間を接合する保護物質層６となし、この上に接着剤を塗布して接着剤層３８を介して金属板７を形成する以外は、第１の実施の形態と同様である。
【０１５４】
即ち、図１３（ａ）〜図１３（ｂ）に示すように、上記の図１（ａ）〜図１（ｄ）に示す工程と同様に、基板１上に粘着シート２を貼り付け、更にその上にアクリル系樹脂等からなるフレーム４２を仮固定し、フレーム４２の開口部１１内に半導体チップ３及び４を装入して粘着シート２上の所定の個所に仮固定する。従って、このフレーム４２は、上記したフレーム１２と同等の機能をなし、半導体チップの位置決めマークも設けられている。
【０１５５】
次に、図１３（ｃ）に示すように、フレーム４２を溶解することによって、半導体チップ３及び４の少なくとも側面同士をフレーム４２の溶解によって形成された保護物質層６によって接合する。
【０１５６】
次に、図１３（ｄ）に示すように、保護物質層６及び半導体チップ３及び４を覆うように、接着剤層３８を塗布して金属板７を接着するか、或いは接着剤層３８付きの金属板７を接着する。
【０１５７】
その後、図９（ｆ）〜図１２（ｒ）の工程とほぼ同様の工程を経て、チップ状電子部品１９を実装基板３０上に実装する。
【０１５８】
本実施の形態においては、フレーム４２を溶解することによって、半導体チップ３及び４の側面同士をフレーム４２の溶解物からなる保護物質層６で接合するため、保護物質の使用量が少なくなり、半導体チップ３、４及び保護物質層６からなる疑似ウェーハ１４の反りを抑制することができると共に、疑似ウェーハ１４の作製工数を減らすことができる。
【０１５９】
その他、本実施の形態においては、上述の第１又は第２の実施の形態で述べたのと同様の作用及び効果が得られる。
【０１６０】
以上に説明した実施の形態は、本発明の技術的思想に基づいて更に変形が可能である。
【０１６１】
例えば、金属板７については、半導体チップ３及び４の背面の全面に形成する必要はなく、例えば、フレーム１２の開口部１１上のみに部分的に形成されてもよい。金属板７の材質は様々であってよく、また金属以外の導電体を用いてもよい。
【０１６２】
また、フレーム１２を用いる場合に、シールド構造が必要であって金属板７が形成される部分と、シールド構造が不要であって金属板７が形成されない部分とが、同一フレーム１２内に存在してもよい。シールド構造が不要な部分（シールドが不要な半導体チップのエリア）においては金属板７が存在しないために、この部分から得られたチップ状電子部品を背面から研削して薄型化し易くなる。
【０１６３】
また、フレーム１２の開口部１１内に装入する半導体チップの数は２以上の複数個であってよいが、単数であってもよい。フレーム１２に設ける位置決め手段は、上述の凹部以外にも印刷等によって形成してよい。
【０１６４】
また、上述の実施の形態において、フレーム１２の表面に設けられた位置合わせマーク１３は、疑似ウェーハ１４を切断してチップ状電子部品１９とした後もチップ状電子部品１９中にフレーム１２と共に残されてよい。
【０１６５】
また、配線保護層１６やランド開口１７を設けた図３（ｍ）の状態でランド開口１７にはんだバンプを一括して形成した後、ダイシングを行うこともできる。
【０１６６】
また、本発明を適用する対象は半導体チップに限ることはなく、個々のチップへの切断を伴う他の各種チップ状電子部品であってもよい。
【０１６７】
【発明の作用効果】
本発明は、上述したように、前記電極面とは反対側の面において前記保護物質層上に導電層が形成されているために、前記チップ状電子部品に対する外部からのノイズを前記導電層を通して放出することができ、良好なシールド効果を得ることができると共に、チップ状電子部品とシールド手段とを一体化して小型化、薄型化することができ、しかもこれをシールド手段の後付け工程なしに簡易な構造で実現することができる。
【０１６８】
また、先願発明と同様に、例えば、良品のチップ部品を再配列して疑似ウェーハとするので、あたかも全品が良品のチップからなるウェーハが得られるため、ウェーハ一括での配線形成及びはんだバンプ処理等も可能になり、低コストのフリップチップ用のチップ状電子部品を作製でき、自社製チップのみならず、他社から購入したベアチップでも容易に配線形成及びはんだバンプ処理等が可能になる。そして、チップ状電子部品を疑似ウェーハから切り出す際に、前記チップ部品間の（側面）を切断するので、チップ部品本体への悪影響（歪みやばり、亀裂等のダメージ）が抑えられる。また、前記保護物質層によって少なくともチップ側面が覆われているので、Ｎｉ等の無電解めっき処理も可能であると共に、前記保護物質層によって少なくともチップ側面が保護されているので、個片化後のチップ状電子部品の実装ハンドリングにおいてもチップが保護され、良好な実装信頼性が得られる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態によるチップ状電子部品の作製工程を順次示す断面図である。
【図２】同、作製工程を順次示す断面図である。
【図３】同、作製工程を順次示す断面図である。
【図４】同、作製工程を順次示す断面図である。
【図５】同、作製工程を順次示す断面図である。
【図６】同、チップ状電子部品の実装工程を含む断面図である。
【図７】同、フレームの平面図（ａ）及び断面図（ｂ）である。
【図８】同、上部カメラ及び下部カメラによる位置検出を行うときの断面図である。
【図９】本発明の第２の実施の形態によるチップ状電子部品の作製工程を順次示す断面図である。
【図１０】同、作製工程を順次示す断面図である。
【図１１】同、作製工程を順次示す断面図である。
【図１２】同、チップ状電子部品の実装工程を含む断面図である。
【図１３】本発明の第３の実施の形態によるチップ状電子部品の作製工程を順次示す断面図である。
【図１４】従来例によるチップ状電子部品の作製工程を順次示す断面図である。
【図１５】同、ＭＣＭ化された実装構造の一部断面側面図（ａ）及び（ｂ）である。
【図１６】同、ウェーハ一括処理に対処する半導体ウェーハの斜視図である。
【図１７】先願発明によるチップ状電子部品の作製工程を順次示す断面図である。
【図１８】同、作製工程を順次示す断面図である。
【図１９】同、作製工程を順次示す断面図である。
【図２０】同、チップ状電子部品の実装工程を含む断面図である。
【符号の説明】
１…基板、２…粘着シート、３、４…半導体チップ、５…電極パッド、
６…保護物質層、７…金属板（金属層）、９…層間絶縁膜、１０…ビアホール、１１…開口部、１２…フレーム、１３…位置合わせマーク、
１４…疑似ウェーハ、１５…配線、１６…配線保護層、１７…ランド開口、
１８…ブレード、１９…チップ状電子部品、２０…ダイシング、
２１…スクライブライン、２２…パッシベーション膜、２３…ＳｉＯ２膜、
２４…シリコン基板、２５…無電解めっき層、２６…ランド、
２７…印刷マスク、２８…はんだペースト、２９…はんだバンプ、
３０…実装基板、３１…ソルダー（はんだ）レジスト、
３２…ソルダー（はんだ）ペースト、３３…電極、３４…基板、
３５…上部カメラ、３６…下部カメラ、３７…真空チャック、３８…接着剤層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip-shaped electronic component suitable for manufacturing a semiconductor device and a method for manufacturing the same, a pseudo wafer used for the manufacturing, and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, there is a strong demand for smaller, thinner, and lighter portable electronic devices such as digital video cameras, digital cellular phones, and notebook PCs (Personal Computers), and how to increase the surface mounting density of semiconductor components. The important point is whether to do it.
[0003]
For this reason, a smaller CSP (Chip Scale Package), which replaces a package IC (QFP (Quad Flat Package), etc.), has already been developed or adopted in some parts. Considering this, it is strongly desired to spread the connection technology using the bare chip and the flip chip method.
[0004]
Furthermore, with the recent increase in the operation speed of LSIs (Large Scale Integrated Circuits) and the reduction in voltage, the connection between a semiconductor chip and an interposer or a motherboard has been aimed at shortening the wiring path and reducing the wiring resistance. The use of the flip-chip connection described above is increasing.
[0005]
For such flip-chip connection using a bump forming technique in flip-chip mounting, for example, a solder bump is formed on a connection pad of a semiconductor chip, and then the solder is again melted by heat to form a mounting board which is a motherboard. A connection method, a method of forming an Au bump on an Al electrode pad by an Au-Stud Bump method, an electrolytic plating method, or the like, and then a method of connecting to a motherboard by using an anisotropic conductive film, an electrolytic plating method, or a vapor deposition method A typical method is to collectively form solder bumps by a method or the like.
[0006]
However, in the case of consumer use, in the case of flip-chip mounting at a lower cost, bumps are formed in a wafer state at once instead of forming bumps after forming a chip (Au-Stump Bump method is a typical example). A forming method is desirable.
[0007]
In view of the recent tendency of the wafer to increase in diameter (150 mmφ → 200 mmφ → 300 mmφ) and the tendency of increasing the number of connection pins of LSI (Large Scale Integrated Circuit) chips (to increase the number of pins), It is a natural direction.
[0008]
Hereinafter, a conventional bump forming method will be described.
[0009]
FIG. 14 shows a process of forming bumps in a batch of wafers by Ni electroless plating and printing of a solder paste, aiming at lower cost. FIG.2This shows a silicon substrate (wafer) on which a film is formed, and FIG. 2B is an enlarged view of a chip portion including the electrode. 14A and 14B, 85 is a silicon substrate (wafer), 65 is an Al electrode pad, and 84 is SiO2Film, 83 is Si3N4, SiO2This is a passivation film made of a film, a polyimide film, or the like.
[0010]
In FIG. 14C, a Ni electroless plating layer (UBM: Under Bump Metal) 72 is selectively formed only on the upper surface of the opened Al electrode pad 65 by the Ni electroless plating method. The Ni electroless plating layer (UBM) 72 is obtained by pre-treating the surface of the Al electrode pad 65 with a phosphoric acid-based etchant, substituting and depositing Zn by Zn treatment, and further immersing the Ni-P plating bath. It can be easily formed and acts as a UBM to help connect the Al electrode pad 65 and the solder bump.
[0011]
FIG. 14D shows a state where the solder paste 74 is transferred onto the Ni electroless plating layer (UBM) 72 by a printing method with a print mask 73 (metal screen) applied. FIG. 14E shows a state in which the solder paste 74 is melted by a wet back (heating and melting) method to form a solder bump 75. As described above, by using the Ni electroless plating method, the solder paste screen printing method, or the like, the solder bumps 75 can be easily formed without using a photo process.
[0012]
On the other hand, the CSP is an approach of reducing the size of each LSI and mounting it at a high density. However, when looking at circuit blocks of digital equipment, CSP is composed of several common circuit blocks. A technology for making a multi-chip package or a module (MCM: Multi Chip Module) has also appeared. An example is a package of an SRAM (Static RAM), a flash memory, and a microcomputer in a digital mobile phone.
[0013]
This MCM technology is expected to exert a great advantage even in recent one-chip system LSI. That is, when memory, logic, and analog LSI are integrated into one chip, different LSI processing processes are processed by the same wafer process, so that the number of masks and processing constants significantly increase, and the development TAT (Turn around time) increases. Is a problem, and a decrease in yield is also a major concern.
[0014]
For this reason, a method in which each LSI is individually manufactured and converted to MCM is considered to be promising. FIG. 15 shows an example of such an MCM technology.
[0015]
FIGS. 15A and 15B show a flip-chip system in which semiconductor chips 53 and 54 are connected face-down to electrodes 78 on a wiring board (circuit board) 79 and fixed with an underfill material 95. I have. Here, when miniaturization and thinning are considered, the flip chip of FIG. 15 is an advantageous method. Considering the reduction of the connection distance and the variation of each connection impedance in future high-speed operation, the flip-chip method seems to be the main method.
[0016]
As the flip-chip type MCM, for example, for a plurality of different types of LSIs, an Au-Stud Bump is formed on the surface of the Al electrode pad 65 of each LSI, and an anisotropic conductive film (ACF: Anisotropic Conductive Film) is formed. Various methods have been proposed, such as a method of connecting to a circuit board via a via, a method of pressure contact using a resin paste, and a method of using an Au plating bump, a Ni electroless plating bump, and a solder bump as a bump.
[0017]
FIG. 15B shows an example in which the metal can be bonded to the wiring board 79 with the solder bumps 75 at a lower resistance and can be reliably connected.
[0018]
The above-described method of forming solder bumps on a wafer at a time can be applied to area pad arrangement on a mounting surface, and has advantages such as batch reflow and double-sided mounting. However, when processing is performed on a wafer having a low cutting-edge yield, the cost per good chip becomes extremely high.
[0019]
That is, FIG. 16 shows a semiconductor wafer 99 in the conventional wafer batch processing. Although a high yield is required in a state-of-the-art LSI, among the chips separated by the scribe line 71, crosses are used. Actually, the number of defective bare chips 97 shown is larger than the number of good bare chips 98 shown by a mark.
[0020]
Further, there is a problem that it is extremely difficult to form a bump when a chip is obtained from another place in the form of a bare chip. That is, although the above two types of bump forming methods have their respective characteristics, they are not technologies that can be used for all areas, and at present, they are selectively used taking advantage of each characteristic. The wafer batch bump processing method is characterized by high yield, a large number of terminals in one wafer (for example, 50,000 terminals / wafer), and formation of low-damage bumps corresponding to area pads. Au stud bumps are characterized by bump processing when obtained in chip units and simple bump processing.
[0021]
When the semiconductor wafer 99 shown in FIG. 16 is cut along the scribe line 71, the chip may be damaged due to stress, cracks, or the like due to the cutting, which may cause a failure. Furthermore, if the process is performed for the non-defective bare chip 98 and the defective bare chip 97 together as a semiconductor wafer 99 until the formation of the solder bumps, the process performed on the defective bare chip 97 becomes useless, which also increases the cost. .
[0022]
Further, in the above-described connection method using solder bumps, it is necessary to form solder bumps on a semiconductor chip in advance, and thus the following problems are raised.
[0023]
For example, the lead time of the manufacturing process from the process of manufacturing a semiconductor chip to the process of forming a solder bump becomes relatively long, and the manufacturing cost increases. This tendency becomes more remarkable especially in a chip state in which a wafer including a plurality of semiconductor chips is divided into respective semiconductor chips.
[0024]
Also, in the formation of solder bumps, certain intervals must be provided in order to prevent adjacent solder bumps on the semiconductor chip from contacting each other and causing a short circuit, and a certain amount of space is required. In a semiconductor chip of a type in which the pitch between adjacent electrode pads for connection to the bump is narrow, the structure becomes relatively unsuitable. This is contrary to the recent tendency to increase the number of pins, and is a problem.
[0025]
Therefore, the present applicant has already proposed a method and structure that solved the above-mentioned problem as Japanese Patent Application No. 2000-122112 (Japanese Patent Application Laid-Open No. 2001-308116). Name). Hereinafter, an example of a method and a structure based on the prior application invention will be described step by step with reference to FIGS.
[0026]
FIG. 17A shows a substrate 51 serving as a temporary support substrate. However, since the heating process for the substrate is performed at 400 ° C. or less, a less expensive glass substrate can be used. This substrate 51 can be used repeatedly.
[0027]
Next, as shown in FIG. 17B, an adhesive sheet 52 of a predetermined thickness, for example, made of an acrylic material, is applied to the substrate 51, the adhesive strength being reduced when heated to a certain temperature or higher.
[0028]
Next, as shown in FIG. 17 (c), a plurality of semiconductor (non-defective bare) chips 53 and 54, which have been confirmed as non-defective products, are arranged with the surface where the electrode pads 65 are exposed downward, and an adhesive sheet 52 is formed. Paste on top.
[0029]
These non-defective semiconductor chips 53 and 54 may be diced in the process of the normal semiconductor wafer 99 shown in FIG. 17, and may be taken out from the stretched state of the used dicing sheet (not shown). It may be transferred from the tray.
[0030]
What is important here is that only good semiconductor chips 53 and 54 are rearranged on the substrate 51 irrespective of chips made by the company or other companies.
[0031]
Next, as shown in FIG. 17D, a protective material such as an organic insulating resin, for example, an epoxy-based or acrylic-based material is uniformly applied from above the chips 53 and 54 to form a protective material layer 55. This application step can be easily realized by a spin coating method, a printing method, or the like.
[0032]
Next, as shown in FIG. 17 (e), by heating to a certain temperature or more, the adhesive force of the adhesive sheet 52 is weakened, and a plurality of the side surfaces and the back surface are continuously solidified by the protective material layer 55. The pseudo wafer 67 including the good semiconductor chips 53 and 54 is peeled off from the substrate 51.
[0033]
Next, as shown in FIG. 17F, the pseudo wafer 67 peeled off from the substrate 51 is turned upside down so that the electrode pads 65 of the semiconductor chips 53 and 54 come to the upper surface.
[0034]
Next, as shown in FIG. 17G, an interlayer insulating film 56 is formed on the upper surface of the pseudo wafer 67.
[0035]
Next, as shown in FIG. 17H, a hole 57 for forming a wiring is formed in the interlayer insulating film 56 and a part of the upper surface of the electrode pad 65 is formed on the electrode pad 65 of each of the semiconductor chips 53 and 54. Provided to be exposed.
[0036]
Next, after a wiring material is applied to the upper surface of the interlayer insulating film 56 and the hole 57, as shown in FIG. 18I, a predetermined wiring pattern 57 is formed using a photoresist or the like.
[0037]
Next, as shown in FIG. 18J, a wiring protection layer 58 is formed so as to cover the rearrangement wiring 57 formed in a predetermined pattern.
[0038]
Next, as shown in FIG. 18K, a plurality of land openings 59 for taking out wiring are provided in the wiring protection layer 58 at predetermined positions so that a part of the upper surface of the wiring 57 is exposed.
[0039]
Next, as shown in FIG. 18 (l), a scribe line 71 is formed by a blade 68 (or laser) in units of a chip-shaped electronic component 69 formed by protecting and reinforcing the semiconductor chips 53 and 54 with a protective material layer 55. Is diced 70 along the individual pieces.
[0040]
FIG. 19 (m) is an enlarged view of the chip-shaped electronic component 69, and a detailed view mainly in the vicinity of the semiconductor chip 54 in the enlarged view. SiO on the substrate 852This has a structure in which an Al electrode pad 65 and a passivation film 83 are formed via a film 84.
[0041]
Next, as shown in FIG. 19N, a Ni electroless plating layer (UBM) 72 is formed in the land openings 59 by a Ni electroless plating method. The Ni electroless plating layer (UBM) 72 is, for example, after pre-treating the upper surface of the wiring 57 with a phosphoric acid-based etchant, substituting and depositing Zn by Zn treatment, and further immersing the Ni-P plating tank. Thereby, it can be easily formed, and functions as a UBM (Under Bump Metal) for assisting connection between the Al electrode pad 65 and a solder bump described later.
[0042]
Further, on the electroless plating layer 72, the lands 100 are continuously formed not only on the land openings 59 but also on the wiring protection layer 58.
[0043]
Next, as shown in FIG. 19 (o), the solder paste 74 is transferred onto the land 100 by a printing method by applying a print mask 73.
[0044]
Next, as shown in FIG. 20 (p), the solder paste 74 is melted by a wet back method to form a solder bump 75. As described above, by using the Ni electroless plating method and the solder paste screen printing method, the solder bumps 75 can be easily formed without using a photo process.
[0045]
As described above, even for the most advanced LSIs with low yield or chips obtained from other companies, only the good semiconductor chips 53 and 54 are attached to the substrate 51, and as if they were 100% good semiconductor chips 53 and 54. A pseudo wafer 67 composed of only the dummy wafer 67 can be manufactured. For this reason, it is possible to form low-cost solder bumps on the whole wafer in the state shown in FIG.
[0046]
In the state of FIG. 18 (i), measurement of electrical characteristics by probe inspection and burn-in were performed to select good semiconductor chips 53 and 54 before the step of FIG. 17 (c). Thereby, only good chips can be sorted out.
[0047]
Next, as shown in FIG. 20 (q), the mounting substrate 60 is provided with an electrode 78 which is surrounded by a solder (solder) resist 76 on a substrate 79 and provided with an electrode 78 to which a solder (solder) paste 77 is applied. The mounted chip-shaped electronic component 69 is mounted.
[0048]
At this time, since the side and back surfaces of the chip-shaped electronic component 69 are covered with the protective material layer 55, the chips 53 and 54 are directly handled during handling such as suction of the chip-shaped electronic component 69 during mounting on the mounting board 60. Since there is no damage, high reliability flip-chip mounting can be expected.
[0049]
Although the above description relates to the flip chip mounting technology of the semiconductor chip, it also relates to the technology of forming the solder bumps for connection in the flip chip high density mounting and the manufacturing method thereof. The chips 53 and 54 are fixed to each other by applying the protective material layer 55 uniformly on the back surface or the like, with the front surface facing down and being arranged on the substrate 51 at equal intervals.
[0050]
Thereafter, the dummy sheet is peeled off from the adhesive sheet 52 to produce a pseudo wafer 67 in which only the good semiconductor chips 53 and 54 are arranged, and bumps are formed on the wafer 67 at a time, so that bump chips can be manufactured at low cost. . This bump chip can be used not only for small and lightweight portable electronic devices but also for all electronic devices.
[0051]
According to the above-described steps, the chip-shaped electronic components (such as the semiconductor chips 53 and 54) 69 and the like (hereinafter, a semiconductor chip will be described as a representative example) 69 other than the electrode pad 65 surface (that is, the side surfaces and the back surfaces of the chips 53 and 54). Are protected by the continuous protective material layer 55, so that the chips 53 and 54 are protected in handling after chip formation, which facilitates handling and obtains good mounting reliability.
[0052]
Also, the semiconductor chips 53 and 54 cut out from the above-described semiconductor wafer 99 and selected only for non-defective products are adhered to the substrate 51, and the protective material layer 55 is applied over the entire surface and then peeled off. Since the pseudo wafer 67 including only the semiconductor chips 53 and 54 is obtained, it is also possible to perform wiring formation, bump processing, and the like on the whole wafer.
[0053]
Further, when the chips 53 and 54 are cut out from the pseudo wafer 67, the portion of the protective material layer 55 between the chips is cut, so that the semiconductor chips 53 and 54 have an adverse effect (damage such as distortion, burrs, cracks, etc.). And can be easily cut.
[0054]
In addition, since the side and back surfaces of the chips 53 and 54 are covered with the protective material layer, Ni electroless plating can be performed. Then, not only in-house manufactured wafers but also bare chips purchased from other companies can be easily solder bumped.
[0055]
In addition, there are few cases where all the different LSI chips mounted on the MCM are supplied from the same semiconductor maker, and investment in the most advanced semiconductor lines is increasing. Instead of supplying the arithmetic processing units) by the same semiconductor maker, they may be separately supplied by a chip from a semiconductor maker that is good at each, and these may be converted into MCM.
[0056]
The above substrate can be used repeatedly, which is advantageous in terms of bump formation cost and environment.
[0057]
Further, in the above-described process, the manufacturing process of the semiconductor chips 53 and 54 is performed as a separate process, and only the chips 53 and 54 that have already been determined to be non-defective are used. The lead time, inspection time, and the like of the manufacturing process before the step of forming the semiconductor device can be relatively shortened, and increase in manufacturing cost can be suppressed.
[0058]
In the formation of solder bumps, certain intervals must be provided to prevent short-circuiting due to contact between adjacent solder bumps on the semiconductor chip, and a certain amount of space is required. As shown in FIG. 2), the degree of freedom in the formation position of the solder bumps is increased by the arrangement shape of the wiring 57, the land 100, and the like. Also, the pitch of the electrode pads can be made shorter and the density can be increased, so that the number of pins can be increased.
[0059]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2001-308116 and drawings (columns 6 to 11, FIGS. 1 to 3)
[0060]
[Problems to be solved by the invention]
However, although the above-mentioned prior invention has the above-mentioned excellent features, it has been found that there are still the following problems to be improved.
[0061]
That is, in particular, when the RF (Radio Frequency) -based LSI chip-shaped electronic component 69 is used, it is necessary to cut off the electrical noise generated between the electronic component and other LSI electronic components to prevent malfunction and the like. In many cases, the entire chip-shaped electronic component 69 is covered with a shield case.
[0062]
In recent years, miniaturization of LSI packages such as CSPs has been rapidly progressing for the purpose of miniaturization and weight reduction. However, mounting a shield case as described above makes it possible to increase the mounting area of a miniaturized LSI package. In addition, the number of processes such as retrofitting of the shield case increases, and the cost increases.
[0063]
Accordingly, an object of the present invention is to provide a chip-shaped electronic component which can effectively realize a noise with respect to the chip-shaped electronic component by utilizing a feature of the invention of the prior application, and which can be easily realized by a simple structure, and a manufacturing method thereof. It is an object of the present invention to provide a method, a pseudo wafer used for manufacturing the same, and a method for manufacturing the same.
[0064]
[Means for Solving the Problems]
That is, the present invention
Fixing a plurality or a plurality of types of chip components on the support,
Forming a protective material layer by applying a protective material to at least a side surface of the chip component,
Forming a conductive layer on the protective material layer,
A step of peeling off the chip component to which the protective material layer is applied from the support;
The present invention relates to a method for manufacturing a pseudo wafer having
Forming an interlayer insulating film and a connection hole on the electrode surface of the chip component;
Providing a conductive connection material in the connection hole;
A step of cutting between the plurality or types of chip components to obtain a chip-shaped electronic component;
And a method for manufacturing a chip-shaped electronic component.
[0065]
The present invention also provides that a plurality or a plurality of types of chip components are integrated by a protective material layer applied to at least a side surface other than the electrode surface, and the protective material layer is provided on a surface opposite to the electrode surface. Providing a pseudo-wafer having a conductive layer applied thereon, and also obtained from the pseudo-wafer, wherein the protective material layer is applied on at least a side surface other than the electrode surface of the chip component, wherein the electrode surface is provided. The present invention also provides a chip-shaped electronic component in which the conductive layer is formed on the protective material layer on the side opposite to the above.
[0066]
According to the present invention, since a conductive layer is formed on the protective material layer on a surface opposite to the electrode surface, external noise to the chip-shaped electronic component is emitted through the conductive layer. In addition to obtaining a good shielding effect, the chip-shaped electronic component and the shielding means can be integrated to reduce the size and thickness, and this can be achieved with a simple structure without a step of attaching the shielding means. Can be realized.
[0067]
Also, as in the prior invention, for example, since a non-defective chip component is rearranged into a pseudo wafer, a wafer composed of all non-defective chips can be obtained. This makes it possible to produce a low-cost flip-chip chip-shaped electronic component, and it is possible to easily perform wiring formation, solder bump processing, and the like not only on in-house manufactured chips but also on bare chips purchased from other companies.
[0068]
Then, when the chip-shaped electronic component is cut out from the pseudo wafer, the chip components are cut between the side surfaces (side surfaces), so that adverse effects on the chip component main body (damage such as distortion, burrs, cracks, etc.) are suppressed.
[0069]
In addition, since at least the chip side surface is covered by the protective material layer, electroless plating of Ni or the like can be performed, and at least the chip side surface is protected by the protective material layer. The chip is protected during the mounting handling of the chip-shaped electronic component, and good mounting reliability is obtained.
[0070]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, in order to prevent deformation of the pseudo wafer (and thus chip-shaped electronic components) due to a difference in thermal expansion coefficient between the protective material layer and the chip components during formation of the protective material layer, the chip components are After fixing a frame having an opening for loading on the support, the chip component is loaded into the opening of the frame and fixed on the support, and after the fixing, the opening is opened. It is desirable to apply the protective substance so as to cover at least a side surface of the chip component in the unit.
[0071]
In this case, in order to improve a shielding effect on the chip-shaped electronic component, it is preferable that the frame is formed of a conductive material and is in contact with the conductive layer.
[0072]
Further, the application of the protective substance may be performed by printing or physical vapor deposition.
[0073]
Further, it is desirable that the conductive layer be electrically extracted on the electrode surface via the conductive connection material.
[0074]
In addition, it is desirable that the plurality of or a plurality of types of chip components be connected to each other through the connection holes by wiring made of the conductive connection material.
[0075]
Further, in order to increase the degree of freedom in selecting the formation position of the external connection terminal such as a solder bump, a second interlayer insulating film is formed on the wiring made of the conductive connection material. It is preferable that the wiring be electrically extracted through a second connection hole formed in the interlayer insulating film.
[0076]
In addition, in order to easily and accurately position the chip component on the support, it is desirable to form the chip component positioning means in the frame near the opening. This positioning means may be left on the surface of the conductive material layer in the chip-shaped electronic component.
[0077]
Further, in order to obtain a shielding effect by grounding the conductive layer, the conductive material layer is applied to an outer surface of the protective material layer applied to a side surface of the chip component. Desirably, it is in contact with the conductive layer.
[0078]
In this case, an interlayer insulating film is formed on the electrode surface of the chip component, a conductive connection material is provided in a connection hole formed in the interlayer insulating film, and the conductive layer is formed through the conductive connection material. It may be electrically extracted on the electrode surface.
[0079]
Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
[0080]
First embodiment
1 to 6 sequentially show a process of manufacturing the pseudo wafer 14 and the chip-shaped electronic component 19 and a process of mounting the chip-shaped electronic component 19 according to the present embodiment.
[0081]
FIG. 1A shows a substrate 1 serving as a temporary support substrate. However, since the heating process for the substrate 1 can be performed at 400 ° C. or less, an inexpensive glass substrate can be used as the substrate 1. The substrate 1 can be used repeatedly.
[0082]
Next, as shown in FIG. 1B, an adhesive sheet 2 having a predetermined thickness, for example, made of an acrylic material, is applied to the substrate 1 so that the adhesive strength is reduced when heated to a certain temperature or higher.
[0083]
Next, as shown in FIG. 1C, a frame 12 made of a conductive material such as copper having an opening 11 into which the semiconductor chips 3 and 4 are inserted is attached on the adhesive sheet 2 (details will be described later). And fix it temporarily. At this time, the position of the opening 11 generally corresponds to the position where the semiconductor chips 3 and 4 are attached, and the attachment accuracy is not particularly limited as long as the frame 12 is within the surface of the substrate 1.
[0084]
Here, the shape, size, material, sticking method, sticking position, and the like of the frame 12, and the shape, size, number, and the like of the openings 11 are arbitrarily determined according to the sticking positions of the semiconductor chips 3, 4, and the like. You can choose.
[0085]
Next, as shown in FIG. 1D, a plurality of semiconductor (non-defective bare) chips 3 and 4 which have been confirmed as non-defective products are inserted into the opening 11 of the frame 12 with the surface where the electrode pads 5 are exposed downward. And is adhered to a predetermined position on the adhesive sheet 2 in the opening 11.
[0086]
The good semiconductor chips 3 and 4 may be obtained by dicing a normal semiconductor wafer 99 into each semiconductor chip as described with reference to FIG. 16, but each good semiconductor chip is formed by stretching a dicing sheet (not shown). It may be taken out of the state or transferred from the chip tray.
[0087]
As described above, when the semiconductor chips 3 and 4 are mounted (temporarily fixed) in the designated positions in the openings 11 of the frame 12, alignment marks (not shown here) previously provided on the upper surface of the frame 12. , It is possible to secure the accuracy of the fixed position of the semiconductor chips 3 and 4 over a wide range of the whole on the substrate 1.
[0088]
In addition, this eliminates the need to use the substrate 51 with a dedicated alignment mark that can be used in the prior invention shown in FIG. 17, and therefore, a versatile and inexpensive substrate can be used as the substrate 1 to be used. This makes it possible to reduce costs.
[0089]
Next, as shown in FIG. 1E, a protective substance made of, for example, an organic insulating resin, for example, an epoxy resin, is poured from the opening 11 onto the chips 3 and 4, and the protective material layer 6 is formed for each opening. Formed. The protective material layer 6 has such an amount as to cover the side surfaces and further the upper surfaces of the semiconductor chips 3 and 4, and is generally formed by a dispensing method (in some cases, a printing method or the like). The material of the protective material layer 6 is preferably an epoxy resin, but may be an acrylic resin or the like, and the material is limited as long as it can protect the semiconductor chips 3 and 4 from mechanical shock or humidity. There is no.
[0090]
Here, in the prior invention shown in FIG. 17, in addition to the function of fixing the semiconductor chip, the protective material layer 55 has a structure of the entire pseudo wafer 67 in which a plurality or a plurality of types of semiconductor chips are connected. Although the function is also provided, in the present embodiment, it is sufficient to mainly fulfill the fixing function between the frame 12 and the semiconductor chips 3 and 4, so that the amount of the protective substance 6 used is minimized. It is possible to However, it is preferable that a protective substance is applied between the semiconductor chips 3 and 4 in order to completely fix the chips, but it is not always necessary.
[0091]
As described above, since the amount of the protective material layer 6 is drastically reduced, the internal stress that tends to occur when the chip is fixed by pouring the protective material is weakened due to the difference in the coefficient of thermal expansion between the semiconductor chip and the protective material layer, As will be described later, the amount of warpage of the pseudo wafer 14 after the pseudo wafer 14 is separated from the substrate 1 can be significantly reduced, and the flatness of the pseudo wafer 14 can be maintained. As a result, it is possible to dramatically improve the workability, yield, and the like when forming the wiring in a later step.
[0092]
Next, as shown in FIG. 2F, a flat metal plate 7 such as copper is attached on the frame 12. At this time, an adhesive (not shown) made of a conductive paste may be used for joining the frame 12 and the metal plate 7.
[0093]
Here, the material of the metal plate 7 is not particularly limited as in the case of the material of the frame 12. In addition, since the frame 12 and the metal plate 7 need to be electrically connected for shielding, the form in which the frame 12 is bonded with a conductive paste is described in FIG. There is no particular limitation on the connection method as long as it is possible and a bonding method can be obtained.
[0094]
Further, in place of the metal plate 7, for example, a metal layer formed by a metallizing method, a plating method, a sputtering method, a vapor deposition method, or the like may be used. In short, any conductive layer formed by various methods other than the attachment of the metal plate may be used. The metal plate 7 may be solid or may be formed in a predetermined pattern.
[0095]
Next, as shown in FIG. 2 (g), in a state where the adhesive force of the adhesive sheet 2 is reduced by heating the adhesive sheet 2 to a certain temperature or higher, the protective material layer 6, the frame 12 and the metal plate 7 are used to form the side and back surfaces. The pseudo wafer 14 composed of a plurality of non-defective semiconductor chips 3 and 4 covered with, for example, is separated from the substrate 1 to complete the process of manufacturing the pseudo wafer 14.
[0096]
At this time, since the amount of the protective material layer 6 is reduced as described above, the amount of warpage of the pseudo wafer 14 is significantly reduced, and the metal plate 7 (or the metal layer) has a certain degree of rigidity. Therefore, the warpage of the pseudo wafer 14 can be further suppressed.
[0097]
Next, as shown in FIG. 2H, the pseudo wafer 14 peeled from the substrate 1 is turned upside down so that the exposed surfaces of the electrode pads 5 of the semiconductor chips 3 and 4 are on the upper side.
[0098]
Next, as shown in FIG. 2I, an interlayer insulating film 9 is formed on the upper surface of the pseudo wafer 14 by a coating method, a chemical vapor deposition method, or the like. Here, the thickness, material, forming method and the like of the interlayer insulating film 9 may be arbitrarily selected.
[0099]
Next, as shown in FIG. 2 (j), via holes 10 for forming wiring are formed in the interlayer insulating film 9 by photolithography, and a part of the upper surface of the electrode pad 5 of each of the semiconductor chips 3 and 4 is exposed. Let it. At the same time, a via hole 10 is also formed on the frame 12 through the interlayer insulating film 9 to expose a part of the upper portion of the frame 12.
[0100]
Here, the size, position, number, formation method, and the like of the via holes 10 can be determined according to the arrangement of the semiconductor chips 3 and 4 and the like.
[0101]
Next, as shown in FIG. 3 (k), after a wiring material is deposited on the upper surface of the interlayer insulating film 9 and in each via hole 10 by a vacuum evaporation method or a sputtering method, a wiring of a predetermined pattern is formed by a photolithography technique. 15 are formed to be used as MCM wiring for connecting the respective chips or as wiring for forming external terminals.
[0102]
For example, after the interlayer insulating film 9 is applied on the pseudo wafer 14 and the via holes 10 are opened in the necessary portions on the electrode pads 5 and the necessary portions on the frame 12 in the interlayer insulating film 9, for example, by a semi-additive method or the like. The wiring 15 is formed.
[0103]
Next, as shown in FIG. 3 (l), a wiring protection layer 16 as a cover coat is formed so as to cover the rearrangement wiring 15 formed in a predetermined pattern. Here, the thickness, material, forming method and the like of the wiring protection layer 16 may be arbitrarily selected.
[0104]
Next, as shown in FIG. 3 (m), a land opening 17 for taking out a wiring required for connection with the outside is formed in a predetermined position on the wiring 15 in the wiring protection layer 16 and one of the upper surfaces of the wiring 15 is formed. Expose the part. Here, the size, quantity, forming method, and the like of the land openings 17 may be arbitrarily selected.
[0105]
Thus, a structure is formed in which the side surfaces of the semiconductor chips 3 and 4 are adhered to the frame 12 via the protective material layer 6 and the back surfaces of the semiconductor chips 3 and 4 are covered with the protective material layer 6 and the metal plate 7.
[0106]
Next, as shown in FIG. 4 (n), at the position of the frame 12, the metal plate 7 and the frame 12 are cut along a scribe line 21 by a blade 18 (or a laser or the like), and dicing 20 is performed. The semiconductor chips 3 and 4 are divided into units each of which is covered with the protective material layer 6, the frame 12, and the metal plate 7.
[0107]
The chip-like electronic component 19 thus obtained electrically connects (grounds) the metal plate 7 to the ground via the frame 12, the wiring 15, and the land opening 17 on the frame 12, as described later. Thus, a structure in which the entire chip-shaped electronic component 19 is surrounded by the shield layer composed of the frame 12 and the metal plate 7 is formed, and the same structure and effect as when the chip-shaped electronic component 19 is surrounded by the shield case can be obtained. However, the shield structure including the frame 12 and the metal plate 7 is much thinner and smaller than the shield case.
[0108]
FIG. 4 (o) is an enlarged view of the chip-shaped electronic component 19 and a detailed view mainly around the semiconductor chip 4. The semiconductor chip 4 (semiconductor chip 3 is also the same)2It has a structure in which an Al electrode pad 5 and a passivation film 22 are formed via a film 23.
[0109]
Next, as shown in FIG. 5 (p), a Ni electroless plating layer (UBM) 25 is formed in the land opening 17 by a Ni electroless plating method. In addition, this Ni electroless plating layer (UBM) 25 is, for example, after pre-treating the upper surface of the wiring 15 with a phosphoric acid-based etchant, substituting and depositing Zn by Zn treatment, and further immersing in a Ni-P plating tank. Thereby, it can be easily formed, and functions as a UBM (Under Bump Metal) which assists connection between the Al electrode pad 5 and a solder bump described later.
[0110]
Further, a land 26 is formed not only on the land opening 17 but also on the wiring protection layer 16 so as to be connected to the electroless plating layer 25.
[0111]
Here, the wiring including the electroless plating layer 25 and the land 26 is useful for rearranging the position of the external terminal and the like. Further, since the land 26 including the wiring 15 has a structure in which the interposer is built up without using a so-called interposer substrate, a wiring structure for rearrangement can be easily formed with high accuracy. In addition, it is extremely advantageous that this can be basically formed by batch processing at the wafer level shown in FIG.
[0112]
Next, as shown in FIG. 5 (q), the solder paste 28 is transferred onto the land 26 by a printing method by applying a print mask 27.
[0113]
Next, as shown in FIG. 6 (r), the solder paste 28 is melted by a wet back method or the like to form a solder bump 29. As described above, by using the Ni electroless plating method, the solder paste screen printing method, or the like, the solder bumps 29 can be easily formed without using a photo process.
[0114]
As described above, even for the most advanced LSI with a low yield or a chip obtained from another company, only the good semiconductor chips 3 and 4 are attached to the substrate 1 as if they were 100% good semiconductor chips 3 and 4. The pseudo wafer 14 composed only of the dummy wafer 14 can be manufactured. In the state shown in FIG. 3 (m), low-cost solder bumps can be formed on the whole wafer.
[0115]
Then, in the state of FIG. 3 (k), measurement of electrical characteristics by probe inspection and burn-in were performed to select good semiconductor chips 3 and 4 before the step of FIG. 1 (d). Thereby, only good chips can be sorted out.
[0116]
Next, as shown in FIG. 6 (s), an individual substrate is provided on a mounting substrate 30 provided with an electrode 33 which is surrounded by a solder (solder) resist 31 and has a solder (solder) paste 32 applied thereon. The formed chip-shaped electronic component 19 is mounted. If solder bumps are formed instead of the solder paste 32, it is not necessary to form the solder bumps 29 on the chip-shaped electronic component 19.
[0117]
Since the side surface and the back surface of the chip-like electronic component 19 are covered and protected by the frame 12 and the metal plate 7 or the like, not only at the time of dicing shown in FIG. In the handling such as the suction of the chip-shaped electronic component 19 during mounting on the mounting board 30 shown in (1), the chips 3 and 4 are not damaged and the dicing and flip-chip mounting can be performed with high reliability.
[0118]
FIG. 7 illustrates the frame 12 used in the present embodiment shown in FIG. 1C in detail. Here, FIG. 7A shows a plan view of the frame 12, and FIG. 7B shows a cross-sectional view of the frame 12, but shows each part in detail as compared with FIG. 1C schematically shown. I have.
[0119]
For example, the frame 12 shown in FIG. 7 is formed by etching or pressing an opening 11 which is slightly larger than a chip area to which the semiconductor chips 3 and 4 indicated by broken lines are temporarily fixed in a plate made of a conductive material containing a metal such as Cu. It has been punched by a processing method or the like.
[0120]
The material of the frame 12 is not particularly limited as long as it can be applied to the above-described processing, but a material having conductivity, being inexpensive and suitable for mass processing is desirable.
[0121]
Simultaneously with the formation of the opening 11, one side of the frame 12 (the surface on which the semiconductor chips 3 and 4 are mounted) in the vicinity of the opening 11 is chip-mounted (temporarily fixed) in a chip area. It is desirable to form an alignment mark 13 as positioning means for alignment. This alignment mark 13 can be formed as a concave portion by, for example, circular half etching.
[0122]
In this case, since the alignment mark 13 determines the chip position accuracy between the modules that make up the semiconductor chips 3 and 4, the pitch between the alignment marks 13 is relatively accurately maintained. It is desirable to form by such a processing method.
[0123]
When each semiconductor chip is inserted and fixed at a predetermined position in the opening 11 as shown in FIG. 1D, the alignment mark 13 provided on the frame 12 as shown in FIG. Thus, the mounting position of each semiconductor chip is identified.
[0124]
That is, the position of the semiconductor chip 4 (or 3) sucked by the vacuum chuck 37 is detected by the upper camera 35, and the position of the alignment mark 13 of the frame 12 temporarily fixed on the substrate 1 is detected by the lower camera 36. Is detected.
[0125]
For example, the distance between the alignment mark 13 and another alignment mark 13 and the distance between the alignment mark 13 and the semiconductor chip are detected by the cameras 35 and 36, and based on the position information based on these detections. The semiconductor chips 3 and 4 can be inserted at regular positions in the opening 11 of the frame 12 in a regular direction, and can be temporarily fixed on the adhesive sheet 2 as shown by a broken line.
[0126]
In addition, the prior invention shown in FIGS. 17 to 20 also has the following problems as compared with the present embodiment.
[0127]
That is, since the protective material layer 55 as an insulating layer exists on the back surface (the surface opposite to the electrode pads 65) of the semiconductor chip of the obtained chip electronic component 69, the chip electronic component 69 The front side and the back side are insulated, and there is no intention to provide a conductive layer such as a wiring layer on the back side to form a circuit. Therefore, it is impossible to cover the chip-shaped electronic component 69 including the back surface side with the shield layer.
[0128]
When the semiconductor chips 53 and 54 are temporarily fixed on the adhesive sheet 52, the semiconductor chips 53 and 54 need to be arranged with relatively accurate positional accuracy in a wide area on the substrate 51. An alignment mark is arranged on the substrate 51 side on which the semiconductor chips 53 and 54 are mounted (temporarily fixed). It is necessary to change the position of the alignment mark for each size of the chip-shaped electronic component 69, and it is necessary to prepare a dedicated substrate 51 for each size of the chip-shaped electronic component 69. It is easy to be up.
[0129]
Further, the difference between the material of the semiconductor chips 53 and 54 (mainly, silicon) and the material of the protective material layer 55 (mainly, for example, epoxy resin), which has a large linear expansion and contraction during curing, is different from that of the protective material layer. After the separation of the dummy wafer 55 from the substrate 51 after the attachment, the warp of the pseudo wafer 67 becomes large, and this warp causes problems in wiring formation on the wafer and mounting of the chip-shaped electronic component 69, and also has a high transportability and a high yield. May inhibit.
[0130]
On the other hand, in the present embodiment, since the metal plate 7 is provided on the back surface of the chip-shaped electronic component 19 and is electrically grounded via the frame 12 and the wiring 15, the periphery of the chip-shaped electronic component 19 is shielded. As a result, malfunctions and the like of the semiconductor chips 3 and 4 due to external noise and the like can be sufficiently prevented.
[0131]
In this case, since the metal plate 7 and the frame 12 forming the shield structure and the chip-shaped electronic component 19 are integrated, the structure becomes smaller and thinner than when a shield case is retrofitted. The area is reduced, and the manufacturing process is simplified.
[0132]
Also, instead of providing a dedicated alignment mark for each of the semiconductor chips 3 and 4 on the substrate 1, a mounting (temporary fixing) position between the semiconductor chips 3 and 4 is determined by an alignment mark 13 provided on the frame 12. Since the accuracy can be secured, it is possible to expand the versatility of the substrate 1 and thereby reduce the cost.
[0133]
In addition, since the semiconductor chips are separated by the frame 12, which is a frame, the amount of the constituent material of the protective material layer 6 for fixing the semiconductor chips 3 and 4, for example, epoxy resin, can be reduced. By reducing the difference in the amount of thermal expansion or contraction between the semiconductor chips 3 and 4, the deformation of the pseudo wafer 14 can be suppressed. As a result, the warp of the pseudo wafer 14 can be reduced, wiring can be easily formed in a later process, the reliability of mounting can be improved, and the transportability and the yield can be improved.
[0134]
In this embodiment, a pseudo wafer 14 in which only non-defective semiconductor chips 3 and 4 are arranged can be manufactured, and wiring (and bump formation if necessary) can be collectively formed on the wafer 14. . This can be used for all electronic devices, not only small and lightweight portable electronic devices.
[0135]
Further, the surface of the chip-shaped electronic component 19 having the semiconductor chips 3 and 4 other than the electrode pad 5 surface (that is, the side and back surfaces of the chips 3 and 4) is protected by the frame 12, the metal plate 7, and the like. In handling, the chips 3 and 4 are protected, handling becomes easy, and good mounting reliability can be obtained.
[0136]
Further, when cutting out the chip-shaped electronic component 19 from the pseudo wafer 14, the portion of the frame 12 between the chips is cut, so that adverse effects on the semiconductor chips 3 and 4 (damage such as distortion, burrs, cracks, etc.) are suppressed. Can be easily cut.
[0137]
Moreover, since the side and back surfaces of the chips 3 and 4 are covered with the frame 12 and the metal plate 7, Ni electroless plating can be performed. Then, not only in-house manufactured wafers but also bare chips purchased from other companies can be easily solder bumped.
[0138]
In addition, there are few cases where all the different LSI chips mounted on the MCM are supplied from the same semiconductor maker, and investment in the most advanced semiconductor lines is increasing. Instead of supplying the arithmetic processing units) by the same semiconductor maker, they may be separately supplied by a chip from a semiconductor maker that is good at each, and these may be converted into MCM.
[0139]
Further, the above-mentioned substrate 1 can be used repeatedly, which is advantageous in terms of cost and environment.
[0140]
Furthermore, in the above-described process, the process of manufacturing the semiconductor chips 3 and 4 is performed as a separate process, and only the chips 3 and 4 that have already been determined to be non-defective are used. In addition to shortening the time up to the step of forming the substrate, the inspection time, and the like, the increase in the manufacturing cost can be suppressed.
[0141]
In the formation of solder bumps, a certain space must be provided to prevent short-circuiting due to contact between adjacent solder bumps on the semiconductor chip, and a certain amount of space is required. As shown in ()), the arrangement of the wirings 15 and the lands 26 increases the degree of freedom in the formation positions of the solder bumps. Even in a semiconductor chip in which the pitch between adjacent electrode pads 5 is narrow, the number of lands 26 is increased. Pinning can be realized.
[0142]
Second embodiment
In the present embodiment, as shown in FIGS. 9 to 11, the protective material layer 6 is formed by covering only the electrode surfaces of the semiconductor chips 3 and 4 with a protective material made of a resin, and the grounding of the metal layer 7 is performed. This is the same as the first embodiment except that the wiring 15 is formed through the protective material layer 6.
[0143]
That is, as shown in FIGS. 9A and 9B, the adhesive sheet 2 is attached on the substrate 1 in the same manner as in the steps shown in FIGS. 1A and 1B.
[0144]
Next, as shown in FIG. 9C, non-defective semiconductor chips 3 and 4 are attached to predetermined locations on the adhesive sheet 2 and temporarily fixed.
[0145]
Next, as shown in FIG. 9D, a protective material made of resin is applied so as to cover the semiconductor chips 3 and 4, thereby forming a protective material layer 6.
[0146]
Thereafter, as shown in FIGS. 9 (e) to 10 (h), a metal plate 7 is provided on the protective material layer 6 in the same manner as in the steps shown in FIGS. 2 (f) to 2 (i). Thereafter, the dummy wafer 14 is peeled off from the substrate 1 to form a pseudo wafer 14, and an interlayer insulating film 9 is formed on the electrode pads 5 of the pseudo wafer 14.
[0147]
Next, as shown in FIG. 10 (i), via holes 10 for wiring are formed in the interlayer insulating film 9 or the protective material layer 6 by photolithography technology, a part of the surface of each electrode pad 5 is exposed, and grounding is performed. A part of the surface of the metal plate 7 serving as a (shield) conductive layer is exposed.
[0148]
Next, as shown in FIG. 10J, each via hole 10 is filled with a wiring material and patterned to form a wiring 15.
[0149]
Next, as shown in FIGS. 10 (k) to 12 (r), the pseudo wafers 14 provided with the wirings 15 and the like are individually formed in the same manner as in the steps of FIGS. 3 (l) to 6 (s) described above. The chip-shaped electronic component 19 is cut into pieces, and solder bumps 29 and the like are formed on the chip-shaped electronic component.
[0150]
According to the present embodiment, the metal layer 7 can be grounded by the wiring 15 through the protective material layer 6 without using the frame 12 in the first embodiment, and the protective material between the semiconductor chips 3 and 4 can be used. Since the chip-shaped electronic component 19 is formed by cutting the layer 6 together with the metal layer 7, the cutting of the pseudo wafer 14 is relatively easy.
[0151]
Further, since the pseudo wafer 14 shown in FIG. 9F is reinforced by the metal plate 7, the above-mentioned warpage can be reduced as compared with the case where the pseudo wafer 14 does not exist. That is, the metal plate 7 also has a warp preventing function together with the shield.
[0152]
In addition, in the present embodiment, the same operations and effects as those described in the first embodiment can be obtained.
[0153]
Third embodiment
In the present embodiment, as shown in FIG. 13, the material of the frame 42 is the same as the material of the protective material layer 6, and the frame 42 is temporarily fixed on the adhesive sheet 2. After the semiconductor chips 3 and 4 are loaded, the frame 42 is melted by heating or the like to form a protective material layer 6 for joining between the side surfaces of the semiconductor chips 3 and 4, and an adhesive is applied thereon and bonded. It is the same as the first embodiment except that the metal plate 7 is formed via the agent layer 38.
[0154]
That is, as shown in FIGS. 13A and 13B, the adhesive sheet 2 is pasted on the substrate 1 in the same manner as in the steps shown in FIGS. A frame 42 made of an acrylic resin or the like is temporarily fixed thereon, and the semiconductor chips 3 and 4 are inserted into the openings 11 of the frame 42 and temporarily fixed at predetermined positions on the adhesive sheet 2. Therefore, the frame 42 has the same function as the frame 12 described above, and is provided with a positioning mark for the semiconductor chip.
[0155]
Next, as shown in FIG. 13C, at least the side surfaces of the semiconductor chips 3 and 4 are joined by the protective material layer 6 formed by dissolving the frame 42 by melting the frame 42.
[0156]
Next, as shown in FIG. 13D, an adhesive layer 38 is applied to cover the protective material layer 6 and the semiconductor chips 3 and 4, and the metal plate 7 is bonded, or the adhesive layer 38 is provided. Is bonded.
[0157]
Thereafter, the chip-shaped electronic component 19 is mounted on the mounting board 30 through substantially the same steps as those shown in FIGS. 9 (f) to 12 (r).
[0158]
In the present embodiment, since the side surfaces of the semiconductor chips 3 and 4 are joined by the protective material layer 6 made of the melted material of the frame 42 by melting the frame 42, the amount of the protective material used is reduced, and The warp of the pseudo wafer 14 including the chips 3 and 4 and the protective material layer 6 can be suppressed, and the number of manufacturing steps of the pseudo wafer 14 can be reduced.
[0159]
In addition, in the present embodiment, the same operations and effects as those described in the first or second embodiment can be obtained.
[0160]
The embodiment described above can be further modified based on the technical idea of the present invention.
[0161]
For example, the metal plate 7 does not need to be formed on the entire back surface of the semiconductor chips 3 and 4, and may be partially formed only on the opening 11 of the frame 12, for example. The material of the metal plate 7 may be various, and a conductor other than metal may be used.
[0162]
When the frame 12 is used, a portion where the metal plate 7 is formed because the shield structure is necessary and a portion where the metal plate 7 is not formed because the shield structure is unnecessary exist in the same frame 12. You may. Since the metal plate 7 does not exist in the portion where the shield structure is unnecessary (the area of the semiconductor chip where the shield is unnecessary), the chip-shaped electronic component obtained from this portion is easily ground from the back surface to make it thinner.
[0163]
Further, the number of semiconductor chips to be inserted into the opening 11 of the frame 12 may be two or more, but may be one. The positioning means provided on the frame 12 may be formed by printing or the like in addition to the above-described recess.
[0164]
Further, in the above-described embodiment, the alignment marks 13 provided on the surface of the frame 12 remain together with the frame 12 in the chip-shaped electronic component 19 even after the pseudo wafer 14 is cut into chip-shaped electronic components 19. May be.
[0165]
Alternatively, dicing may be performed after solder bumps are collectively formed in the land openings 17 in the state shown in FIG. 3M where the wiring protection layer 16 and the land openings 17 are provided.
[0166]
Further, the object to which the present invention is applied is not limited to a semiconductor chip, and may be various other chip-shaped electronic components that involve cutting into individual chips.
[0167]
Operation and Effect of the Invention
According to the present invention, as described above, since a conductive layer is formed on the protective material layer on the surface opposite to the electrode surface, external noise to the chip-shaped electronic component is transmitted through the conductive layer. In addition to being able to emit, a good shielding effect can be obtained, and the chip-shaped electronic component and the shielding means can be integrated to reduce the size and thickness, and this can be simplified without any additional step of shielding means. It can be realized with a simple structure.
[0168]
Also, as in the prior invention, for example, since a non-defective chip component is rearranged into a pseudo wafer, a wafer composed of all non-defective chips can be obtained. This makes it possible to produce a low-cost flip-chip chip-shaped electronic component, and it is possible to easily perform wiring formation, solder bump processing, and the like not only on in-house manufactured chips but also on bare chips purchased from other companies. Then, when the chip-shaped electronic component is cut out from the pseudo wafer, the side surfaces between the chip components are cut, so that adverse effects on the chip component body (damage such as distortion, burrs, cracks, etc.) are suppressed. In addition, since at least the chip side surface is covered by the protective material layer, electroless plating of Ni or the like can be performed, and at least the chip side surface is protected by the protective material layer. The chip is protected during the mounting handling of the chip-shaped electronic component, and good mounting reliability is obtained.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views sequentially showing steps of manufacturing a chip-shaped electronic component according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view sequentially showing a manufacturing process.
FIG. 3 is a cross-sectional view sequentially showing a manufacturing process.
FIG. 4 is a cross-sectional view sequentially showing the manufacturing steps.
FIG. 5 is a cross-sectional view sequentially showing the manufacturing steps.
FIG. 6 is a cross-sectional view including a step of mounting a chip-shaped electronic component.
FIG. 7 is a plan view (a) and a sectional view (b) of the frame.
FIG. 8 is a sectional view when position detection is performed by the upper camera and the lower camera.
FIG. 9 is a cross-sectional view sequentially showing the steps of manufacturing the chip-shaped electronic component according to the second embodiment of the present invention.
FIG. 10 is a cross-sectional view sequentially showing the manufacturing steps.
FIG. 11 is a cross-sectional view sequentially showing the manufacturing process.
FIG. 12 is a cross-sectional view including a step of mounting a chip-shaped electronic component.
FIG. 13 is a cross-sectional view sequentially showing the steps of manufacturing the chip-shaped electronic component according to the third embodiment of the present invention.
FIG. 14 is a cross-sectional view sequentially showing steps of manufacturing a chip-shaped electronic component according to a conventional example.
FIGS. 15A and 15B are partial cross-sectional side views of the mounting structure converted into the MCM.
FIG. 16 is a perspective view of a semiconductor wafer for coping with wafer batch processing.
FIG. 17 is a sectional view sequentially showing the steps of manufacturing the chip-shaped electronic component according to the invention of the prior application.
FIG. 18 is a cross-sectional view sequentially showing the manufacturing process.
FIG. 19 is a cross-sectional view sequentially showing the manufacturing process.
FIG. 20 is a cross-sectional view including a step of mounting a chip-shaped electronic component.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Adhesive sheet, 3, 4 ... Semiconductor chip, 5 ... Electrode pad,
Reference numeral 6: protective material layer, 7: metal plate (metal layer), 9: interlayer insulating film, 10: via hole, 11: opening, 12: frame, 13: alignment mark,
14: pseudo wafer, 15: wiring, 16: wiring protection layer, 17: land opening,
18 ... blade, 19 ... chip-shaped electronic component, 20 ... dicing,
21: scribe line, 22: passivation film, 23: SiO2film,
24: silicon substrate, 25: electroless plating layer, 26: land,
27: print mask, 28: solder paste, 29: solder bump,
30: mounting board, 31: solder (solder) resist,
32: solder (solder) paste, 33: electrode, 34: substrate,
35: upper camera, 36: lower camera, 37: vacuum chuck, 38: adhesive layer

Claims (29)

支持体上に複数個又は複数種のチップ部品を固定する工程と、
前記チップ部品の少なくとも側面に保護物質を被着させて保護物質層を形成する工程と、
前記保護物質層上に導電層を形成する工程と、
前記保護物質層が被着された前記チップ部品を前記支持体から剥離する工程と、
前記チップ部品の電極面上に層間絶縁膜及び接続孔を形成する工程と、
前記接続孔に導電性接続材を設ける工程と、
前記複数個又は複数種のチップ部品間を切断して、チップ状電子部品を得る工程と
を有する、チップ状電子部品の製造方法。Fixing a plurality or a plurality of types of chip components on the support,
Forming a protective material layer by applying a protective material to at least a side surface of the chip component,
Forming a conductive layer on the protective material layer,
Peeling the chip component to which the protective material layer is applied from the support,
Forming an interlayer insulating film and a connection hole on the electrode surface of the chip component;
Providing a conductive connection material in the connection hole;
Cutting the plurality of or a plurality of types of chip components to obtain a chip-shaped electronic component. 前記チップ部品を装入するための開口部を有する枠体を前記支持体上に固定した後、前記枠体の前記開口部内に前記チップ部品を装入して前記支持体上に固定し、この固定後に前記開口部内において前記チップ部品の少なくとも側面を覆うように前記保護物質を被着させる、請求項１に記載のチップ状電子部品の製造方法。After fixing a frame having an opening for loading the chip component on the support, the chip component is loaded into the opening of the frame and fixed on the support, and The method for manufacturing a chip-shaped electronic component according to claim 1, wherein the protective substance is applied so as to cover at least a side surface of the chip component in the opening after the fixing. 前記枠体を導電性物質で形成する、請求項２に記載のチップ状電子部品の製造方法。The method for manufacturing a chip-shaped electronic component according to claim 2, wherein the frame is formed of a conductive material. 前記保護物質の被着を印刷又は物理的蒸着によって行う、請求項１又は２に記載のチップ状電子部品の製造方法。The method for manufacturing a chip-shaped electronic component according to claim 1, wherein the application of the protective substance is performed by printing or physical vapor deposition. 前記導電性接続材を介して前記導電層を前記電極面上に電気的に取り出す、請求項１〜３のいずれか１項に記載のチップ状電子部品の製造方法。4. The method of manufacturing a chip-shaped electronic component according to claim 1, wherein the conductive layer is electrically extracted on the electrode surface via the conductive connection material. 5. 前記接続孔を介して前記複数個又は複数種のチップ部品間を前記導電性接続材からなる配線によって接続する、請求項１に記載のチップ状電子部品の製造方法。The method for manufacturing a chip-shaped electronic component according to claim 1, wherein the plurality of or the plurality of types of chip components are connected to each other through the connection hole by a wiring made of the conductive connection material. 前記導電性接続材からなる配線上に第２の層間絶縁膜を形成し、この第２の層間絶縁膜に形成した第２の接続孔を介して前記配線を電気的に取り出す、請求項１に記載のチップ状電子部品の製造方法。2. The method according to claim 1, wherein a second interlayer insulating film is formed on the wiring made of the conductive connecting material, and the wiring is electrically extracted through a second connection hole formed in the second interlayer insulating film. A method for producing the chip-shaped electronic component according to the above. 前記開口部の近傍において前記枠体に前記チップ部品の位置決め手段を形成する、請求項２に記載のチップ状電子部品の製造方法。3. The method for manufacturing a chip-shaped electronic component according to claim 2, wherein said chip component positioning means is formed in said frame near said opening. 支持体上に複数個又は複数種のチップ部品を固定する工程と、
前記チップ部品の少なくとも側面に保護物質を被着させて保護物質層を形成する工程と、
前記保護物質層上に導電層を形成する工程と、
前記保護物質層が被着された前記チップ部品を前記支持体から剥離する工程と
を有する、疑似ウェーハの製造方法。Fixing a plurality or a plurality of types of chip components on the support,
Forming a protective material layer by applying a protective material to at least a side surface of the chip component,
Forming a conductive layer on the protective material layer,
Separating the chip component on which the protective material layer has been adhered from the support. 前記チップ部品の前記剥離工程後に、前記チップ部品の電極面上に層間絶縁膜及び接続孔を形成し、前記接続孔に導電性接続材を設ける、請求項８に記載の疑似ウェーハの製造方法。9. The method of manufacturing a pseudo wafer according to claim 8, wherein after the step of separating the chip component, an interlayer insulating film and a connection hole are formed on an electrode surface of the chip component, and a conductive connection material is provided in the connection hole. 前記チップ部品を装入するための開口部を有する枠体を前記支持体上に固定した後、前記枠体の前記開口部内に前記チップ部品を装入して前記支持体上に固定し、この固定後に前記開口部内において前記チップ部品の少なくとも側面を覆うように前記保護物質を被着させる、請求項９に記載の疑似ウェーハの製造方法。After fixing a frame having an opening for loading the chip component on the support, the chip component is loaded into the opening of the frame and fixed on the support, The method of manufacturing a pseudo wafer according to claim 9, wherein the protection material is applied so as to cover at least a side surface of the chip component in the opening after the fixing. 前記枠体を導電性物質で形成する、請求項１１に記載の疑似ウェーハの製造方法。The method of claim 11, wherein the frame is formed of a conductive material. 前記保護物質の被着を印刷又は物理的蒸着によって行う、請求項９に記載の疑似ウェーハの製造方法。The method of claim 9, wherein applying the protective material is performed by printing or physical vapor deposition. 前記導電性接続材を介して前記導電層を前記電極面上に電気的に取り出す、請求項１０〜１２のいずれか１項に記載の疑似ウェーハの製造方法。The method of manufacturing a pseudo wafer according to any one of claims 10 to 12, wherein the conductive layer is electrically extracted on the electrode surface via the conductive connection material. 前記接続孔を介して前記複数個又は複数種のチップ部品間を前記導電性接続材からなる配線によって接続する、請求項１０に記載の疑似ウェーハの製造方法。The method of manufacturing a pseudo wafer according to claim 10, wherein the plurality of or a plurality of types of chip components are connected to each other through the connection holes by wiring made of the conductive connection material. 前記導電性接続材からなる配線上に第２の層間絶縁膜を形成し、この第２の層間絶縁膜に形成した第２の接続孔を介して前記配線を電気的に取り出す、請求項１０に記載の疑似ウェーハの製造方法。11. The wiring according to claim 10, wherein a second interlayer insulating film is formed on the wiring made of the conductive connecting material, and the wiring is electrically extracted through a second connection hole formed in the second interlayer insulating film. The manufacturing method of the pseudo wafer described in the above. 前記開口部の近傍において前記枠体に前記チップ部品の位置決め手段を形成する、請求項１１に記載の疑似ウェーハの製造方法。12. The method of manufacturing a pseudo wafer according to claim 11, wherein a positioning means for the chip component is formed in the frame near the opening. チップ部品の電極面以外の少なくとも側面に保護物質層が被着されていて、前記電極面とは反対側の面において前記保護物質層上に導電層が形成されている、チップ状電子部品。A chip-shaped electronic component, wherein a protective material layer is applied to at least a side surface of the chip component other than the electrode surface, and a conductive layer is formed on the protective material layer on a surface opposite to the electrode surface. 前記チップ部品の側面に被着された前記保護物質層の外面に導電性物質層が被着され、この導電性物質層が前記導電層に接触している、請求項１８に記載のチップ状電子部品。19. The chip-shaped electronic device according to claim 18, wherein a conductive material layer is applied to an outer surface of the protective material layer applied to a side surface of the chip component, and the conductive material layer is in contact with the conductive layer. parts. 前記チップ部品の電極面上に層間絶縁膜が形成され、この層間絶縁膜に形成した接続孔に導電性接続材が設けられており、この導電性接続材を介して前記導電層が前記電極面上に電気的に取り出されている、請求項１８又は１９に記載のチップ状電子部品。An interlayer insulating film is formed on the electrode surface of the chip component, and a conductive connection material is provided in a connection hole formed in the interlayer insulating film. The conductive layer is provided on the electrode surface via the conductive connection material. The chip-shaped electronic component according to claim 18, wherein the chip-shaped electronic component is electrically extracted above. 前記接続孔を介して複数個又は複数種のチップ部品間が、前記導電性接続材からなる配線によって接続されている、請求項２０に記載のチップ状電子部品。21. The chip-shaped electronic component according to claim 20, wherein a plurality of or a plurality of types of chip components are connected to each other through the connection hole by a wiring made of the conductive connection material. 前記導電性接続材からなる配線上に第２の層間絶縁膜が形成され、この第２の層間絶縁膜に形成した第２の接続孔を介して前記配線が電気的に取り出されている、請求項２０に記載のチップ状電子部品。A second interlayer insulating film is formed on the wiring made of the conductive connection material, and the wiring is electrically extracted through a second connection hole formed in the second interlayer insulating film. Item 21. A chip-shaped electronic component according to item 20. 前記導電性物質層の表面に前記チップ部品の位置決め手段が残されている、請求項１９に記載のチップ状電子部品。20. The chip-shaped electronic component according to claim 19, wherein a positioning means for the chip component is left on a surface of the conductive material layer. 複数個又は複数種のチップ部品が、電極面以外の少なくとも側面に被着された保護物質層によって一体化されていて、前記電極面とは反対側の面において前記保護物質層上に導電層が被着されている、疑似ウェーハ。A plurality or a plurality of types of chip components are integrated by a protective material layer applied to at least a side surface other than the electrode surface, and a conductive layer is formed on the protective material layer on a surface opposite to the electrode surface. A pseudo wafer that has been deposited. 前記チップ部品の側面に被着された前記保護物質層の外面に導電性物質層が被着され、この導電性物質層が前記導電層に接触している、請求項２４に記載の疑似ウェーハ。25. The pseudo wafer according to claim 24, wherein a conductive material layer is applied to an outer surface of the protective material layer applied to a side surface of the chip component, and the conductive material layer is in contact with the conductive layer. 前記チップ部品の電極面上に層間絶縁膜が形成され、この層間絶縁膜に形成した接続孔に導電性接続材が設けられており、この導電性接続材を介して前記導電層が前記電極面上に電気的に取り出されている、請求項２３又は２４に記載の疑似ウェーハ。An interlayer insulating film is formed on the electrode surface of the chip component, and a conductive connection material is provided in a connection hole formed in the interlayer insulating film. The conductive layer is provided on the electrode surface via the conductive connection material. 25. The pseudo wafer according to claim 23, wherein the pseudo wafer is electrically extracted above. 前記接続孔を介して複数個又は複数種のチップ部品間が、前記導電性接続材からなる配線によって接続されている、請求項２６に記載の疑似ウェーハ。27. The pseudo wafer according to claim 26, wherein a plurality of or a plurality of types of chip components are connected via the connection hole by a wiring made of the conductive connection material. 前記導電性接続材からなる配線上に第２の層間絶縁膜が形成され、この第２の層間絶縁膜に形成した第２の接続孔を介して前記配線が電気的に取り出されている、請求項２６に記載の疑似ウェーハ。A second interlayer insulating film is formed on the wiring made of the conductive connection material, and the wiring is electrically extracted through a second connection hole formed in the second interlayer insulating film. Item 29. The pseudo wafer according to item 26. 前記導電性物質層の表面に前記チップ部品の位置決め手段が残されている、請求項２５に記載の疑似ウェーハ。26. The pseudo wafer according to claim 25, wherein positioning means for the chip component is left on a surface of the conductive material layer.
JP2003127734A 2003-05-06 2003-05-06 Chip-like electronic component and manufacturing method thereof, pseudo wafer used for manufacturing the same, and manufacturing method thereof Pending JP2004335629A (en)

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