JP2004281550A - Semiconductor wafer and method of chamfering the same - Google Patents

Semiconductor wafer and method of chamfering the same Download PDF

Info

Publication number
JP2004281550A
JP2004281550A JP2003068425A JP2003068425A JP2004281550A JP 2004281550 A JP2004281550 A JP 2004281550A JP 2003068425 A JP2003068425 A JP 2003068425A JP 2003068425 A JP2003068425 A JP 2003068425A JP 2004281550 A JP2004281550 A JP 2004281550A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
wafer
chamfering
thickness
thickness direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003068425A
Other languages
Japanese (ja)
Inventor
Kazuyuki Umetsu
一之 梅津
Hidemi Omori
秀美 大森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dowa Holdings Co Ltd
Original Assignee
Dowa Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dowa Mining Co Ltd filed Critical Dowa Mining Co Ltd
Priority to JP2003068425A priority Critical patent/JP2004281550A/en
Publication of JP2004281550A publication Critical patent/JP2004281550A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer which can be protected against chipping or damage even when it is reduced to 200 μm or below in thickness by grinding its rear surface, and to provide a method of chamfering the same. <P>SOLUTION: A rotary grinding stone 100 provided with a groove arcuate in cross section on its outer peripheral surface is rotated as the semiconductor wafer 102 is rotated. The peripheral edge of the semiconductor wafer 102 is brought into contact with the groove of the rotary grinding stone, so as to deviate the center line of the semiconductor wafer 102 in the direction of thickness from the center line of the groove of the rotary grinding stone in the direction of thickness by a prescribed distance D to chamfer the peripheral edge of the semiconductor wafer 102. The prescribed distance D (mm) is so set as to make an angle larger than 60°. The angle is formed by a tangential line on the end face of the semiconductor wafer 102 at a position distant from either of the surfaces of the semiconductor wafer 102 by a prescribed distance T (0.2 mm or below), with a line in parallel with either of the surfaces of the semiconductor wafer 102 in the cross sectional shape of the semiconductor wafer 102 in the direction of thickness. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体ウエハおよびその面取り加工方法に関し、特に、裏面を研削することにより厚さを薄くして半導体基板として使用される半導体ウエハおよびその面取り加工方法に関する。
【０００２】
【従来の技術】
一般に、半導体ウエハ（以下、「ウエハ」という）の周縁部は、ハンドリングや自動搬送の際のチッピング（欠け）を防止するために、面取り加工が施されている。このような面取り加工の方法として、周縁の中央部に平坦面が形成されるとともにこの平坦面の上端および下端に傾斜面が形成された溝付き砥石を回転させ、この溝付き砥石にウエハの周縁を当接させて面取り加工する方法が知られている（例えば、特許文献１参照）。この方法により面取り加工されたウエハの周縁部の形状は、図１（ａ）に示すように、ウエハ１０の周縁部にウエハ１０の表面および裏面から所定の角度θ（一般にθ＝２０°程度）傾斜した斜面が形成された形状である。
【０００３】
また、半導体レーザなどを作製する際の半導体基板としてウエハを使用する場合には、エピタキシャル成長後にウエハの裏面を研削することによりウエハの厚さを１００μｍ程度まで薄くして使用している。
【０００４】
しかし、上記の特許文献１に開示された方法により面取り加工されたウエハ１０では、裏面を研削して厚さ１００μｍ程度まで薄くすると、図１（ｂ）に示すように、ウエハ１０の周縁部が非常に鋭角になり、チッピング（欠け）が生じたり、破損し易くなるという問題がある。
【０００５】
このようにウエハの裏面を研削して厚さを薄くした場合の問題を解消するために、研削後のウエハの平坦な表面の端から端面までの水平距離が研削後の厚さより小さくなるようにウエハの端面を加工する方法が提案されている（例えば、特許文献２参照）。また、ウエハの周縁に位置する端面における厚さ方向の断面形状が曲線状に突出した凸形状であり且つこの凸形状の頂部が裏面から見て研削すべき厚さ分よりも表面寄りに位置するようにウエハの端面を加工する方法も提案されている（例えば、特許文献３参照）。
【０００６】
【特許文献１】
特開平７−５８０６５号公報（段落番号０００６）
【特許文献２】
特許第２８２１４０８号公報（段落番号０００８）
【特許文献３】
特開２００１−１５３９５号公報（段落番号０００９）
【０００７】
【発明が解決しようとする課題】
しかし、上記の特許文献２および特許文献３に開示された方法は、ウエハの裏面を研削してウエハを厚さ２５０〜３００μｍ程度に薄肉化した場合にウエハの端部にクラックや欠けが生じるのを防止する方法であり、半導体レーザなどを作製する際の半導体基板としてウエハを使用するためにウエハの裏面を研削して２００μｍ以下、特に１００μｍ程度の厚さにする場合には、チッピング（欠け）や破損の防止が十分ではない。
【０００８】
したがって、本発明は、このような従来の問題点に鑑み、裏面を研削して２００μｍ以下の厚さにしてもチッピング（欠け）や破損を防止することができる、半導体ウエハおよびその面取り加工方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
本発明者らは、上記課題を解決するために鋭意研究した結果、半導体ウエハの厚さ方向の断面形状において、外周面に対応する端面を円弧状に形成し、且つ一方の表面から厚さ方向に所定の距離Ｔ（Ｔは０．２ｍｍ以下）の位置における端面上の接線とその一方の表面に平行な方向との間の角度が６０°よりも大きくなるようにすることにより、裏面を研削して２００μｍ以下の厚さにしてもチッピング（欠け）や破損を防止することができることを見出し、本発明を完成するに至った。
【００１０】
すなわち、本発明による半導体ウエハは、厚さ方向の断面形状において、外周面に対応する端面が円弧状に形成され、且つ一方の表面から厚さ方向に所定の距離Ｔ（Ｔは０．２ｍｍ以下）の位置における端面上の接線とその一方の表面に平行な方向との間の角度が６０°よりも大きいことを特徴とする。
【００１１】
この半導体ウエハにおいて、所定の距離Ｔが０．１ｍｍ以下であるのが好ましい。また、端面の半径は、好ましくは０．２〜０．４ｍｍ、さらに好ましくは０．２５〜０．３２ｍｍである。
【００１２】
また、本発明による半導体ウエハの面取り加工方法は、外周面に円弧状断面の溝を備えた回転砥石を回転させるとともに、半導体ウエハを回転させながら、半導体ウエハの厚さ方向の中心線が回転砥石の溝の厚さ方向の中心線から厚さ方向に所定の距離Ｄだけずれるように、半導体ウエハの周縁を回転砥石の溝に当接させることにより、半導体ウエハの周縁を面取り加工することを特徴とする。
【００１３】
この半導体ウエハの面取り加工方法において、所定の距離Ｄ（ｍｍ）は、面取り加工後の半導体ウエハの厚さ方向の断面形状において、半導体ウエハの一方の表面から厚さ方向に所定の距離Ｔ（Ｔは０．２ｍｍ以下）の位置における半導体ウエハの端面上の接線と半導体ウエハの一方の表面に平行な方向との間の角度が６０°よりも大きくなるような距離であるのが好ましい。所定の距離Ｔは、０．１ｍｍ以下であるのがさらに好ましい。また、円弧状断面の半径は、好ましくは０．２〜０．４ｍｍ、さらに好ましくは０．２５〜０．３２ｍｍである。
【００１４】
【発明の実施の形態】
以下、添付図面を参照して本発明による半導体ウエハおよびその面取り加工方法の実施の形態について説明する。
【００１５】
図２に示すように、外周面に所定の半径の円弧状断面の溝１００ａを備えた回転砥石１００を回転させるとともに、ウエハ１０２を回転させながら、ウエハ１０２の周縁を回転砥石１００の溝１００ａに当接させることにより、ウエハ１０２の周縁を面取り加工する。このとき、ウエハ１０２の厚さ方向の中心線を回転砥石１００の溝１００ａの厚さ方向の中心線から所定の高さＤだけずらすことにより、図３（ａ）に示すように、面取り加工されたウエハ１０２の端面の円弧の中心が、ウエハ１０２の厚さ方向の中心線から厚さ方向に所定の距離Ｄ（図２参照）だけずれ、ウエハ１０２の表面側から所定の距離、例えば１００μｍの位置におけるウエハ１０２の端面上の接線とウエハ１０２の表面と平行な方向との間の角度がθ＞６０°（図３（ｃ）参照）の面取り形状になるようにする。このように面取り加工することにより、図３（ｂ）に示すように、ウエハ１０２の裏面を研削して所定の厚さ、例えば１００μｍ程度まで薄くしても、ウエハ１０２の端面の形状が鋭角にならないようにすることができる。
【００１６】
【実施例】
以下、添付図面を参照して本発明による半導体ウエハおよびその面取り加工方法の実施例について詳細に説明する。
【００１７】
まず、厚さ４５０μｍのウエハを面取り加工して、ウエハの端部の断面形状を図４（ａ）に示すような断面形状にした。すなわち、図４（ａ）に示すように、ウエハの端面が半径０．３２ｍｍの円弧状断面を有し、ウエハの表面に対して垂直方向に延びる端面上の接線とウエハの表面側の平坦部の先端との間隔が７０μｍ、その接線とウエハの裏面側の平坦部の先端との間隔が１２０μｍ、ウエハの表面と平行な線上で端面の円弧の中心を含む線とウエハの表面との間隔が２００μｍ、その端面の円弧の中心を含む線とウエハの裏面との間隔が２５０μｍになるようにウエハを面取り加工した。
【００１８】
次に、このように面取り加工したウエハの裏面を研削して、図４（ｂ）に示すように厚さ１００μｍにした。このようにして得られたウエハを（図示しない）縦置きウエハキャリアに収容して揺動式超音波洗浄装置によって洗浄したところ、ウエハの端面に鋭角部分がないため、チッピングや破損による不良発生率は２％（１００枚中２枚）であった。
【００１９】
［比較例］
厚さ４５０μｍのウエハを従来の面取り加工方法により面取り加工して、ウエハの端部の断面形状を図５（ａ）に示すような断面形状にした。すなわち、図５（ａ）に示すように、ウエハの表面側の平坦部の先端とウエハの端面との間隔が３００μｍ、裏面側の平坦部の先端と端面との間隔が２７０μｍ、表面側の斜面の高さの差が１２０μｍ、裏面側の斜面の高さの差が１１０μｍ、端面の厚さ方向の長さが２２０μｍになるようにウエハを面取り加工した。
【００２０】
次に、このように面取り加工したウエハの裏面を研削して、図５（ｂ）に示すように厚さ１００μｍにした。このようにして得られたウエハを（図示しない）縦置きウエハキャリアに収容して揺動式超音波洗浄装置によって洗浄したところ、ウエハの端面の鋭角部分からチッピングや破損を生じ、不良発生率は１０％（１００枚中１０枚）であった。
【００２１】
【発明の効果】
上述したように、本発明によれば、ウエハの裏面を研削して２００μｍ以下の厚さにしてもチッピング（欠け）や破損を防止することができ、得られたウエハを半導体レーザなどを作製する際の半導体基板として使用することができる。
【図面の簡単な説明】
【図１】従来の半導体ウエハの面取り加工方法によって面取り加工された半導体ウエハを概略的に示す断面図であり、（ａ）は面取り加工後の断面形状を示し、（ｂ）は１００μｍの厚さまで裏面を研削した後の断面形状を示す。
【図２】本発明による半導体ウエハの面取り加工方法を説明する概略図。
【図３】本発明による半導体ウエハの面取り加工方法によって面取り加工された半導体ウエハを概略的に示す断面図であり、（ａ）は面取り加工後の断面形状を示し、（ｂ）は１００μｍの厚さまで裏面を研削した後の断面形状を示す。
【図４】実施例において面取り加工された半導体ウエハの端部を概略的に示す断面図であり、（ａ）は面取り加工後の断面形状を示し、（ｂ）は１００μｍの厚さまで裏面を研削した後の断面形状を示す。
【図５】比較例において面取り加工された半導体ウエハの端部を概略的に示す断面図であり、（ａ）は面取り加工後の断面形状を示し、（ｂ）は１００μｍの厚さまで裏面を研削した後の断面形状を示す。
【符号の説明】
１００ 回転砥石
１００ａ 溝
１０２ 半導体ウエハ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor wafer and a method for chamfering the same, and more particularly to a semiconductor wafer used as a semiconductor substrate with a reduced thickness by grinding the back surface and a method for chamfering the same.
[0002]
[Prior art]
Generally, a peripheral portion of a semiconductor wafer (hereinafter, referred to as “wafer”) is chamfered in order to prevent chipping (chipping) during handling and automatic transfer. As a method of such chamfering, a grooved whetstone having a flat surface formed at the center of the periphery and having inclined surfaces formed at upper and lower ends of the flat surface is rotated. There is known a method of chamfering by abutting (see, for example, Patent Document 1). As shown in FIG. 1A, the shape of the peripheral portion of the wafer chamfered by this method has a predetermined angle θ (generally about θ = 20 °) from the front and back surfaces of the wafer 10 to the peripheral portion of the wafer 10. The shape is such that an inclined slope is formed.
[0003]
Further, when a wafer is used as a semiconductor substrate when manufacturing a semiconductor laser or the like, the thickness of the wafer is reduced to about 100 μm by grinding the back surface of the wafer after epitaxial growth.
[0004]
However, in the case of the wafer 10 chamfered by the method disclosed in the above-mentioned Patent Document 1, when the back surface is ground to reduce the thickness to about 100 μm, as shown in FIG. There is a problem that the angle becomes very sharp, chipping (chipping) occurs, and breakage easily occurs.
[0005]
In order to solve the problem of reducing the thickness by grinding the back surface of the wafer in this manner, the horizontal distance from the edge of the flat surface of the wafer after grinding to the end surface is set to be smaller than the thickness after grinding. A method for processing an end face of a wafer has been proposed (for example, see Patent Document 2). Further, the cross-sectional shape in the thickness direction at the end face located at the peripheral edge of the wafer is a convex shape protruding in a curved shape, and the top of this convex shape is located closer to the front surface than the thickness to be ground when viewed from the back surface. A method of processing the end face of a wafer in this way has also been proposed (for example, see Patent Document 3).
[0006]
[Patent Document 1]
JP-A-7-58065 (paragraph number 0006)
[Patent Document 2]
Japanese Patent No. 2821408 (paragraph number 0008)
[Patent Document 3]
JP 2001-15395 A (paragraph number 0009)
[0007]
[Problems to be solved by the invention]
However, according to the methods disclosed in Patent Documents 2 and 3 described above, when the back surface of the wafer is ground to reduce the thickness of the wafer to a thickness of about 250 to 300 μm, cracks or chips occur at the edge of the wafer. When the back surface of the wafer is ground to a thickness of 200 μm or less, particularly about 100 μm in order to use the wafer as a semiconductor substrate when manufacturing a semiconductor laser or the like, chipping (chipping) occurs. And prevention of damage is not sufficient.
[0008]
Therefore, in view of such a conventional problem, the present invention provides a semiconductor wafer and a chamfering method for the same which can prevent chipping (chipping) or breakage even when the back surface is ground to a thickness of 200 μm or less. The purpose is to provide.
[0009]
[Means for Solving the Problems]
The present inventors have conducted intensive studies to solve the above problems, and as a result, in the cross-sectional shape in the thickness direction of the semiconductor wafer, formed an end face corresponding to the outer peripheral surface in an arc shape, and from one surface in the thickness direction The back surface is ground by making the angle between a tangent line on the end face at a position of a predetermined distance T (T is 0.2 mm or less) and a direction parallel to one of the surfaces larger than 60 °. The inventors have found that chipping (cracking) and breakage can be prevented even when the thickness is 200 μm or less, and have completed the present invention.
[0010]
That is, in the semiconductor wafer according to the present invention, in the cross-sectional shape in the thickness direction, an end face corresponding to the outer peripheral surface is formed in an arc shape, and a predetermined distance T (T is 0.2 mm or less) from one surface in the thickness direction. The angle between the tangent line on the end face at the position ()) and the direction parallel to one of the surfaces is greater than 60 °.
[0011]
In this semiconductor wafer, it is preferable that the predetermined distance T is 0.1 mm or less. The radius of the end face is preferably 0.2 to 0.4 mm, more preferably 0.25 to 0.32 mm.
[0012]
In addition, the method for chamfering a semiconductor wafer according to the present invention includes rotating a rotary grindstone having a groove having an arc-shaped cross section on the outer peripheral surface, and rotating the semiconductor wafer while the center line in the thickness direction of the semiconductor wafer is rotated with the rotary grindstone. The peripheral edge of the semiconductor wafer is chamfered by abutting the peripheral edge of the semiconductor wafer against the groove of the rotating grindstone so as to be shifted by a predetermined distance D in the thickness direction from the center line in the thickness direction of the groove. And
[0013]
In this method for chamfering a semiconductor wafer, the predetermined distance D (mm) is a predetermined distance T (T) in the thickness direction from one surface of the semiconductor wafer in the cross-sectional shape in the thickness direction of the semiconductor wafer after chamfering. Is preferably 0.2 mm or less) such that the angle between the tangent line on the end face of the semiconductor wafer at the position and the direction parallel to one surface of the semiconductor wafer is larger than 60 °. More preferably, the predetermined distance T is 0.1 mm or less. Further, the radius of the arc-shaped cross section is preferably 0.2 to 0.4 mm, more preferably 0.25 to 0.32 mm.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of a semiconductor wafer and a chamfering method for the same according to the present invention will be described below with reference to the accompanying drawings.
[0015]
As shown in FIG. 2, while rotating the rotating grindstone 100 provided with a groove 100 a having an arc-shaped cross section of a predetermined radius on the outer peripheral surface, and rotating the wafer 102, the peripheral edge of the wafer 102 is inserted into the groove 100 a of the rotating grindstone 100. By making contact, the peripheral edge of the wafer 102 is chamfered. At this time, the center line in the thickness direction of the wafer 102 is shifted by a predetermined height D from the center line in the thickness direction of the groove 100a of the rotary grindstone 100, so that the chamfering is performed as shown in FIG. The center of the circular arc on the end face of the wafer 102 is shifted from the center line in the thickness direction of the wafer 102 by a predetermined distance D (see FIG. 2) in the thickness direction, and a predetermined distance from the front surface side of the wafer 102, for example, 100 μm. The angle between the tangent line on the end face of the wafer 102 at the position and the direction parallel to the surface of the wafer 102 is set to be a chamfered shape of θ> 60 ° (see FIG. 3C). By chamfering in this manner, as shown in FIG. 3B, even if the back surface of the wafer 102 is ground and thinned to a predetermined thickness, for example, about 100 μm, the shape of the end face of the wafer 102 becomes an acute angle. Can be prevented.
[0016]
【Example】
Hereinafter, embodiments of a semiconductor wafer and a method for chamfering the same according to the present invention will be described in detail with reference to the accompanying drawings.
[0017]
First, a wafer having a thickness of 450 μm was chamfered so that the cross-sectional shape of the edge of the wafer was as shown in FIG. That is, as shown in FIG. 4A, the end face of the wafer has an arc-shaped cross section with a radius of 0.32 mm, and a tangent line on the end face extending in a direction perpendicular to the surface of the wafer and a flat portion on the front side of the wafer. The distance between the tangent line and the front end of the flat part on the back side of the wafer is 120 μm, and the distance between the line including the center of the arc of the end face on the line parallel to the front surface of the wafer and the front surface of the wafer is 70 μm. The wafer was chamfered so that the distance between the back surface of the wafer and the line including the center of the circular arc of the end face was 250 μm.
[0018]
Next, the back surface of the chamfered wafer was ground to a thickness of 100 μm as shown in FIG. The wafer thus obtained was housed in a vertically placed wafer carrier (not shown) and washed by an oscillating ultrasonic cleaning apparatus. Since there was no sharp edge on the end face of the wafer, the incidence of defects due to chipping or breakage Was 2% (2 out of 100).
[0019]
[Comparative example]
A wafer having a thickness of 450 μm was chamfered by a conventional chamfering method, so that the cross-sectional shape of the end portion of the wafer was as shown in FIG. That is, as shown in FIG. 5A, the distance between the tip of the flat part on the front surface side of the wafer and the end face of the wafer is 300 μm, the distance between the tip of the flat part on the back side and the end face is 270 μm, and the slope on the front side. The wafer was chamfered so that the difference in height was 120 μm, the difference in height of the rear slope was 110 μm, and the length of the end face in the thickness direction was 220 μm.
[0020]
Next, the back surface of the chamfered wafer was ground to a thickness of 100 μm as shown in FIG. The wafer obtained in this manner is housed in a vertical wafer carrier (not shown) and cleaned by an oscillating ultrasonic cleaning apparatus. 10% (10 out of 100).
[0021]
【The invention's effect】
As described above, according to the present invention, chipping (chipping) and breakage can be prevented even when the back surface of the wafer is ground to a thickness of 200 μm or less, and a semiconductor laser or the like is manufactured from the obtained wafer. Can be used as a semiconductor substrate.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a semiconductor wafer chamfered by a conventional semiconductor wafer chamfering method, in which (a) shows a cross-sectional shape after chamfering, and (b) shows up to a thickness of 100 μm. The cross-sectional shape after grinding the back surface is shown.
FIG. 2 is a schematic diagram illustrating a method for chamfering a semiconductor wafer according to the present invention.
FIG. 3 is a cross-sectional view schematically showing a semiconductor wafer chamfered by the method for chamfering a semiconductor wafer according to the present invention, wherein (a) shows a cross-sectional shape after chamfering, and (b) shows a thickness of 100 μm. The cross-sectional shape after grinding the back surface is shown.
4A and 4B are cross-sectional views schematically showing an end portion of a semiconductor wafer which has been chamfered in an example, where FIG. 4A shows a cross-sectional shape after the chamfering, and FIG. 4B shows a back surface ground to a thickness of 100 μm. The cross-sectional shape after the above is shown.
FIGS. 5A and 5B are cross-sectional views schematically showing an end portion of a chamfered semiconductor wafer in a comparative example, in which FIG. 5A shows a cross-sectional shape after the chamfering process, and FIG. 5B shows a back surface ground to a thickness of 100 μm. The cross-sectional shape after the above is shown.
[Explanation of symbols]
100 rotary grindstone 100a groove 102 semiconductor wafer

Claims (9)

厚さ方向の断面形状において、外周面に対応する端面が円弧状に形成され、且つ一方の表面から厚さ方向に所定の距離Ｔ（Ｔは０．２ｍｍ以下）の位置における端面上の接線とその一方の表面に平行な方向との間の角度が６０°よりも大きいことを特徴とする、半導体ウエハ。In the cross-sectional shape in the thickness direction, an end surface corresponding to the outer peripheral surface is formed in an arc shape, and a tangent line on the end surface at a position at a predetermined distance T (T is 0.2 mm or less) from one surface in the thickness direction. A semiconductor wafer, characterized in that the angle between the direction parallel to one of the surfaces is greater than 60 °. 前記所定の距離Ｔが０．１ｍｍ以下であることを特徴とする、請求項１に記載の半導体ウエハ。2. The semiconductor wafer according to claim 1, wherein the predetermined distance T is 0.1 mm or less. 前記端面の半径が０．２〜０．４ｍｍであることを特徴とする、請求項１または２に記載の半導体ウエハ。The semiconductor wafer according to claim 1, wherein a radius of the end face is 0.2 to 0.4 mm. 前記端面の半径が０．２５〜０．３２ｍｍであることを特徴とする、請求項１または２に記載の半導体ウエハ。The semiconductor wafer according to claim 1, wherein a radius of the end face is 0.25 to 0.32 mm. 外周面に円弧状断面の溝を備えた回転砥石を回転させるとともに、半導体ウエハを回転させながら、半導体ウエハの厚さ方向の中心線が回転砥石の溝の厚さ方向の中心線から厚さ方向に所定の距離Ｄだけずれるように、半導体ウエハの周縁を回転砥石の溝に当接させることにより、半導体ウエハの周縁を面取り加工することを特徴とする、半導体ウエハの面取り加工方法。While rotating the rotating grindstone having a groove with an arc-shaped cross section on the outer peripheral surface, while rotating the semiconductor wafer, the center line in the thickness direction of the semiconductor wafer is shifted from the center line in the thickness direction of the groove of the rotating grindstone in the thickness direction. A method of chamfering a semiconductor wafer, wherein the periphery of the semiconductor wafer is chamfered by bringing the periphery of the semiconductor wafer into contact with a groove of a rotary grindstone so as to be shifted by a predetermined distance D. 前記所定の距離Ｄ（ｍｍ）が、面取り加工後の前記半導体ウエハの厚さ方向の断面形状において、前記半導体ウエハの一方の表面から厚さ方向に所定の距離Ｔ（Ｔは０．２ｍｍ以下）の位置における前記半導体ウエハの端面上の接線と前記半導体ウエハの一方の表面に平行な方向との間の角度が６０°よりも大きくなるような距離であることを特徴とする、請求項５に記載の半導体ウエハの面取り加工方法。The predetermined distance D (mm) is a predetermined distance T (T is 0.2 mm or less) in the thickness direction from one surface of the semiconductor wafer in the cross-sectional shape in the thickness direction of the semiconductor wafer after chamfering. 6. The distance according to claim 5, wherein an angle between a tangent line on the end face of the semiconductor wafer at the position of (b) and a direction parallel to one surface of the semiconductor wafer is larger than 60 °. The method for chamfering a semiconductor wafer as described in the above. 前記所定の距離Ｔが０．１ｍｍ以下であることを特徴とする、請求項６に記載の半導体ウエハの面取り加工方法。7. The method according to claim 6, wherein the predetermined distance T is 0.1 mm or less. 前記円弧状断面の半径が０．２〜０．４ｍｍであることを特徴とする、請求項５乃至７のいずれかに記載の半導体ウエハの面取り加工方法。The method of chamfering a semiconductor wafer according to claim 5, wherein a radius of the arc-shaped cross section is 0.2 to 0.4 mm. 前記円弧状断面の半径が０．２５〜０．３２ｍｍであることを特徴とする、請求項５乃至７のいずれかに記載の半導体ウエハの面取り加工方法。The method of chamfering a semiconductor wafer according to claim 5, wherein a radius of the arc-shaped cross section is 0.25 to 0.32 mm.
JP2003068425A 2003-03-13 2003-03-13 Semiconductor wafer and method of chamfering the same Pending JP2004281550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003068425A JP2004281550A (en) 2003-03-13 2003-03-13 Semiconductor wafer and method of chamfering the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003068425A JP2004281550A (en) 2003-03-13 2003-03-13 Semiconductor wafer and method of chamfering the same

Publications (1)

Publication Number Publication Date
JP2004281550A true JP2004281550A (en) 2004-10-07

Family

ID=33285768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003068425A Pending JP2004281550A (en) 2003-03-13 2003-03-13 Semiconductor wafer and method of chamfering the same

Country Status (1)

Country Link
JP (1) JP2004281550A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012176608A1 (en) * 2011-06-23 2012-12-27 旭硝子株式会社 Method for manufacturing laminated body
KR20150007952A (en) * 2013-07-11 2015-01-21 미쓰비시덴키 가부시키가이샤 Method for manufacturing semiconductor device
CN110140195A (en) * 2016-10-13 2019-08-16 胜高股份有限公司 The grinding method of Silicon Wafer, the manufacturing method of Silicon Wafer and Silicon Wafer
CN113809149A (en) * 2021-07-23 2021-12-17 上海先进半导体制造有限公司 Wafer, semiconductor device and semiconductor device processing method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012176608A1 (en) * 2011-06-23 2012-12-27 旭硝子株式会社 Method for manufacturing laminated body
KR20140031328A (en) * 2011-06-23 2014-03-12 아사히 가라스 가부시키가이샤 Method for manufacturing laminated body
JPWO2012176608A1 (en) * 2011-06-23 2015-02-23 旭硝子株式会社 Manufacturing method of laminate
KR101895098B1 (en) * 2011-06-23 2018-09-04 에이지씨 가부시키가이샤 Method for manufacturing laminated body
KR20150007952A (en) * 2013-07-11 2015-01-21 미쓰비시덴키 가부시키가이샤 Method for manufacturing semiconductor device
KR101672213B1 (en) 2013-07-11 2016-11-03 미쓰비시덴키 가부시키가이샤 Method for manufacturing semiconductor device
CN110140195A (en) * 2016-10-13 2019-08-16 胜高股份有限公司 The grinding method of Silicon Wafer, the manufacturing method of Silicon Wafer and Silicon Wafer
CN110140195B (en) * 2016-10-13 2022-11-08 胜高股份有限公司 Method for polishing silicon wafer, method for manufacturing silicon wafer, and silicon wafer
CN113809149A (en) * 2021-07-23 2021-12-17 上海先进半导体制造有限公司 Wafer, semiconductor device and semiconductor device processing method
CN113809149B (en) * 2021-07-23 2023-12-12 上海先进半导体制造有限公司 Wafer, semiconductor device and semiconductor device processing method

Similar Documents

Publication Publication Date Title
EP1808887B1 (en) Production method of semiconductor wafer
TWI387510B (en) Method for processing chamfering of semiconductor wafers and correction of groove shape of whetstone
US7195545B2 (en) Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer
CN1324660C (en) Rectangular nitride semiconductor substrate capable of identifying outside and inside
US7258931B2 (en) Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
US8796820B2 (en) Semiconductor wafer and semiconductor device wafer
JPH02275613A (en) Semiconductor silicon wafer and its manufacture
JPH0624200B2 (en) Semiconductor device substrate processing method
KR20110016822A (en) Method for producing a polished semiconductor wafer
US20120028439A1 (en) Semiconductor And Solar Wafers And Method For Processing Same
JP2004281550A (en) Semiconductor wafer and method of chamfering the same
JP4492293B2 (en) Manufacturing method of semiconductor substrate
JP3935977B2 (en) Notched semiconductor wafer
JP2021160999A (en) Semiconductor substrate and method for manufacturing the same
JPH03177023A (en) Preparation of epitaxial wafer
JP6565780B2 (en) Wafer edge polishing pad, wafer edge polishing apparatus, and wafer edge polishing method
JP2005205543A (en) Wafer grinding method and wafer
JP2010040549A (en) Semiconductor wafer and manufacturing method thereof
JP3516203B2 (en) Compound semiconductor wafer
JP2007013012A (en) Beveling method of end face of silicon wafer for solar cell
US20090286047A1 (en) Semiconductor wafer
US20120025353A1 (en) Semiconductor And Solar Wafers
CN100511668C (en) Rectangular nitride semiconductor substrate with identified inner and outer surfaces
KR100831019B1 (en) Grinding wheel and method of wafer with improvement of surface roughness in manufacturing process of wafer
JPS6381934A (en) Wafer and manufacture thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060130

A977 Report on retrieval

Effective date: 20080820

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080902

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090106