JP2004274039A - Bilateral device, manufacturing method thereof, and semiconductor device - Google Patents

Bilateral device, manufacturing method thereof, and semiconductor device Download PDF

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JP2004274039A
JP2004274039A JP2004038698A JP2004038698A JP2004274039A JP 2004274039 A JP2004274039 A JP 2004274039A JP 2004038698 A JP2004038698 A JP 2004038698A JP 2004038698 A JP2004038698 A JP 2004038698A JP 2004274039 A JP2004274039 A JP 2004274039A
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JP4961658B2 (en
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Mutsumi Kitamura
睦美 北村
Naoto Fujishima
直人 藤島
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a bilateral device with a high withstand voltage and low on-voltage, and a manufacturing method thereof. <P>SOLUTION: An n-type extended drain region 4 is formed on each trench bottom 3a, and a p-type offset region 5 is formed in each divided semiconductor region, then a first n-type source region 9 and a second n-type source region 10 are formed on the surface of the p-type offset region 5, thereby decreasing each planar distance between the first n-type source region 9 and the second n-type source region 10 for higher cell density. Higher withstand voltage is achieved by maintaining the withstand voltage along each trench. Making the voltage of each gate electrode 7 higher than that of each first n-type source electrode 11 and that of each second n-type source electrode 12, a channel is formed on each trench sidewall, thereby realizing a bilateral LMOSFET (lateral metal oxide semiconductor field effect transistor) with high withstand voltage and low on-voltage, in which a current flows bilaterally. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

この発明、双方向素子を有するパワー集積回路（パワーＩＣ）などの半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device such as a power integrated circuit (power IC) having a bidirectional element and a method of manufacturing the same.

バッテリーなどの電源装置では、バッテリーを充電する場合と、バッテリーを放電する場合（負荷へ電流を供給する場合）の双方を制御して、バッテリーの過充電や過放電を防止している。そのため、交流信号や交流電力のオン・オフできる双方向の半導体スイッチが必要となり、この双方向の半導体スイッチとして、単方向半導体素子を逆並列に接続した複合型の双方向素子が用いられている。
また、この複合型の双方向素子とこれを制御する制御用ＩＣを同一の半導体基板に集積したパワーＩＣを用いて電源装置を小型化することが行われている。
また、単一の双方向素子も開発されており、その一例として、双方向横型絶縁ゲートトランジスタ（ＬＩＧＢＴ）が提案されている（例えば、非特許文献１参照）。つぎにこの双方向ＬＩＧＢＴについてその構造と動作を説明する。 2. Description of the Related Art In a power supply device such as a battery, both charging a battery and discharging a battery (supplying a current to a load) are controlled to prevent overcharging and overdischarging of the battery. Therefore, a bidirectional semiconductor switch capable of turning on / off an AC signal or AC power is required. As the bidirectional semiconductor switch, a composite bidirectional element in which unidirectional semiconductor elements are connected in antiparallel is used. .
In addition, a power supply device is miniaturized by using a power IC in which the composite type bidirectional element and a control IC for controlling the same are integrated on the same semiconductor substrate.
Also, a single bidirectional element has been developed, and as one example, a bidirectional lateral insulated gate transistor (LIGBT) has been proposed (for example, see Non-Patent Document 1). Next, the structure and operation of the bidirectional LIGBT will be described.

図３０は、双方向ＬＩＧＢＴの要部断面図である。双方向ＬＩＧＢＴでは、ｎ半導体層５０３の表面側に２つのｐ+ ウェル領域５０４、５０５が形成され、ｐ+ウェル領域５０４、５０５の中にｎ+ エミッタ領域５０６、５０７が形成される。ｐ+ ウェル領域５０４、５０５はｎ半導体層５０３の表面に露出するように形成され且つ所定の耐圧を維持できるように所定距離（ドリフト距離）だけ離間して形成される。また、ｎ+エミッタ領域５０６、５０７もｎ半導体層５０３の表面（ｐ+ ウェル領域５０４、５０５の表面）に露出するように形成される。
ｐ+ ウェル領域５０４、５０５のうちで２つのｎ+ エミッタ領域５０６、５０７の間に位置する部位の上には、ゲート絶縁膜５０８、５０９を介してポリシリコン等からなる絶縁ゲート型のゲート電極５１０、５１１が形成される。また、ｐ+ウェル領域５０４、５０５とｎ+ エミッタ領域５０６、５０７とに跨がる形でエミッタ電極５１２、５１３が形成されている。この構造では、ゲート電極５１０、５１１への印加電圧を制御すれば、エミッタ電極５１２、５１３間を双方向に流れる主電流のオン・オフを制御できる。 FIG. 30 is a cross-sectional view of a main part of the bidirectional LIGBT. In the bidirectional LIGBT, two p + well regions 504 and 505 are formed on the surface side of the n semiconductor layer 503, and n + emitter regions 506 and 507 are formed in the p + well regions 504 and 505. The p + well regions 504 and 505 are formed so as to be exposed on the surface of the n semiconductor layer 503 and are separated by a predetermined distance (drift distance) so as to maintain a predetermined breakdown voltage. Further, n + emitter regions 506 and 507 are also formed to be exposed on the surface of n semiconductor layer 503 (the surfaces of p + well regions 504 and 505).
An insulated gate type gate electrode made of polysilicon or the like is formed on the portion of the p + well regions 504 and 505 located between the two n + emitter regions 506 and 507 via gate insulating films 508 and 509. 510 and 511 are formed. Further, emitter electrodes 512 and 513 are formed so as to extend over the p + well regions 504 and 505 and the n + emitter regions 506 and 507. In this structure, by controlling the voltage applied to the gate electrodes 510 and 511, the on / off of the main current flowing bidirectionally between the emitter electrodes 512 and 513 can be controlled.

図３１は、図３０の双方向ＬＩＧＢＴの出力特性を示す図である。ｐｎ接合の内蔵電位に起因する立ち上がり電圧（０．６Ｖ）以上にならないと主電流は流れ始めないため、小さな電流領域ではオン電圧が高く、オン損失が大きくなる。
これを改善するために、立ち上がりで電圧が零ＶとなるＭＯＳＦＥＴで双方向素子を形成した単一の双方向ＭＯＳＦＥＴがある（例えば、特許文献１参照）。その内容について説明する。
図３２は、従来の双方向ＭＯＳＦＥＴの要部断面図である。ここでは双方向ＬＤＭＯＳＦＥＴ（Ｌａｔｅｒａｌ Ｄｏｕｂｌｅ−Ｄｉｆｆｕｓｅｄ ＭＯＳＦＥＴ）を例示する。前記の例と同様に、ＳＯＩ構造を有しており、半導体基板１０１の上に絶縁層１０２を介してｎ半導体層１０３が形成される。ｎ半導体層１０３の表面側には２つのｎ++ドレイン領域１０４、１０５が形成されるとともに、両ｎ++ドレイン領域１０４、１０５の間でｐ+ウェル領域１０６が形成される。ｐ+ ウェル領域１０６は絶縁層１０２に達する深さに形成され、ｎ半導体基板１０３を２つの領域に分割している。さらに、ｐ+ウェル領域１０６の中には２つのｎ++ソース領域１０７、１０８が形成されるとともに、両ｎ++ソース領域１０７、１０８の間でｐ++ベースコンタクト１０９領域が形成される。ｎ++ドレイン領域１０４、１０５とｐ+ウェル領域１０６とはｎ半導体基板１０３の表面に露出し、ｎ++ソース領域１０７、１０８、ｐ++ベースコンタクト領域１０９はｐ+ウェル領域１０６の表面に露出する。ｐ+ ウェル領域１０６上には、ゲート絶縁膜１１０、１１１を介して絶縁ゲート型のゲート電極１１２、１１３が形成され、両ゲート電極１１２、１１３は共通に接続される。ｎ++ドレイン領域１０４、１０５にはそれぞれドレイン電極１１４、１１５が接続される。さらに、ｎ++ソース領域１０７、１０８とｐ++ベースコンタクト領域１０９とに跨がる形でソース電極１１７が接続される。 FIG. 31 is a diagram showing output characteristics of the bidirectional LIGBT of FIG. Since the main current does not start flowing until the rising voltage (0.6 V) due to the built-in potential of the pn junction is exceeded, the on-voltage is high and the on-loss increases in a small current region.
In order to improve this, there is a single bidirectional MOSFET in which a bidirectional element is formed by a MOSFET whose voltage becomes zero V at the rise (for example, see Patent Document 1). The contents will be described.
FIG. 32 is a cross-sectional view of a main part of a conventional bidirectional MOSFET. Here, a bidirectional LDMOSFET (Lateral Double-Diffused MOSFET) is exemplified. As in the above example, the semiconductor device has an SOI structure, and an n semiconductor layer 103 is formed on a semiconductor substrate 101 with an insulating layer 102 interposed therebetween. On the surface side of the n semiconductor layer 103, two n ++ drain regions 104 and 105 are formed, and ap + well region 106 is formed between the two n ++ drain regions 104 and 105. The p + well region 106 is formed to a depth reaching the insulating layer 102, and divides the n semiconductor substrate 103 into two regions. Further, two n ++ source regions 107 and 108 are formed in the p + well region 106, and a p ++ base contact 109 region is formed between the two n ++ source regions 107 and 108. . The n ++ drain regions 104 and 105 and the p + well region 106 are exposed on the surface of the n semiconductor substrate 103, and the n ++ source regions 107 and 108 and the p ++ base contact region 109 are exposed on the surface of the p + well region 106. Exposure to On the p + well region 106, insulated gate type gate electrodes 112 and 113 are formed via gate insulating films 110 and 111, and both gate electrodes 112 and 113 are commonly connected. Drain electrodes 114 and 115 are connected to the n ++ drain regions 104 and 105, respectively. Further, the source electrode 117 is connected so as to extend over the n ++ source regions 107 and 108 and the p ++ base contact region 109.

上述した双方向ＬＤＭＯＳＦＥＴをオン状態にするには、ゲート電極１１２、１１３とソース電極１１７の間にゲート電極１１２、１１３が正電位になるように電圧を印加する。このとき、ｐ+ウェル領域１０６におけるゲート絶縁膜１１０、１１１の直下にチャネルが形成される。ここで、ドレイン電極１１４、１１５間にドレイン電極１１４側が高電位になるように電圧が印加されているとすれば、ドレイン電極１１４→ｎ++ドレイン領域１０４→ｎ半導体層１０３→ゲート電極１１２に対応するチャネル→ｎ++ソース領域１０７→ソース電極１１７→ｎ++ソース領域１０８→ゲート電極１１３に対応するチャネル→ｎ半導体層１０３→ｎ++ドレイン領域１０５→ドレイン電極１１５の経路で電子電流が流れる。このとき、電流は電子電流が支配しており（つまりモノポーラであり）、電流通路に接合がないから低電位においてもオフセット成分が生じない。つまり、微小電流領域においても直線性がよい。ドレイン電極１１４、１１５に印加される電圧極性が逆になった場合には電流の向きが逆になるが同様に動作する。その結果、図３３に示すように、交流電流を流すことができるとともに、微小電流領域においても直線性のよい動作が期待できる。 To turn on the above-described bidirectional LDMOSFET, a voltage is applied between the gate electrodes 112 and 113 and the source electrode 117 so that the gate electrodes 112 and 113 have a positive potential. At this time, a channel is formed immediately below the gate insulating films 110 and 111 in the p + well region 106. Here, assuming that a voltage is applied between the drain electrodes 114 and 115 so that the potential of the drain electrode 114 becomes high, the drain electrode 114 → the n ++ drain region 104 → the n semiconductor layer 103 → the gate electrode 112 The corresponding channel → the n ++ source region 107 → the source electrode 117 → the n ++ source region 108 → the channel corresponding to the gate electrode 113 → the n semiconductor layer 103 → the n ++ drain region 105 → the electron current in the route of the drain electrode 115 Flows. At this time, the current is dominated by the electron current (that is, it is monopolar), and there is no junction in the current path, so that no offset component occurs even at a low potential. That is, the linearity is good even in the minute current region. When the polarity of the voltage applied to the drain electrodes 114 and 115 is reversed, the direction of the current is reversed, but the operation is the same. As a result, as shown in FIG. 33, an alternating current can flow, and an operation with good linearity can be expected even in a minute current region.

一方、上述した双方向ＬＤＭＯＳＦＥＴをオフ状態にするには、ゲート電極１１２、１１３とソース電極１１７を短絡させる。これによってｐ+ ウェル領域１０６においてゲート絶縁膜１１０、１１１の直下に形成されていたチャネルが消滅し電子電流が流れなくなり、オフ状態となるのである。オフ状態ではドレイン電極１１４、１１５間に正負いずれの電圧を印加しても電流は流れない。つまり交流電圧に対してオフ状態になる。ここに、耐圧は双方向ＬＤＭＯＳＦＥＴの片側部分の耐圧に等しい。
上述した双方向ＬＤＭＯＳＦＥＴをもちいる１チップで交流電力をオン・オフさせることができ、しかも、導通時には微小電流領域においても電圧・電流特性の直線性がよく、信号電流のオン・オフに用いることが可能となる。また、ゲート電極１１２、１１３は共通接続されソース電極１１７は１つであるから、ゲートに制御信号を与える駆動回路も１つでよく制御が容易である。 On the other hand, to turn off the above-described bidirectional LDMOSFET, the gate electrodes 112 and 113 and the source electrode 117 are short-circuited. As a result, the channel formed immediately below the gate insulating films 110 and 111 in the p + well region 106 disappears, the electron current stops flowing, and the p + well region 106 is turned off. In the off state, no current flows regardless of whether a positive or negative voltage is applied between the drain electrodes 114 and 115. That is, it is turned off with respect to the AC voltage. Here, the breakdown voltage is equal to the breakdown voltage of one side portion of the bidirectional LDMOSFET.
AC power can be turned on and off with a single chip using the above-described bidirectional LDMOSFET, and when conducting, the linearity of the voltage-current characteristics is good even in a small current region, so that it can be used for turning on and off the signal current. Becomes possible. In addition, since the gate electrodes 112 and 113 are commonly connected and the number of the source electrodes 117 is one, only one drive circuit for supplying a control signal to the gate is required and control is easy.

前記のように、主電流はｐｎ接合を通らずにチャネルを通って流れるために、基本的に抵抗体を流れる電流と同じであり、電流は零電圧以上で流れ、小さな電流領域でのオン電圧は小さくなり、オン損失を小さくすることができる。
特開平１１−２２４９５０号公報 ＩＳＰＳＤ（Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｓｙｍｐｏｓｉｕｍ ｏｎ Ｐｏｗｅｒ Ｓｅｍｉｃｏｎｄｕｃｔｅｒ Ｄｅｖｉｃｅｓ ａｎｄ ＩＣｓ）１９９７、ｐｐ３７−４０） As described above, since the main current flows through the channel without passing through the pn junction, the main current is basically the same as the current flowing through the resistor. Is reduced, and the on-loss can be reduced.
JP-A-11-224950 ISPSD (International Symposium on Power Semiconductor Devices and ICs) 1997, pp. 37-40)

しかし、図３２の双方向ＬＤＭＯＳＦＥＴは、耐圧は双方向ＬＤＭＯＳＦＥＴの一方のＭＯＳＦＥＴの耐圧で維持するために、順逆耐圧を維持するためには両方のＭＯＳＦＥＴでそれぞれ耐圧が必要で、占有面積が２倍必要になり、ドレイン領域間での占有面積は大きくなる。また、プレーナ構造であるため双方向ＬＤＭＯＳＦＥＴを構成するセルの微細化が困難であり、従って、オン電圧を改善することが難しい。
この発明の目的は、前記の課題を解決して、双方向素子のセル密度を上げてオン電圧を小さくできる高耐圧の半導体装置およびその製造方法を提供することにある。 However, in the bidirectional LDMOSFET of FIG. 32, the breakdown voltage is maintained by the breakdown voltage of one MOSFET of the bidirectional LDMOSFET. In order to maintain the forward / reverse breakdown voltage, the breakdown voltage is required for both MOSFETs, and the occupied area is doubled. As a result, the area occupied by the drain regions increases. Also, because of the planar structure, it is difficult to miniaturize the cells constituting the bidirectional LDMOSFET, and it is therefore difficult to improve the on-voltage.
An object of the present invention is to solve the above-mentioned problems and to provide a high-breakdown-voltage semiconductor device capable of increasing a cell density of a bidirectional element and reducing an on-voltage, and a method of manufacturing the same.

前記の目的を達成するために、第１導電形半導体領域内に形成されたトレンチにより、前記半導体領域の表面層を分割して形成された第１、第２の分割半導体領域と、前記トレンチの底面または底面および側壁に形成された第１導電形の第１領域と、前記第１、第２の分割半導体領域にそれぞれ形成された、前記トレンチの側壁および前記第１領域に接する第２導電形の第２、第３領域と、前記第１の分割半導体領域に、前記トレンチの側壁と接し、前記第２領域に接して形成された第１導電形の第４領域と、前記第２の分割半導体領域に、前記トレンチの側壁と接し、前記第３領域に接して形成された第１導電形の第５領域と、前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第４領域に渡って第１絶縁膜を介して形成された第１制御電極と、前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第５領域に渡って第２絶縁膜を介して形成された第２制御電極と、前記第４領域上に形成された第１主電極と、前記第５領域上に形成された第２主電極と、を有する構成とする。   In order to achieve the above object, first and second divided semiconductor regions formed by dividing a surface layer of the semiconductor region by a trench formed in a first conductivity type semiconductor region; A first conductive type first region formed on the bottom surface or the bottom surface and the side wall; and a second conductive type contacting the trench side wall and the first region formed on the first and second divided semiconductor regions, respectively. Second and third regions, a fourth region of the first conductivity type formed in contact with a side wall of the trench and in contact with the second region, in the first divided semiconductor region, and in the second divided region. A fifth region of a first conductivity type formed in contact with a side wall of the trench in contact with the semiconductor region, and a fifth region of the first conductivity type formed in contact with the third region; Through the first insulating film over the fourth region A first control electrode formed, a second control electrode formed on the trench sidewall of the first divided semiconductor region from the first region to the fifth region via a second insulating film, The semiconductor device includes a first main electrode formed on the fourth region and a second main electrode formed on the fifth region.

また、前記第１領域と前記第２領域および前記第１領域と前記第３領域との間に前記第１領域より不純物濃度の低い第６領域を備えるとよい。
また、前記第１制御電極と前記第２制御電極が電気的に接続されるとよい。
また、前記第１制御電極と前記第２制御電極が電気的に絶縁されるとよい。
また、前記半導体領域が第２導電形の半導体基板の表面層に形成された領域であるとよい。
また、前記第１、第２の分割半導体領域を、それぞれ複数個備えるとよい。
また、前記第１の分割半導体領域と、前記第２の分割半導体領域とが互いに隣接して形成されるとよい。
また、前記第１、第２の分割半導体領域を、それぞれ複数個備え、隣接する分割半導体領域の間の前記トレンチ幅が、同じ分割領域間よりも異なる分割領域間の方が広いとよい。 Further, a sixth region having a lower impurity concentration than the first region may be provided between the first region and the second region, and between the first region and the third region.
Further, it is preferable that the first control electrode and the second control electrode are electrically connected.
Further, it is preferable that the first control electrode and the second control electrode are electrically insulated.
Further, it is preferable that the semiconductor region is a region formed in a surface layer of a semiconductor substrate of the second conductivity type.
It is preferable that a plurality of the first and second divided semiconductor regions are provided.
Further, it is preferable that the first divided semiconductor region and the second divided semiconductor region are formed adjacent to each other.
Further, it is preferable that a plurality of the first and second divided semiconductor regions are provided, and the trench width between adjacent divided semiconductor regions is wider between different divided regions than between the same divided regions.

また、前記第１、２の主電極は、それぞれ前記第２、第３領域と電気的に接続されるとよい。
また、前記制御電極の内側に層間絶縁膜を介して前記第１領域に達する導電体を有するとよい。
また、前記トレンチの底面に形成され、前記第２、第３領域と接し、前記導電体と接する第２導電形の第７領域を有するとよい。
また、前記双方向素子と、該双方向素子を制御する制御用回路とを同一の半導体基板に形成するとよい。
また、第１導電形の半導体領域の表面層に第２導電型の拡散領域を形成する工程と、前記拡散領域表面からトレンチを形成し、該トレンチにより囲まれた第１、第２の分割半導体領域を形成する工程と、前記トレンチ底面から拡散により前記半導体領域と接続する第１導電形の第１領域を形成する工程と、前記第１の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第２領域の表面層より前記トレンチの側壁と接するように第１導電形の第４領域を形成する工程と、前記第２の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第３領域の表面層より前記トレンチの側壁と接するように第１導電型の第５領域を形成する工程と、前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第４領域に渡って絶縁膜を介して第１制御電極を形成する工程と、前記第２の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第５領域に渡って絶縁膜を介して第２制御電極を形成する工程と、前記第４領域上に第１主電極を形成する工程と、前記第５領域上に第２主電極を形成する工程と、を含む製造方法とする。 Further, the first and second main electrodes may be electrically connected to the second and third regions, respectively.
Further, it is preferable that a conductor reaching the first region via an interlayer insulating film is provided inside the control electrode.
The semiconductor device may further include a seventh region of a second conductivity type formed on the bottom surface of the trench, in contact with the second and third regions, and in contact with the conductor.
Further, it is preferable that the bidirectional element and a control circuit for controlling the bidirectional element are formed on the same semiconductor substrate.
Forming a second conductivity type diffusion region in a surface layer of the first conductivity type semiconductor region; forming a trench from the surface of the diffusion region; and forming first and second divided semiconductors surrounded by the trench. Forming a region, forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the bottom of the trench, and forming the semiconductor region and the first region in the first divided semiconductor region. Forming a fourth region of the first conductivity type so as to be in contact with a side wall of the trench from a surface layer of a second region surrounded by the region and the trench; and forming the semiconductor region in the second divided semiconductor region. Forming a fifth region of a first conductivity type so as to contact a side wall of the trench from a surface layer of a third region surrounded by the first region and the trench; and forming a fifth region of the first divided semiconductor region. Trench side Forming a first control electrode through an insulating film from the first region to the fourth region; and forming the first control electrode on the trench sidewall of the second divided semiconductor region from the first region to the fifth region. Forming a second control electrode over an area through an insulating film, forming a first main electrode on the fourth area, and forming a second main electrode on the fifth area; And a manufacturing method including:

また、前記トレンチを前記半導体領域に達するように形成し、前記第１領域は前記半導体領域内部に形成する製造方法とするとよい。
また、前記トレンチを前記半導体領域に達するように形成し、前記第１領域は前記第２、第３領域と接続するように形成する製造方法とするとよい。
また、第１導電形の半導体領域表面からトレンチを形成し、該トレンチにより囲まれた第１、第２の分割半導体領域を形成する工程と、前記半導体領域の表面層に第２導電型の拡散領域を形成する工程と、前記トレンチ底面から拡散により前記半導体領域と接続する第１導電形の第１領域を形成する工程と、前記第１の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第２領域の表面層より前記トレンチの側壁と接するように第１導電形の第４領域を形成する工程と、前記第２の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第３領域の表面層より前記トレンチの側壁と接するように第１導電型の第５領域を形成する工程と、前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第４領域に渡って絶縁膜を介して第１制御電極を形成する工程と、前記第２の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第５領域に渡って絶縁膜を介して第２制御電極を形成する工程と、前記第４領域上に第１主電極を形成する工程と、前記第５領域上に第２主電極を形成する工程と、を含む製造方法とする。 The manufacturing method may be such that the trench is formed so as to reach the semiconductor region, and the first region is formed inside the semiconductor region.
The manufacturing method may be such that the trench is formed so as to reach the semiconductor region, and the first region is formed so as to be connected to the second and third regions.
Forming a trench from the surface of the semiconductor region of the first conductivity type, forming first and second divided semiconductor regions surrounded by the trench; and diffusing a second conductivity type in a surface layer of the semiconductor region. Forming a region, forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the bottom of the trench, and forming the semiconductor region and the first region in the first divided semiconductor region. Forming a fourth region of the first conductivity type so as to be in contact with a side wall of the trench from a surface layer of a second region surrounded by the region and the trench; and forming the semiconductor region in the second divided semiconductor region. Forming a fifth region of a first conductivity type from a surface layer of a third region surrounded by the first region and the trench so as to be in contact with a sidewall of the trench; and forming a fifth region of the first divided semiconductor region. Trench Forming a first control electrode on a wall via an insulating film from the first region to the fourth region; and forming the first control electrode on the trench side wall of the second divided semiconductor region from the first region. Forming a second control electrode through an insulating film over five regions, forming a first main electrode on the fourth region, and forming a second main electrode on the fifth region And a manufacturing method including:

また、前記第１制御電極と前記第２制御電極との間に層間絶縁膜を形成する工程を含む製造方法とするとよい。
また、前記層間絶縁膜に前記第１領域に達する開口部を形成する工程と、該開口部に導電体を充填する工程と、を含む製造方法とするとよい。
また、前記トレンチの底面に、前記１領域と隣接して、前記第２、第３領域と接するように第２導電形の第６領域を形成する工程を含む製造方法とするとよい。
また、前記第１、第２の分割半導体領域をそれぞれ複数個形成する製造方法とするとよい。
また、前記第１の分割半導体領域と前記第２の分割半導体領域との間の前記トレンチを第１のトレンチ、前記第１の分割半導体領域同士の間および前記第２の分割半導体領域同士の間の前記トレンチを第２のトレンチ、とした場合前記第１のトレンチの幅を前記第２のトレンチの幅より広く形成する製造方法とするとよい。 In addition, the manufacturing method may include a step of forming an interlayer insulating film between the first control electrode and the second control electrode.
It is preferable that the manufacturing method includes a step of forming an opening reaching the first region in the interlayer insulating film, and a step of filling the opening with a conductor.
The manufacturing method may include a step of forming a sixth region of the second conductivity type on the bottom surface of the trench, adjacent to the first region and in contact with the second and third regions.
Further, it is preferable to adopt a manufacturing method of forming a plurality of the first and second divided semiconductor regions.
In addition, the trench between the first divided semiconductor region and the second divided semiconductor region is defined as a first trench, between the first divided semiconductor regions, and between the second divided semiconductor regions. In the case where the trench is a second trench, the manufacturing method may be such that the width of the first trench is formed wider than the width of the second trench.

この発明によれば、半導体基板にトレンチを形成し、このトレンチの側壁にゲート電極を形成し、トレンチ底面下にドレイン領域を形成し、そのドレイン領域上に絶縁膜を形成し、トレンチで囲まれた半導体領域に第１、第２ソース領域を形成を形成することで、双方向素子の高耐圧化と低オン電圧化を図ることができる。
また、トレンチで囲まれた半導体領域に第１、第２ソース領域とコンタクト領域を形成し、これらの上に第１、第２ソース電極を形成することで、双方向素子の安全動作領域を広くすることができる。
また、半導体基板にトレンチを形成し、このトレンチの側壁にゲート電極を形成し、トレンチ底面下に浮遊したソース領域を形成し、そのソース領域上に絶縁膜を形成し、トレンチで囲まれた半導体領域に第１、第２ドレイン領域を形成を形成することで、双方向素子の高耐圧化と低オン電圧化を図ることができる。 According to the present invention, a trench is formed in a semiconductor substrate, a gate electrode is formed on a side wall of the trench, a drain region is formed below a bottom surface of the trench, an insulating film is formed on the drain region, and the trench is surrounded by the trench. By forming the first and second source regions in the formed semiconductor region, it is possible to achieve a high withstand voltage and a low on-voltage of the bidirectional element.
In addition, the first and second source regions and the contact region are formed in the semiconductor region surrounded by the trench, and the first and second source electrodes are formed thereon, so that the safe operation region of the bidirectional element can be widened. can do.
Also, a trench is formed in a semiconductor substrate, a gate electrode is formed on a side wall of the trench, a source region is formed under the trench bottom, an insulating film is formed on the source region, and a semiconductor surrounded by the trench is formed. By forming the first and second drain regions in the region, it is possible to achieve a high withstand voltage and a low on-voltage of the bidirectional element.

また、トレンチ底面下にソース領域とベースピックアップ領域を形成し、これらの上に金属電極を形成することで、双方向素子の安全動作領域を広くすることができる。   Further, by forming a source region and a base pickup region below the bottom of the trench and forming a metal electrode thereon, a safe operation region of the bidirectional element can be widened.

以下の説明では第１導電形をｎ形とし、第２導電形をｐ形として説明したがこれを逆にしても構わない。   In the following description, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be p-type, but this may be reversed.

図１、この発明の第１実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＡ部拡大図、同図（ｃ）は同図（ｂ）のＸ−Ｘ線で切断した要部断面図である。ここでは双方向ＬＭＯＳＦＥＴ（双方向横型ＭＯＳＦＥＴ）を例に挙げて説明する。この双方向ＬＭＯＳＦＥＴの構造はＴＬＰＭ（トレンチ・ラテラル・パワー・ＭＯＳＦＥＴ）構造と類似している。
ｐ半導体基板１にｎウェル領域２を形成し、このｎウェル領域２にトレンチ３を形成し、このトレンチ底面３ａ下にｎドレイン領域４を形成し、ｎウェル領域２の表面層にｐオフセット領域５を形成する。
トレンチ３内壁にゲート絶縁膜６を形成し、トレンチ側壁３ｂにゲート絶縁膜を介してゲート電極７を形成する。トレンチ３に囲まれたｐオフセット領域５の表面にトレンチ３と接するように選択的に第１ｎソース領域９と第２ｎソース領域１０を形成する。この第１ｎソース領域９と第２ｎソース領域１０はトレンチ３を挟んで交互に形成される。ゲート電極７上とトレンチ３内部を層間絶縁膜８で充填し平坦化する。全面に層間絶縁膜８ａを形成した後、この層間絶縁膜にコンタクトホールを開口して、第１ｎソース領域９上と第２ｎソース領域１０上に第１ソース電極１１と第２ソース電極１２をそれぞれ形成する。第１ソース電極１１同士、第２ソース電極１２同士は第１ソース配線１３、第２ソース配線１４でそれぞれ接続する。またゲート電極７は図示しないゲートパッドとゲート配線を介して接続する。 1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of a main part, and FIG. 1B is an enlarged view of a portion A in FIG. FIG. 3C is a cross-sectional view of a main part taken along line XX of FIG. Here, a bidirectional LMOSFET (bidirectional lateral MOSFET) will be described as an example. The structure of this bidirectional LMOSFET is similar to a TLPM (trench lateral power MOSFET) structure.
An n-well region 2 is formed in a p-type semiconductor substrate 1, a trench 3 is formed in the n-well region 2, an n-drain region 4 is formed below the trench bottom surface 3a, and a p-offset region is formed in a surface layer of the n-well region 2. 5 is formed.
A gate insulating film 6 is formed on the inner wall of the trench 3, and a gate electrode 7 is formed on the trench side wall 3b via the gate insulating film. First n source region 9 and second n source region 10 are selectively formed on the surface of p offset region 5 surrounded by trench 3 so as to be in contact with trench 3. The first n source regions 9 and the second n source regions 10 are formed alternately with the trench 3 interposed therebetween. The gate electrode 7 and the inside of the trench 3 are filled with an interlayer insulating film 8 and flattened. After an interlayer insulating film 8a is formed on the entire surface, a contact hole is opened in the interlayer insulating film, and a first source electrode 11 and a second source electrode 12 are formed on the first n source region 9 and the second n source region 10, respectively. Form. The first source electrodes 11 are connected to each other and the second source electrodes 12 are connected to each other via a first source wiring 13 and a second source wiring 14. The gate electrode 7 is connected to a gate pad (not shown) via a gate wiring.

前記したように、ｎドレイン領域４をトレンチ底部に形成されていることで、電界が緩和され３０Ｖ程度の高耐圧を確保することができる。
また、前記のように、ゲート電極７とｎドレイン領域４をトレンチ３底部に形成することで、耐圧がトレンチ３に沿って維持されるようになり、そのため、第１ｎソース領域９と第２ｎソース領域１０の表面での間隔を狭くでき、セルの微細化ができる。その結果、オン電圧を低下させることができる。
尚、前記したようにｐ半導体基板１を用いることで、この基板１をグランド電位にすることができて、図示しないＣＭＯＳ回路などをこの基板１に形成することが容易になる。また、前記のトレンチ底部に形成されるｎ拡張ｎドレイン領域４は、離れて形成されているが、それぞれのｎドレイン領域４が接するように形成しても構わない。 As described above, since the n-drain region 4 is formed at the bottom of the trench, the electric field is relaxed and a high withstand voltage of about 30 V can be secured.
Further, as described above, by forming the gate electrode 7 and the n-drain region 4 at the bottom of the trench 3, the withstand voltage is maintained along the trench 3, so that the first n-source region 9 and the second n-source The interval on the surface of the region 10 can be reduced, and the cell can be miniaturized. As a result, the ON voltage can be reduced.
By using the p semiconductor substrate 1 as described above, the substrate 1 can be set to the ground potential, and it becomes easy to form a CMOS circuit or the like (not shown) on the substrate 1. Further, the n-extended n-drain regions 4 formed at the bottom of the trench are formed apart from each other, but may be formed so that the respective n-drain regions 4 are in contact with each other.

また、図２に記載のような構成としても構わない。図２（ａ）は、ｎウェル領域２が図１（ｃ）におけるｎドレイン領域４を兼ねている構成である。図２（ａ）（ｂ）は半導体基板がｎ型の場合の構成であり、同図（ｂ）では、半導体基板１が図１（ｃ）におけるｎドレイン領域４を兼ねている構成である。同図（ｃ）では、同図（ｂ）においてｎドレイン領域４をさらに形成したものである。
また、図１（ｃ）では、ゲート電極７がトレンチ３内に左右に分かれて形成されているが、図２のように１つとなっていても構わない。
図３は、図１の双方向ＬＭＯＳＦＥＴの等価回路図である。この双方向ＬＤＭＯＳＦＥＴ５０の動作について説明する。第１ソース端子Ｓ１に対して第２ソース端子Ｓ２に高電圧を印加し、第２ソース端子Ｓ２より高い電圧をゲート端子Ｇに印加することで、図１の第１、第２ｎソース領域９、１０とｎドレイン領域４に挟まれたｐオフセット領域５側面にチャネルが形成されて第２ソース端子Ｓ２から第１ソース端子Ｓ１に電流が流れる。第２ソース端子Ｓ２に対して第１ソース端子Ｓ１に高電圧を印加し、第１ソース端子Ｓ１より高い電圧をゲート端子Ｇに印加することで、第１、第２ｎソース領域９、１０とｎドレイン領域４に挟まれたｐオフセット領域５側面にチャネルが形成されて第１ソース端子Ｓ１から第２ソース端子Ｓ２に電流が流れる。このように、双方向に電流を流すことができる双方向ＬＭＯＳＦＥＴとなる。 Further, a configuration as shown in FIG. 2 may be used. FIG. 2A shows a configuration in which the n-well region 2 also serves as the n-drain region 4 in FIG. 1C. FIGS. 2A and 2B show a configuration in the case where the semiconductor substrate is an n-type, and FIG. 2B shows a configuration in which the semiconductor substrate 1 also serves as the n-drain region 4 in FIG. 1C. In FIG. 3C, the n-drain region 4 in FIG. 3B is further formed.
Further, in FIG. 1C, the gate electrode 7 is formed in the trench 3 so as to be divided into right and left, but may be one as shown in FIG.
FIG. 3 is an equivalent circuit diagram of the bidirectional LMOSFET of FIG. The operation of the bidirectional LDMOSFET 50 will be described. By applying a high voltage to the second source terminal S2 with respect to the first source terminal S1 and applying a voltage higher than the second source terminal S2 to the gate terminal G, the first and second n source regions 9 in FIG. A channel is formed on the side surface of the p offset region 5 sandwiched between the drain region 10 and the n drain region 4, and a current flows from the second source terminal S2 to the first source terminal S1. By applying a high voltage to the first source terminal S1 with respect to the second source terminal S2 and applying a voltage higher than the first source terminal S1 to the gate terminal G, the first and second n source regions 9, 10 and n A channel is formed on the side surface of the p-offset region 5 sandwiched between the drain regions 4, and a current flows from the first source terminal S1 to the second source terminal S2. As described above, a bidirectional LMOSFET capable of flowing a current in both directions is obtained.

一方、ゲート端子Ｇを第１、第２ソース端子Ｓ１、Ｓ２の内の低電位側の端子の電位にするか、グランド電位にすることで、ｐオフセット領域５に形成されたチャネルを消滅させて双方向ＬＭＯＳＦＥＴを阻止状態とすることができる。   On the other hand, by setting the gate terminal G to the potential of the lower potential side terminal of the first and second source terminals S1 and S2 or to the ground potential, the channel formed in the p offset region 5 is extinguished. The bidirectional LMOSFET can be in a blocking state.

図４は、この発明の第２実施例の半導体装置の構成図であり、同図（ａ）は図１（ｂ）に相当する要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。図１との違いは、ｐオフセット領域５の表面層に第１および第２ｎソース領域９、１０に囲まれたｐコンタクト領域１５、１６を形成し、第１ｎソース領域９上と第２ｎソース領域１０上とそれぞれのｐコンタクト１５、１６を形成している点である。動作は図３の説明と同じである。
前記のように、ｐコンタクト領域１５、１６を形成することで、ｐオフセット領域５の電位が安定し、双方向ＬＭＯＳＦＥＴの安全動作領域が広くなる。その他は第１実施例と同じである。
尚、この双方向ＬＭＯＳＦＥＴはｐコンタクト領域１５、１６が形成されることで寄生ダイオードが内蔵され、双方向ＩＧＢＴとしての動作モードもある。そのため、ゲート電圧（ゲート電極７の電圧）が高電位側のソース電極の電圧より低い場合でも第１ソース電極１１と第２ソース電極１２の間に主電流を流すことができる。 4A and 4B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention. FIG. 4A is a plan view of a main part corresponding to FIG. 1B, and FIG. It is principal part sectional drawing cut | disconnected by XX of FIG. The difference from FIG. 1 is that p contact regions 15 and 16 surrounded by first and second n source regions 9 and 10 are formed in the surface layer of the p offset region 5, and the p contact regions 15 and 16 are formed on the first n source region 9 and the second n source region. 10 and the p contacts 15 and 16 are formed. The operation is the same as that described with reference to FIG.
By forming the p-contact regions 15 and 16 as described above, the potential of the p-offset region 5 is stabilized, and the safe operation region of the bidirectional LMOSFET is widened. Others are the same as the first embodiment.
The bidirectional LMOSFET has a built-in parasitic diode due to the formation of the p contact regions 15 and 16, and also has an operation mode as a bidirectional IGBT. Therefore, even when the gate voltage (the voltage of the gate electrode 7) is lower than the voltage of the source electrode on the high potential side, the main current can flow between the first source electrode 11 and the second source electrode 12.

図５は、この発明の第３実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＢ部拡大図、同図（ｃ）は同図（ｂ）のＸ−Ｘ線で切断した要部断面図である。ここでは双方向ＬＭＯＳＦＥＴを例に挙げて説明する。
ｐ半導体基板１にｎウェル領域２を形成し、このｎウェル領域２にトレンチ３３を形成し、このトレンチ底面３３ａ下にｎソース領域３４を形成し、ｎウェル領域２の表面層にｐオフセット領域３５を形成する。
トレンチ３３内壁にゲート絶縁膜３６を形成し、トレンチ側壁３３ｂにゲート絶縁膜３６を介してゲート電極３７を形成する。トレンチ３３に囲まれたｐオフセット領域３５の表面にトレンチ３３と接するように第１ｎドレイン領域３９と第２ｎドレイン領域４０を形成する。この第１ｎドレイン領域３９と第２ｎドレイン領域４０はトレンチ３３を挟んで交互に形成される。ゲート電極３７上とトレンチ３３内部を層間絶縁膜３８で充填し平坦化する。この層間絶縁膜３８にコンタクトホールを開口して、第１ｎドレイン領域３９上と第２ｎドレイン領域４０上に第１ドレイン電極４１と第２ドレイン電極４２をそれぞれ形成し、またｎソース領域３４の表面を露出させ、ピックアップ電極４５を充填する。このピックアップ電極４５はｎソース領域が複数に分割されて形成されている場合等電位にする効果があり、また、制御電圧を印加して所定の電位とすることが可能である。例えば、装置のオフ時にグランド電位を印加しＤ１、Ｄ２間に電流が流れないようにすることができる。また、第１ドレイン電極４１同士、第２ドレイン電極４２同士は第１ドレイン配線４３、第２ドレイン配線４４でそれぞれ接続する。またゲート電極３７は図示しないゲートパッドとゲート配線を介して接続する。 5A and 5B are configuration diagrams of a semiconductor device according to a third embodiment of the present invention. FIG. 5A is a plan view of a main part, and FIG. 5B is an enlarged view of a portion B in FIG. FIG. 3C is a cross-sectional view of a main part taken along line XX of FIG. Here, a bidirectional LMOSFET will be described as an example.
An n well region 2 is formed in a p semiconductor substrate 1, a trench 33 is formed in the n well region 2, an n source region 34 is formed below the trench bottom surface 33a, and a p offset region is formed in a surface layer of the n well region 2. 35 is formed.
A gate insulating film 36 is formed on the inner wall of the trench 33, and a gate electrode 37 is formed on the trench side wall 33b via the gate insulating film 36. A first n drain region 39 and a second n drain region 40 are formed on the surface of the p offset region 35 surrounded by the trench 33 so as to be in contact with the trench 33. The first n drain regions 39 and the second n drain regions 40 are formed alternately with the trench 33 interposed therebetween. The gate electrode 37 and the inside of the trench 33 are filled with an interlayer insulating film 38 and flattened. A contact hole is opened in the interlayer insulating film 38, a first drain electrode 41 and a second drain electrode 42 are formed on the first n drain region 39 and the second n drain region 40, respectively. And the pickup electrode 45 is filled. This pickup electrode 45 has an effect of setting the same potential when the n source region is formed by dividing the source region into a plurality of parts, and can be set at a predetermined potential by applying a control voltage. For example, a ground potential can be applied when the device is off to prevent a current from flowing between D1 and D2. The first drain electrodes 41 and the second drain electrodes 42 are connected by a first drain wiring 43 and a second drain wiring 44, respectively. The gate electrode 37 is connected to a gate pad (not shown) via a gate wiring.

ｎソース領域３４をトレンチ底部に形成し、その上に層間絶縁膜３８が被覆されていることで、電界が緩和され３０Ｖ程度の高耐圧を確保することができる。
また、前記のように、ゲート電極３７とｐオフセット領域３５をトレンチ内に形成することで、耐圧がトレンチ側壁３３ｂに沿って維持されるようになり、そのため、第１ｎドレイン領域３９と第２ｎドレイン領域４０の表面での間隔を狭くでき、セルの微細化ができる。その結果、オン電圧を低下させることができる。
尚、前記したようにｐ半導体基板１を用いることで、この基板１をグランド電位にすることができて、図示しないＣＭＯＳ回路などをこの基板１に形成することが容易になる。また、前記のトレンチ底部に形成されるｎソース領域３４は、離れて形成されているが、それぞれのｎドレイン領域３４が接するように形成しても構わない。 Since the n source region 34 is formed at the bottom of the trench and is covered with the interlayer insulating film 38, the electric field is relaxed and a high withstand voltage of about 30 V can be secured.
Further, as described above, by forming the gate electrode 37 and the p-offset region 35 in the trench, the breakdown voltage is maintained along the trench side wall 33b, so that the first n-drain region 39 and the second n-drain The interval on the surface of the region 40 can be reduced, and the cell can be miniaturized. As a result, the ON voltage can be reduced.
By using the p semiconductor substrate 1 as described above, the substrate 1 can be set to the ground potential, and it becomes easy to form a CMOS circuit or the like (not shown) on the substrate 1. Although the n source regions 34 formed at the bottom of the trench are formed apart from each other, they may be formed so that the respective n drain regions 34 are in contact with each other.

図６は、図５の双方向ＬＭＯＳＦＥＴの等価回路図である。この双方向ＬＭＯＳＦＥＴ６０の動作について説明する。第１ドレイン端子Ｄ１に対して第２ドレイン端子Ｄ２に高電圧を印加し、第１ドレイン端子Ｄ１より高い電圧をゲート端子Ｇに印加することで、図５に示す第１、第２ｎドレイン領域３９、４０とｎソース領域３４に挟まれたｐオフセット領域３５側面にチャネルが形成されて第２ドレイン端子Ｄ２から第１ドレイン端子Ｄ１に電流が流れる。第２ドレイン端子Ｄ２に対して第１ドレイン端子Ｄ１に高電圧を印加し、第２ドレイン端子Ｄ２より高い電圧をゲート電極Ｇに印加することで、第１、第２ｎドレイン領域３９、４０とｎソース領域３４に挟まれたｐオフセット領域３５側面にチャネルが形成されて第１ドレイン端子Ｄ１から第２ドレイン端子Ｄ２に電流が流れる。このように、双方向のＬＭＯＳＦＥＴとなる。   FIG. 6 is an equivalent circuit diagram of the bidirectional LMOSFET of FIG. The operation of the bidirectional LMOSFET 60 will be described. By applying a high voltage to the second drain terminal D2 with respect to the first drain terminal D1 and applying a voltage higher than the first drain terminal D1 to the gate terminal G, the first and second n drain regions 39 shown in FIG. , 40 and a channel is formed on the side surface of p offset region 35 interposed between n source regions 34, and current flows from second drain terminal D2 to first drain terminal D1. By applying a high voltage to the first drain terminal D1 with respect to the second drain terminal D2 and applying a higher voltage to the gate electrode G than the second drain terminal D2, the first and second n drain regions 39, 40 and n A channel is formed on the side surface of the p offset region 35 interposed between the source regions 34, and current flows from the first drain terminal D1 to the second drain terminal D2. Thus, a bidirectional LMOSFET is obtained.

一方、ゲート端子Ｇを第１、第２ドレイン端子Ｄ１、Ｄ２の内低い電位と同じ電位にすることで、ｐオフセット領域３５に形成されたチャネルを消滅させ、双方向ＬＭＯＳＦＥＴを阻止状態とすることができる。   On the other hand, by setting the gate terminal G to the same potential as the lower potential of the first and second drain terminals D1 and D2, the channel formed in the p-offset region 35 is extinguished, and the bidirectional LMOSFET is brought into a blocking state. Can be.

図７は、この発明の第４実施例の半導体装置の構成図であり、同図（ａ）は図５（ｂ）に相当する要部平面図、同図（ｂ）は同図（ａ）のＸ１−Ｘ１で切断した要部断面図、同図（ｃ）は同図（ａ）のＸ２−Ｘ２で切断した要部断面図である。ここでは双方向ＬＭＯＳＦＥＴを例に挙げて説明する。
図５との違いは、トレンチ底面３３ａ下のｎソース領域３４の隣にｐベースピックアップ領域４６を形成し、このｎソース領域３４とｐベースピックアップ領域３６に接するようにピックアップ電極４５を形成した点である。動作は図５で説明した内容と同じである。
このように、ｐベースピックアップ領域４６を形成し、このｐベースピックアップ領域４６とｎソース領域３４をピックアップ電極４５で短絡することで、ｐオフセット領域３５の電位が安定し、双方向ＬＭＯＳＦＥＴの安全動作領域が広くなる。その他は第３実施例と同じである。 7A and 7B are configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention. FIG. 7A is a plan view of a main part corresponding to FIG. 5B, and FIG. (C) is a cross-sectional view of a main part taken along line X2-X2 in (a) of FIG. Here, a bidirectional LMOSFET will be described as an example.
The difference from FIG. 5 is that a p-base pickup region 46 is formed next to the n-source region 34 below the trench bottom surface 33a, and a pickup electrode 45 is formed so as to be in contact with the n-source region 34 and the p-base pickup region 36. It is. The operation is the same as that described with reference to FIG.
Thus, by forming the p base pickup region 46 and short-circuiting the p base pickup region 46 and the n source region 34 by the pickup electrode 45, the potential of the p offset region 35 is stabilized, and the safe operation of the bidirectional LMOSFET is achieved. The area becomes wider. Others are the same as the third embodiment.

図８は、この発明の第５実施例の半導体装置の要部配置図である。ここでは、バッテリー装置に搭載されるパワーＩＣを例として示した。
このパワーＩＣは、同一半導体基板９１に双方向ＬＭＯＳＦＥＴ５０と駆動・保護回路部５１と残量回路部５２を形成する。駆動・保護回路部５１と残量回路部５２は電池セル９２の電圧と、電池セル９２に図示しないチャジャーから流入する充電電流と、電池セ９２ルから負荷（携帯機器など）へ流出する放電電流を抵抗９３で検出して、双方向ＬＭＯＳＦＥＴ５０を正常に制御し、過充電や過放電のような異常時の場合には双方向ＬＭＯＳＦＥＴ５０をオフする信号を双方向ＬＭＯＳＦＥＴ５０へ伝送する働きをする。尚、駆動・保護回路部５１にはチャージポンプ回路５３が入っており、双方向ＬＭＯＳＦＥＴ５０の第１、第２ソース端子Ｓ１、Ｓ２の電圧より高い電圧をゲート端子Ｇへ与えることができるようになっている。また、制御端子は電池セル９２の電荷残量を外部から指定する端子である。 FIG. 8 is a layout view of a main part of a semiconductor device according to a fifth embodiment of the present invention. Here, the power IC mounted on the battery device is shown as an example.
In this power IC, a bidirectional LMOSFET 50, a drive / protection circuit unit 51, and a remaining amount circuit unit 52 are formed on the same semiconductor substrate 91. The drive / protection circuit unit 51 and the remaining amount circuit unit 52 are provided with a voltage of the battery cell 92, a charging current flowing into the battery cell 92 from a charger (not shown), and a discharging current flowing out of the battery cell 92 to a load (eg, a portable device). Is detected by the resistor 93, and the bidirectional LMOSFET 50 is controlled normally, and in the case of an abnormality such as overcharge or overdischarge, a signal for turning off the bidirectional LMOSFET 50 is transmitted to the bidirectional LMOSFET 50. The drive / protection circuit unit 51 includes a charge pump circuit 53, and can apply a voltage higher than the voltages of the first and second source terminals S1 and S2 of the bidirectional LMOSFET 50 to the gate terminal G. ing. The control terminal is a terminal for externally specifying the remaining charge of the battery cell 92.

図９は、この発明の第６実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｃ）は工程順に示した要部製造工程断面図である。これは図１の双方向ＬＭＯＳＦＥＴの製造方法である。
ｐ半導体基板１上に、ｎウェル領域２を形成し、続いて、表面濃度１×１０17ｃｍ-3、拡散深さ１μｍのｐオフセット領域５を形成し、酸化膜をマスクとしてｎウェル領域２に幅１．５μｍのトレンチ３を形成し、トレンチ３の窓からトレンチ３の底面３ａに表面濃度１×１０18ｃｍ-3、拡散深さ１μｍのｎドレイン領域４をイオン注入と熱処理（ドライブ）で形成する（同図（ａ））。ここでは、ウェル領域２、ｐオフセット領域５を形成した後にトレンチ３を形成したが、トレンチ３を形成した後で形成してもよい。
つぎに、トレンチ側壁３ｂのチャネル形成箇所に図示しないしきい値調整用のイオン注入をチルド角４５度で行い、表面濃度７×１０16ｃｍ-3、拡散深さ０．３μｍの拡散層を形成する。続いて、チャネル形成箇所を清浄化しトレンチ内壁にゲート絶縁膜６（例えば、ゲート酸化膜）を形成し、このゲート絶縁膜６上にゲート電極７となるドープドポリシリコンを０．３μｍの厚さで堆積させ、異方性エッチングによりゲート電極７を形成する（同図（ｂ））。 9A to 9C show a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention. FIGS. 9A to 9C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a method for manufacturing the bidirectional LMOSFET of FIG.
An n-well region 2 is formed on a p-type semiconductor substrate 1, a p-offset region 5 having a surface concentration of 1 × 10 17 cm −3 and a diffusion depth of 1 μm is formed, and an n-well region 2 is formed using an oxide film as a mask. A trench 3 having a width of 1.5 μm is formed, and an n-drain region 4 having a surface concentration of 1 × 10 18 cm −3 and a diffusion depth of 1 μm is ion-implanted and heat-treated (drive) from the window of the trench 3 to the bottom surface 3 a of the trench 3. (FIG. 3A). Here, the trench 3 is formed after the well region 2 and the p-offset region 5 are formed, but may be formed after the trench 3 is formed.
Next, ion implantation for threshold adjustment (not shown) is performed at a tilde angle of 45 degrees in a channel formation portion of the trench side wall 3b at a tilde angle of 45 degrees to form a diffusion layer having a surface concentration of 7 × 10 16 cm −3 and a diffusion depth of 0.3 μm. I do. Subsequently, the channel forming portion is cleaned to form a gate insulating film 6 (for example, a gate oxide film) on the inner wall of the trench. On this gate insulating film 6, doped polysilicon serving as a gate electrode 7 is formed to a thickness of 0.3 μm. And the gate electrode 7 is formed by anisotropic etching (FIG. 4B).

つぎに、ｐオフセット領域５の表面層に第１、第２ｎソース領域９、１０を形成し、層間絶縁膜８として酸化膜を堆積する。この工程でトレンチ内部は層間絶縁膜８が充填され、エッチバックにより層間絶縁膜８の表面を平坦化する。続いて、第１、第２ｎソース領域９、１０にコンタクト抵抗低減のためのイオン注入を行い、この第１、第２ｎソース領域９、１０上にアルミニウムなどで第１、第２ソース電極１１、１２を形成する。続いて、図示しない第１ソース配線、第２ソース配線を形成する（同図（ｃ））。   Next, first and second n source regions 9 and 10 are formed in the surface layer of the p offset region 5, and an oxide film is deposited as an interlayer insulating film 8. In this step, the inside of the trench is filled with the interlayer insulating film 8, and the surface of the interlayer insulating film 8 is planarized by etch back. Subsequently, ion implantation for reducing contact resistance is performed on the first and second n source regions 9 and 10, and the first and second source electrodes 11 are formed on the first and second n source regions 9 and 10 with aluminum or the like. 12 is formed. Subsequently, a first source wiring and a second source wiring (not shown) are formed (FIG. 3C).

図１０は、この発明の第７実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｃ）は工程順に示した要部製造工程断面図である。これは図３の双方向ＬＭＯＳＦＥＴの製造方法である。
図９と違うのは、図１０（ｃ）で、ｐコンタクト領域１５、１６を形成し、第１、第２ソース電極１１、１２とこのｐコンタクト領域１５、１６が接している点である。 10A to 10C show a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention. FIGS. 10A to 10C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a method for manufacturing the bidirectional LMOSFET of FIG.
9 is different from FIG. 9 in that p contact regions 15 and 16 are formed in FIG. 10C and the first and second source electrodes 11 and 12 and the p contact regions 15 and 16 are in contact with each other.

図１１は、この発明の第８実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｃ）は工程順に示した要部製造工程断面図である。これは図５の双方向ＬＭＯＳＦＥＴの製造方法である。
ｐ半導体基板１上に、ｎウェル領域２を形成し、図示しない酸化膜をマスクとしてｎウェル領域２に幅３μｍのトレンチ３３を形成し、トレンチ３３の窓からトレンチの底面３３ａに表面濃度１×１０18ｃｍ-3、拡散深さ１μｍのｎソース領域３４をイオン注入と熱処理（ドライブ）で形成する。続いて、マスク酸化膜を除去し、表面濃度１×１０17ｃｍ-3、拡散深さ１μｍのｐオフセット領域３５をｎドレイン領域３４と接するように、トレンチ３３で分割された分離半導体領域６１に形成する（同図（ａ））。
つぎに、トレンチの側壁３３ｂのチャネル形成箇所に、図示しないしきい値調整用のイオン注入をチルド角４５度で行い、表面濃度７×１０16ｃｍ-3、拡散深さ０．３μｍの拡散層を形成する。続いて、チャネル形成箇所を清浄化しトレンチ内壁にゲート絶縁膜３６を形成し、このゲート絶縁膜３６上にゲート電極３７となるドープドポリシリコンを０．３μｍの厚さで堆積させ、異方性エッチングによりゲート電極３７を形成する（同図（ｂ））。 FIGS. 11A to 11C show a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention. FIGS. 11A to 11C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a method for manufacturing the bidirectional LMOSFET of FIG.
An n-well region 2 is formed on a p-type semiconductor substrate 1, a 3 μm wide trench 33 is formed in the n-well region 2 using an oxide film (not shown) as a mask, and a surface concentration of 1 × An n source region 34 of 10 18 cm −3 and a diffusion depth of 1 μm is formed by ion implantation and heat treatment (drive). Subsequently, the mask oxide film is removed, and a p-offset region 35 having a surface concentration of 1 × 10 17 cm −3 and a diffusion depth of 1 μm is formed on the isolation semiconductor region 61 divided by the trench 33 so as to be in contact with the n-drain region 34. (FIG. 3A).
Next, ion implantation for threshold adjustment (not shown) is performed at a tilde angle of 45 degrees into a channel formation portion of the trench side wall 33b to form a diffusion layer having a surface concentration of 7 × 10 16 cm −3 and a diffusion depth of 0.3 μm. To form Subsequently, the channel formation portion is cleaned, a gate insulating film 36 is formed on the inner wall of the trench, and doped polysilicon serving as a gate electrode 37 is deposited on the gate insulating film 36 to a thickness of 0.3 μm, A gate electrode 37 is formed by etching (FIG. 4B).

つぎに、ｐオフセット領域３５の表面層に第１、第２ｎドレイン領域３９、４０を形成し、層間絶縁膜３８として酸化膜を堆積する。この工程では幅の広いトレンチ内部は層間絶縁膜３８で充填されず、エッチバックによりトレンチ底部の層間絶縁膜３８がエッチングで除去されｎソース領域３４の表面が露出する。続いて、トレンチの底面３３に図示しないバリアメタルを形成し、タングステンなどのピックアップ電極４５を埋め込み平坦化する。続いて、第１、第２ドレイン領域３９、４０にコンタクト抵抗低減のためのイオン注入を行い、この第１、第２ｎドレイン領域３９、４０上にアルミニウムなどで第１、第２ドレイン電極４１、４２を形成する。このとき、同時にピックアップ電極４５上にもアルミニウム膜を形成する。続いて、図示しない第１ドレイン配線、第２ドレイン配線を形成する（同図（ｃ））。   Next, first and second n drain regions 39 and 40 are formed in the surface layer of the p offset region 35, and an oxide film is deposited as an interlayer insulating film 38. In this step, the inside of the wide trench is not filled with the interlayer insulating film 38, and the interlayer insulating film 38 at the bottom of the trench is removed by etching back to expose the surface of the n source region 34. Subsequently, a barrier metal (not shown) is formed on the bottom surface 33 of the trench, and a pickup electrode 45 such as tungsten is buried and flattened. Subsequently, ion implantation for reducing contact resistance is performed on the first and second drain regions 39 and 40, and the first and second drain electrodes 41 and 42 are formed on the first and second n drain regions 39 and 40 with aluminum or the like. 42 is formed. At this time, an aluminum film is also formed on the pickup electrode 45 at the same time. Subsequently, a first drain wiring and a second drain wiring (not shown) are formed (FIG. 3C).

図１２は、この発明の第９実施例の半導体装置の製造方法であり、同図（ａ）、（ｂ）は図１１（ａ）に相当しする要部製造工程断面図、同図（ｃ）、（ｄ）は図１１（ｃ）に相当する要部製造工程断面図である。尚、同図（ａ）、（ｃ）は図７（ａ）のＸ１−Ｘ１に相当する要部製造工程断面図、同図（ｂ）、（ｄ）は図７（ａ）のＸ２−Ｘ２に相当する要部製造工程断面図である。これは図７の双方向ＬＭＯＳＦＥＴの製造方法である。
図１１と違うのは、図１２（ａ）で、トレンチ底部にｐベースピックアップ領域４６を形成し、図１２（ｃ）で、ピックアップ電極４５とこのｐベースピックアップ領域４６が接している点である。 12A and 12B show a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention. FIGS. 12A and 12B are cross-sectional views of a main part manufacturing process corresponding to FIG. 11D and 11D are cross-sectional views of a main part manufacturing step corresponding to FIG. 7 (a) and 7 (c) are cross-sectional views of a main part manufacturing process corresponding to X1-X1 of FIG. 7 (a), and FIGS. 7 (b) and 7 (d) are X2-X2 of FIG. 7 (a). FIG. 13 is a sectional view of a relevant part manufacturing step corresponding to FIG. This is a method for manufacturing the bidirectional LMOSFET of FIG.
11 is different from FIG. 11 in that a p-base pickup region 46 is formed at the bottom of the trench in FIG. 12A, and the pickup electrode 45 is in contact with the p-base pickup region 46 in FIG. 12C. .

図１３は、この発明の第１０実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｃ）は工程順に示した要部製造工程断面図である。これは図１の双方向ＬＭＯＳＦＥＴとＣＭＯＳを同一半導体基板に形成した製造方法である。ＣＭＯＳは図７の駆動・保護回路や残量回路を形成するための基本素子である。
ｐ半導体基板７１上に、ｎウェル領域７２を形成し、図示しない酸化膜をマスクとしてｎウェル領域７２に幅１．５μｍのトレンチ７３を形成し、ｐウェル領域７６も形成し、トレンチ７３の窓からトレンチの底面７３ａに表面濃度１×１０17ｃｍ-3、拡散深さ１μｍのｎドレイン領域７４をイオン注入と熱処理（ドライブ）で形成する。続いて、マスク酸化膜を除去し、表面濃度１×１０17ｃｍ-3、拡散深さ１μｍのｐオフセット領域７５を形成しする（同図（ａ））。 13A to 13C show a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention. FIGS. 13A to 13C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a manufacturing method in which the bidirectional LMOSFET and the CMOS shown in FIG. 1 are formed on the same semiconductor substrate. CMOS is a basic element for forming the drive / protection circuit and the remaining amount circuit of FIG.
An n-well region 72 is formed on p-semiconductor substrate 71, a 1.5-μm wide trench 73 is formed in n-well region 72 using an oxide film (not shown) as a mask, and a p-well region 76 is also formed. Then, an n-drain region 74 having a surface concentration of 1 × 10 17 cm −3 and a diffusion depth of 1 μm is formed on the bottom surface 73a of the trench by ion implantation and heat treatment (drive). Subsequently, the mask oxide film is removed to form a p-offset region 75 having a surface concentration of 1 × 10 17 cm −3 and a diffusion depth of 1 μm (FIG. 7A).

つぎに、ＬＯＣＯＳ工程により表面の素子分離を行い、ＣＭＯＳ部のチャネル形成箇所およびトレンチ側壁７３ｂのチャネル形成箇所に図示しないしきい値調整用のイオン注入をチルド角４５度で行い、表面濃度７×１０16ｃｍ-3、拡散深さ０．３μｍの拡散層を形成する。続いて、チャネル形成箇所を清浄化し、トレンチ内壁にゲート絶縁膜７９を形成し、このゲート絶縁膜７９上にゲート電極８０となるドープドポリシリコンを０．３μｍの厚さで堆積させ、異方性エッチングによりＣＭＯＳ部とトレンチ内部のゲート電極８０を形成する（同図（ｂ））。
つぎに、ｐオフセット領域７５の表面層に第１、第２ｎソース領域８１、８２を形成し、ＣＭＯＳ部にソース／ドレイン領域８３、８４を形成し、層間絶縁膜８７として酸化膜を堆積する。この工程でトレンチ内部は層間絶縁膜８７が充填され、エッチバックにより層間絶縁膜８７の表面を平坦化する。続いて、層間絶縁膜８７にコンタクトホールを形成し、開口部にコンタクト抵抗低減のためのプラグイオン注入を行い、第１、第２ｎソース領域８１、８２上にアルミニウムでなどで第１、第２ソース電極８５、８６を形成し、ＣＭＯＳ部のソース／ドレイン領域８３、８４上にソース／ドレイン電極８８、８９を形成する（同図（ｃ））。 Next, element isolation on the surface is performed by a LOCOS step, and ion implantation for threshold adjustment (not shown) is performed at a tilde angle of 45 degrees into a channel formation portion of the CMOS portion and a channel formation portion of the trench side wall 73b, and a surface concentration of 7 × A diffusion layer having a diffusion depth of 10 16 cm −3 and a depth of 0.3 μm is formed. Subsequently, the channel forming portion is cleaned, a gate insulating film 79 is formed on the inner wall of the trench, and doped polysilicon serving as a gate electrode 80 is deposited on the gate insulating film 79 to a thickness of 0.3 μm. A CMOS portion and a gate electrode 80 inside the trench are formed by reactive etching (FIG. 4B).
Next, first and second n source regions 81 and 82 are formed in the surface layer of the p offset region 75, source / drain regions 83 and 84 are formed in the CMOS portion, and an oxide film is deposited as an interlayer insulating film 87. In this step, the inside of the trench is filled with the interlayer insulating film 87, and the surface of the interlayer insulating film 87 is flattened by etch back. Subsequently, contact holes are formed in the interlayer insulating film 87, plug ions are implanted into the openings to reduce the contact resistance, and the first and second n-type source regions 81 and 82 are formed on the first and second n-type source regions 81 and 82 with aluminum or the like. Source electrodes 85 and 86 are formed, and source / drain electrodes 88 and 89 are formed on the source / drain regions 83 and 84 in the CMOS section (FIG. 3C).

前記した本発明の半導体装置とは別の半導体装置であってゲート配線構造まで含めた実施例について説明する。ゲート配線とソース電極は同時に金属膜で形成される。ここでは、コンタクトホールで接続されソース領域の真上に配置されたものをソース電極とし、それ以外の箇所をゲート配線とする。   An embodiment which is a semiconductor device different from the semiconductor device of the present invention and includes a gate wiring structure will be described. The gate wiring and the source electrode are simultaneously formed of a metal film. Here, the one connected by the contact hole and arranged immediately above the source region is defined as a source electrode, and the other part is defined as a gate wiring.

図１４から図１７は、この発明の第１１実施例の半導体装置であって、ゲート配線構造まで含めた要部構成図であり、図１４は平面図、図１５は図１４のＸ−Ｘ線で切断した断面図、図１６は図１４のＹ−Ｙ線で切断した断面図、図１７は図１４のＺ−Ｚ線で切断した断面図である。図１４は、表面から見た平面図であり、影に隠れた部分は点線で示す。また、層間絶縁膜２０８ａは図示していない。
図１と異なる点のみ説明すると、図１では一個の第１ｎソース領域９と一個の第２ｎソース領域１０が交互に配置されていたが、この実施例では、第１ｎソース領域２０９が隣接して複数個形成され、また第２ｎソース領域２１０も隣接して複数個形成されている。また、ｐオフセット領域２０５がｎドレイン領域２０４と接していない。さらに、各ソース領域には図４と同様にｐコンタクト領域２１５、２１６が形成されている。図１では図示しなかったゲート配線構造が図示されている。 14 to 17 show a semiconductor device according to an eleventh embodiment of the present invention, showing a main part configuration including a gate wiring structure. FIG. 14 is a plan view, and FIG. 15 is a line XX of FIG. 16, FIG. 16 is a cross-sectional view taken along line YY in FIG. 14, and FIG. 17 is a cross-sectional view taken along line ZZ in FIG. FIG. 14 is a plan view as viewed from the surface, and a portion hidden by a shadow is indicated by a dotted line. The interlayer insulating film 208a is not shown.
Only the points different from FIG. 1 will be described. In FIG. 1, one first n source region 9 and one second n source region 10 are alternately arranged. In this embodiment, however, the first n source regions 209 are adjacent to each other. A plurality of the second n source regions 210 are formed adjacent to each other. Further, the p offset region 205 is not in contact with the n drain region 204. Further, p contact regions 215 and 216 are formed in each source region as in FIG. A gate wiring structure not shown in FIG. 1 is shown.

前記の、ｐオフセット領域２０５がｎドレイン領域２０４と接しない場合は、接する場合に比べ耐圧を高くすることができ、オン抵抗を下げることができる。しかしながらｐオフセットの幅（ｎウェル領域２０２とソース領域２０９との間の幅）が狭いため製造時に高精度が要求される。
図１４から図１７に示すように、第１ｎソース領域２０９と層間絶縁膜２０８ａに形成されたコンタクトホール２１７を介して接続した第１ソース電極２１１と、第１ソース電極２１１と接続する第１ソース配線２１３とは同時に金属膜で形成される。また、第２ｎソース領域２１０と層間絶縁膜２０８ａに形成されたコンタクトホール２１７を介して接続した第２ソース電極２１２と、第２ソース電極２１２と接続する第２ソース配線２１４とは同時に金属膜で形成される。隣接した第１ｎソース領域２０９同士および第２ｎソース領域２１０同士の間はゲート絶縁膜２０６を介して形成されたゲート電極２０７で埋め込まれている。また第１ｎソース領域２０９群と第２ｎソース領域２１０群は互いに層間絶縁膜２０８を挟んで対峙している。トレンチ外周２０３ａを大きくして、この第１ｎソース領域２０９群と第２ｎソース領域２１０群を交互に多数配置することで電流容量を増加させることができる。 When the p-offset region 205 is not in contact with the n-drain region 204, the withstand voltage can be increased and the on-resistance can be reduced as compared with the case where the p-offset region 205 is in contact. However, since the width of the p-offset (the width between the n-well region 202 and the source region 209) is small, high precision is required during manufacturing.
As shown in FIGS. 14 to 17, a first source electrode 211 connected to the first n source region 209 via a contact hole 217 formed in the interlayer insulating film 208a, and a first source electrode connected to the first source electrode 211 The wiring 213 is formed simultaneously with a metal film. In addition, the second source electrode 212 connected to the second n source region 210 via the contact hole 217 formed in the interlayer insulating film 208a and the second source wiring 214 connected to the second source electrode 212 are simultaneously formed of a metal film. It is formed. A space between the adjacent first n source regions 209 and between the second n source regions 210 is filled with a gate electrode 207 formed with a gate insulating film 206 interposed therebetween. The first n source region 209 group and the second n source region 210 group face each other with the interlayer insulating film 208 interposed therebetween. The current capacity can be increased by enlarging the trench outer periphery 203a and alternately arranging a large number of the first n source regions 209 and the second n source regions 210.

ゲート電極２０７を形成するポリシリコンは、ｎソース領域２０９、２１０が形成されているトレンチ外周２０３ａから岬のように突き出した細長いトレンチ２０３ｂを形成し、そのトレンチ２０３ｂの内壁に形成されたゲート絶縁膜２０６を介してポリシリコン配線２１８が形成され、このポリシリコン配線２１８はｐ半導体基板２０１上に形成されたゲート絶縁膜２０６上にも形成される。このポリシリコン配線２１８と金属膜のゲート配線２１９とが層間絶縁膜２０８ａに開けたコンタクトホール２１７を介して接続する。
このように、前記した本発明の半導体装置では、トレンチ外周２０３ａの側壁全域に形成されるポリシリコン（ゲート電極２０７）で繋がっているため、ゲート電極２０７は１個となる。
このようにゲート電極が１個の半導体装置を使った適用装置例を前記の図８に示した。 The polysilicon forming the gate electrode 207 forms an elongated trench 203b protruding like a cap from the outer periphery 203a of the trench where the n source regions 209 and 210 are formed, and a gate insulating film formed on the inner wall of the trench 203b. Polysilicon wiring 218 is formed via 206, and this polysilicon wiring 218 is also formed on gate insulating film 206 formed on p semiconductor substrate 201. The polysilicon wiring 218 and the gate wiring 219 of a metal film are connected via a contact hole 217 formed in the interlayer insulating film 208a.
As described above, in the above-described semiconductor device of the present invention, since the polysilicon (gate electrode 207) formed over the entire sidewall of the trench outer periphery 203a is connected, only one gate electrode 207 is provided.
FIG. 8 shows an example of an application apparatus using a semiconductor device having a single gate electrode.

図１８は、図８の双方向ＬＭＯＳＦＥＴと駆動・保護回路部を抜き書きした図であり、同図（ａ）〜同図（ｃ）は電池セルが過充電されるときの時間的な経過を示した図である。
同図（ａ）において、図８の電池セル９２に図示しない負荷である携帯機器を接続した状態で充電している場合は、ゲート端子Ｇにオン信号を与え、左右のｎチャネルＭＯＳＦＥＴをオン状態として、電池セル９２に双方向ＬＭＯＳＦＥＴ５０を介して右から左方向に充電電流Ｉ１が流れる。このとき、電池セル９２から負荷へ放電電流Ｉ２が供給されている。つまり、電池セル９２は充電されなが放電も行っている。
同図（ｂ）において、電池セル９２が過充電したとき、ゲート端子Ｇにオフ信号を与え、左右のｎチャネルＭＯＳＦＥＴをオフ状態にする。左右のｎチャネルＭＯＳＦＥＴがオフ状態になると、負荷と電池セル９２は回路的に切り離され、電池セル９２へ充電電流Ｉ１が流れなくなり、過充電は停止する。またそれと同時に電池セル９２から負荷へ放電電流Ｉ２が供給されなくなる。この過充電期間に図８のバッテリーチャージャーのプラグが抜かれた場合は、負荷へ電流が全く供給されなくなり、負荷は動作不能に陥る。 FIGS. 18A and 18B are diagrams in which the bidirectional LMOSFET and the drive / protection circuit unit of FIG. 8 are extracted and shown. FIGS. 18A to 18C show the time course when the battery cell is overcharged. FIG.
8A, when charging is performed in a state where a portable device, which is a load (not shown), is connected to the battery cell 92 in FIG. 8, an ON signal is supplied to the gate terminal G to turn on the left and right n-channel MOSFETs. As a result, the charging current I1 flows from the right to the left through the bidirectional LMOSFET 50 in the battery cell 92. At this time, the discharge current I2 is being supplied from the battery cell 92 to the load. That is, the battery cell 92 is discharging while not being charged.
In FIG. 9B, when the battery cell 92 is overcharged, an off signal is supplied to the gate terminal G to turn off the left and right n-channel MOSFETs. When the left and right n-channel MOSFETs are turned off, the load and the battery cell 92 are separated from each other in circuit, the charging current I1 does not flow to the battery cell 92, and the overcharge stops. At the same time, the discharge current I2 is not supplied from the battery cell 92 to the load. If the battery charger of FIG. 8 is unplugged during this overcharge period, no current is supplied to the load, and the load becomes inoperable.

これを避けるために、同図（ｃ）で示すように、ゲート端子Ｇに再度オン信号を与え双方向ＬＭＯＳＦＥＴ５０をオン状態にして、電池セル９２から負荷へ放電電流Ｉ２を供給する。しかし、電池セル９２の電圧が正常電圧になったことを検出してオン信号を駆動・保護回路５１から出力するために、時間遅れが生じて、その間は電池セル９２から負荷へ電流が供給されない状態、つまり、瞬断が生じる。
これを解決する方法として、左右のｎチャネルＭＯＳＦＥＴにそれぞれゲート電極を設けた双方向ＬＭＯＳＦＥＴを用いる方法がある。
図１９は、２つのゲート電極を有する双方向ＬＭＯＳＦＥＴの等価回路図である。これは前記の図６に相当する図である。
図６と異なる点は、ゲート電極が２つあるため、図６のゲート端子Ｇが第１ゲート端子Ｇ１と第２ゲート端子Ｇ２の２つの端子になっており、それぞれのｎチャネルＭＯＳＦＥＴ３３１、３３２が個別に動作させることができるようにした点と、ｎチャネルＭＯＳＦＥＴの寄生ダイオード３３３、３３４を動作に利用している点である。 To avoid this, an ON signal is again supplied to the gate terminal G to turn on the bidirectional LMOSFET 50 to supply the discharge current I2 from the battery cell 92 to the load, as shown in FIG. However, since the drive / protection circuit 51 outputs an ON signal by detecting that the voltage of the battery cell 92 has become a normal voltage, a time delay occurs, and during that time, no current is supplied from the battery cell 92 to the load. A state, that is, a momentary interruption occurs.
As a method of solving this, there is a method of using a bidirectional LMOSFET in which a gate electrode is provided for each of the left and right n-channel MOSFETs.
FIG. 19 is an equivalent circuit diagram of a bidirectional LMOSFET having two gate electrodes. This is a diagram corresponding to FIG.
The difference from FIG. 6 is that since there are two gate electrodes, the gate terminal G in FIG. 6 is a first terminal G1 and a second gate terminal G2, and the respective n-channel MOSFETs 331 and 332 are The point is that they can be operated individually, and the point is that the parasitic diodes 333 and 334 of the n-channel MOSFET are used for the operation.

この２つのゲート電極を有する双方向ＬＭＯＳＦＥＴ３００を用いた動作モードをつぎに説明する。
図２０は、図１８に相当する図であり、同図（ａ）〜同図（ｃ）は電池セルが過充電されるときの時間的な経過を示した図である。
同図（ａ）において、第１、第２ゲート端子Ｇ１、Ｇ２に駆動・保護回路５１からオン信号を与え、左右のｎチャネルＭＯＳＦＥＴ３３１、３３２がオン状態となり、電池セル９２へ充電電流Ｉ１が流れる。このとき、電池セル９２から負荷へ放電電流Ｉ２が供給されている。つまり、電池セル９２は充電されなが放電も行っている。
同図（ｂ）において、電池セル９２が過充電したとき、第１ゲート端子Ｇ１にオフ信号を与え、充電電流Ｉ１を停止させる。このとき、第２ゲート端子Ｇ２にはオン信号を与えたままにしておく。そうすると、充電電流Ｉ１が停止しても、放電電流Ｉ２が寄生ダイオード３３３とｎチャネルＭＯＳＦＥＴ３３２を通って負荷へ流れるため、前記の瞬断は起こらない。 An operation mode using the bidirectional LMOSFET 300 having the two gate electrodes will be described below.
FIG. 20 is a diagram corresponding to FIG. 18, and FIGS. 20A to 20C are diagrams illustrating a lapse of time when the battery cells are overcharged.
In FIG. 7A, an ON signal is given to the first and second gate terminals G1 and G2 from the drive / protection circuit 51, the left and right n-channel MOSFETs 331 and 332 are turned on, and the charging current I1 flows to the battery cell 92. . At this time, the discharge current I2 is being supplied from the battery cell 92 to the load. That is, the battery cell 92 is discharging while not being charged.
In FIG. 6B, when the battery cell 92 is overcharged, an off signal is given to the first gate terminal G1 to stop the charging current I1. At this time, the ON signal is kept applied to the second gate terminal G2. Then, even if the charging current I1 stops, the above-mentioned momentary interruption does not occur because the discharging current I2 flows to the load through the parasitic diode 333 and the n-channel MOSFET 332.

同図（ｃ）において、電池セル９２が正常電圧に戻った時点で、第１ゲート端子Ｇ１にオン信号が再び与えられて、左のｎチャネルＭＯＳＦＥＴ３３１をオン状態とする。この状態で左右のｎチャネルＭＯＳＦＥＴ３３１、３３２を介して、放電電流Ｉ２が負荷へ供給され、正常動作に戻る。
このように、２つのゲート電極を有する双方向ＬＭＯＳＦＥＴ３００を用いることで、負荷への電流が途切れることなく供給されるようになる。
つぎに、２つのゲート電極を有する半導体装置の構成について説明する。 In FIG. 9C, when the battery cell 92 returns to the normal voltage, an ON signal is again supplied to the first gate terminal G1, and the left n-channel MOSFET 331 is turned ON. In this state, the discharge current I2 is supplied to the load via the left and right n-channel MOSFETs 331 and 332, and the operation returns to the normal operation.
As described above, by using the bidirectional LMOSFET 300 having two gate electrodes, the current can be supplied to the load without interruption.
Next, a configuration of a semiconductor device having two gate electrodes is described.

図２１から図２５は、この発明の第１２実施例の半導体装置であって、ゲート配線まで含めた要部構成図であり、図２１は平面図、図２２は図２１のＡ−Ａ線で切断した断面図、図２３は図２１のＢ−Ｂ線で切断した断面図、図２４は図２１のＣ−Ｃ線で切断した断面図、図２５は図２１のＤ−Ｄ線で切断した断面図である。図２１は、表面から見た平面図であり、影に隠れた部分は点線で示し、層間絶縁膜３０８ａは図示していない。トレンチ内には柱状のトレンチ残し部分である島３４１、３４２が複数個あり、この図ではＭＯＳＦＥＴとして動作する島３４１（デバイスセル）が６個（図の３０９と３１０が形成されている島）と、ゲート配線を形成する島３４２が２個ある。島３４１にはｐオフセット領域３０５とｎソース領域３０９、３１０およびソース電極３１１、３１２が形成される。 図１４から図１７との違いは、ゲート電極が層間絶縁膜３０８でそれぞれ囲まれた第１ゲート電極３０７ａと第２ゲート電極３０７ｂが独立してあり、これらのゲート電極３０７ａ、３０７ｂは、トレンチ外周３０３ａ側壁のポリシリコン３０７とは切り離されている点と、それぞれのゲート電極３０７ａ、３０７ｂがポリシリコン配線３１８を介して金属の第１ゲート配線３１９と第２ゲート配線３２０に接続している点である。   FIGS. 21 to 25 show a semiconductor device according to a twelfth embodiment of the present invention. FIG. 21 is a plan view of a main part including a gate wiring, FIG. 21 is a plan view, and FIG. 23 is a sectional view taken along line BB of FIG. 21, FIG. 24 is a sectional view taken along line CC of FIG. 21, and FIG. 25 is a sectional view taken along line DD of FIG. It is sectional drawing. FIG. 21 is a plan view as viewed from the surface, where a portion hidden by a shadow is indicated by a dotted line, and the interlayer insulating film 308a is not illustrated. In the trench, there are a plurality of islands 341 and 342, which are the remaining portions of the columnar trenches. And two islands 342 forming gate wiring. On the island 341, a p offset region 305, n source regions 309 and 310, and source electrodes 311 and 312 are formed. The difference from FIGS. 14 to 17 is that the first gate electrode 307a and the second gate electrode 307b whose gate electrodes are respectively surrounded by the interlayer insulating film 308 are independent, and these gate electrodes 307a and 307b The point that the gate electrode 307a and the gate electrode 307b are connected to the metal first gate wiring 319 and the second gate wiring 320 through the polysilicon wiring 318 is separated from the polysilicon 307 on the side wall 303a. is there.

このように、トレンチ外周３０３ａに形成されたポリシリコン３０７と、第１ゲート電極３０７ａおよび第２ゲート電極３０７ｂは層間絶縁膜３０８で分離されているため、第１ｎソース領域３０９を形成した島３４１と第２ｎソース領域３１０を形成した島３４１の間隔Ｗ１は、ゲート電極を形成するためのポリシリコンで埋まらない広さとする。一方、第１、第２ｎソース領域３０９、３１０を形成する島３４１同士の間隔Ｗｇ１は、ゲート電極を形成するポリシリコンで完全に埋まる広さにする。ゲート電極３０７ａ、３０７ｂを金属のゲート配線３１９、３２０と接続するためのポリシリコン配線３１８を形成する島３４２とｎソース領域３０９、３１０を形成する島３４１の間隔Ｗｇ２もポリシリコンで埋まるようにするためにＷｇ１と同じ間隔にする。
具体的な例で説明すると、例えば、ゲート電極を形成するポリシリコンの厚さを０．３μｍとした場合はＷ１は１μｍ程度とし、Ｗｇ１、Ｗｇ２は０．５μｍ程度とする。また、表面を平坦化するためにはＷ１はソース領域を形成する島３４１の幅以下とするのが好ましい。 As described above, since the polysilicon 307 formed on the trench outer periphery 303a and the first gate electrode 307a and the second gate electrode 307b are separated by the interlayer insulating film 308, the island 341 on which the first n source region 309 is formed is formed. The distance W1 between the islands 341 where the second n source regions 310 are formed is set to a width that is not filled with polysilicon for forming a gate electrode. On the other hand, the distance Wg1 between the islands 341 forming the first and second n-type source regions 309 and 310 is set to a width that is completely filled with polysilicon forming the gate electrode. The space Wg2 between the island 342 forming the polysilicon wiring 318 for connecting the gate electrodes 307a and 307b to the metal gate wirings 319 and 320 and the island 341 forming the n source regions 309 and 310 are also filled with polysilicon. Therefore, the interval is set to be the same as Wg1.
For example, when the thickness of the polysilicon forming the gate electrode is 0.3 μm, W1 is about 1 μm, and Wg1 and Wg2 are about 0.5 μm. Further, in order to flatten the surface, W1 is preferably set to be equal to or less than the width of the island 341 forming the source region.

このようにして、独立した第１ゲート電極３０７ａと第２ゲート電極３０７ｂを形成することで、図２０で説明した効果が得られる。   By forming the independent first and second gate electrodes 307a and 307b in this manner, the effect described with reference to FIG. 20 can be obtained.

図２６〜図２９は、この発明の第１３実施例の半導体装置の製造方法を示す図であり、工程順に示した要部工程断面図である。各図において（ａ）は図２２に相当する箇所の断面図、（ｂ）は図２３に相当する箇所の断面図、（ｃ）は図２４に相当する箇所の断面図である。
図２６において、ｐ半導体基板３０１の表面層に、例えば、表面濃度５×１０16ｃｍ-2、深さ４μｍ程度ｎウェル領域３０２を形成し、表面からｎウェル領域３０２に達するトレンチ３０３をメッシュ状に深さ２μｍ程度に形成し、柱状にトレンチ残し部分、所謂島３４１、３４２を形成する。この島３４１、３４２は、後工程で第１、第２ｐオフセット領域、第１、第２ｎソース領域を形成する島３４１と、第１、第２ゲート電極、第１、第２ゲート配線と接続するポリシリコン配線３１８を形成する島３４２となる。 26 to 29 are views showing a method for manufacturing a semiconductor device according to the thirteenth embodiment of the present invention, and are cross-sectional views of main steps in the order of steps. In each figure, (a) is a cross-sectional view of a portion corresponding to FIG. 22, (b) is a cross-sectional view of a portion corresponding to FIG. 23, and (c) is a cross-sectional view of a portion corresponding to FIG.
In FIG. 26, for example, an n-well region 302 having a surface concentration of 5 × 10 16 cm −2 and a depth of about 4 μm is formed in a surface layer of a p-type semiconductor substrate 301, and a trench 303 reaching the n-well region 302 from the surface is formed in a mesh shape. Then, a trench-remaining portion, that is, islands 341 and 342 are formed in a columnar shape. The islands 341 and 342 are connected to the island 341 that forms the first and second p-offset regions and the first and second n-source regions in a later step, and the first and second gate electrodes and the first and second gate wirings. The island 342 forms the polysilicon wiring 318.

島３４１同士の間隔Ｗｇ１と、島３４１と島３４２の間隔Ｗｇ２は等しく、０．５μｍ程度とすることで、ポリシリコンのエッチバック（ポリシリコンのパターニング）でもポリシリコンが切り離されず、間隔はポリシリコンで埋まる状態にできる。また、これらの島３４１、３４２とトレンチ外周３０３ａの側壁の間隔Ｗ１および第１ソース領域３０９および第２ソース領域３１０を形成する島３４１同士の間隔Ｗ１を１μｍ以上とすることで、ポリシリコンのエッチバックで、ポリシリコンを完全に切り離すことができる。
図２７において、ゲート絶縁膜３０６を形成し、３０Ｖから５０Ｖ程度の耐圧を持たせるために、トレンチ底面のｎウェル領域３０２に１×１０17ｃｍ-3以上の高濃度でｎドレイン領域３０４を形成し、このｎドレイン領域３０４と離してｐオフセット領域３０５を形成する（接続する場合もある）。その後、０．３μｍ程度の厚さで第１、第２ゲート電極３０７ａ、３０７ｂ、ポリシリコン配線３１８となるポリシリコンを全面に形成し、島３４１同士の間、島３４１と島３４２の間をポリシリコンで完全に埋めた後、パターニングする。 The distance Wg1 between the islands 341 and the distance Wg2 between the islands 341 and 342 are equal and about 0.5 μm, so that the polysilicon is not separated even by polysilicon etch back (polysilicon patterning). Can be filled with. By setting the distance W1 between the islands 341 and 342 and the side wall of the trench outer periphery 303a and the distance W1 between the islands 341 forming the first source region 309 and the second source region 310 to 1 μm or more, the polysilicon etching is performed. At the back, the polysilicon can be completely separated.
In FIG. 27, a gate insulating film 306 is formed, and an n-drain region 304 is formed at a high concentration of 1 × 10 17 cm −3 or more in the n-well region 302 on the bottom of the trench in order to have a withstand voltage of about 30 V to 50 V. Then, a p-offset region 305 is formed apart from the n-drain region 304 (it may be connected). Thereafter, polysilicon, which will be the first and second gate electrodes 307a and 307b and the polysilicon wiring 318, is formed on the entire surface with a thickness of about 0.3 μm, and polysilicon is formed between the islands 341 and between the islands 341 and 342. After completely filling with silicon, patterning is performed.

図２８において、第１、第２ゲート電極３０７ａ、３０７ｂをマスクに１×１０20ｃｍ-3以上の高濃度で第１、第２ｎソース領域３０９、３１０を形成し、この第１、第２ソース領域３０９、３１０を貫通してｐオフセット領域３０５に達する高濃度のｐコンタクト領域３１６を形成し、表面に層間絶縁膜３０８ａを形成する。
図２９において、層間絶縁膜３０８ａにコンタクトホール３１７を形成し、このコンタクトホール３１７で第１、第２ｎソース領域３０９、３１０、ｐコンタクト領域３１５、３１６と接続する金属の第１、第２ソース電極３１１、３１２と、この第１、第２ソース電極３１１、３１２と同時に形成された第１、第２ソース配線３１３、３１４および第１、第２ゲート電極３０７ａ、３０７ｂと同時に形成されたポリシリコン配線３１８と接続する金属の第１、第２ゲート配線３１９、３２０を形成する。 In FIG. 28, the first and second n source regions 309 and 310 are formed at a high concentration of 1 × 10 20 cm −3 or more using the first and second gate electrodes 307a and 307b as a mask. A high-concentration p contact region 316 that reaches the p offset region 305 through the regions 309 and 310 is formed, and an interlayer insulating film 308a is formed on the surface.
In FIG. 29, a contact hole 317 is formed in an interlayer insulating film 308a, and first and second metal source electrodes connected to the first and second n source regions 309 and 310 and the p contact regions 315 and 316 in the contact hole 317. 311 and 312, and first and second source wirings 313 and 314 formed simultaneously with the first and second source electrodes 311 and 312, and polysilicon wiring formed simultaneously with the first and second gate electrodes 307a and 307b. Metal first and second gate wirings 319 and 320 connected to 318 are formed.

ゲート電極などのポリシリコンの厚さを０．３μｍ程度としたとき、Ｗ１は１μｍ以上とし、表面を平坦化するために島の幅以下とするとよい。また、Ｗｇ１＝Ｗｇ２は０．５μｍ以下とするとよい。   When the thickness of polysilicon such as a gate electrode is about 0.3 μm, W1 may be 1 μm or more, and may be smaller than the width of an island to flatten the surface. Further, Wg1 = Wg2 may be set to 0.5 μm or less.

この発明の第１実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＡ部拡大図、（ｃ）は（ｂ）のＸ−Ｘ線で切断した要部断面図1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view of a main part, FIG. 1B is an enlarged view of a portion A of FIG. 1A, and FIG. Sectional view 図１と異なる構成の図であり、（ａ）は、ｎウェル領域が図１（ｃ）におけるｎドレイン領域４を兼ねている図、（ｂ）は、半導体基板１が図１（ｃ）におけるｎドレイン領域を兼ねている図、（ｃ）は、（ｂ）においてｎドレイン領域４をさらに形成した図FIGS. 2A and 2B are diagrams of a configuration different from FIG. 1A, in which FIG. 1A is a diagram in which an n-well region also serves as an n-drain region 4 in FIG. 1C, and FIG. The figure also serving as an n-drain region, and (c) is a view in which an n-drain region 4 is further formed in (b). 図１の双方向ＬＭＯＳＦＥＴの等価回路図FIG. 1 is an equivalent circuit diagram of the bidirectional LMOSFET. この発明の第２実施例の半導体装置の構成図であり、（ａ）は図１（ｂ）に相当する要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図2A and 2B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, wherein FIG. 1A is a plan view of a main part corresponding to FIG. 1B, and FIG. 1B is a main part cut along line XX of FIG. Sectional view この発明の第３実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＢ部拡大図、（ｃ）は（ｂ）のＸ−Ｘ線で切断した要部断面図It is a block diagram of the semiconductor device of 3rd Example of this invention, (a) is a principal part top view, (b) is the B section enlarged view of (a), (c) is XX line of (b). Sectional view 図５の双方向ＬＭＯＳＦＥＴの等価回路図Equivalent circuit diagram of the bidirectional LMOSFET of FIG. この発明の第４実施例の半導体装置の構成図であり、（ａ）は図５（ｂ）に相当する要部平面図、（ｂ）は（ａ）のＸ１−Ｘ１で切断した要部断面図、（ｃ）は（ａ）のＸ２−Ｘ２で切断した要部断面図It is a block diagram of the semiconductor device of 4th Example of this invention, (a) is a principal part plane view corresponding to FIG.5 (b), (b) is a principal part cross section cut | disconnected by X1-X1 of (a). FIG. 3C is a cross-sectional view of a main part taken along line X2-X2 of FIG. この発明の第５実施例の半導体装置の要部配置図Main part layout of a semiconductor device according to a fifth embodiment of the present invention. この発明の第６実施例の半導体装置の製造方法であり、（ａ）から（ｃ）は工程順に示した要部製造工程断面図14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. この発明の第７実施例の半導体装置の製造方法であり、（ａ）から（ｃ）は工程順に示した要部製造工程断面図14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. この発明の第８実施例の半導体装置の製造方法であり、（ａ）から（ｃ）は工程順に示した要部製造工程断面図14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. この発明の第９実施例の半導体装置の製造方法であり、（ａ）、（ｂ）は図１１（ａ）に相当する要部製造工程断面図、（ｃ）、（ｄ）は図１１（ｃ）に相当する要部製造工程断面図This is a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention, in which (a) and (b) are cross-sectional views of a main part manufacturing step corresponding to FIG. 11 (a), and FIGS. Sectional manufacturing process sectional view corresponding to c) この発明の第１０実施例の半導体装置の製造方法であり、（ａ）から（ｃ）は工程順に示した要部製造工程断面図14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. この発明の第１１実施例の半導体装置の要部平面図Main part plan view of a semiconductor device according to an eleventh embodiment of the present invention. 図１４のＸ−Ｘ線で切断した断面図FIG. 14 is a cross-sectional view taken along line XX of FIG. 14. 図１４のＹ−Ｙ線で切断した断面図FIG. 14 is a sectional view taken along line YY in FIG. 14. 図１４のＺ−Ｚ線で切断した断面図FIG. 14 is a sectional view taken along line ZZ in FIG. 14. 図８の双方向ＬＭＯＳＦＥＴと駆動・保護回路部を抜き書きした図であり、（ａ）〜（ｃ）は電池セルが過充電されるときの時間的な経過を示した図FIG. 9 is a diagram in which the bidirectional LMOSFET and the drive / protection circuit unit of FIG. 8 are drawn and omitted, and (a) to (c) are diagrams illustrating a time course when the battery cell is overcharged. ２つのゲート電極を有する双方向ＬＭＯＳＦＥＴの等価回路図Equivalent circuit diagram of a bidirectional LMOSFET having two gate electrodes ２つのゲート電極を有する双方向ＬＭＯＳＦＥＴを用いた場合の図１８に相当する図であり、（ａ）〜（ｃ）は電池セルが過充電されるときの時間的な経過を示した図FIG. 19 is a diagram corresponding to FIG. 18 in the case where a bidirectional LMOSFET having two gate electrodes is used, and (a) to (c) are diagrams illustrating a time course when a battery cell is overcharged. この発明の第１２実施例の半導体装置の要部平面図Main part plan view of a semiconductor device according to a twelfth embodiment of the present invention. 図２１のＡ−Ａ線で切断した断面図Sectional drawing cut | disconnected by the AA line of FIG. 図２１のＢ−Ｂ線で切断した断面図Sectional drawing cut | disconnected by the BB line of FIG. 図２１のＣ−Ｃ線で切断した断面図Sectional drawing cut | disconnected by CC line of FIG. 図２１のＤ−Ｄ線で切断した断面図Sectional drawing cut | disconnected by the DD line of FIG. この発明の第１３実施例の半導体装置の製造方法の要部工程断面図であり、（ａ）は図２２に相当する箇所の断面図、（ｂ）は図２３に相当する箇所の断面図、（ｃ）は図２４に相当する箇所の断面図FIGS. 23A and 23B are cross-sectional views of main parts of a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention, in which FIG. 23A is a cross-sectional view of a part corresponding to FIG. (C) is a sectional view of a portion corresponding to FIG. 図２６に続く、この発明の第１３実施例の半導体装置の製造方法の要部工程断面図であり、（ａ）は図２２に相当する箇所の断面図、（ｂ）は図２３に相当する箇所の断面図、（ｃ）は図２４に相当する箇所の断面図FIG. 27 is a cross-sectional view of a main part step of the method for manufacturing a semiconductor device according to the thirteenth embodiment of the present invention, following FIG. 26, where (a) is a cross-sectional view of a portion corresponding to FIG. FIG. 24C is a cross-sectional view of a portion, and FIG. 図２７に続く、この発明の第１３実施例の半導体装置の製造方法の要部工程断面図であり、（ａ）は図２２に相当する箇所の断面図、（ｂ）は図２３に相当する箇所の断面図、（ｃ）は図２４に相当する箇所の断面図FIG. 28 is a cross-sectional view of a main part of a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention, following FIG. 27, wherein (a) is a cross-sectional view of a portion corresponding to FIG. FIG. 24C is a cross-sectional view of a portion, and FIG. 図２８に続く、この発明の第１３実施例の半導体装置の製造方法の要部工程断面図であり、（ａ）は図２２に相当する箇所の断面図、（ｂ）は図２３に相当する箇所の断面図、（ｃ）は図２４に相当する箇所の断面図FIG. 29 is a cross-sectional view of a main part step of a manufacturing method of a semiconductor device according to a thirteenth embodiment of the present invention, following FIG. 28, where (a) is a cross-sectional view of a portion corresponding to FIG. FIG. 24C is a cross-sectional view of a portion, and FIG. 従来の双方向ＬＩＧＢＴの要部断面図Sectional view of main part of conventional bidirectional LIGBT 図２９の双方向ＬＩＧＢＴの出力特性を示す図The figure which shows the output characteristic of the bidirectional LIGBT of FIG. 従来の別の双方向ＭＯＳＦＥＴの要部断面図Sectional view of main part of another conventional bidirectional MOSFET 図３２の双方向ＬＩＧＢＴの出力特性を示す図The figure which shows the output characteristic of the bidirectional LIGBT of FIG.

符号の説明Explanation of reference numerals

１、７１ ２０１、３０１ ｐ半導体基板
２、７２ ２０２、３０２ ｎウェル領域
３、３３、７３、２０３、３０３ トレンチ
３ａ、３３ａ、７３ａ 底面
３ｂ、３３ｂ、７３ｂ 側面
４、７４、２０４、３０４ ｎドレイン領域
５、３５、７５、２０５、３０５ ｐオフセット領域
６、３６、７９、２０６、３０６ ゲート絶縁膜
７、３７、８０、２０７ ゲート電極
８、３８、８７、２０８、２０８ａ、３０８、３０８ａ 層間絶縁膜
９、８１、２０９、３０９ 第１ｎソース領域
１０、８２、２１０、３１０ 第２ｎソース領域
１１、８５、２１１、３１１ 第１ソース電極
１２、８６、２１２、３１２ 第２ソース電極
１３、２１３、３１３ 第１ソース配線
１４、２１４、３１４ 第２ソース配線
１５、１６、２１５、２１６、３１５、３１６ ｐコンタクト領域
３４ ｎソース領域
３９ 第１ｎドレイン領域
４０ 第２ｎドレイン領域
４１ 第１ドレイン電極
４２ 第２ドレイン電極
４３ 第１ドレイン配線
４４ 第２ドレイン配線
４５ ピックアップ電極
４６ ｐベースピックアップ領域
５０、６０ 双方向ＬＭＯＳＦＥＴ
５１ 駆動・保護回路部
５２ 残量回路部
５３ チャージポンプ回路
６１ 分割半導体領域
７０、９０、９１ 半導体基板
８３、８４ ソース／ドレイン領域
８８、８９ ソース／ドレイン電極
９２ バッテリー装置
２０３ａ、３０３ａ トレンチ外周
２０３ｂ 突き出したトレンチ
３０７ ポリシリコン
２１７、３１７ コンタクトホール
２１８、３１８ ポリシリコン配線
２１９ ゲート配線
３００ 双方向ＬＭＯＳＦＥＴ
３０７ａ 第１ゲート電極
３０７ｂ 第２ゲート電極
３１９ 第１ゲート配線
３２０ 第２ゲート配線
３３１、３３２ ｎチャネルＭＯＳＦＥＴ
３３３、３３４ 寄生ダイオード
３４１、３４２ 島
Ｓ１ 第１ソース端子
Ｓ２ 第２ソース端子
Ｇ ゲート端子
Ｇ１ 第１ゲート端子
Ｇ２ 第２ゲート端子
Ｄ１ 第１ドレイン端子
Ｄ２ 第２ドレイン端子 1, 71 201, 301 p semiconductor substrate
2, 72 202, 302 n-well region
3, 33, 73, 203, 303 trench
3a, 33a, 73a Bottom
3b, 33b, 73b Side view
4, 74, 204, 304 n drain region
5, 35, 75, 205, 305 p offset region
6, 36, 79, 206, 306 Gate insulating film
7, 37, 80, 207 Gate electrode
8, 38, 87, 208, 208a, 308, 308a Interlayer insulating film
9, 81, 209, 309 1st n source region 10, 82, 210, 310 2nd n source region 11, 85, 211, 311 1st source electrode 12, 86, 212, 312 2nd source electrode 13, 213, 313 1 source wiring 14, 214, 314 second source wiring 15, 16, 215, 216, 315, 316 p contact region 34 n source region 39 first n drain region 40 second n drain region 41 first drain electrode 42 second drain electrode 43 First drain wiring 44 Second drain wiring 45 Pickup electrode 46 p base pickup area 50, 60 Bidirectional LMOSFET
REFERENCE SIGNS LIST 51 Drive / protection circuit unit 52 Remaining circuit unit 53 Charge pump circuit 61 Divided semiconductor region 70, 90, 91 Semiconductor substrate 83, 84 Source / drain region 88, 89 Source / drain electrode 92 Battery device 203a, 303a Trench outer periphery 203b Projection Trench 307 polysilicon 217, 317 contact hole 218, 318 polysilicon wiring 219 gate wiring 300 bidirectional LMOSFET
307a first gate electrode 307b second gate electrode 319 first gate wiring 320 second gate wiring 331, 332 n-channel MOSFET
333, 334 Parasitic diode 341, 342 Island
S1 First source terminal
S2 Second source terminal
G Gate terminal
G1 First gate terminal
G2 Second gate terminal
D1 first drain terminal
D2 Second drain terminal

Claims (21)

第１導電形半導体領域内に形成されたトレンチにより、前記半導体領域の表面層を分割して形成された第１、第２の分割半導体領域と、
前記トレンチの底面または底面および側壁に形成された第１導電形の第１領域と、
前記第１、第２の分割半導体領域にそれぞれ形成された、前記トレンチの側壁および前記第１領域に接する第２導電形の第２、第３領域と、
前記第１の分割半導体領域に、前記トレンチの側壁と接し、前記第２領域に接して形成された第１導電形の第４領域と、
前記第２の分割半導体領域に、前記トレンチの側壁と接し、前記第３領域に接して形成された第１導電形の第５領域と、
前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第４領域に渡って第１絶縁膜を介して形成された第１制御電極と、
前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第５領域に渡って第２絶縁膜を介して形成された第２制御電極と、
前記第４領域上に形成された第１主電極と、
前記第５領域上に形成された第２主電極と、
を有する双方向素子。 First and second divided semiconductor regions formed by dividing a surface layer of the semiconductor region by a trench formed in the first conductivity type semiconductor region;
A first region of a first conductivity type formed on a bottom surface or a bottom surface and a side wall of the trench;
Second and third regions of the second conductivity type, which are formed in the first and second divided semiconductor regions, respectively, and are in contact with the side wall of the trench and the first region;
A fourth region of a first conductivity type formed in contact with the sidewall of the trench and in contact with the second region, in the first divided semiconductor region;
A fifth region of a first conductivity type formed in contact with the side wall of the trench and in contact with the third region, in the second divided semiconductor region;
A first control electrode formed on the trench sidewall of the first divided semiconductor region from the first region to the fourth region via a first insulating film;
A second control electrode formed on the trench sidewall of the first divided semiconductor region from the first region to the fifth region via a second insulating film;
A first main electrode formed on the fourth region,
A second main electrode formed on the fifth region,
A bidirectional element having: 前記第１領域と前記第２領域および前記第１領域と前記第３領域との間に前記第１領域より不純物濃度の低い第６領域を備えたことを特徴とする請求項１に記載の双方向素子。 2. The device according to claim 1, further comprising a sixth region having a lower impurity concentration than the first region, between the first region and the second region, and between the first region and the third region. 3. Directional element. 前記第１制御電極と前記第２制御電極が電気的に接続されたことを特徴とする請求項１または２のいずれかに記載の双方向素子。 The bidirectional element according to claim 1, wherein the first control electrode and the second control electrode are electrically connected. 前記第１制御電極と前記第２制御電極が電気的に絶縁されたことを特徴とする請求項１または２のいずれかに記載の双方向素子。 3. The bidirectional device according to claim 1, wherein the first control electrode and the second control electrode are electrically insulated. 前記半導体領域が第２導電形の半導体基板の表面層に形成された領域であることを特徴とする請求項１に記載の双方向素子。 The bidirectional element according to claim 1, wherein the semiconductor region is a region formed on a surface layer of a semiconductor substrate of the second conductivity type. 前記第１、第２の分割半導体領域を、それぞれ複数個備えたことを特徴とする請求項１〜５のいずれか一つに記載の双方向素子。 The bidirectional element according to claim 1, wherein a plurality of the first and second divided semiconductor regions are provided. 前記第１の分割半導体領域と、前記第２の分割半導体領域とが互いに隣接して形成されたことを特徴とする請求項６に記載の双方向素子。 The bidirectional device according to claim 6, wherein the first divided semiconductor region and the second divided semiconductor region are formed adjacent to each other. 前記第１、第２の分割半導体領域を、それぞれ複数個備え、隣接する分割半導体領域の間の前記トレンチ幅が、同じ分割領域間よりも異なる分割領域間の方が広いことを特徴とする請求項１〜５のいずれかに記載の双方向素子。 A plurality of the first and second divided semiconductor regions are provided, and the trench width between adjacent divided semiconductor regions is wider between different divided regions than between the same divided regions. Item 6. The bidirectional element according to any one of Items 1 to 5. 前記第１、２の主電極は、それぞれ前記第２、第３領域と電気的に接続されることを特徴とする請求項１〜８のいずれかに記載の双方向素子。 The bidirectional element according to claim 1, wherein the first and second main electrodes are electrically connected to the second and third regions, respectively. 前記制御電極の内側に層間絶縁膜を介して前記第１領域に達する導電体を有することを特徴とする請求項１〜９のいずれかに記載の双方向素子。 The bidirectional element according to claim 1, further comprising a conductor that reaches the first region via an interlayer insulating film inside the control electrode. 前記トレンチの底面に形成され、前記第２、第３領域と接し、前記導電体と接する第２導電形の第７領域を有することを特徴とする請求項１０記載の双方向素子。 The bidirectional device according to claim 10, further comprising a seventh region of a second conductivity type formed on a bottom surface of the trench, in contact with the second and third regions, and in contact with the conductor. 前記双方向素子と、該双方向素子を制御する制御用回路とを同一の半導体基板に形成した請求項１〜１１のいずれかに記載の双方向素子を含む半導体装置。 The semiconductor device including the bidirectional element according to claim 1, wherein the bidirectional element and a control circuit for controlling the bidirectional element are formed on the same semiconductor substrate. 第１導電形の半導体領域の表面層に第２導電型の拡散領域を形成する工程と、
前記拡散領域表面からトレンチを形成し、該トレンチにより囲まれた第１、第２の分割半導体領域を形成する工程と、
前記トレンチ底面から拡散により前記半導体領域と接続する第１導電形の第１領域を形成する工程と、
前記第１の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第２領域の表面層より前記トレンチの側壁と接するように第１導電形の第４領域を形成する工程と、
前記第２の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第３領域の表面層より前記トレンチの側壁と接するように第１導電型の第５領域を形成する工程と、
前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第４領域に渡って絶縁膜を介して第１制御電極を形成する工程と、
前記第２の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第５領域に渡って絶縁膜を介して第２制御電極を形成する工程と、
前記第４領域上に第１主電極を形成する工程と、
前記第５領域上に第２主電極を形成する工程と、
を含むことを特徴とする双方向素子の製造方法。 Forming a diffusion region of the second conductivity type in a surface layer of the semiconductor region of the first conductivity type;
Forming a trench from the surface of the diffusion region and forming first and second divided semiconductor regions surrounded by the trench;
Forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the trench bottom surface;
A fourth region of a first conductivity type is formed in the first divided semiconductor region so as to be in contact with a side wall of the trench from a surface layer of the semiconductor region, the first region, and a second region surrounded by the trench. The process of
A fifth region of the first conductivity type is formed in the second divided semiconductor region from a surface layer of the third region surrounded by the semiconductor region, the first region, and the trench so as to be in contact with a sidewall of the trench. The process of
Forming a first control electrode on the trench side wall of the first divided semiconductor region via an insulating film from the first region to the fourth region;
Forming a second control electrode on the trench sidewall of the second divided semiconductor region via an insulating film from the first region to the fifth region;
Forming a first main electrode on the fourth region;
Forming a second main electrode on the fifth region;
A method for manufacturing a bidirectional device, comprising: 前記トレンチを前記半導体領域に達するように形成し、前記第１領域は前記半導体領域内部に形成することを特徴とする請求項１３に記載の双方向素子の製造方法。 14. The method according to claim 13, wherein the trench is formed to reach the semiconductor region, and the first region is formed inside the semiconductor region. 前記トレンチを前記半導体領域に達するように形成し、前記第１領域は前記第２、第３領域と接続するように形成することを特徴とする請求項１４に記載の双方向素子の製造方法。 The method according to claim 14, wherein the trench is formed to reach the semiconductor region, and the first region is formed to be connected to the second and third regions. 第１導電形の半導体領域表面からトレンチを形成し、該トレンチにより囲まれた第１、第２の分割半導体領域を形成する工程と、
前記半導体領域の表面層に第２導電型の拡散領域を形成する工程と、
前記トレンチ底面から拡散により前記半導体領域と接続する第１導電形の第１領域を形成する工程と、
前記第１の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第２領域の表面層より前記トレンチの側壁と接するように第１導電形の第４領域を形成する工程と、
前記第２の分割半導体領域内で、前記半導体領域、前記第１領域および前記トレンチに囲まれた第３領域の表面層より前記トレンチの側壁と接するように第１導電型の第５領域を形成する工程と、
前記第１の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第４領域に渡って絶縁膜を介して第１制御電極を形成する工程と、
前記第２の分割半導体領域の前記トレンチ側壁に、前記第１領域から前記第５領域に渡って絶縁膜を介して第２制御電極を形成する工程と、
前記第４領域上に第１主電極を形成する工程と、
前記第５領域上に第２主電極を形成する工程と、
を含むことを特徴とする双方向素子の製造方法。 Forming a trench from the surface of the semiconductor region of the first conductivity type and forming first and second divided semiconductor regions surrounded by the trench;
Forming a diffusion region of the second conductivity type in a surface layer of the semiconductor region;
Forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the trench bottom surface;
A fourth region of the first conductivity type is formed in the first divided semiconductor region so as to be in contact with a side wall of the trench from a surface layer of the semiconductor region, the first region, and a second region surrounded by the trench. The process of
A fifth region of the first conductivity type is formed in the second divided semiconductor region from a surface layer of the third region surrounded by the semiconductor region, the first region, and the trench so as to be in contact with a sidewall of the trench. The process of
Forming a first control electrode on the trench side wall of the first divided semiconductor region via an insulating film from the first region to the fourth region;
Forming a second control electrode on the trench sidewall of the second divided semiconductor region via an insulating film from the first region to the fifth region;
Forming a first main electrode on the fourth region;
Forming a second main electrode on the fifth region;
A method for manufacturing a bidirectional device, comprising: 前記第１制御電極と前記第２制御電極との間に層間絶縁膜を形成する工程を含むことを特徴とする請求項１３〜１６のいずれかに記載の双方向素子の製造方法。 17. The method according to claim 13, further comprising a step of forming an interlayer insulating film between the first control electrode and the second control electrode. 前記層間絶縁膜に前記第１領域に達する開口部を形成する工程と、
該開口部に導電体を充填する工程と、
を含むことを特徴とする請求項１７に記載の双方向素子の製造方法。 Forming an opening reaching the first region in the interlayer insulating film;
Filling the opening with a conductor;
The method for manufacturing a bidirectional element according to claim 17, comprising: 前記トレンチの底面に、前記１領域と隣接して、前記第２、第３領域と接するように第２導電形の第６領域を形成する工程を含むことを特徴とする請求項１８に記載の双方向素子の製造方法。 19. The method according to claim 18, further comprising: forming a sixth region of the second conductivity type on the bottom surface of the trench, adjacent to the first region and in contact with the second and third regions. A method for manufacturing a bidirectional element. 前記第１、第２の分割半導体領域をそれぞれ複数個形成することを特徴とする請求項１３〜１８のいずれかに記載の双方向素子の製造方法。 19. The method according to claim 13, wherein a plurality of the first and second divided semiconductor regions are formed. 前記第１の分割半導体領域と前記第２の分割半導体領域との間の前記トレンチを第１のトレンチ、前記第１の分割半導体領域同士の間および前記第２の分割半導体領域同士の間の前記トレンチを第２のトレンチ、とした場合前記第１のトレンチの幅を前記第２のトレンチの幅より広く形成することを特徴とする請求項２０に記載の双方向素子の製造方法。 The trench between the first divided semiconductor region and the second divided semiconductor region is formed as a first trench, between the first divided semiconductor regions, and between the second divided semiconductor regions. 21. The method according to claim 20, wherein when the trench is a second trench, the width of the first trench is formed wider than the width of the second trench.
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