JP2004241496A - Wiring substrate and electronic device employing the same - Google Patents

Wiring substrate and electronic device employing the same Download PDF

Info

Publication number
JP2004241496A
JP2004241496A JP2003027397A JP2003027397A JP2004241496A JP 2004241496 A JP2004241496 A JP 2004241496A JP 2003027397 A JP2003027397 A JP 2003027397A JP 2003027397 A JP2003027397 A JP 2003027397A JP 2004241496 A JP2004241496 A JP 2004241496A
Authority
JP
Japan
Prior art keywords
signal wiring
conductor
wiring
layer
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003027397A
Other languages
Japanese (ja)
Inventor
Takashi Inoue
貴志 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2003027397A priority Critical patent/JP2004241496A/en
Publication of JP2004241496A publication Critical patent/JP2004241496A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Waveguides (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of transferring a high-frequency signal excellently by controlling the characteristic impedance of a signal wiring conductor within the range of 50Ω±10% to reduce reflective noise, and an electronic device employing the board. <P>SOLUTION: The wiring board is constituted of at least a pair of signal wiring conductors 3 and a grounding or power supply conductor layer 4 which are extended on the main surface of an insulating substrate 1 so as to be neighbored to each other, and which are laminated so that the grounding or power supply conductor layers 4 are opposed to the upper and lower sides of the pair signal wiring conductors 3 through an insulating layer 2, consisting of epoxy resin and inorganic insulating filler while having a dielectric constant of 3.5-4.5, In such a wiring board, the thickness T of one side of the insulating layer 2 between the pair of signal wiring conductors 3 and the grounding or power supply conductor layer 4 is specified so as to be not less than 3 times the width W of the pair of signal wiring conductors and the other thickness T of the same is specified so as to be equal to the width W of the pair of signal wiring conductors while the space S between the wirings of the pair of signal wiring conductors is specified so as to be not more than the width W of the same conductors. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、半導体素子等の電子部品を実装するために用いられる配線基板およびこの配線基板に電子部品を実装して成る電子装置に関するもので、特に電気特性を考慮し配線効率を向上した配線基板に関する。
【0002】
【従来の技術】
一般に現在の電子装置は、高速化、大容量伝送化が顕著になってきている。それに伴い電子装置に搭載される配線基板およびパッケージは電気的ロスの少ない形態が要求されている。また、電子装置を構成する配線基板にも小型化・薄型化・多端子化が求められてきており、それを実現するために信号配線導体等の導体層の幅を細くするとともにその間隔を狭くし、さらに配線の多層化・配線間を接続する貫通導体の小径化により高密度配線化が図られている。
【0003】
このような高密度配線が可能な配線基板として、ビルドアップ法を採用して製作された配線基板が知られている。ビルドアップ法とは、例えば、ガラスクロスやアラミド不布織等の補強材に耐熱性や耐薬品性を有するエポキシ樹脂に代表される熱硬化性樹脂を含浸させて複合化した絶縁基板上に、間に導体層を挟んでエポキシ樹脂等の熱硬化性樹脂から成る接着材を塗布して絶縁層を形成するとともに絶縁層を加熱硬化させた後、配線導体層上部の絶縁層にレーザで径が50〜200μm程度の貫通孔を穿設し、しかる後、絶縁層表面を化学粗化し、さらに無電解銅めっき法および電解銅めっき法を用いて貫通孔側面および貫通孔底面の導体層上に導体膜を被着して貫通導体を形成するとともに絶縁層表面に貫通導体と接続する導体層を形成し、さらに、絶縁層や貫通導体・導体層の形成を複数回繰り返すことにより配線基板を製作する方法である。
【0004】
このような配線基板の導体層は、用途によって、信号配線導体および接地または電源導体層に機能化されている。このうち信号配線導体は、電子部品に出入力される電気信号を外部の電気回路基板に伝播させるための導電路としての機能を有し、所定の回路形状にパターン化した薄膜導体から構成されている。
【0005】
他方、接地または電源導体層は、配線基板に実装される半導体素子等の電子部品に接地または電源電位を供給する機能を有し、信号配線導体を流れる電流によって発生する電磁波をシールドし、他の配線層に生じるノイズを防止する機能を有し、絶縁層の略全面をめっきしたベタパターンの薄膜導体から成る。このような役割を担う接地または電源導体層および信号配線導体は、それぞれ配線基板の表面に設けた電子部品接続用の電子部品接続パッドに貫通導体を介して電気的に接続され、配線基板に実装される電子部品への電磁波のシールド・電力の供給あるいは信号の伝達を行うことができるような積層構造に配置されている。また、信号配線導体は上下に絶縁層を挟んで接地または電源導体層が対向するように積層されている。
【0006】
また信号配線は、電子部品が誤作動することがないように、信号遅延や反射・クロストーク・ノイズ等の伝達ロスを低減させることが重要な課題となっている。このような信号配線は、高周波信号を伝達させるために、一般的に差動(波長の位相が異なる)信号を使用するのでペア(対)信号配線導体として形成されている。
【0007】
そして、ペア信号配線導体は、その配線幅が20〜30μm程度、その配線間隔が40〜60μmの微細パターンであるので、この特性インピーダンスを配線基板に一般に要求される50Ω±10%の範囲に制御するために、絶縁層はその厚みが20〜50μmに、誘電率は3.5〜4.5に調整されている。
【0008】
【特許文献1】
特開2001−326505号公報
【0009】
【発明が解決しようとする課題】
しかしながら、この従来の配線基板は、近年の高密度配線への要求に伴いペア信号配線導体の配線間隔を狭くすると、ペア信号配線導体間の容量結合によるキャパシタンスが大きくなり過ぎるため、ペア信号配線導体の特性インピーダンを50Ω±10%の範囲に制御できない。このように特性インピーダンスの制御とペア配線導体の高密度配線との両立が難しいという問題を有していた。
【0010】
本発明は、かかる従来技術の問題点に鑑み完成されたものであり、その目的はペア信号配線導体の幅に対する絶縁層を厚みおよびペア信号配線導体の配線間隔を制御することより、ペア信号配線導体の特性インピーダンスを50Ω±10%の範囲に制御するとともに高密配線が可能な配線基板およびこれを用いた電子装置を提供することにある。
【0011】
【発明が解決するための手段】
本発明の配線基板は、絶縁基板の主面に、互いに隣接して延びる少なくとも一対のペア信号配線導体と接地または電源導体層とを、ペア信号配線導体の上下にエポキシ樹脂および無機絶縁フィラーを含有して成る誘電率が3.5〜4.5の絶縁層を介して接地または電源導体層が対向するようにして積層して成る配線基板において、ペア信号配線導体と接地または電源導体層との間の絶縁層は、その一方の厚みがペア信号配線導体の幅の3倍以上であるとともに他方の厚みがペア信号配線導体の幅と同等であり、かつペア信号配線導体の間隔がペア信号配線導体の幅以下であることを特徴とするものである。
【0012】
本発明の電子装置は、上記の配線基板の表面に信号配線導体と接続される電子部品接続パッドを設けるとともにこの電子部品接続パッドに配線基板に搭載した電子部品の電極を接続して成ることを特徴とする。
【0013】
本発明の配線基板および電子装置によれば、ペア信号配線導体と接地または電源導体層との間の絶縁層は、その一方の厚みがペア信号配線導体の幅の3倍以上であるとともに他方の厚みがペア信号配線導体の幅と同等であり、かつペア信号配線導体の間隔をペア信号配線導体の幅以下としたことから、ペア信号配線導体と接地または電源導体層およびペア信号配線導体同士のキャパシタンスを制御して、ペア信号配線導体の特性インピーダンスを50Ω±10%の範囲に制御するとともにペア信号配線導体の配線間隔が狭くできるので高密度配線が可能な配線基板および電子装置とすることができる。
【0014】
【発明の実施の形態】
次に、本発明の配線基板およびこれを用いた電子装置を添付の図面に基づいて詳細に説明する。
【0015】
図1は、本発明の配線基板に電子部品を実装して成る電子装置の実施形態の一例を示す断面図であり、図2は、その要部拡大断面図である。
【0016】
これらの図において、1は絶縁基板、2は絶縁層、3はペア信号配線導体、4は接地または電源導体層、5は電子部品接続パッドで、主にこれらで本発明の配線基板が構成される。また、この配線基板に電子部品6を搭載し、これを電子部品接続パッド5に半田等を介して電気的に接続することにより本発明の電子装置と成る。
【0017】
本発明の配線基板は、電子部品6を支持する支持部材としての機能を有し、絶縁基板1の表面および/または裏面の主面に複数の絶縁層2と導体層とを複数積層することによって形成されている。導体層はペア信号配線導体3と接地または電源導体層4とから構成される。
【0018】
配線基板を構成する絶縁基板1は、絶縁層2の支持体としての機能を有し、例えばガラスクロス−エポキシ樹脂やガラスクロス−ビスマレイミドトリアジン樹脂・ガラスクロス−ポリフェニレンエーテル樹脂・アラミド繊維−エポキシ樹脂等の樹脂材料から成り、常法により製作される。また、絶縁基板1の主面には、接地または電源導体層4が被着形成されており、これらの接地または電源導体層4を絶縁基板1の内部に形成されたスルーホール導体1aに電気的に接続している。さらに、絶縁基板1の主面には、ペア信号配線導体3と接地または電源導体層4とを、ペア信号配線導体3の上下に絶縁層2を介して接地または電源導体層4が対向するようにして積層している。
【0019】
絶縁層2は、ペア信号配線導体3や接地または電源導体層4を支持する支持部材として機能し、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂・ポリフェニレンエーテル樹脂等の熱硬化性樹脂と無機絶縁性フィラーとからなり、さらに耐クラック性を付与するためにエラストマーを加えてもよい。なお、このような絶縁層2の誘電率は3.5〜4.5に調整されている。
【0020】
このような絶縁層2は、例えばエポキシ樹脂と熱可塑性樹脂・エラストマー・無機絶縁性フィラーに溶剤等を添加した混合物を混練して液状ワニスを得、この液状ワニスをポリエチレンテレフタレート(PET)製離型シート上に塗布し、60〜100℃の温度で乾燥することによりフィルム状に成形し、このフィルムを絶縁基板1の表面に真空ラミネータを用いて圧着し、オーブンで熱硬化することにより積層される。また、絶縁層2には、炭酸ガスレーザやYAGレーザ・UVレーザ等の従来周知のレーザを用いて直径が30〜300μm程度の貫通孔7が形成されているとともに、その内部に銅や金・ニッケル・アルミニウム等の金属薄膜を被着することにより、上下に位置する導体層等同士を電気的に接続する貫通導体8が形成されている。
【0021】
絶縁層2の表面には、ペア信号配線導体3および接地または電源導体層4から成る導体層が被着形成されている。導体層は、配線基板に搭載される電子部品6を外部電気回路基板(図示せず)に電気的に接続する導電路としての機能を有する。
【0022】
なお、接地または電源導体層4は、設計上必要な絶縁基板1および絶縁層2の略全面にはベタパターン状に形成されている。
【0023】
ペア信号配線導体3や接地または電源導体層4・貫通配線8を形成する金属材料としては、電気抵抗値が低いという観点からは銅や金・ニッケル・アルミニウム等の金属が好ましく、安価という観点からは銅が好ましい。なお、金属薄膜の厚みは、高速の信号を伝達させるという観点からは3μm以上であることが好ましく、金属薄膜を絶縁基板1や絶縁層2に被着形成する際に金属薄膜に大きな応力を残留させず、金属薄膜が絶縁基板1や絶縁層2から剥離しにくいものとするためには30μm以下としておくことが好ましい。
【0024】
そして、本発明の配線基板においては、ペア信号配線導体3と接地または電源導体層4との間の絶縁層2は、その一方の厚みT1がペア信号配線導体3の幅Wの3倍以上であるとともに他方の厚みT2がペア信号配線導体の幅Wと同等であり、かつペア信号配線導体の配線間隔Sがペア信号配線導体の幅W以下であることが重要である。
【0025】
本発明の配線基板によれば、ペア信号配線導体3と接地または電源導体層4との間の絶縁層1は、その一方の厚みT1がペア信号配線導体の幅Wの3倍以上であるとともに他方の厚みT2がペア信号配線導体の幅Wと同等であり、かつペア信号配線導体の間隔Sがペア信号配線導体の幅W以下としたことから、ペア信号配線導体3と接地または電源導体層4およびペア信号配線導体3同士のキャパシタンスを制御して、ペア信号配線導体3の特性インピーダンスを50Ω±10%の範囲に制御するとともにペア信号配線導体の配線間隔Sが狭くできるので高密度配線が可能な配線基板および電子装置とすることができる。
【0026】
ペア信号配線導体3と接地または電源導体層4との間の絶縁層1は、その一方の厚みT1をペア信号配線導体の幅Wの3倍未満とするとともに他方の厚みT2をペア信号配線導体の幅W未満とすると、ペア信号配線導体3と接地または電源導体層4とのキャパシタンスが大きくなり、特性インピーダンスを50Ω±10%の範囲に制御するにはペア信号配線導体3の配線間隔Sを広げる必要があり、高密度配線が困難となる傾向にある。従って、ペア信号配線導体の間隔Sをペア信号配線導体の幅W以下とする高密度配線を行うには、ペア信号配線導体3と接地または電源導体層4との間の絶縁層1は、その一方の厚みT1をペア信号配線導体の幅Wの3倍以上とするとともに他方の厚みT2をペア信号配線導体の幅Wと同等にしなければならない。また、ビルドアップ配線基板ような高密度なペア信号配線導体では、配線幅Wが20〜40μmと細いのでキャパシタンスを発生させるマイクロストリップ構造とするには、少なくとも片方の絶縁層の厚みTをペア信号配線導体の幅Wと同等にしなければならない。
【0027】
このようなペア信号配線導体3および接地または電源導体層4の金属薄膜は、次に述べる方法により形成される。まず、絶縁層2の所望の個所に、例えば炭酸レーザを用いて貫通孔を形成した後に、絶縁層2の表面および貫通孔7の内壁を過マンガン酸塩類水溶液等の粗化液に浸漬して粗化する。次に、絶縁層2の表面および貫通孔7の内壁を無電解めっきの触媒と成る例えばパラジウムの水溶液中に浸漬して絶縁層2の表面と貫通孔7の内壁に触媒を被着させ、さらに、絶縁層2の表面と貫通孔7の内壁を硫酸銅・ロッセル塩・ホルマリン・EDTAナトリウム塩・安定剤等から成る無電解めっき液に約30分間浸漬して、数μmの無電解銅めっき膜を析出させる。そして次に、絶縁層2の表面に耐めっき樹脂層をラミネートし露光と現像により薄膜導体と成る所定の配線パターンを形成し、しかる後に、硫酸・硫酸銅5水和物・塩素・光沢剤等から成る電解銅めっき液に数A/dmの電流を印加しながら数時間浸漬することにより貫通導体8が貫通孔6の内壁や内部に薄膜導体が形成される。さらに、水酸化ナトリウム水溶液に浸漬し感光性ドライフィルムレジストを剥離し、しかる後、硫酸・過酸化水素水溶液で剥離した耐めっき樹脂層下の無電解銅めっき膜表面をエッチングすることにより、絶縁層2の表面にペア信号配線導体3や接地または電源導体層4が形成される。
【0028】
そして、このようなペア信号配線導体3や接地または電源導体層4・貫通配線8を形成した絶縁層2の上面に、次の絶縁層2を積層するとともに上記と同じ工程を繰り返してペア信号配線導体3や接地または電源導体層4・貫通配線8を形成し、さらにこれを複数回繰り返すことにより絶縁層2が複数層積層される。
【0029】
また、配線基板の最外層に形成された絶縁層2の表面には、電子部品の高周波信号電極と接続するために、ペア信号配線導体3の一部を用いて成る電子部品接続パッド5が形成されている。さらに、電子部品接続パッド5が形成されている最外層の反対側の最外層には、外部電気回路基板(図示せず)の電極と接続するための外部接続用パッド9が、ペア信号配線導体3の一部を用いて形成されている。
【0030】
配線基板を電子部品6と強固に接続するためには、電子部品接続パッド5上に形成される導体バンプ10aの直径を50〜200μmにする必要がある。従って、電子部品接続パッド5の直径も100〜220μmにする必要がある。電子部品接続パッド5の直径が100μmより小さくなると導体バンプ10aとの接続面積が少なくなり、電子部品6の高周波信号電極を強固に接続できなくなる傾向にあり、220μmより大きくなると単位面積当たりの電子部品接続パッド5数が少なくなり、配線基板の多端子化が困難となる傾向にある。
【0031】
なお、配線基板に電子部品6を実装する際の熱履歴から絶縁層2および電子部品接続パッド5、外部接続パッド9を保護するために、絶縁層2の最外層表面に感光性樹脂から成る耐半田樹脂層11を被着形成してもよい。また、この場合、耐半田樹脂層11の電子部品接続パッド5および外部接続パッド9の上部には露光・現像により電子部品接続パッド5と電子部品の高周波信号用電極とを接続する導体バンプ10a用の開口および、外部接続パッド9と外部電気回路基板の電極とを接続する導体バンプ10b用の開口が形成される。さらに、開口底の電子部品接続パッド5および外部接続パッド9の表面にニッケル・金等の良導電性で耐腐蝕性に優れた金属をめっき法により1〜20μmの厚さに被着させておくと、電子部品接続パッド5および外部接続パッド9の表面の酸化腐食を有効に防止できるとともに電子部品接続パッド5と導体バンプ10aおよび外部接続パッド9と導体バンプ10bの接続を良好とすることができる。
【0032】
また、本発明の電子装置は、配線基板表面の電子部品接続パッド5と配線基板に搭載した電子部品6の高周波信号用電極とを導体バンプ10aを介して電気的に接続することによって形成される。
【0033】
なお、電子部品接続パッド5および外部接続パッド9上に被着された耐半田樹脂層11の開口の形状は円形状であることが望ましく、さらに、それらの径は電子部品接続パッド5側が50〜300μm、外部接続パッド9側が300〜900μmの範囲とすることが好ましい。
【0034】
導体バンプ10a・10bは、電子部品接続パッド5と電子部品6の各電極とを、および外部接続パッド9と外部電気回路基板(図示せず)の高周波信号用電極とを電気的に接続する機能を有し、配線基板表面の電子部品接続パッド5および外部接続パッド9上に半田等の金属により形成されている。このような導体バンプ10a・10bは、金や鉛−錫・錫−亜鉛・錫−銀−ビスマス等の合金の導電材料から成り、例えば導電材料が鉛−錫から成る半田の場合、鉛−錫から成るぺーストを耐半田樹脂層11の開口にスクリーン印刷法によって印刷、あるいは鉛−錫から成る半田ボールを耐半田樹脂層11の開口に載置した後、リフロー炉を通すことによって電子部品接続パッド5および外部接続パッド9上に固着形成される。しかる後、電子部品6を導体バンプ10a上に載置し、リフロー炉を通すことによって電子部品接続パッド5と電子部品6の各回路とが電気的に接続される。なお、電子部品6と配線基板表面との間に、熱硬化性樹脂とフィラーとから成るアンダーフィル材12を注入することによって、導体バンプ10aが保護されるとともに電子部品6が配線基板に強固に固着される。
【0035】
かくして、本発明の電子装置によれば、上記の配線基板に電子部品6を実装するとともに、配線基板の電子部品接続パッド5と電子部品6の電極とを半田を介して電気的に接続して成ることから、特性インピーダンスを安定させることができるとともに高密度配線が可能な電子装置とすることができる。
【0036】
なお、本発明の配線基板および電子装置は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であることは言うまでもない。
【0037】
【実施例】
本発明の配線基板の特性インピーダンスを評価するために、以下に説明するような配線基板を製作し、TDR(タイム・ドメイン・リフレクトメトリ)測定を行なった。TDR測定法とは、ステップジェネレータおよびオシロスコープを使用し、ステップジェネレータにより外部接続パッドに急峻なエッジをもつ信号(入射波)を送り、送りこまれた信号は伝送ラインの伝搬速度で信号配線上および貫通導体を伝わり、入射波の一部が反射され、この入射波と反射波の電圧をオシロスコープにてモニタすることにより外部接続パッドの特性インピーダンス(Zo値)を測定する方法である。
【0038】
まず、エポキシ樹脂と熱可塑性樹脂・エラストマー・無機絶縁性フィラーに溶剤等を添加した混合物を混練して液状ワニスを得、この液状ワニスをポリエチレンテレフタレート(PET)製離型シート上に塗布し、60〜100℃の温度で乾燥することにより、厚みが10〜130μmのフィルム状に成形して、接地導体層を被着した絶縁基板主面に厚みが50〜130μmのフィルムをラミネートすることにより積層した後、150〜180℃で熱硬化を行なって一方の絶縁層を形成した。次に、その絶縁層に炭酸ガスレーザやYAGレーザ・UVレーザ等の従来周知のレーザを用いて直径が50μm程度の貫通孔を形成した後、絶縁層の表面および貫通孔内壁を過マンガン酸塩類水溶液等の粗化液に浸漬して粗化する。次に、絶縁層2の表面および貫通孔内壁に銅めっき膜を被着することにより幅が20〜40μmのペア信号配線導体および貫通導体が形成される。さらに、これらに厚みが10〜50μmのフィルムをラミネートすることにより積層した後、150〜180℃で熱硬化を行なって他方の絶縁層を形成した。他方の絶縁層上に接地導体層を被着した。これらを繰返すことにより、配線基板を製作した。
【0039】
ここで、ペア信号配線導体の幅Wと一方の絶縁層の厚みT1・他方の絶縁層の厚みT2・ペア信号配線導体の配線間隔S・特性インピーダンス値との関係を表1に示す。
【0040】
【表1】

Figure 2004241496
【0041】
表1に示すように、絶縁層2の誘電率Erが3.5〜4.5の範囲、ペア信号配線導体の幅Wが20〜40μmの範囲において、ペア信号配線導体3と接地または電源導体層4との間の絶縁層2は、その一方の厚みT1をペア信号配線導体の幅Wの3倍以上にするとともに他方の厚みT2をペア信号配線導体の幅Wと同等にし、かつペア信号配線導体の配線間隔Sをペア信号配線導体の幅W以下にすることにより、外部接続パッド8の特性インピーダンスの値を50Ω±10%の範囲内とすることができた。
【0042】
【発明の効果】
本発明の配線基板および電子装置によれば、ペア信号配線導体と接地または電源導体層との間の絶縁層は、その一方の厚みがペア信号配線導体の幅の3倍以上であるとともに他方の厚みがペア信号配線導体の幅と同等であり、かつペア信号配線導体の間隔をペア信号配線導体の幅以下としたことから、ペア信号配線導体と接地または電源導体層およびペア信号配線導体同士のキャパシタンスを制御して、ペア信号配線導体の特性インピーダンスを50Ω±10%の範囲に制御するとともにペア信号配線導体の配線間隔が狭くできるので高密度配線が可能な配線基板および電子装置とすることができる。
【図面の簡単な説明】
【図1】本発明の配線基板に電子部品を搭載して成る電子装置の実施の形態の一例を示す断面図である。
【図2】図1に示す配線基板の要部拡大断面図である。
【符号の説明】
1・・・・・・・絶縁基板
2・・・・・・・絶縁層
3・・・・・・・ペアー信号配線導体
4・・・・・・・接地または電源導体層
5・・・・・・・電子部品接続パッド
6・・・・・・・電子部品
W・・・・・・・ペアー信号配線導体の配線幅
T・・・・・・・絶縁層の厚み
S・・・・・・・ペアー信号配線導体の配線間隔[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for mounting electronic components such as semiconductor elements and an electronic device having electronic components mounted on the wiring board, and more particularly to a wiring board having improved wiring efficiency in consideration of electrical characteristics. About.
[0002]
[Prior art]
In general, current electronic devices have been remarkably improved in speed and transmission capacity. Accordingly, a wiring board and a package mounted on an electronic device are required to have a form with less electric loss. In addition, there has been a demand for smaller, thinner, and more multi-terminal wiring boards that constitute electronic devices. To achieve this, the width of conductor layers, such as signal wiring conductors, has been reduced and the spacing between them has been reduced. In addition, high-density wiring has been achieved by increasing the number of wiring layers and reducing the diameter of through conductors connecting the wirings.
[0003]
As a wiring board capable of such high-density wiring, a wiring board manufactured by employing a build-up method is known. With the build-up method, for example, a reinforcing material such as glass cloth or aramid non-woven fabric is impregnated with a thermosetting resin typified by an epoxy resin having heat resistance and chemical resistance, on an insulating substrate that is composited, After applying an adhesive made of a thermosetting resin such as epoxy resin with the conductive layer in between, forming an insulating layer and heating and curing the insulating layer, the diameter of the insulating layer above the wiring conductive layer is measured with a laser. A through hole of about 50 to 200 μm is formed, and thereafter, the surface of the insulating layer is chemically roughened, and a conductor is formed on the conductor layer on the side surface and the bottom surface of the through hole using electroless copper plating and electrolytic copper plating. A wiring board is manufactured by forming a through conductor by applying a film, forming a conductor layer connected to the through conductor on the surface of the insulating layer, and further repeating the formation of the insulating layer and the through conductor / conductor layer a plurality of times. Is the way.
[0004]
The conductor layer of such a wiring board is functionalized into a signal wiring conductor and a ground or power supply conductor layer depending on the application. Among them, the signal wiring conductor has a function as a conductive path for propagating an electric signal input / output to the electronic component to an external electric circuit board, and is constituted by a thin film conductor patterned into a predetermined circuit shape. I have.
[0005]
On the other hand, the ground or power supply conductor layer has a function of supplying a ground or power supply potential to an electronic component such as a semiconductor element mounted on the wiring board, shields an electromagnetic wave generated by a current flowing through the signal wiring conductor, and It has a function of preventing noise generated in the wiring layer, and is made of a solid pattern thin-film conductor in which almost the entire surface of the insulating layer is plated. The ground or power supply conductor layer and the signal wiring conductor that play such a role are electrically connected to electronic component connection pads for connecting electronic components provided on the surface of the wiring substrate via through conductors, and are mounted on the wiring substrate. It is arranged in a laminated structure capable of shielding electromagnetic waves, supplying power or transmitting signals to electronic components to be manufactured. The signal wiring conductors are stacked so that the ground or power supply conductor layers face each other with an insulating layer interposed therebetween.
[0006]
In signal wiring, it is important to reduce signal loss and transmission loss such as reflection, crosstalk, and noise so that electronic components do not malfunction. Such a signal wiring is generally formed as a pair (pair) signal wiring conductor because a differential signal (having a different wavelength phase) is used to transmit a high-frequency signal.
[0007]
Since the paired signal wiring conductor is a fine pattern having a wiring width of about 20 to 30 μm and a wiring interval of 40 to 60 μm, the characteristic impedance is controlled within a range of 50Ω ± 10% generally required for a wiring board. For this purpose, the insulating layer is adjusted to have a thickness of 20 to 50 μm and a dielectric constant of 3.5 to 4.5.
[0008]
[Patent Document 1]
JP 2001-326505 A
[Problems to be solved by the invention]
However, in this conventional wiring board, if the wiring interval between the paired signal wiring conductors is reduced in accordance with the demand for high-density wiring in recent years, the capacitance due to capacitive coupling between the paired signal wiring conductors becomes too large. Cannot be controlled within the range of 50Ω ± 10%. As described above, there is a problem that it is difficult to achieve both the control of the characteristic impedance and the high-density wiring of the pair wiring conductors.
[0010]
The present invention has been completed in view of the problems of the related art, and an object of the present invention is to control the thickness of the insulating layer with respect to the width of the paired signal wiring conductor and the wiring interval of the paired signal wiring conductor by controlling the wiring distance of the paired signal wiring conductor. It is an object of the present invention to provide a wiring board capable of controlling the characteristic impedance of a conductor within a range of 50Ω ± 10% and enabling high-density wiring, and an electronic device using the same.
[0011]
Means for Solving the Invention
The wiring board of the present invention includes at least a pair of paired signal wiring conductors extending adjacent to each other and a ground or power supply conductor layer on the main surface of the insulating substrate, and an epoxy resin and an inorganic insulating filler above and below the paired signal wiring conductors. In a wiring board formed by stacking the ground or power supply conductor layers facing each other via an insulating layer having a dielectric constant of 3.5 to 4.5, the pair signal wiring conductor and the ground or power supply conductor layer The thickness of one of the insulating layers between the pair of signal wiring conductors is at least three times the width of the pair signal wiring conductor, the other thickness is equal to the width of the pair signal wiring conductor, and the distance between the pair signal wiring conductors is The width is not more than the width of the conductor.
[0012]
An electronic device according to the present invention includes an electronic component connecting pad connected to a signal wiring conductor provided on a surface of the wiring substrate, and an electrode of an electronic component mounted on the wiring substrate connected to the electronic component connecting pad. Features.
[0013]
According to the wiring board and the electronic device of the present invention, the insulating layer between the paired signal wiring conductor and the ground or power supply conductor layer has one of the thicknesses equal to or more than three times the width of the paired signal wiring conductor and the other. Since the thickness is equal to the width of the paired signal wiring conductor and the interval between the paired signal wiring conductors is equal to or less than the width of the paired signal wiring conductor, the distance between the paired signal wiring conductor and the ground or the power supply conductor layer and the paired signal wiring conductor is reduced. By controlling the capacitance to control the characteristic impedance of the paired signal wiring conductor within a range of 50Ω ± 10% and to reduce the wiring interval between the paired signal wiring conductors, a wiring board and an electronic device capable of high-density wiring can be provided. it can.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a wiring board of the present invention and an electronic device using the same will be described in detail with reference to the accompanying drawings.
[0015]
FIG. 1 is a cross-sectional view showing an example of an embodiment of an electronic device in which an electronic component is mounted on a wiring board according to the present invention, and FIG. 2 is an enlarged cross-sectional view of a main part thereof.
[0016]
In these figures, 1 is an insulating substrate, 2 is an insulating layer, 3 is a paired signal wiring conductor, 4 is a ground or power supply conductive layer, 5 is an electronic component connection pad, and these mainly constitute the wiring board of the present invention. You. The electronic device of the present invention is provided by mounting the electronic component 6 on the wiring board and electrically connecting the electronic component 6 to the electronic component connection pad 5 via solder or the like.
[0017]
The wiring board of the present invention has a function as a support member for supporting the electronic component 6, and is formed by stacking a plurality of insulating layers 2 and a plurality of conductor layers on the main surface of the front surface and / or back surface of the insulating substrate 1. Is formed. The conductor layer includes a pair signal wiring conductor 3 and a ground or power supply conductor layer 4.
[0018]
The insulating substrate 1 constituting the wiring substrate has a function as a support for the insulating layer 2, and is, for example, glass cloth-epoxy resin, glass cloth-bismaleimide triazine resin, glass cloth-polyphenylene ether resin, aramid fiber-epoxy resin. Etc., and is manufactured by an ordinary method. A grounding or power supply conductor layer 4 is formed on the main surface of the insulating substrate 1, and the grounding or power supply conductor layer 4 is electrically connected to the through-hole conductor 1 a formed inside the insulating substrate 1. Connected to Further, on the main surface of the insulating substrate 1, the paired signal wiring conductor 3 and the grounding or power supply conductor layer 4 are arranged so that the grounding or power supply conductor layer 4 is opposed to the upper and lower sides of the paired signal wiring conductor 3 via the insulating layer 2. And laminated.
[0019]
The insulating layer 2 functions as a support member for supporting the paired signal wiring conductor 3 and the grounding or power supply conductor layer 4, and includes a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin, a polyphenylene ether resin, and an inorganic insulating filler. , And an elastomer may be added for imparting crack resistance. The dielectric constant of the insulating layer 2 is adjusted to 3.5 to 4.5.
[0020]
Such an insulating layer 2 is formed by kneading a mixture of, for example, an epoxy resin and a thermoplastic resin / elastomer / inorganic insulating filler to which a solvent or the like is added, to obtain a liquid varnish, and releasing the liquid varnish from polyethylene terephthalate (PET). A film is formed by coating on a sheet and drying at a temperature of 60 to 100 ° C., and the film is laminated on the surface of the insulating substrate 1 by pressure bonding using a vacuum laminator and thermosetting in an oven. . In the insulating layer 2, a through hole 7 having a diameter of about 30 to 300 μm is formed using a conventionally known laser such as a carbon dioxide gas laser or a YAG laser or a UV laser, and copper, gold, nickel or the like is formed therein. The through conductor 8 that electrically connects the upper and lower conductor layers and the like is formed by applying a metal thin film such as aluminum.
[0021]
On the surface of the insulating layer 2, a conductor layer including a pair signal wiring conductor 3 and a ground or power supply conductor layer 4 is formed by adhesion. The conductor layer has a function as a conductive path for electrically connecting the electronic component 6 mounted on the wiring board to an external electric circuit board (not shown).
[0022]
The ground or power supply conductor layer 4 is formed in a solid pattern over substantially the entire surface of the insulating substrate 1 and the insulating layer 2 necessary for design.
[0023]
As a metal material for forming the pair signal wiring conductor 3, the ground or power supply conductor layer 4, and the through wiring 8, a metal such as copper, gold, nickel, or aluminum is preferable from the viewpoint of low electric resistance, and a low cost. Is preferably copper. The thickness of the metal thin film is preferably 3 μm or more from the viewpoint of transmitting a high-speed signal. When the metal thin film is formed on the insulating substrate 1 or the insulating layer 2, a large stress is applied to the metal thin film. In order not to make the metal thin film peel off from the insulating substrate 1 or the insulating layer 2, the thickness is preferably 30 μm or less.
[0024]
In the wiring board of the present invention, the thickness T1 of one of the insulating layers 2 between the paired signal wiring conductor 3 and the ground or power supply conductor layer 4 is three times or more the width W of the paired signal wiring conductor 3. It is important that the thickness T2 of the other pair is equal to the width W of the paired signal wiring conductor, and that the wiring interval S of the paired signal wiring conductor is not more than the width W of the paired signal wiring conductor.
[0025]
According to the wiring board of the present invention, the thickness T1 of one of the insulating layers 1 between the pair signal wiring conductor 3 and the ground or power supply conductor layer 4 is at least three times the width W of the pair signal wiring conductor. Since the other thickness T2 is equal to the width W of the paired signal wiring conductor and the interval S between the paired signal wiring conductors is equal to or less than the width W of the paired signal wiring conductor, the paired signal wiring conductor 3 is connected to the ground or power supply conductor layer. 4 and the paired signal wiring conductors 3 are controlled to control the characteristic impedance of the paired signal wiring conductors 3 in the range of 50Ω ± 10% and the wiring interval S of the paired signal wiring conductors can be narrowed, so that high-density wiring is achieved. Possible wiring boards and electronic devices can be obtained.
[0026]
The insulating layer 1 between the pair signal wiring conductor 3 and the ground or power supply conductor layer 4 has one thickness T1 less than three times the width W of the pair signal wiring conductor and the other thickness T2 of the pair signal wiring conductor. Is smaller than the width W, the capacitance between the paired signal wiring conductor 3 and the grounding or power supply conductor layer 4 becomes large. To control the characteristic impedance within the range of 50Ω ± 10%, the wiring interval S of the paired signal wiring conductor 3 must be reduced. It is necessary to spread the wiring, and there is a tendency that high-density wiring becomes difficult. Therefore, in order to perform high-density wiring in which the interval S between the paired signal wiring conductors is equal to or less than the width W of the paired signal wiring conductors, the insulating layer 1 between the paired signal wiring conductors 3 and the ground or power supply conductor layer 4 needs One thickness T1 must be equal to or more than three times the width W of the paired signal wiring conductor, and the other thickness T2 must be equal to the width W of the paired signal wiring conductor. Further, in a high-density pair signal wiring conductor such as a build-up wiring board, the wiring width W is as thin as 20 to 40 μm. It must be equal to the width W of the wiring conductor.
[0027]
Such a thin metal film of the pair signal wiring conductor 3 and the ground or power supply conductor layer 4 is formed by a method described below. First, after forming a through hole at a desired place of the insulating layer 2 using, for example, a carbon dioxide laser, the surface of the insulating layer 2 and the inner wall of the through hole 7 are immersed in a roughening solution such as a permanganate aqueous solution. Roughens. Next, the surface of the insulating layer 2 and the inner wall of the through hole 7 are immersed in an aqueous solution of, for example, palladium, which serves as a catalyst for electroless plating, so that the catalyst is applied to the surface of the insulating layer 2 and the inner wall of the through hole 7. Then, the surface of the insulating layer 2 and the inner wall of the through hole 7 are immersed in an electroless plating solution comprising copper sulfate, Rossel salt, formalin, sodium EDTA, a stabilizer, etc. for about 30 minutes to form a few μm electroless copper plating film. Is precipitated. Next, a plating-resistant resin layer is laminated on the surface of the insulating layer 2 and a predetermined wiring pattern to be a thin film conductor is formed by exposure and development, and thereafter, sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, etc. The thin film conductor is formed on the inner wall and inside of the through hole 6 by immersing for several hours while applying a current of several A / dm 2 to the electrolytic copper plating solution composed of Further, the photosensitive dry film resist is stripped by dipping in an aqueous solution of sodium hydroxide, and thereafter, the insulating layer is etched by etching the surface of the electroless copper plating film under the plating-resistant resin layer stripped with a sulfuric acid / hydrogen peroxide solution. A pair signal wiring conductor 3 and a ground or power supply conductor layer 4 are formed on the surface of the substrate 2.
[0028]
Then, the next insulating layer 2 is laminated on the upper surface of the insulating layer 2 on which the paired signal wiring conductor 3 and the ground or power supply conductor layer 4 and the through wiring 8 are formed, and the same process as described above is repeated. The conductor 3, the ground or power supply conductor layer 4, and the through wiring 8 are formed, and this is repeated a plurality of times, whereby a plurality of insulating layers 2 are laminated.
[0029]
On the surface of the insulating layer 2 formed on the outermost layer of the wiring board, an electronic component connection pad 5 formed by using a part of the paired signal wiring conductor 3 is formed in order to connect to a high-frequency signal electrode of the electronic component. Have been. Further, on the outermost layer on the opposite side of the outermost layer on which the electronic component connection pads 5 are formed, external connection pads 9 for connecting to electrodes of an external electric circuit board (not shown) are provided with paired signal wiring conductors. 3 is formed.
[0030]
In order to firmly connect the wiring board to the electronic component 6, the diameter of the conductor bump 10a formed on the electronic component connection pad 5 needs to be 50 to 200 μm. Therefore, the diameter of the electronic component connection pad 5 also needs to be 100 to 220 μm. When the diameter of the electronic component connection pad 5 is smaller than 100 μm, the connection area with the conductor bump 10 a decreases, and the high frequency signal electrode of the electronic component 6 tends to be unable to be firmly connected. When it is larger than 220 μm, the electronic component per unit area The number of connection pads 5 decreases, and it tends to be difficult to increase the number of terminals of the wiring board.
[0031]
In order to protect the insulating layer 2, the electronic component connection pads 5, and the external connection pads 9 from the heat history when the electronic component 6 is mounted on the wiring board, the outermost layer of the insulating layer 2 is made of a photosensitive resin made of a photosensitive resin. The solder resin layer 11 may be attached and formed. In this case, on the upper part of the electronic component connection pad 5 and the external connection pad 9 of the solder-resistant resin layer 11, a conductor bump 10a for connecting the electronic component connection pad 5 and the high-frequency signal electrode of the electronic component by exposure and development. And an opening for the conductor bump 10b for connecting the external connection pad 9 to the electrode of the external electric circuit board. Further, a metal having good conductivity and excellent corrosion resistance, such as nickel or gold, is applied to the surface of the electronic component connection pad 5 and the external connection pad 9 at the bottom of the opening to a thickness of 1 to 20 μm by plating. In addition, oxidation corrosion of the surfaces of the electronic component connection pads 5 and the external connection pads 9 can be effectively prevented, and the connection between the electronic component connection pads 5 and the conductor bumps 10a and between the external connection pads 9 and the conductor bumps 10b can be improved. .
[0032]
Further, the electronic device of the present invention is formed by electrically connecting the electronic component connection pads 5 on the surface of the wiring substrate and the high frequency signal electrodes of the electronic component 6 mounted on the wiring substrate via the conductor bumps 10a. .
[0033]
It is desirable that the shape of the opening of the solder resistant resin layer 11 attached on the electronic component connection pad 5 and the external connection pad 9 is circular, and the diameter of the opening is 50 to 50 on the electronic component connection pad 5 side. It is preferable that the thickness is 300 μm and the external connection pad 9 side is in the range of 300 to 900 μm.
[0034]
The conductor bumps 10a and 10b have a function of electrically connecting the electronic component connection pad 5 and each electrode of the electronic component 6, and the external connection pad 9 and a high-frequency signal electrode of an external electric circuit board (not shown). And is formed of metal such as solder on the electronic component connection pads 5 and the external connection pads 9 on the surface of the wiring board. Such conductive bumps 10a and 10b are made of a conductive material of an alloy such as gold or lead-tin-tin-zinc-tin-silver-bismuth. For example, when the conductive material is a solder made of lead-tin, lead-tin Is printed on the opening of the solder-resistant resin layer 11 by screen printing, or a solder ball made of lead-tin is placed on the opening of the solder-resistant resin layer 11 and then passed through a reflow furnace to connect electronic components. It is fixedly formed on the pad 5 and the external connection pad 9. Thereafter, the electronic component 6 is placed on the conductor bump 10a and is passed through a reflow furnace, so that the electronic component connection pad 5 and each circuit of the electronic component 6 are electrically connected. By injecting an underfill material 12 made of a thermosetting resin and a filler between the electronic component 6 and the surface of the wiring board, the conductive bump 10a is protected and the electronic component 6 is firmly attached to the wiring board. It is fixed.
[0035]
Thus, according to the electronic device of the present invention, the electronic component 6 is mounted on the wiring board, and the electronic component connection pads 5 of the wiring board and the electrodes of the electronic component 6 are electrically connected via the solder. Accordingly, an electronic device that can stabilize characteristic impedance and can perform high-density wiring can be provided.
[0036]
It should be noted that the wiring board and the electronic device of the present invention are not limited to the above-described embodiments, and it is needless to say that various changes can be made without departing from the scope of the present invention.
[0037]
【Example】
In order to evaluate the characteristic impedance of the wiring board of the present invention, a wiring board as described below was manufactured, and TDR (time domain reflectometry) was measured. The TDR measurement method uses a step generator and an oscilloscope, and sends a signal (incident wave) having a sharp edge to an external connection pad by the step generator. This is a method of measuring a characteristic impedance (Zo value) of an external connection pad by monitoring a voltage of the incident wave and the reflected wave with an oscilloscope by transmitting a part of an incident wave through a conductor.
[0038]
First, a liquid varnish is obtained by kneading a mixture of an epoxy resin, a thermoplastic resin, an elastomer, and an inorganic insulating filler to which a solvent or the like is added, and the liquid varnish is applied on a release sheet made of polyethylene terephthalate (PET). By drying at a temperature of 100100 ° C., a film having a thickness of 10 to 130 μm was formed, and a film having a thickness of 50 to 130 μm was laminated on the main surface of the insulating substrate on which the ground conductor layer was applied. Thereafter, heat curing was performed at 150 to 180 ° C. to form one insulating layer. Next, a through hole having a diameter of about 50 μm is formed in the insulating layer using a conventionally known laser such as a carbon dioxide gas laser or a YAG laser or a UV laser, and then the surface of the insulating layer and the inner wall of the through hole are subjected to a permanganate aqueous solution. Immersion in a roughening solution such as Next, a pair of signal wiring conductors and through conductors having a width of 20 to 40 μm are formed by depositing a copper plating film on the surface of the insulating layer 2 and the inner wall of the through hole. Furthermore, after laminating these by laminating a film having a thickness of 10 to 50 μm, thermosetting was performed at 150 to 180 ° C. to form the other insulating layer. A ground conductor layer was deposited on the other insulating layer. By repeating these, a wiring board was manufactured.
[0039]
Table 1 shows the relationship between the width W of the paired signal wiring conductor, the thickness T1 of one insulating layer, the thickness T2 of the other insulating layer, the wiring interval S of the paired signal wiring conductor, and the characteristic impedance value.
[0040]
[Table 1]
Figure 2004241496
[0041]
As shown in Table 1, when the dielectric constant Er of the insulating layer 2 is in the range of 3.5 to 4.5 and the width W of the paired signal wiring conductor is in the range of 20 to 40 μm, the paired signal wiring conductor 3 is connected to the ground or power supply conductor. The insulating layer 2 between itself and the layer 4 has one thickness T1 equal to or more than three times the width W of the paired signal wiring conductor and the other thickness T2 equal to the width W of the paired signal wiring conductor. By setting the wiring interval S between the wiring conductors to be equal to or less than the width W of the pair signal wiring conductor, the value of the characteristic impedance of the external connection pad 8 could be set within the range of 50Ω ± 10%.
[0042]
【The invention's effect】
According to the wiring board and the electronic device of the present invention, the insulating layer between the paired signal wiring conductor and the ground or power supply conductor layer has one of the thicknesses equal to or more than three times the width of the paired signal wiring conductor and the other. Since the thickness is equal to the width of the paired signal wiring conductor and the interval between the paired signal wiring conductors is equal to or less than the width of the paired signal wiring conductor, the distance between the paired signal wiring conductor and the ground or the power supply conductor layer and the paired signal wiring conductor is reduced. By controlling the capacitance to control the characteristic impedance of the paired signal wiring conductor within a range of 50Ω ± 10% and to reduce the wiring interval between the paired signal wiring conductors, a wiring board and an electronic device capable of high-density wiring can be provided. it can.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating an example of an embodiment of an electronic device in which electronic components are mounted on a wiring board according to the present invention.
FIG. 2 is an enlarged sectional view of a main part of the wiring board shown in FIG.
[Explanation of symbols]
1 ... Insulating substrate 2 ... Insulating layer 3 ... Pair signal wiring conductor 4 ... Ground or power supply conductor layer 5 ... ···································································································· Thickness of the insulating layer ..Wiring intervals of pair signal wiring conductors

Claims (2)

絶縁基板の主面に、互いに隣接して延びる少なくとも一対のペア信号配線導体と接地または電源導体層とを、前記ペア信号配線導体の上下にエポキシ樹脂および無機絶縁フィラーを含有して成る誘電率が3.5〜4.5の絶縁層を介して前記接地または電源導体層が対向するようにして積層して成る配線基板において、前記ペア信号配線導体と前記接地または電源導体層との間の絶縁層は、その一方の厚みが前記ペア信号配線導体の幅の3倍以上であるとともに他方の厚みが前記ペア信号配線導体の幅と同等であり、かつ前記ペア信号配線導体の配線間隔が前記ペア信号配線導体の幅以下であることを特徴とする配線基板。On the main surface of the insulating substrate, at least a pair of paired signal wiring conductors extending adjacent to each other and a ground or power supply conductor layer, and a dielectric constant containing epoxy resin and an inorganic insulating filler above and below the paired signal wiring conductors. In a wiring board formed by stacking the ground or power supply conductor layers so as to face each other with an insulation layer of 3.5 to 4.5 interposed therebetween, the insulation between the paired signal wiring conductor and the ground or power supply conductor layer is provided. In the layer, one of the thicknesses is at least three times the width of the paired signal wiring conductor, the other thickness is equal to the width of the paired signal wiring conductor, and the wiring interval of the paired signal wiring conductor is the pair. A wiring board having a width equal to or less than a width of a signal wiring conductor. 請求項1記載の配線基板の表面に前記ペア信号配線導体および前記接地または電源導体層と接続される電子部品接続パッドを設けるとともに該電子部品接続パッドに前記配線基板に搭載した電子部品の電極を接続して成ることを特徴とする電子装置。An electronic component connection pad connected to the paired signal wiring conductor and the ground or power supply conductor layer is provided on a surface of the wiring board according to claim 1, and an electrode of an electronic component mounted on the wiring substrate is provided on the electronic component connection pad. An electronic device characterized by being connected.
JP2003027397A 2003-02-04 2003-02-04 Wiring substrate and electronic device employing the same Pending JP2004241496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003027397A JP2004241496A (en) 2003-02-04 2003-02-04 Wiring substrate and electronic device employing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003027397A JP2004241496A (en) 2003-02-04 2003-02-04 Wiring substrate and electronic device employing the same

Publications (1)

Publication Number Publication Date
JP2004241496A true JP2004241496A (en) 2004-08-26

Family

ID=32955144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003027397A Pending JP2004241496A (en) 2003-02-04 2003-02-04 Wiring substrate and electronic device employing the same

Country Status (1)

Country Link
JP (1) JP2004241496A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073622A (en) * 2004-08-31 2006-03-16 Nec Electronics Corp Semiconductor apparatus, package substrate therefor and manufacturing method thereof
CN102548189A (en) * 2010-12-28 2012-07-04 易鼎股份有限公司 Characteristic impedance accuracy control structure of circuit board
JP2014192497A (en) * 2013-03-28 2014-10-06 Ngk Spark Plug Co Ltd Wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073622A (en) * 2004-08-31 2006-03-16 Nec Electronics Corp Semiconductor apparatus, package substrate therefor and manufacturing method thereof
JP4559163B2 (en) * 2004-08-31 2010-10-06 ルネサスエレクトロニクス株式会社 Package substrate for semiconductor device, method for manufacturing the same, and semiconductor device
CN102548189A (en) * 2010-12-28 2012-07-04 易鼎股份有限公司 Characteristic impedance accuracy control structure of circuit board
JP2014192497A (en) * 2013-03-28 2014-10-06 Ngk Spark Plug Co Ltd Wiring board

Similar Documents

Publication Publication Date Title
US8129625B2 (en) Multilayer printed wiring board
JP5311653B2 (en) Wiring board
JP2003273525A (en) Wiring board
JP2002261455A (en) Multilayer interconnection board and electronic device using it
JP4540262B2 (en) Wiring substrate and semiconductor device using the same
JP2012099536A (en) Wiring board
JP2004063929A (en) Wiring board and electronic equipment using it
JP4315580B2 (en) Printed wiring board and printed wiring board manufacturing method
JP3801880B2 (en) Wiring substrate and semiconductor device using the same
JP2004179545A (en) Wiring board
JP2003198146A (en) Multilayer wiring substrate and electronic device using the same
JP2005019732A (en) Wiring substrate and electronic device using it
JP2004241496A (en) Wiring substrate and electronic device employing the same
JP2011216519A (en) Method of manufacturing wiring board
JP2005136042A (en) Wiring board, electric apparatus, and their manufacturing method
JP2003224227A (en) Wiring board and semiconductor device employing it
JP4437361B2 (en) Printed wiring board and printed wiring board manufacturing method
JP3840148B2 (en) WIRING BOARD AND ELECTRONIC DEVICE USING THE SAME
JP3990578B2 (en) WIRING BOARD AND ELECTRONIC DEVICE USING THE SAME
JP2004207338A (en) Wiring board
JP2004063531A (en) Circuit board and electronic device using the same
JP2003133737A (en) Multilayer wiring board and method of manufacturing the same
JP2003283147A (en) Wiring board and electronic device using the same
JP2004266180A (en) Wiring board
JP4492071B2 (en) Wiring board manufacturing method