JP2004179386A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2004179386A
JP2004179386A JP2002343725A JP2002343725A JP2004179386A JP 2004179386 A JP2004179386 A JP 2004179386A JP 2002343725 A JP2002343725 A JP 2002343725A JP 2002343725 A JP2002343725 A JP 2002343725A JP 2004179386 A JP2004179386 A JP 2004179386A
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interlayer insulating
insulating film
wiring
wiring layer
semiconductor device
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Takeaki Inoue
武明 井上
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable semiconductor device that is fine multilayer interconnection for composing an integrated circuit, suppresses an increase in wiring capacity, and has an interlayer insulating film, where hygroscopicity is low and strength is high, and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: Lower layer wiring 11 being an arbitrary metal wiring pattern and upper layer wiring 12 are formed in interlayer insulating films 10 (101, 102) in multilayer interconnection. The interlayer insulating films 10 for separating the wiring 11 from the wiring 12 consist of the first interlayer insulating film 101 and the second interlayer insulating film 102 having a low dielectric constant as compared with the first interlayer insulating film 101. In the interlayer insulating films 10, the second interlayer insulating film 102 is provided in the interlayer of a region, where the lower layer wiring 11 is overlapped to the upper layer wiring 12, and other regions are occupied by the first interlayer insulating film 101. The first interlayer insulating film 101 is in an organic film family, such as a silicon oxide film, and has low hygroscopicity and high physical strength as compared with the second interlayer insulating film 102 having a low dielectric constant. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の多層配線構造に係り、特に層間絶縁膜に低誘電率膜を利用する半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
半導体集積回路装置では、高集積回路化、低電圧電源、動作高速化が要求される。そこで、低抵抗の配線材を用いるのはもとより、配線層間の絶縁膜に、シリコン酸化膜のような通常の無機膜系に代るさらなる低誘電率膜が利用されるようになってきた。有機系低誘電率膜、無機系低誘電率膜、いわゆる有機系、無機系のＬｏｗ−ｋ 膜や、膜中に多くの空孔を導入した多孔質Ｌｏｗ−ｋ 膜などの利用である。これにより、配線の低容量化を図り、配線遅延（ＲＣ遅延）の影響を抑えて高速動作を妨げないようにする。
【０００３】
例えば、半導体集積回路を構成する任意の配線層を形成する。この配線層上に層間絶縁膜としてＬｏｗ−ｋ 膜を塗布法などで形成する。この層間絶縁膜上においてリソグラフィ工程を介して選択的に開口する。これにより、所定の配線層が露出するビアホール領域を形成する。このビアホール領域と共に配線領域となる溝を形成してもよい。その後、ビアホール領域にバリアメタル材料をスパッタ法により被覆する。
【０００４】
次に、上記ビアホール領域に配線材料を埋め込む。例えば、タングステンやアルミニウム等の配線材のスパッタ法による充填がなされる。あるいは銅配線であれば、銅のシード層のスパッタ及び電解メッキ法による銅の堆積などが代表的である。銅配線であれば、コンタクト領域及び配線領域となる溝（配線溝）を含む領域上に銅配線材料が堆積される。その後、化学的機械的研磨（ＣＭＰ）技術により、必要な配線部分のみに配線材料を埋め込んだ形に加工する。すなわち、タングステンプラグやアルミプラグ、銅プラグあるいは銅のデュアルダマシン配線などになる。その後、プラグ材上には次層の配線層をパターニングし、層間絶縁膜として再度Ｌｏｗ−ｋ 膜を形成する。デュアルダマシン配線上なら層間絶縁膜として再度Ｌｏｗ−ｋ 膜を形成する。
【０００５】
【発明が解決しようとする課題】
Ｌｏｗ−ｋ 材料は、従来層間絶縁膜として用いられるシリコン酸化膜よりも物理的強度が弱い。また、吸湿性も高く、多層配線回路が微細になるほど、その信頼性の低下が懸念される。配線材は、その周辺をバリア材で保護する形態がとられているものの、全面に層間絶縁膜としてＬｏｗ−ｋ 膜が配されるため強度低下、腐食の影響を受け易い。
【０００６】
本発明は上記のような事情を考慮してなされたもので、集積回路を構成する微細な多層配線で、配線容量の増大を抑えると共に、より低吸湿で高い強度が得られる層間絶縁膜を有する高信頼性の半導体装置及びその製造方法を提供しようとするものである。
【０００７】
【課題を解決するための手段】
本発明に係る半導体装置は、集積回路のため所定の金属配線部材を配して多層配線が構成される半導体装置であって、前記多層配線に関し任意の隣接した下層配線と上層配線を隔てる層間の絶縁膜として、第１層間絶縁膜及び少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を具備し、前記層間の絶縁膜のうち前記下層配線と上層配線の重なり合う領域の層間では前記第２層間絶縁膜が配され、その他の領域は前記第１層間絶縁膜で占められていることを特徴とする。
【０００８】
また、本発明に係る半導体装置は、集積回路のため所定の金属配線部材を配して多層配線が構成される半導体装置であって、前記多層配線に関し任意の隣接した下層配線と上層配線を隔てる層間の絶縁膜として、第１層間絶縁膜及び少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を具備し、前記層間の絶縁膜のうち前記下層配線と上層配線の重なり合う領域の層間及び隣接する同一の配線層間の一部領域において前記第２層間絶縁膜が配され、その他の領域は前記第１層間絶縁膜で占められていることを特徴とする。
【０００９】
上記それぞれの本発明に係る半導体装置によれば、低誘電率の第２層間絶縁膜を配する領域を、配線層間の狭い配線容量が大きくなる領域に限定する。その他の層間絶縁膜領域は第１層間絶縁膜で構成し、低誘電率の層間絶縁膜を設けた特長を活かしつつ、吸湿性や強度的な短所を顕在化させない。
なお、再認識する限定的事項として、上記本発明それぞれの前記第１層間絶縁膜は前記第２層間絶縁膜に比べて低吸湿性及び物理的強度が優れていることを特徴とする。
【００１０】
本発明に係るより好ましい半導体装置は、前記第１層間絶縁膜は無機系低誘電率膜、有機系低誘電率膜、膜中に空孔を導入した多孔質低誘電率膜から選択されるいずれかの膜で構成されることを特徴とする。
また、本発明に係るより好ましい半導体装置は、前記第１層間絶縁膜は無機膜系で、前記第１層間絶縁膜は有機系低誘電率膜、有機系低誘電率膜、膜中に空孔を導入した多孔質低誘電率膜から選択されるいずれかの膜で構成されることを特徴とする。
【００１１】
本発明に係る半導体装置の製造方法は、所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、多層配線層形成予定に応じパターニングされた任意の第１配線層上を含んで第１層間絶縁膜を形成する工程と、少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域を選択的に除去する工程と、前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を形成する工程と、前記第１層間絶縁膜上及び第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、を具備したことを特徴とする。
【００１２】
さらに、より好ましい本発明に係る半導体装置の製造方法は、所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、多層配線層形成予定に応じパターニングされた任意の第１配線層上を含んで第１層間絶縁膜を形成する工程と、少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域及び前記第１配線層のパターンが隣り合う所定の前記第１層間絶縁膜の一部領域を選択的に除去する工程と、前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を形成する工程と、前記第１層間絶縁膜上及び第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、を具備したことを特徴とする。
【００１３】
上記ぞれそれ本発明に係る半導体装置の製造方法によれば、低誘電率の第２層間絶縁膜を必要領域に限定的に形成するために、前もって大部分を構成する第１層間絶縁膜を形成した後、選択的に除去する工程を経る。その後、除去領域に第２層間絶縁膜が設けられる。
なお、再認識する限定的事項として、上記本発明それぞれの前記第１層間絶縁膜は前記第２層間絶縁膜に比べて低吸湿性及び物理的強度に優れた膜を用いることを特徴とする。
【００１４】
また、本発明に係る半導体装置の製造方法は、所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、多層配線層形成予定に応じパターニングされた任意の第１配線層上に、後から形成される第２層間絶縁膜より低誘電率の第１層間絶縁膜を形成する工程と、少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域を選択的に残し他は除去する工程と、前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低吸湿性で物理的膜強度の優れた第２層間絶縁膜を形成する工程と、前記第１層間絶縁膜上及び前記第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、を具備したことを特徴とする。
【００１５】
さらに、より好ましい本発明の半導体装置の製造方法は、所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、多層配線層形成予定に応じパターニングされた任意の第１配線層上に、後から形成される第２層間絶縁膜より低誘電率の第１層間絶縁膜を形成する工程と、少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域及び前記第１配線層のパターンが隣り合う所定の前記第１層間絶縁膜の一部領域を選択的に残し他は除去する工程と、前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低吸湿性で物理的強度の優れた第２層間絶縁膜を形成する工程と、前記第１層間絶縁膜上及び前記第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、を具備したことを特徴とする。
【００１６】
上記それぞれ本発明に係る半導体装置の製造方法によれば、低吸湿性で物理的強度の優れた層間絶縁膜としての第２層間絶縁膜に比べて、より限定的に利用する低誘電率の第１層間絶縁膜を先に形成する。このため、第１層間絶縁膜に対し必要領域を選択的に残すような除去工程を前もって行う。その後、第２層間絶縁膜を設けるようにする。
【００１７】
なお、本発明に係るそれぞれの半導体装置の製造方法では、前記第１配線層または前記第２配線層は、ダマシン構造の形態がとられるプラグ配線形成、あるいは、それぞれ下層の導電領域へのホール形状の形成と共に配線溝の形成を伴なうデュアル・ダマシン構造の形態がとられる配線形成工程が含まれることを特徴とする。素子の微細化に応じた安定した集積回路配線の実現に寄与する。
【００１８】
なお、本発明に係るそれぞれの半導体装置の製造方法では、前記第１配線層、前記第１層間絶縁膜、前記第２層間絶縁膜、前記第２配線層のうちの少なくともいずれかの形成時において化学的機械的研磨による平坦化工程を経ることを特徴とする。素子の微細化に応じた安定した集積回路配線の実現に寄与する。
【００１９】
【発明の実施の形態】
図１は、本発明の第１実施形態に係る半導体装置の要部を示す断面図である。半導体基板に形成される半導体集積回路内の多層配線を示している。多層配線における層間の絶縁膜１０（１０１，１０２）中に任意の金属配線パターンである下層配線１１、上層配線１２が形成されている。下層配線１１と上層配線１２は必要領域においてプラグ金属２２により接続されている。配線１１，１２を隔てる層間の絶縁膜１０は、第１層間絶縁膜１０１及び少なくとも前記第１層間絶縁膜１０１よりも低誘電率の第２層間絶縁膜１０２からなる。これら層間の絶縁膜１０のうち、下層配線１１と上層配線１２の重なり合う領域の層間では第２層間絶縁膜１０２が配され、その他の領域は第１層間絶縁膜１０１で占められている。
【００２０】
上記低誘電率の第２層間絶縁膜１０２とは、比誘電率をｋとしてｋ＜３．０を有するいわゆるＬｏｗ−ｋ 膜をいう。Ｌｏｗ−ｋ 膜は有機系、無機系があり、かつ膜中に多くの空孔を導入した多孔質Ｌｏｗ−ｋ 膜を利用することも考えられる。また、第１層間絶縁膜１０１は、シリコン酸化膜のような通常の無機膜系であり、Ｌｏｗ−ｋ 膜である第２層間絶縁膜１０２より低吸湿性で物理的強度が高い。さらにＬｏｗ−ｋ 膜よりも低吸湿性となっている。
【００２１】
上記実施形態の構成によれば、層間絶縁膜１０に関し、低誘電率の第２層間絶縁膜１０２を配する領域を、配線層間の狭い配線容量が大きくなる領域に限定する。その他の領域は、強度に優れ低吸湿性の第１層間絶縁膜１０１で占められる。これにより、低誘電率の層間絶縁膜を設けた特性を活かしつつ、吸湿性や強度的な短所を顕在化させない。すなわち、配線容量を小さくし、動作高速化に寄与し、低吸湿性及び高い強度を得る。
【００２２】
図２（ａ）〜（ｃ）は、それぞれ本発明の第２実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図であり、上記図１の構成を実現する。図１中と同様の箇所には同一の符号を付して説明する。
図２（ａ）に示すように、半導体集積回路内の多層配線に応じて、層間絶縁膜の領域上に任意の金属配線パターンである下層配線１１が形成される。下層配線１１は、図示しないが周囲にチタン／窒化チタン積層等バリアメタルの形成を含むアルミニウム合金などの金属配線である。次に、この下層配線１１上を十分に覆う第１層間絶縁膜１０１を形成する。第１層間絶縁膜１０１はＴＥＯＳ（テトラエトキシシラン）等、シリコン酸化膜のような通常の無機膜とし、例えばＣＶＤ（化学気相成長）法やプラズマＣＶＤ法により形成する。
次に、図２（ｂ）に示すように、ＣＭＰ（化学的機械的研磨）法またはエッチバック法を用いて第１層間絶縁膜１０１を平坦化する。その後、次層の形成予定である上層配線層（１２）がこの下層配線１１上に重なる第１層間絶縁膜１０１の領域を予めリソグラフィ技術により選択的に除去する。基本的には時間制御でエッチング除去する。図示しないが、除去領域の精度誤差を許容するため予め下層配線１１側壁に第１層間絶縁膜１０１と選択比のとれる部材を設けてもよい。次に、図２（ｃ）に示すように、第１層間絶縁膜１０１よりも低誘電率の第２層間絶縁膜１０２を形成する。第２層間絶縁膜１０２は塗布法その他の方法などを用いて形成するＬｏｗ−ｋ 膜である。例えば、塗布法による有機系低誘電率膜（シロキサン系、有機ポリマー（Ｓｉ−Ｏ基なし）、または多孔質材料）の形成が考えられる。あるいは、塗布法による無機系低誘電率膜（Ｓｉ−Ｏ基を有するシロキサン系、または多孔質材料）の形成、さらには、ＣＶＤ法によるＳｉＯＦ系の膜などの形成が考えられる。その後、ＣＭＰ技術を経て平坦化する。これにより、必要領域のみにＬｏｗ−ｋ 膜が残留し、第１層間絶縁膜１０１及び第２層間絶縁膜１０２からなる層間絶縁膜１０が構成される。次に、リソグラフィ工程を経て、第２層間絶縁膜１０２を介する下層配線１１との必要なビアホール２１を形成する。次に、ビアホールを埋めるプラグ金属２２を埋め込み形成し、平坦化して必要領域のみ残す。
【００２３】
その後は、層間絶縁膜１０上に上層配線１２をパターニング形成する。これらプラグ金属及び上層配線１２はそれぞれ図示しないバリアメタル（またはバリア材）の形成を含む。このような工程を経ることにより、前記図１で示す構成となる。すなわち、層間の絶縁膜１０のうち、下層配線１１と上層配線１２の重なり合う領域の層間では第２層間絶縁膜１０２が配され、その他の領域は第１層間絶縁膜１０１で占められている。
【００２４】
図３（ａ）〜（ｃ）は、それぞれ本発明の第３実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図であり、上記図１の構成を実現する。図１中と同様の箇所には同一の符号を付して説明する。
図３（ａ）に示すように、半導体集積回路内の多層配線に応じて、層間絶縁膜の領域上に任意の金属配線パターンである下層配線１１が形成される。下層配線１１は、前記第２実施形態と同様に図示しないがバリアメタルの形成を含むアルミニウム合金などの金属配線である。次に、この下層配線１１上を十分に覆う第２層間絶縁膜１０２を形成する。第２層間絶縁膜１０２は前記第２実施形態と同様のＬｏｗ−ｋ 膜であり、例えば有機系、無機系、あるいは多孔質のＬｏｗ−ｋ 膜いずれかを形成する。
次に、図３（ｂ）に示すように、ＣＭＰ（化学的機械的研磨）法またはエッチバック法を用いて第２層間絶縁膜１０２を平坦化する。その後、次層の形成予定である上層配線層（１２）がこの下層配線１１上に重なる第２層間絶縁膜１０２の領域を予めリソグラフィ技術により選択的に残し、それ以外を除去する。基本的には時間制御でエッチング除去する。図示しないが、除去領域の精度誤差を許容するため予め下層配線１１側壁に第２層間絶縁膜１０２と選択比のとれる部材を設けてもよい。
次に、図３（ｃ）に示すように、第２層間絶縁膜１０２よりも低吸湿性で物理的膜強度の優れた第１層間絶縁膜１０１を形成する。第１層間絶縁膜１０１はシリコン酸化膜のような通常の無機膜とし、例えばＣＶＤ（化学気相成長）法やプラズマＣＶＤ法により形成する。その後、ＣＭＰ技術を経て平坦化する。これにより、必要領域のみにＬｏｗ−ｋ 膜が残留し、第１層間絶縁膜１０１及び第２層間絶縁膜１０２からなる層間絶縁膜１０が構成される。次に、リソグラフィ工程を経て、第２層間絶縁膜１０２を介する下層配線１１との必要なビアホール２１を形成する。次に、ビアホールを埋めるプラグ金属２２を埋め込み形成し、平坦化して必要領域のみ残す。
【００２５】
その後は、層間絶縁膜１０上に上層配線１２をパターニング形成する。これらプラグ金属及び上層配線１２はそれぞれ図示しないバリアメタル（またはバリア材）の形成を含む。このような工程を経ることにより、前記図１で示す構成となる。すなわち、層間の絶縁膜１０のうち、下層配線１１と上層配線１２の重なり合う領域の層間では第２層間絶縁膜１０２が配され、その他の領域は第１層間絶縁膜１０１で占められている。
【００２６】
上記第２、第３実施形態ぞれそれに係る半導体装置の製造方法によれば、低誘電率の第２層間絶縁膜１０２を必要領域に限定的に形成するために、第１層間絶縁膜１０１または第２層間絶縁膜１０２いずれか一方を前もって形成する。その後、第２層間絶縁膜１０２または第１層間絶縁膜１０１を残りの必要領域に設ける。これら第１層間絶縁膜１０１、第２層間絶縁膜１０２の形成にはＣＭＰ等の平坦化工程を経ることによって、リソグラフィ工程の精度はいっそう向上する。
【００２７】
図４は、本発明の第４実施形態に係る半導体装置の要部を示す断面図である。半導体基板に形成される半導体集積回路内の多層配線を示している。多層配線における層間の絶縁膜４０（４０１，４０２）を介在させて任意の金属配線パターンである下層配線４１、上層配線４２が形成されている。下層配線４１と上層配線４２は必要領域において接続部４３を有する。これら配線４１，４２を隔てる層間の絶縁膜４０は、第１層間絶縁膜４０１及び少なくとも前記第１層間絶縁膜４０１よりも低誘電率の第２層間絶縁膜４０２からなる。これら層間の絶縁膜４０のうち、下層配線４１と上層配線４２の重なり合う領域の層間及び隣接する同一の配線層間の一部領域では第２層間絶縁膜４０２が配され、その他の領域は第１層間絶縁膜４０１で占められている。
【００２８】
上記低誘電率の第２層間絶縁膜４０２とは、前記第１実施形態同様に、いわゆるＬｏｗ−ｋ 膜をいう。有機系、無機系、多孔質系の膜等、様々なＬｏｗ−ｋ 膜を利用することが考えられる。また、第１層間絶縁膜４０１は、シリコン酸化膜のような通常の無機膜系であり、Ｌｏｗ−ｋ 膜である第２層間絶縁膜４０２より物理的強度が高い。さらにＬｏｗ−ｋ 膜よりも低吸湿性となっている。
【００２９】
上記実施形態の構成によれば、層間絶縁膜４０に関し、低誘電率の第２層間絶縁膜４０２を配する領域を、上下配線層間さらには同一配線層間の狭い、配線容量が大きくなる領域に限定する。その他の領域は、強度に優れ低吸湿性の第１層間絶縁膜４０１で占められる。これにより、低誘電率の層間絶縁膜を設けた特性を活かしつつ、吸湿性や強度的な短所を顕在化させない。すなわち、配線容量を小さくし、動作高速化に寄与し、低吸湿性及び高い強度を得る。
【００３０】
図５（ａ）〜（ｄ）は、それぞれ本発明の第５実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図であり、上記図４の構成を実現する。図４中と同様の箇所には同一の符号を付して説明する。
図５（ａ）に示すように、半導体集積回路内の多層配線に応じて、層間絶縁膜の領域に任意の金属配線パターンである下層配線４１が形成される。下層配線４１は、図示しないが周囲に窒化タンタル、窒化タングステン、窒化膜系等のバリアメタルまたはバリア材の形成を含む銅などの埋め込み金属配線である。次に、この下層配線４１上を覆う第１層間絶縁膜４０１を形成する。第１層間絶縁膜４０１はＴＥＯＳ（テトラエトキシシラン）等、シリコン酸化膜のような通常の無機膜とし、例えばＣＶＤ（化学気相成長）法やプラズマＣＶＤ法により形成する。
次に、図５（ｂ）に示すように、次層の形成予定である上層配線層（４２）がこの下層配線４１上に重なる第１層間絶縁膜４０１の領域と、下層配線４１相互隣接間の第１層間絶縁膜４０１の一部領域を予めリソグラフィ技術により選択的に除去する。基本的には時間制御でエッチング除去する。除去領域の精度誤差は、図示しないが下層配線４１周囲のバリアメタルまたはバリア材で許容できる範囲とする。
次に、図５（ｃ）に示すように、第１層間絶縁膜４０１よりも低誘電率の第２層間絶縁膜４０２を形成する。第２層間絶縁膜４０２は塗布法その他の方法などを用いて形成するＬｏｗ−ｋ 膜である。例えば、塗布法による有機系低誘電率膜（シロキサン系、有機ポリマー（Ｓｉ−Ｏ基なし）、または多孔質材料）の形成が考えられる。あるいは、塗布法による無機系低誘電率膜（Ｓｉ−Ｏ基を有するシロキサン系、または多孔質材料）の形成、さらには、ＣＶＤ法によるＳｉＯＦ系の膜などの形成が考えられる。その後、ＣＭＰ技術を経て平坦化する。これにより、必要領域のみにＬｏｗ−ｋ 膜が残留し、第１層間絶縁膜４０１及び第２層間絶縁膜４０２からなる層間絶縁膜４０が構成される。
次に、図５（ｄ）に示すように、リソグラフィ工程を経て、層間絶縁膜４０に対して所定の配線溝５１を形成する。さらに、第２層間絶縁膜４０２を介する下層配線１１との必要なビアホール５２を形成する。ビアホール５２の形成時はビアホール５２以外の領域を図示しないレジストで覆い、ビアホール５２のエッチング形成後、レジストを除去する。
【００３１】
その後は、ビアホール５２及び配線溝５１に対し、図示しないバリアメタルまたはバリア材の被覆、メッキ用シード層の形成を経て銅配線部材を形成する。その後、ＣＭＰ法により平坦化して必要領域のみ残す。これにより、デュアルダマシン配線構造を実現する。このような工程を経ることにより、前記図４で示す構成となる。すなわち、層間の絶縁膜４０のうち、下層配線４１と上層配線４２の重なり合う領域の層間及び隣接する同一の配線層間の一部領域では第２層間絶縁膜４０２が配され、その他の領域は第１層間絶縁膜４０１で占められている。
【００３２】
図６（ａ）〜（ｄ）は、それぞれ本発明の第６実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図であり、上記図４の構成を実現する。図４中と同様の箇所には同一の符号を付して説明する。
図６（ａ）に示すように、半導体集積回路内の多層配線に応じて、層間絶縁膜の領域上に任意の金属配線パターンである下層配線４１が形成される。下層配線４１は、前記第５実施形態と同様に、周囲にバリアメタルまたはバリア材（図示せず）の形成を含む銅などの埋め込み金属配線である。次に、この下層配線４１上を覆う第２層間絶縁膜４０２を形成する。第２層間絶縁膜４０２は前記第５実施形態と同様のＬｏｗ−ｋ 膜であり、例えば有機系、無機系、多孔質のＬｏｗ−ｋ 膜いずれかを形成する。
次に、図６（ｂ）に示すように、次層の形成予定である上層配線層（４２）がこの下層配線４１上に重なる第２層間絶縁膜４０２の領域と、下層配線４１相互隣接間の第２層間絶縁膜４０１の一部領域を予めリソグラフィ技術により選択的に残し、それ以外を除去する。基本的には時間制御でエッチング除去する。除去領域の精度誤差は、図示しないが下層配線４１周囲のバリアメタルまたはバリア材で許容できる範囲とする。
次に、図６（ｃ）に示すように、第２層間絶縁膜４０２よりも低吸湿性で物理的膜強度の優れた第１層間絶縁膜４０１を形成する。第１層間絶縁膜４０１はシリコン酸化膜のような通常の無機膜とし、例えばＣＶＤ（化学気相成長）法やプラズマＣＶＤ法により形成する。その後、ＣＭＰ技術を経て平坦化する。これにより、必要領域のみにＬｏｗ−ｋ 膜が残留し、第１層間絶縁膜４０１及び第２層間絶縁膜４０２からなる層間絶縁膜４０が構成される。
次に、図６（ｄ）に示すように、リソグラフィ工程を経て、層間絶縁膜４０に対して所定の配線溝６１を形成する。さらに、第２層間絶縁膜４０２を介する下層配線１１との必要なビアホール６２を形成する。ビアホール６２の形成時はビアホール６２以外の領域を図示しないレジストで覆い、ビアホール６２のエッチング形成後、レジストを除去する。
【００３３】
その後は、ビアホール６２及び配線溝６１に対し、図示しないバリアメタルまたはバリア材の被覆、メッキ用シード層の形成を経て銅配線部材を形成する。その後、ＣＭＰ法により平坦化して必要領域のみ残す。これにより、デュアルダマシン配線構造を実現する。このような工程を経ることにより、前記図４で示す構成となる。すなわち、層間の絶縁膜４０のうち、下層配線４１と上層配線４２の重なり合う領域の層間及び隣接する同一の配線層間の一部領域では第２層間絶縁膜４０２が配され、その他の領域は第１層間絶縁膜４０１で占められている。
【００３４】
上記第５、第６実施形態ぞれそれに係る半導体装置の製造方法によれば、低誘電率の第２層間絶縁膜４０２を必要領域に限定的に形成するために、第１層間絶縁膜４０１または第２層間絶縁膜４０２いずれか一方を前もって形成する。その後、第２層間絶縁膜４０２または第１層間絶縁膜４０１を残りの必要領域に設ける。これら第１層間絶縁膜４０１、第２層間絶縁膜４０２の形成にはＣＭＰ等の平坦化工程を経ることによって、リソグラフィ工程の精度はいっそう向上する。
【００３５】
また、配線溝５１，６１、ビアホール５２，６２を形成する技術として、ダブルハードマスクを使用する方法もある（図示せず）。これは、層間絶縁膜上にビアホール用のマスク層と配線溝用のマスク層をそれぞれリソグラフィ技術を用いてパターニングする。このマスク２層の異なるエッチング選択比を利用してビアホール及び配線溝を自己整合的に形成する。
【００３６】
なお、前記第１実施形態の構成において、前記第４実施形態に示す、隣接する同一の配線層間の一部領域への低誘電率の第２層間絶縁膜を設けるようにしてもよい。
図７は、本発明の第７実施形態に係る半導体装置の要部を示す断面図である。図１中と同様の箇所には同一の符号を付して説明は省略する。
【００３７】
また、前記第４実施形態の構成において、前記第１実施形態に示す、上下配線層で重なり合う領域の層間絶縁膜だけ低誘電率の第２層間絶縁膜を設けるようにしてもよい。
図８は、本発明の第８実施形態に係る半導体装置の要部を示す断面図である。図４中と同様の箇所には同一の符号を付して説明は省略する。
【００３８】
以上、各実施形態及びその方法によれば、低誘電率の層間絶縁膜を配する領域を、配線層間の狭い、配線容量が大きくなる領域に限定する。その他の層間絶縁膜領域は低誘電率では劣るが低吸湿性や物理的強度に優れた層間絶縁膜で構成する。これにより、低誘電率の層間絶縁膜を設けた特長を活かしつつ、吸湿性や強度的な短所を顕在化させない。この結果、集積回路を構成する微細な多層配線で、配線容量の増大を抑えると共に、より低吸湿で高い強度が得られる層間絶縁膜を有する高信頼性の半導体装置及びその製造方法を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態に係る半導体装置の要部を示す断面図。
【図２】（ａ）〜（ｃ）は、それぞれ本発明の第２実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図。
【図３】（ａ）〜（ｃ）は、それぞれ本発明の第３実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図。
【図４】本発明の第４実施形態に係る半導体装置の要部を示す断面図。
【図５】（ａ）〜（ｄ）は、それぞれ本発明の第５実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図。
【図６】（ａ）〜（ｄ）は、それぞれ本発明の第６実施形態に係る半導体装置の製造方法の要部を工程順に示す断面図。
【図７】本発明の第７実施形態に係る半導体装置の要部を示す断面図。
【図８】本発明の第８実施形態に係る半導体装置の要部を示す断面図。
【符号の説明】
１０，４０…層間の絶縁膜、１０１，４０１…第１層間絶縁膜、１０２，４０２…第２層間絶縁膜、１１，４１…下層配線、１２，４２…上層配線、２１，５２，６２…ビアホール、２２…プラグ金属、４３…接続部、５１，６１…配線溝。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer wiring structure of a semiconductor device, and more particularly to a semiconductor device using a low dielectric constant film as an interlayer insulating film and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor integrated circuit device, high integration, low voltage power supply, and high speed operation are required. Therefore, in addition to using low-resistance wiring materials, further low-dielectric-constant films, such as silicon oxide films, have been used as insulating films between wiring layers, instead of ordinary inorganic films. Use is made of an organic low dielectric constant film, an inorganic low dielectric constant film, a so-called organic or inorganic Low-k film, or a porous Low-k film having many holes introduced therein. Thus, the capacity of the wiring is reduced, and the effect of the wiring delay (RC delay) is suppressed so that the high-speed operation is not hindered.
[0003]
For example, an arbitrary wiring layer forming a semiconductor integrated circuit is formed. On this wiring layer, a Low-k film is formed as an interlayer insulating film by a coating method or the like. Openings are selectively formed on the interlayer insulating film through a lithography process. As a result, a via hole region where a predetermined wiring layer is exposed is formed. A groove serving as a wiring region may be formed together with the via hole region. Thereafter, a barrier metal material is coated on the via hole region by a sputtering method.
[0004]
Next, a wiring material is embedded in the via hole region. For example, a wiring material such as tungsten or aluminum is filled by a sputtering method. Alternatively, in the case of copper wiring, sputtering of a copper seed layer and deposition of copper by an electrolytic plating method are typical. In the case of a copper wiring, a copper wiring material is deposited on a region including a groove (wiring groove) serving as a contact region and a wiring region. After that, by a chemical mechanical polishing (CMP) technique, processing is performed so that only a necessary wiring portion is embedded with a wiring material. That is, it is a tungsten plug, an aluminum plug, a copper plug, or a copper dual damascene wiring. After that, the next wiring layer is patterned on the plug material, and a Low-k film is formed again as an interlayer insulating film. On the dual damascene wiring, a Low-k film is formed again as an interlayer insulating film.
[0005]
[Problems to be solved by the invention]
The Low-k material has lower physical strength than a silicon oxide film conventionally used as an interlayer insulating film. In addition, the hygroscopicity is high, and as the multilayer wiring circuit becomes finer, its reliability may be reduced. Although the wiring member is formed in such a form that its periphery is protected by a barrier material, since the Low-k film is provided as an interlayer insulating film on the entire surface, the wiring member is easily affected by a reduction in strength and corrosion.
[0006]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has an interlayer insulating film capable of suppressing an increase in wiring capacitance and obtaining high strength with lower moisture absorption, in a fine multilayer wiring constituting an integrated circuit. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
A semiconductor device according to the present invention is a semiconductor device in which a predetermined metal wiring member is arranged for an integrated circuit to form a multilayer wiring, and a multilayer wiring is provided between any adjacent lower layer wiring and an upper layer wiring separating the upper wiring. As an insulating film, a first interlayer insulating film and at least a second interlayer insulating film having a lower dielectric constant than the first interlayer insulating film are provided, and an interlayer insulating film between the interlayers in a region where the lower wiring and the upper wiring overlap. Is characterized in that the second interlayer insulating film is provided, and other regions are occupied by the first interlayer insulating film.
[0008]
Further, a semiconductor device according to the present invention is a semiconductor device in which a predetermined metal wiring member is arranged for an integrated circuit to form a multilayer wiring, and separates an adjacent lower layer wiring and an upper layer wiring with respect to the multilayer wiring. A first interlayer insulating film and at least a second interlayer insulating film having a dielectric constant lower than that of the first interlayer insulating film as an interlayer insulating film, and a region of the interlayer insulating film where the lower wiring and the upper wiring overlap each other; The second interlayer insulating film is arranged in a portion of the first interlayer insulating film and in a partial region between the same wiring layers adjacent to each other, and the other region is occupied by the first interlayer insulating film.
[0009]
According to each of the above-described semiconductor devices according to the present invention, the region where the second interlayer insulating film having a low dielectric constant is provided is limited to a region where a narrow wiring capacitance between wiring layers is large. The other interlayer insulating film region is formed of the first interlayer insulating film, and does not make the moisture absorbing property and strength disadvantages obvious while taking advantage of the feature of providing the low dielectric constant interlayer insulating film.
It should be noted that the first interlayer insulating film of each of the present invention is characterized in that it has lower hygroscopicity and physical strength than the second interlayer insulating film.
[0010]
In a more preferable semiconductor device according to the present invention, the first interlayer insulating film is any one selected from an inorganic low dielectric constant film, an organic low dielectric constant film, and a porous low dielectric constant film in which holes are introduced in the film. It is characterized by being composed of such a film.
Further, in a more preferable semiconductor device according to the present invention, the first interlayer insulating film is an inorganic film type, and the first interlayer insulating film is an organic low dielectric constant film, an organic low dielectric constant film, and pores in the film. Characterized in that it is composed of any film selected from porous low-dielectric-constant films into which is introduced.
[0011]
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a circuit wiring is formed including a predetermined metal wiring member, wherein the first wiring layer is patterned according to a multilayer wiring layer formation schedule. A step of forming a first interlayer insulating film including the upper portion, and a step of forming the first interlayer insulating film in which at least a second wiring layer of a next layer formed according to the formation schedule of the multilayer wiring layer overlaps the first wiring layer. Selectively removing a region; forming a second interlayer insulating film having a dielectric constant lower than at least the first interlayer insulating film in a removed region of the first interlayer insulating film; Patterning the predetermined second wiring layer on the upper and second interlayer insulating films.
[0012]
Furthermore, a more preferable method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which circuit wiring is formed including a predetermined metal wiring member, and wherein an arbitrary pattern is formed in accordance with a multilayer wiring layer formation schedule. Forming a first interlayer insulating film including on the first wiring layer; and forming the first interlayer insulating film on the first wiring layer, wherein at least a second wiring layer of the next layer formed according to the schedule for forming the multilayer wiring layer overlaps the first wiring layer. Selectively removing a predetermined region of the first interlayer insulating film adjacent to the region of the interlayer insulating film and the pattern of the first wiring layer; Forming a second interlayer insulating film having a dielectric constant lower than that of the first interlayer insulating film; and patterning a predetermined second wiring layer on the first interlayer insulating film and the second interlayer insulating film. It is characterized by having.
[0013]
According to the method of manufacturing a semiconductor device according to the present invention, the first interlayer insulating film, which constitutes most of the first interlayer insulating film, is formed in advance in order to form the low dielectric constant second interlayer insulating film only in a necessary region. After the formation, it undergoes a step of selectively removing. After that, a second interlayer insulating film is provided in the removal region.
It should be noted that the first interlayer insulating film of each of the present invention is characterized by using a film having lower hygroscopicity and physical strength than the second interlayer insulating film.
[0014]
Further, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a circuit wiring is formed including a predetermined metal wiring member, and wherein an arbitrary first pattern patterned according to a multilayer wiring layer formation schedule. Forming a first interlayer insulating film having a lower dielectric constant than a second interlayer insulating film to be formed later on the wiring layer, and a second wiring layer of a next layer formed at least according to the schedule for forming the multilayer wiring layer Selectively removing a region of the first interlayer insulating film that overlaps with the first wiring layer and removing the other, and removing moisture in the removed region of the first interlayer insulating film at least lower than that of the first interlayer insulating film. Forming a second interlayer insulating film having excellent physical film strength and patterning the predetermined second wiring layer on the first interlayer insulating film and the second interlayer insulating film. It is characterized by having.
[0015]
Further, a more preferred method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which circuit wiring is formed including a predetermined metal wiring member, and wherein an arbitrary first pattern is formed according to a multilayer wiring layer formation schedule. A step of forming a first interlayer insulating film having a lower dielectric constant than a second interlayer insulating film to be formed later on one wiring layer, and a second wiring of a next layer formed at least in accordance with the schedule for forming the multilayer wiring layer A region of the first interlayer insulating film where a layer overlaps the first wiring layer and a part of the predetermined first interlayer insulating film adjacent to the pattern of the first wiring layer are selectively left and others are removed. Forming a second interlayer insulating film having lower hygroscopicity and excellent physical strength than at least the first interlayer insulating film in a region where the first interlayer insulating film is removed; And a predetermined time on the second interlayer insulating film. A step of patterning the second wiring layer, characterized by comprising a.
[0016]
According to each of the above-described methods for manufacturing a semiconductor device according to the present invention, the second dielectric film having a low dielectric constant that is more limitedly utilized as compared with the second interlayer insulating film as the interlayer insulating film having low moisture absorption and excellent physical strength. One interlayer insulating film is formed first. For this reason, a removal step for selectively leaving a necessary region in the first interlayer insulating film is performed in advance. After that, a second interlayer insulating film is provided.
[0017]
In the method for manufacturing a semiconductor device according to the present invention, the first wiring layer or the second wiring layer may be formed by a plug wiring having a damascene structure, or may be formed into a hole in a lower conductive region. And a wiring forming step in which a dual damascene structure is formed along with the formation of wiring grooves. It contributes to the realization of stable integrated circuit wiring according to the miniaturization of elements.
[0018]
In the method of manufacturing a semiconductor device according to the present invention, at least one of the first wiring layer, the first interlayer insulating film, the second interlayer insulating film, and the second wiring layer is formed. It is characterized by going through a planarization step by chemical mechanical polishing. It contributes to the realization of stable integrated circuit wiring according to the miniaturization of elements.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a sectional view showing a main part of the semiconductor device according to the first embodiment of the present invention. 1 shows a multilayer wiring in a semiconductor integrated circuit formed on a semiconductor substrate. A lower wiring 11 and an upper wiring 12 which are arbitrary metal wiring patterns are formed in an insulating film 10 (101, 102) between layers in the multilayer wiring. The lower wiring 11 and the upper wiring 12 are connected to each other by a plug metal 22 in a necessary area. The interlayer insulating film 10 separating the wirings 11 and 12 comprises a first interlayer insulating film 101 and at least a second interlayer insulating film 102 having a dielectric constant lower than that of the first interlayer insulating film 101. Of the insulating films 10 between these layers, a second interlayer insulating film 102 is provided between layers where the lower wiring 11 and the upper wiring 12 overlap, and the other region is occupied by the first interlayer insulating film 101.
[0020]
The second interlayer insulating film 102 having a low dielectric constant is a so-called Low-k film having a relative dielectric constant of k and k <3.0. The Low-k film is of an organic type or an inorganic type, and it is also conceivable to use a porous Low-k film in which many holes are introduced in the film. In addition, the first interlayer insulating film 101 is a normal inorganic film system such as a silicon oxide film, and has lower hygroscopicity and higher physical strength than the second interlayer insulating film 102 which is a Low-k film. Further, it has lower hygroscopicity than the Low-k film.
[0021]
According to the configuration of the above-described embodiment, in the interlayer insulating film 10, the area where the second interlayer insulating film 102 having a low dielectric constant is arranged is limited to the area where the wiring capacity between wiring layers is small and the wiring capacity is large. The other region is occupied by the first interlayer insulating film 101 having excellent strength and low hygroscopicity. This makes it possible to make use of the characteristics of providing the interlayer insulating film having a low dielectric constant and not to make the disadvantages of hygroscopicity and strength apparent. That is, the wiring capacitance is reduced, the operation speed is increased, and low hygroscopicity and high strength are obtained.
[0022]
FIGS. 2A to 2C are cross-sectional views showing a main part of a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps, and realize the configuration of FIG. The same parts as those in FIG. 1 are described with the same reference numerals.
As shown in FIG. 2A, a lower wiring 11 which is an arbitrary metal wiring pattern is formed on the region of the interlayer insulating film according to the multilayer wiring in the semiconductor integrated circuit. The lower wiring 11 is a metal wiring such as an aluminum alloy (not shown) including a barrier metal such as a titanium / titanium nitride laminate formed around the lower wiring 11. Next, a first interlayer insulating film 101 sufficiently covering the lower wiring 11 is formed. The first interlayer insulating film 101 is a normal inorganic film such as a silicon oxide film such as TEOS (tetraethoxysilane), and is formed by, for example, a CVD (chemical vapor deposition) method or a plasma CVD method.
Next, as shown in FIG. 2B, the first interlayer insulating film 101 is planarized by using a CMP (chemical mechanical polishing) method or an etch-back method. After that, the region of the first interlayer insulating film 101 where the upper wiring layer (12) on which the next layer is to be formed overlaps the lower wiring line 11 is selectively removed in advance by lithography. Basically, etching is removed by time control. Although not shown, a member having a selectivity with respect to the first interlayer insulating film 101 may be provided on the side wall of the lower wiring 11 in advance to allow a precision error in the removed region. Next, as shown in FIG. 2C, a second interlayer insulating film 102 having a lower dielectric constant than the first interlayer insulating film 101 is formed. The second interlayer insulating film 102 is a low-k film formed using a coating method or another method. For example, formation of an organic low dielectric constant film (siloxane system, organic polymer (without Si—O group), or porous material) by a coating method can be considered. Alternatively, formation of an inorganic low-dielectric-constant film (a siloxane-based material having a Si—O group or a porous material) by a coating method, and further, formation of a SiOF-based film by a CVD method, or the like can be considered. After that, it is planarized through a CMP technique. As a result, the Low-k film remains only in the necessary region, and the interlayer insulating film 10 including the first interlayer insulating film 101 and the second interlayer insulating film 102 is formed. Next, via a lithography process, a necessary via hole 21 with the lower wiring 11 via the second interlayer insulating film 102 is formed. Next, a plug metal 22 filling the via hole is buried and formed, and flattened to leave only a necessary region.
[0023]
After that, the upper wiring 12 is formed on the interlayer insulating film 10 by patterning. Each of the plug metal and the upper wiring 12 includes formation of a barrier metal (or barrier material) not shown. Through these steps, the configuration shown in FIG. 1 is obtained. That is, in the interlayer insulating film 10, the second interlayer insulating film 102 is disposed between the regions where the lower wiring 11 and the upper wiring 12 overlap, and the other region is occupied by the first interlayer insulating film 101.
[0024]
FIGS. 3A to 3C are cross-sectional views showing a main part of a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps, and realize the configuration of FIG. The same parts as those in FIG. 1 are described with the same reference numerals.
As shown in FIG. 3A, a lower wiring 11 which is an arbitrary metal wiring pattern is formed on a region of an interlayer insulating film according to a multilayer wiring in a semiconductor integrated circuit. The lower layer wiring 11 is a metal wiring of an aluminum alloy or the like including the formation of a barrier metal (not shown) as in the second embodiment. Next, a second interlayer insulating film 102 that sufficiently covers the lower wiring 11 is formed. The second interlayer insulating film 102 is a Low-k film similar to that of the second embodiment, and forms, for example, any of an organic, inorganic, or porous Low-k film.
Next, as shown in FIG. 3B, the second interlayer insulating film 102 is planarized by using a CMP (chemical mechanical polishing) method or an etch back method. After that, a region of the second interlayer insulating film 102 where the upper wiring layer (12) to be formed with the next layer overlaps the lower wiring line 11 is selectively left in advance by lithography, and the other portions are removed. Basically, etching is removed by time control. Although not shown, a member having a selectivity with respect to the second interlayer insulating film 102 may be provided in advance on the side wall of the lower wiring 11 in order to allow an accuracy error in the removed region.
Next, as shown in FIG. 3C, a first interlayer insulating film 101 having lower hygroscopicity and excellent physical film strength than the second interlayer insulating film 102 is formed. The first interlayer insulating film 101 is a normal inorganic film such as a silicon oxide film, and is formed by, for example, a CVD (chemical vapor deposition) method or a plasma CVD method. After that, it is planarized through a CMP technique. As a result, the Low-k film remains only in the necessary region, and the interlayer insulating film 10 including the first interlayer insulating film 101 and the second interlayer insulating film 102 is formed. Next, via a lithography process, a necessary via hole 21 with the lower wiring 11 via the second interlayer insulating film 102 is formed. Next, a plug metal 22 filling the via hole is buried and formed, and flattened to leave only a necessary region.
[0025]
After that, the upper wiring 12 is formed on the interlayer insulating film 10 by patterning. Each of the plug metal and the upper wiring 12 includes formation of a barrier metal (or barrier material) not shown. Through these steps, the configuration shown in FIG. 1 is obtained. That is, in the interlayer insulating film 10, the second interlayer insulating film 102 is disposed between the regions where the lower wiring 11 and the upper wiring 12 overlap, and the other region is occupied by the first interlayer insulating film 101.
[0026]
According to the method of manufacturing a semiconductor device according to each of the second and third embodiments, the first interlayer insulating film 101 or the first interlayer insulating film 101 is formed in order to form the low dielectric constant second interlayer insulating film 102 only in a necessary region. One of the second interlayer insulating films 102 is formed in advance. After that, the second interlayer insulating film 102 or the first interlayer insulating film 101 is provided in the remaining necessary region. The formation of the first interlayer insulating film 101 and the second interlayer insulating film 102 goes through a planarization process such as CMP, so that the accuracy of the lithography process is further improved.
[0027]
FIG. 4 is a sectional view showing a main part of a semiconductor device according to a fourth embodiment of the present invention. 1 shows a multilayer wiring in a semiconductor integrated circuit formed on a semiconductor substrate. A lower wiring 41 and an upper wiring 42, which are arbitrary metal wiring patterns, are formed with an interlayer insulating film 40 (401, 402) between the multilayer wirings. The lower wiring 41 and the upper wiring 42 have a connection portion 43 in a necessary area. The interlayer insulating film 40 separating the wirings 41 and 42 includes a first interlayer insulating film 401 and at least a second interlayer insulating film 402 having a lower dielectric constant than the first interlayer insulating film 401. Among the insulating films 40 between these layers, a second interlayer insulating film 402 is provided in an interlayer of a region where the lower wiring 41 and the upper wiring 42 overlap and in a partial region between the same wiring layers adjacent to each other. Occupied by the insulating film 401.
[0028]
The low dielectric constant second interlayer insulating film 402 refers to a so-called Low-k film as in the first embodiment. Various Low-k films such as organic, inorganic, and porous films may be used. The first interlayer insulating film 401 is a normal inorganic film such as a silicon oxide film, and has higher physical strength than the second interlayer insulating film 402 which is a Low-k film. Further, it has lower hygroscopicity than the Low-k film.
[0029]
According to the configuration of the above-described embodiment, with respect to the interlayer insulating film 40, the region where the second interlayer insulating film 402 having a low dielectric constant is disposed is limited to the region between the upper and lower wiring layers and also to the narrow region between the same wiring layers and where the wiring capacitance becomes large. I do. The other area is occupied by the first interlayer insulating film 401 having excellent strength and low hygroscopicity. This makes it possible to make use of the characteristics of providing the interlayer insulating film having a low dielectric constant and not to make the disadvantages of hygroscopicity and strength apparent. That is, the wiring capacitance is reduced, the operation speed is increased, and low hygroscopicity and high strength are obtained.
[0030]
FIGS. 5A to 5D are cross-sectional views showing a main part of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention in the order of steps, and realize the configuration shown in FIG. The same parts as those in FIG. 4 are described with the same reference numerals.
As shown in FIG. 5A, a lower wiring 41 which is an arbitrary metal wiring pattern is formed in the region of the interlayer insulating film according to the multilayer wiring in the semiconductor integrated circuit. The lower wiring 41 is a buried metal wiring such as tantalum nitride, tungsten nitride, or a barrier metal such as a nitride film-based material or a copper containing a barrier material, although not shown. Next, a first interlayer insulating film 401 covering the lower wiring 41 is formed. The first interlayer insulating film 401 is a normal inorganic film such as a silicon oxide film such as TEOS (tetraethoxysilane), and is formed by, for example, a CVD (chemical vapor deposition) method or a plasma CVD method.
Next, as shown in FIG. 5B, a region of the first interlayer insulating film 401 where the upper wiring layer (42) on which the next layer is to be formed overlaps the lower wiring 41, and a region between the lower wiring 41 adjacent to each other. Of the first interlayer insulating film 401 is selectively removed by lithography in advance. Basically, etching is removed by time control. Although not shown, the accuracy error of the removal region is set within a range allowable by the barrier metal or the barrier material around the lower wiring 41.
Next, as shown in FIG. 5C, a second interlayer insulating film 402 having a lower dielectric constant than the first interlayer insulating film 401 is formed. The second interlayer insulating film 402 is a Low-k film formed using a coating method or another method. For example, formation of an organic low dielectric constant film (siloxane system, organic polymer (without Si—O group), or porous material) by a coating method can be considered. Alternatively, formation of an inorganic low-dielectric-constant film (a siloxane-based material having a Si—O group or a porous material) by a coating method, and further, formation of a SiOF-based film by a CVD method, or the like can be considered. After that, it is planarized through a CMP technique. As a result, the Low-k film remains only in the necessary region, and the interlayer insulating film 40 including the first interlayer insulating film 401 and the second interlayer insulating film 402 is formed.
Next, as shown in FIG. 5D, a predetermined wiring groove 51 is formed in the interlayer insulating film 40 through a lithography process. Further, a necessary via hole 52 with the lower wiring 11 via the second interlayer insulating film 402 is formed. When the via hole 52 is formed, a region other than the via hole 52 is covered with a resist (not shown), and after the via hole 52 is formed by etching, the resist is removed.
[0031]
Thereafter, a copper wiring member is formed on the via hole 52 and the wiring groove 51 through coating of a barrier metal or a barrier material (not shown) and formation of a plating seed layer. After that, it is flattened by the CMP method to leave only necessary regions. Thus, a dual damascene wiring structure is realized. Through these steps, the configuration shown in FIG. 4 is obtained. That is, in the interlayer insulating film 40, the second interlayer insulating film 402 is provided in a region between the lower wiring 41 and the upper wiring 42 where the lower wiring 41 and the upper wiring 42 overlap and in a partial region between the same wiring layers adjacent to each other. Occupied by the interlayer insulating film 401.
[0032]
6 (a) to 6 (d) are cross-sectional views showing a main part of a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention in the order of steps, and realize the configuration of FIG. The same parts as those in FIG. 4 are described with the same reference numerals.
As shown in FIG. 6A, a lower wiring 41 which is an arbitrary metal wiring pattern is formed on the region of the interlayer insulating film in accordance with the multilayer wiring in the semiconductor integrated circuit. The lower wiring 41 is a buried metal wiring such as copper including a barrier metal or a barrier material (not shown) formed around the lower wiring 41 as in the fifth embodiment. Next, a second interlayer insulating film 402 covering the lower wiring 41 is formed. The second interlayer insulating film 402 is a Low-k film similar to that of the fifth embodiment, and for example, forms any of an organic, inorganic, and porous Low-k film.
Next, as shown in FIG. 6B, the upper wiring layer (42) where the next layer is to be formed is overlapped on the lower wiring 41 by the region of the second interlayer insulating film 402 and the lower wiring 41 Part of the second interlayer insulating film 401 is selectively left in advance by lithography, and the other part is removed. Basically, etching is removed by time control. Although not shown, the accuracy error of the removal region is set within a range allowable by the barrier metal or the barrier material around the lower wiring 41.
Next, as shown in FIG. 6C, a first interlayer insulating film 401 having lower hygroscopicity and excellent physical film strength than the second interlayer insulating film 402 is formed. The first interlayer insulating film 401 is a normal inorganic film such as a silicon oxide film, and is formed by, for example, a CVD (chemical vapor deposition) method or a plasma CVD method. After that, it is planarized through a CMP technique. As a result, the Low-k film remains only in the necessary region, and the interlayer insulating film 40 including the first interlayer insulating film 401 and the second interlayer insulating film 402 is formed.
Next, as shown in FIG. 6D, a predetermined wiring groove 61 is formed in the interlayer insulating film 40 through a lithography process. Further, a necessary via hole 62 with the lower wiring 11 via the second interlayer insulating film 402 is formed. When the via hole 62 is formed, a region other than the via hole 62 is covered with a resist (not shown), and after the via hole 62 is formed by etching, the resist is removed.
[0033]
Thereafter, a copper wiring member is formed in the via hole 62 and the wiring groove 61 through coating of a barrier metal or a barrier material (not shown) and formation of a plating seed layer. After that, it is flattened by the CMP method to leave only necessary regions. Thus, a dual damascene wiring structure is realized. Through these steps, the configuration shown in FIG. 4 is obtained. That is, in the interlayer insulating film 40, the second interlayer insulating film 402 is provided in a region between the lower wiring 41 and the upper wiring 42 where the lower wiring 41 and the upper wiring 42 overlap and in a partial region between the same wiring layers adjacent to each other. Occupied by the interlayer insulating film 401.
[0034]
According to the method of manufacturing the semiconductor device according to each of the fifth and sixth embodiments, the first interlayer insulating film 401 or the first interlayer insulating film 401 is formed in order to form the low dielectric constant second interlayer insulating film 402 only in a necessary region. One of the second interlayer insulating films 402 is formed in advance. After that, the second interlayer insulating film 402 or the first interlayer insulating film 401 is provided in the remaining necessary area. The precision of the lithography process is further improved by forming the first interlayer insulating film 401 and the second interlayer insulating film 402 through a planarization process such as CMP.
[0035]
As a technique for forming the wiring grooves 51 and 61 and the via holes 52 and 62, there is a method using a double hard mask (not shown). In this method, a mask layer for a via hole and a mask layer for a wiring groove are respectively patterned on an interlayer insulating film by using a lithography technique. Via holes and wiring trenches are formed in a self-aligned manner by utilizing the different etching selectivity of the two mask layers.
[0036]
In the configuration of the first embodiment, a low-dielectric-constant second interlayer insulating film may be provided in a partial region between the same adjacent wiring layers as shown in the fourth embodiment.
FIG. 7 is a sectional view showing a main part of a semiconductor device according to a seventh embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
[0037]
Further, in the configuration of the fourth embodiment, the second interlayer insulating film having a low dielectric constant may be provided only in the interlayer insulating film in the region where the upper and lower wiring layers overlap as shown in the first embodiment.
FIG. 8 is a sectional view showing a main part of a semiconductor device according to an eighth embodiment of the present invention. The same parts as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.
[0038]
As described above, according to each of the embodiments and the method, the region where the low dielectric constant interlayer insulating film is disposed is limited to a region between wiring layers that is narrow and has a large wiring capacitance. Other interlayer insulating film regions are formed of interlayer insulating films which are inferior in low dielectric constant but excellent in low moisture absorption and physical strength. Thereby, while utilizing the feature of providing the interlayer insulating film having a low dielectric constant, the disadvantages of hygroscopicity and strength are not revealed. As a result, it is possible to provide a highly reliable semiconductor device having an interlayer insulating film capable of suppressing an increase in wiring capacitance and obtaining a higher strength with lower moisture absorption by fine multilayer wiring forming an integrated circuit and a method of manufacturing the same. Can be.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a main part of a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views illustrating a main part of a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.
FIGS. 3A to 3C are cross-sectional views illustrating a main part of a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.
FIG. 4 is a sectional view showing a main part of a semiconductor device according to a fourth embodiment of the present invention.
FIGS. 5A to 5D are cross-sectional views illustrating a main part of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention in the order of steps.
FIGS. 6A to 6D are cross-sectional views illustrating a main part of a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention in the order of steps.
FIG. 7 is a sectional view showing a main part of a semiconductor device according to a seventh embodiment of the present invention.
FIG. 8 is a sectional view showing a main part of a semiconductor device according to an eighth embodiment of the present invention.
[Explanation of symbols]
10, 40 ... interlayer insulating film, 101, 401 ... first interlayer insulating film, 102, 402 ... second interlayer insulating film, 11, 41 ... lower wiring, 12, 42 ... upper wiring, 21, 52, 62 ... via hole , 22 ... plug metal, 43 ... connection part, 51, 61 ... wiring groove.

Claims (12)

集積回路のため所定の金属配線部材を配して多層配線が構成される半導体装置であって、
前記多層配線に関し任意の隣接した下層配線と上層配線を隔てる層間の絶縁膜として、第１層間絶縁膜及び少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を具備し、
前記層間の絶縁膜のうち前記下層配線と上層配線の重なり合う領域の層間では前記第２層間絶縁膜が配され、その他の領域は前記第１層間絶縁膜で占められていることを特徴とする半導体装置。A semiconductor device in which multilayer wiring is configured by arranging predetermined metal wiring members for an integrated circuit,
A first interlayer insulating film and a second interlayer insulating film having a dielectric constant lower than at least the first interlayer insulating film as an interlayer insulating film separating any adjacent lower layer wiring and upper layer wiring with respect to the multilayer wiring;
A semiconductor, wherein the second interlayer insulating film is disposed between layers of the interlayer insulating film where the lower wiring and the upper wiring overlap, and the other region is occupied by the first interlayer insulating film. apparatus. 集積回路のため所定の金属配線部材を配して多層配線が構成される半導体装置であって、
前記多層配線に関し任意の隣接した下層配線と上層配線を隔てる層間の絶縁膜として、第１層間絶縁膜及び少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を具備し、
前記層間の絶縁膜のうち前記下層配線と上層配線の重なり合う領域の層間及び隣接する同一の配線層間の一部領域において前記第２層間絶縁膜が配され、その他の領域は前記第１層間絶縁膜で占められていることを特徴とする半導体装置。A semiconductor device in which multilayer wiring is configured by arranging predetermined metal wiring members for an integrated circuit,
A first interlayer insulating film and a second interlayer insulating film having a dielectric constant lower than at least the first interlayer insulating film as an interlayer insulating film separating any adjacent lower layer wiring and upper layer wiring with respect to the multilayer wiring;
In the interlayer insulating film, the second interlayer insulating film is disposed in an interlayer of a region where the lower wiring and the upper wiring overlap and in a partial region between adjacent wiring layers, and the other region is the first interlayer insulating film. A semiconductor device characterized by being occupied by. 前記第１層間絶縁膜は前記第２層間絶縁膜に比べて少なくとも低吸湿性及び物理的強度に優れていることを特徴とする請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the first interlayer insulating film has at least low hygroscopicity and excellent physical strength as compared with the second interlayer insulating film. 前記第１層間絶縁膜は無機系低誘電率膜、有機系低誘電率膜、膜中に空孔を導入した多孔質低誘電率膜から選択されるいずれかの膜で構成されることを特徴とする請求項１〜３いずれか一つに記載の半導体装置。The first interlayer insulating film is formed of any one of an inorganic low dielectric constant film, an organic low dielectric constant film, and a porous low dielectric constant film having holes introduced therein. The semiconductor device according to claim 1, wherein 前記第１層間絶縁膜は無機膜系で、前記第１層間絶縁膜は有機系低誘電率膜、有機系低誘電率膜、膜中に空孔を導入した多孔質低誘電率膜から選択されるいずれかの膜で構成されることを特徴とする請求項１〜３いずれか一つに記載の半導体装置。The first interlayer insulating film is an inorganic film type, and the first interlayer insulating film is selected from an organic low dielectric constant film, an organic low dielectric constant film, and a porous low dielectric constant film having holes introduced therein. The semiconductor device according to claim 1, wherein the semiconductor device is formed of any one of films. 所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、
多層配線層形成予定に応じパターニングされた任意の第１配線層上を含んで第１層間絶縁膜を形成する工程と、
少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域を選択的に除去する工程と、
前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を形成する工程と、
前記第１層間絶縁膜上及び第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、
を具備したことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which circuit wiring is configured to include a predetermined metal wiring member,
Forming a first interlayer insulating film including on an arbitrary first wiring layer patterned according to a multilayer wiring layer formation schedule;
Selectively removing at least a region of the first interlayer insulating film where a second wiring layer of a next layer formed according to the schedule for forming the multilayer wiring layer overlaps the first wiring layer;
Forming a second interlayer insulating film having a lower dielectric constant than at least the first interlayer insulating film in a removed region of the first interlayer insulating film;
Patterning a predetermined second wiring layer on the first interlayer insulating film and the second interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: 所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、
多層配線層形成予定に応じパターニングされた任意の第１配線層上を含んで第１層間絶縁膜を形成する工程と、
少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域及び前記第１配線層のパターンが隣り合う所定の前記第１層間絶縁膜の一部領域を選択的に除去する工程と、
前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低誘電率の第２層間絶縁膜を形成する工程と、
前記第１層間絶縁膜上及び第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、
を具備したことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which circuit wiring is configured to include a predetermined metal wiring member,
Forming a first interlayer insulating film including on an arbitrary first wiring layer patterned according to a multilayer wiring layer formation schedule;
At least a region of the first interlayer insulating film where a second wiring layer of a next layer formed according to the formation schedule of the multilayer wiring layer overlaps the first wiring layer and a pattern of the first wiring layer are adjacent to each other. Selectively removing a partial region of the first interlayer insulating film;
Forming a second interlayer insulating film having a lower dielectric constant than at least the first interlayer insulating film in a removed region of the first interlayer insulating film;
Patterning a predetermined second wiring layer on the first interlayer insulating film and the second interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: 前記第１層間絶縁膜は前記第２層間絶縁膜に比べて低吸湿性及び物理的強度に優れた膜を用いることを特徴とする請求項６または７記載の半導体装置の製造方法。8. The method for manufacturing a semiconductor device according to claim 6, wherein the first interlayer insulating film is a film having lower hygroscopicity and physical strength than the second interlayer insulating film. 所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、
多層配線層形成予定に応じパターニングされた任意の第１配線層上に、後から形成される第２層間絶縁膜より低誘電率の第１層間絶縁膜を形成する工程と、
少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域を選択的に残し他は除去する工程と、
前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低吸湿性で物理的膜強度の優れた第２層間絶縁膜を形成する工程と、
前記第１層間絶縁膜上及び前記第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、
を具備したことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which circuit wiring is configured to include a predetermined metal wiring member,
Forming a first interlayer insulating film having a lower dielectric constant than a second interlayer insulating film to be formed later on an arbitrary first wiring layer patterned according to a schedule for forming a multilayer wiring layer;
A step of selectively removing at least a region of the first interlayer insulating film where at least a second wiring layer formed next according to the formation schedule of the multilayer wiring layer overlaps the first wiring layer, and
Forming a second interlayer insulating film having a lower hygroscopicity and a higher physical film strength than at least the first interlayer insulating film in a region where the first interlayer insulating film is removed;
Patterning a predetermined second wiring layer on the first interlayer insulating film and the second interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: 所定の金属配線部材を含んで回路配線が構成される半導体装置の製造方法であって、
多層配線層形成予定に応じパターニングされた任意の第１配線層上に、後から形成される第２層間絶縁膜より低誘電率の第１層間絶縁膜を形成する工程と、
少なくとも前記多層配線層形成予定に応じ形成される次層の第２配線層が前記第１配線層上に重なる前記第１層間絶縁膜の領域及び前記第１配線層のパターンが隣り合う所定の前記第１層間絶縁膜の一部領域を選択的に残し他は除去する工程と、
前記第１層間絶縁膜の除去領域に少なくとも前記第１層間絶縁膜よりも低吸湿性で物理的強度の優れた第２層間絶縁膜を形成する工程と、
前記第１層間絶縁膜上及び前記第２層間絶縁膜上に所定の前記第２配線層をパターニングする工程と、
を具備したことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which circuit wiring is configured to include a predetermined metal wiring member,
Forming a first interlayer insulating film having a lower dielectric constant than a second interlayer insulating film to be formed later on an arbitrary first wiring layer patterned according to a schedule for forming a multilayer wiring layer;
At least a region of the first interlayer insulating film where a second wiring layer of a next layer formed according to the formation schedule of the multilayer wiring layer overlaps the first wiring layer and a pattern of the first wiring layer are adjacent to each other. Selectively removing a part of the first interlayer insulating film and removing the other region;
Forming at least a second interlayer insulating film having a lower hygroscopicity and a higher physical strength than the first interlayer insulating film in a removed region of the first interlayer insulating film;
Patterning a predetermined second wiring layer on the first interlayer insulating film and the second interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: 前記第１配線層または前記第２配線層は、ダマシン構造の形態がとられるプラグ配線形成、あるいは、それぞれ下層の導電領域へのホール形状の形成と共に配線溝の形成を伴なうデュアル・ダマシン構造の形態がとられる配線形成工程が含まれることを特徴とする請求項６〜１０いずれか一つに記載の半導体装置の製造方法。The first wiring layer or the second wiring layer is formed of a plug wiring in the form of a damascene structure, or a dual damascene structure including formation of a hole shape in a lower conductive region and formation of a wiring groove. 11. The method of manufacturing a semiconductor device according to claim 6, further comprising a wiring forming step taking the form of (b). 前記第１配線層、前記第１層間絶縁膜、前記第２層間絶縁膜、前記第２配線層のうちの少なくともいずれかの形成時において化学的機械的研磨による平坦化工程を経ることを特徴とする請求項６〜１１いずれか一つに記載の半導体装置の製造方法。A flattening step by chemical mechanical polishing is performed when forming at least one of the first wiring layer, the first interlayer insulating film, the second interlayer insulating film, and the second wiring layer. The method of manufacturing a semiconductor device according to claim 6.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US7732927B2 (en) 2006-11-24 2010-06-08 Fujitsu Limited Semiconductor device having a interlayer insulation film with low dielectric constant and high mechanical strength

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732927B2 (en) 2006-11-24 2010-06-08 Fujitsu Limited Semiconductor device having a interlayer insulation film with low dielectric constant and high mechanical strength

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