JP2004158575A - Package for semiconductor device and semiconductor device employing it - Google Patents

Package for semiconductor device and semiconductor device employing it Download PDF

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Publication number
JP2004158575A
JP2004158575A JP2002321749A JP2002321749A JP2004158575A JP 2004158575 A JP2004158575 A JP 2004158575A JP 2002321749 A JP2002321749 A JP 2002321749A JP 2002321749 A JP2002321749 A JP 2002321749A JP 2004158575 A JP2004158575 A JP 2004158575A
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input
semiconductor element
wiring conductor
base
pad
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JP2002321749A
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JP3847247B2 (en
Inventor
Tetsuo Hirakawa
哲生 平川
Shin Matsuda
伸 松田
Yoshinobu Sawa
義信 澤
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package for a semiconductor element in which transmission characteristics of electric signal are improved between I/O pads and first wiring conductors connecting an external electric circuit and a semiconductor element by preventing reflection of high frequency electric signals on the I/O pads effectively, and to provide a semiconductor device employing it. <P>SOLUTION: The package for a semiconductor element comprises a substrate 1 having a part 1a for mounting a semiconductor element 6, a plurality of ground wiring conductors 2b and first wiring conductors 2a formed on the substrate 1, ground pads 3b and I/O pads 3a formed on the substrate 1 and connected electrically with the ground wiring conductors 2b and first wiring conductors 2a, second wiring conductors 4 led out from the mounting part 1a of the substrate 1 to the upper surface or side face thereof, and a connector 5 consisting of conductive wires 5a and an insulating enclosure 5b wherein the wirs 5a are connected electrically with the second wiring conductors 4. The I/O pad 3a has a plane area not larger than 0.196 mm<SP>2</SP>and a dummy pad 3c having a plane area not smaller than two times that of the I/O pad 3a is formed on the lower surface of the substrate 1. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は高周波の電気信号を送受信する半導体素子を収納する半導体素子収納用パッケージ、およびその半導体素子収納用パッケージを用いて成る半導体装置に関するものである。
【０００２】
【従来の技術】
従来、電気信号を送受信する半導体素子を収容するための半導体素子収納用パッケージは、一般に、酸化アルミニウム質焼結体、ムライト質焼結体、窒化アルミニウム質焼結体等の電気絶縁材料から成り、上面に半導体素子の搭載部が形成された基体と、タングステン、モリブデン、マンガン等の金属材料から成り、基体の半導体素子搭載部から下面にかけて被着導出された複数の電気信号の入出力用およびグランド用の配線導体と、この配線導体と電気的に接続するようにして基体の下面に形成された複数個のグランド用パッドおよび入出力用パッドと、基体の搭載部より上面もしくは側面にかけて導出されている出入力用の配線導体と、導電性の線材と絶縁性の外囲体とから成り、線材の一端が出入力用配線導体に接続され、他端が外部に導出されているコネクターとにより構成されている。
【０００３】
かかる半導体素子収納用パッケージは、その搭載部に電気信号を送受信する半導体素子がＡｕ−Ｓｎろう材あるいは半田等の接合材を介して接着固定されるとともに、半導体素子の電極が入出力配線導体、グランド用配線導体および出入力配線導体にボンディングワイヤや接続用リボン、半田等の導電性接続材を介して接続され、その後、必要に応じて蓋体等で半導体素子を封止することによって半導体装置となる。
【０００４】
また前記半導体装置は基体の下面に形成されているグランド用パッドおよび入出力用パッドを外部電気回路基板の回路導体に半田バンプ等を介し接続させることによって内部に収容する半導体素子が外部電気回路に接続され、同時にコネクターに同軸ケーブル等を介し外部の通信装置等の外部機器を接続させることによって半導体素子と外部機器とが接続するようになっている。
【０００５】
なお、前記半導体装置に使用されている半導体素子は複数の電気信号を合成して一つの電気信号に変換する、或いは一つの電気信号を分離して複数の電気信号に変換する機能を有しており、外部電気回路から入出力用パッド及び第１配線導体を介して入力される５〜１０ＧＨｚの複数の電気信号は半導体素子で合成されて４０〜８０ＧＨｚの一つの電気信号となり、この４０〜８０ＧＨｚの電気信号は第２配線導体を介してコネクターに伝送されるとともにコネクターより外部の通信装置等の外部機器に伝送され、またコネクターを介して外部機器より伝送された４０〜８０ＧＨｚの電気信号は半導体素子で５〜１０ＧＨｚの複数の電気信号に変換され、各々の５〜１０ＧＨｚの電気信号は第１配線導体及び入出力用パッドを介して外部電気回路に伝送されることとなる。
【０００６】
また前記酸化アルミニウム質焼結体やムライト質焼結体等から成る基体はその線膨張係数が４×１０−６／℃〜７．５×１０−６／℃であるのに対し、外部電気回路基板は一般にガラスエポキシ樹脂材で形成されており、その線膨張係数は約１５×１０−６／℃程度であり、大きく相違することから外部電気回路基板の回路導体に入出力用パッドを半田バンプ等を介して接続した後、基体と外部電気回路基板に熱が作用すると基体と外部電気回路基板の熱膨張量の相違に起因して大きな応力が発生しこの応力によって入出力用パッドが基体より剥離したり、半田バンプに破断が発生して半導体素子と外部電気回路との間の接続が破られてしまう。そのためこの従来の半導体素子収納用パッケージ等は入出力用パッドを直径が１ｍｍ以上の円形形状（平面積が０．７８５ｍｍ２以上の円形形状）とし基体と入出力用パッドとの接合強度を強くするとともに外部電気回路基板の回路導体と入出力用パッドとを接続する半田バンプ等の量を多くし破断が発生しないようにしている。
【０００７】
【特許文献１】
特開２００２−１６４４６６号公報
【０００８】
【発明が解決しようとする課題】
しかしながら、この従来の半導体素子収納用パッケージおよび半導体装置においては、第１配線導体と外部電気回路基板の回路導体とを接続する入出力用パッドが直径１ｍｍ以上の円形形状（平面積で０．７８５ｍｍ２以上の円形形状）をなし、第１配線導体の外形寸法（直径が約０．３ｍｍ以上、平面積で約０．０７ｍｍ２以上の円形形状等）に比し約１０倍以上大きく、入出力用パッドのインピーダンスが第１配線導体や外部電気回路基板の回路導体に比べ低いものとなっている。そのためこの入出力用パッドを介して第１配線導体と外部電気回路基板の回路導体とを接続するとともに５〜１０ＧＨｚの電気信号を伝送させた場合、５〜１０ＧＨｚの電気信号は高周波信号であるためインピーダンスが低い入出力用パッドで反射等を起こし、伝送特性が大きく劣化してしまうという欠点を有していた。
【０００９】
本発明は上記欠点に鑑み案出されたもので、その目的は入出力用パッドでの高周波の電気信号の反射等を有効に防止し、外部電気回路と半導体素子とを接続する第１配線導体および入出力用パッドでの電気信号の伝送特性を改善した半導体素子収納用パッケージおよび半導体装置を提供することにある。
【００１０】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第１配線導体と、前記基体の下面に形成され、前記グランド配線導体および第１配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面もしくは側面にかけて導出されている第２配線導体と、導電性の線材と絶縁性の外囲体とから成り、線材が前記第２配線導体に電気的に接続されているコネクターとで形成され、前記入出力用パッドの平面積が０．１９６ｍｍ２以下であり、かつ前記基体の下面に前記入出力用パッドよりも２倍以上大きな平面積を有するダミーパッドが形成されていることを特徴とするものである。
【００１１】
また本発明の半導体装置は、上記構成の半導体素子収納用パッケージと４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子とから成り、前記パッケージの搭載部に半導体素子を搭載固定するとともに該半導体素子の各電極を第１配線導体および第２配線導体に電気的に接続したことを特徴とするものである。
【００１２】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、第１配線導体を外部電気回路基板の回路導体に接続する入出力用パッドの平面積を０．１９６ｍｍ２以下とし、入出力用パッドのインピーダンスを第１配線導体や外部電気回路基板の回路導体のインピーダンスに近似させたことから入出力用パッドを介して第１配線導体と外部電気回路基板の回路導体とを接続するとともに５〜１０ＧＨｚの高周波の電気信号を伝送させたとしても入出力用パッドで大きな反射等を起こすことはなく、伝送特性を優れたものとなすことができる。
【００１３】
また本発明の半導体素子収納用パッケージおよび半導体装置によれば、基体の下面、即ち、入出力用パッドが形成されている面に入出力用パッドよりも２倍以上大きな平面積を有するダミーパッドを設けたことから入出力用パッドを外部電気回路基板の回路導体に、ダミーパッドを外部電気回路基板の回路導体や予備に形成したパッドに半田バンプ等を介して接続させ、しかる後、基体と外部電気回路基板に熱が作用した場合、基体と外部電気回路基板との間に両者の線膨張係数の相違に起因する大きな熱応力が発生するものの基体と外部電気回路基板とは前記ダミーパッドによる接続によって強固に固定されているため入出力用パッドが基体より剥離したり半田バンプ等に破断が発生することはほとんどなく、これによって半導体素子と外部電気回路との接続の信頼性を極めて高いものとなすことができる。
【００１４】
【発明の実施の形態】
次に、本発明を添付図面に基づき詳細に説明する。
図１は本発明の半導体素子収納用パッケージの一実施礼を示し、１は基体、２ａは第１配線導体、２ｂはグランド配線導体、３ａは入出力用パッド、３ｂはグランド用パッド、４は第２配線導体、５はコネクターである。これら基体１、第１配線導体２ａ、グランド配線導体２ｂ、入出力用パッド３ａ、グランド用パッド３ｂ、第２配線導体４およびコネクター５により半導体素子６を収納するための半導体素子収納用パッケージ７が基本的に構成される。
【００１５】
前記基体１は酸化アルミニウム質焼結体、ムライト質焼結体、ガラスセラミックス、窒化アルミニウム質焼結体等の電気絶縁材料から成り、例えば、酸化アルミニウム質焼結体から成る場合、酸化アルミニウム、酸化ケイ素、酸化マグネシウム、酸化カルシウム等の原料粉末に適当な有機溶剤、溶媒、可塑剤、分散剤を添加混合して泥漿物を作り、この泥漿物を従来周知のドクターブレード法やカレンダーロール法等のシート成形法を採用しシート状に形成してセラミックグリーンシート（セラミック生シート）を得、しかる後、それらセラミックグリーンシートに適当な打ち抜き加工を施すとともにこれを必要に応じて複数枚積層し、約１６００℃の高温で焼成することによって製作される。
【００１６】
また前記基体１は、半導体素子の搭載部１ａから下面にかけて複数個の第１配線導体２ａおよびグランド用配線導体２ｂが形成されており、該各配線導体２ａ、２ｂは半導体素子の電気信号入出力用、接地用の各電極を、入出力用パッド３ａやグランド用パッド３ｂに接続するための導電路として作用し、搭載部１ａ側の一端には半導体素子６の電気信号入出力用、接地用の各電極が導電性接続材を介して電気的に接続される。
【００１７】
前記第１配線導体２ａおよびグランド用配線導体２ｂ、入出力用パッド３ａおよびグランド用パッド３ｂは、タングステン、モリブデン、マンガン等の金属材料から成り、例えばタングステンから成る場合であれば、タングステン粉末に有機溶剤を添加して成る金属ペーストを基体１となるセラミックグリーンシートの表面に所定パターンに印刷しておくことにより形成される。
【００１８】
この第１配線導体２ａおよびグランド用配線導体２ｂの基体１下面側の一端は、それぞれ対応する入出力用パッド３ａおよびグランド用パッド３ｂと電気的に接続しており、これらの入出力用パッド３ａ、グランド用パッド３ｂを外部電気回路の所定の信号用や接地用等の回路導体に接続することにより、半導体素子６の電気信号入出力用、接地用の各電極が外部電気回路と電気的に接続される。
【００１９】
また前記基体１は、半導体素子の搭載部１ａから上面や側面等にかけて第２配線導体４が形成されており、該第２配線導体４は半導体素子６の電極をコネクター５の線材５ａに接続するための導電路として作用し、搭載部１ａ側の一端には半導体素子６の電極が導電性接続材８を介して電気的に接続される。
【００２０】
前記第２配線導体４は、上述の第１配線導体２ａ等と同様に、タングステン、モリブデン等の金属材料から成り、例えばタングステンから成る場合であれば、タングステン粉末に有機溶剤等を添加して成る金属ペーストを基体１となるセラミックグリーンシートの表面にスクリーン印刷法により所定パターンに印刷しておくことによって形成される。
【００２１】
この第２配線導体４の基体１外表面側の一端はコネクター５の線材５ａと電気的に接続しており、このコネクター５を同軸ケーブル等を介して通信装置等の外部機器に接続することにより半導体素子６と外部機器との間で高周波信号の送受信が行われる。
【００２２】
前記コネクター５は、半導体素子収納用パッケージ７の第２配線導体４を同軸ケーブル等を介して外部機器に接続するための接続体として作用し、例えば、鉄−ニッケル−コバルト合金等の金属の線材５ａの周囲を、ホウ珪酸系ガラス等の絶縁性の外囲体５ｂで取り囲んだ構造である。
【００２３】
前記線材５ａと外囲体５ｂとから成るコネクター５は、例えば、鉄−ニッケル−コバルト合金から成る線材５ａを、鉄−ニッケル−コバルト合金等の金属から成る円筒状の容器の中央にセットし、容器内にホウ珪酸ガラス等のガラス粉末を充填した後、ガラス粉末を加熱溶融させて線材５ａの周囲に被着させることによって製作される。
【００２４】
かくして上述の半導体素子収納用パッケージによれば、基体１の搭載部１ａに半導体素子６を搭載するとともにガラス、樹脂、ロウ材等の接着材を介して固定し、しかる後、半導体素子６の各電極を第１配線導体２ａおよびグランド用配線導体２ｂに、例えば、ボンディングワイヤ８を介して接続し、最後に蓋体１０を基体１の上面に封止材を介して接合させ、半導体素子６を気密に封止することによって半導体装置１１となる。
【００２５】
この半導体装置１１は基体１下面の入出力用パッド３ａおよびグランド用パッド３ｂが外部電気回路基板の所定の信号用や接地用等の回路導体に半田バンプ等の外部端子を介して接続され、これによって半導体素子６の信号用、接地用の各電極は外部電気回路と電気的に接続される。
【００２６】
また、この半導体装置１１に取着されているコネクター５の線材５ａに同軸ケーブル等の外部接続用の導線を接続することにより、半導体素子６の電極が通信装置等の外部機器に接続される。
【００２７】
そしてかかる半導体装置１１は、外部電気回路から供給される５〜１０ＧＨｚの複数電気信号を入出力用パッド３ａ及び第１配線導体２ａを介して半導体素子６に入力させ、半導体素子６でこれら入力された電気信号を合成して、４０〜８０ＧＨｚの電気信号とするとともにこれを第２配線導体４を介してコネクター５に出力し、該コネクター５の線材５ａを介して外部の通信装置等の外部機器に伝送する、或いは、外部の通信装置等の外部機器から伝送された４０〜８０ＧＨｚの一つの電気信号をコネクター５の線材５ａ及び第２配線導体４を介して半導体素子６に入力し、半導体素子６で入力された４０〜８０ＧＨｚの電気信号を５〜１０ＧＨｚの複数の電気信号に変換するとともにこれらの個々の電気信号を第１配線導体２ａ及び入出力用パッド３ａを介して外部電気回路に供給することとなる。
【００２８】
本発明の半導体素子収納用パッケージおよびこれを用いた半導体装置においては、第１配線導体２ａと外部電気回路基板の回路導体を接続する入出力用パッド３ａの平面積を０．１９６ｍｍ２以下としておくことが重要である。
【００２９】
前記入出力用パッド３ａの平面積を０．１９６ｍｍ２以下としておくと入出力用パッド３ａのインピーダンスが第１配線導体２ａと外部電気回路基板の回路導体等のインピーダンスに近似し、その結果、入出力用パッド３ａを介して第１配線導体２ａと外部電気回路基板の回路導体とを接続するとともに５〜１０ＧＨｚの高周波の電気信号を伝送させたとしても入出力用パッド３ａで大きな反射等を起こすことはなく、伝送特性が極めて優れたものとなすことができる。
【００３０】
なお、前記入出力用パッド３ａはその平面積が０．１９６ｍｍ２を超えると第１配線導体２ａと外部電気回路基板の回路導体とを入出力用パッド３ａを介して接続した後、５〜１０ＧＨｚの高周波の電気信号が伝送された場合、入出力用パッド３ａで電気信号に反射が発生し伝送特性が大きく劣化してしまう。従って、前記入出力用パッド３ａはその平面積が０．１９６ｍｍ２以下のものに特定される。
【００３１】
また前記入出力用パッド３ａの平面積を０．１９６ｍｍ２以下にする方法としては、金属ペーストを基体１となるグリーンシートに印刷しておくことによって入出力用パッド３ａを形成する際、スクリーン印刷におけるスクリーンマスクの開口を０．１９６ｍｍ２以下としておくことによって行われる。
【００３２】
また本発明の半導体素子収納用パッケージおよび半導体装置においては、図２に示すように、入出力用パッド３ａが形成されている基体１の下面、即ち、入出力用パッド３ａが形成されている面に入出力用パッド３ａよりも２倍以上大きな平面積を有するダミーパッド３ｃを設けておくことが重要である。
【００３３】
前記基体１の下面に入出力用パッド３ａよりも２倍以上大きな平面積を有するダミーパッド３ｃを設けると、入出力用パッド３ａを外部電気回路基板の回路導体に、ダミーパッド３ｃを外部電気回路基板の回路導体や予備に形成したパッドに半田バンプ等を介して接続させ、しかる後、基体１と外部電気回路基板に熱が作用した場合、基体１と外部電気回路基板に熱が作用した場合、基体１と外部電気回路基板との間に両者の線膨張係数の相違に起因する大きな熱応力が発生するものの基体１と外部電気回路基板とは前記ダミーパッド３ｃによる接続によって強固に固定されているため、入出力用パッド３ａの平面積が０．１９６ｍｍ２以下と小さいものであっても、入出力用パッド３ａが基体１より剥離したり、半田バンプ等に破断が発生することはほとんどなく、これによって半導体素子６と外部電気回路との接続の信頼性を極めて高いものとなすことができる。
【００３４】
なお、前記ダミーパッド３ｃは、その平面積が入出力用パッド３ａの平面積に対し２倍未満であるとダミーパッド３ｃを介しての基体１と外部電気回路との接続強度が弱いものとなり、その結果、基体１と外部電気回路基板との間に発生する両者の線膨張係数の相違に起因した応力によって入出力用パッド３ａに剥離等が生じてしまう。従って、前記ダミーパッド３ｃはその平面積が入出力用パッド３ａの平面積に対し２倍以上のものに特定される。
【００３５】
また前記ダミーパッド３ｃはタングステン、モリブデン等から成り、基体１の下面に入出力用パッド３ａを形成する際に同時に、同様の方法によって形成される。
【００３６】
更に前記ダミーパッド３ｃは、基体１の下面に金属ペーストをスクリーン印刷により所定パターンに印刷することによって形成する際、スクリーン印刷におけるスクリーンマスクの開口を大きくしておくことによって入出力用パッド３ａよりも２倍以上の平面積に形成される。
【００３７】
なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。
【００３８】
【発明の効果】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、第１配線導体を外部電気回路基板の回路導体に接続する入出力用パッドの平面積を０．１９６ｍｍ２以下とし、入出力用パッドのインピーダンスを第１配線導体や外部電気回路基板の回路導体のインピーダンスに近似させたことから入出力用パッドを介して第１配線導体と外部電気回路基板の回路導体とを接続するとともに５〜１０ＧＨｚの高周波の電気信号を伝送させたとしても入出力用パッドで大きな反射等を起こすことはなく、伝送特性を優れたものとなすことができる。
【００３９】
また本発明の半導体素子収納用パッケージおよび半導体装置によれば、基体の下面、即ち、入出力用パッドが形成されている面に入出力用パッドよりも２倍以上大きな平面積を有するダミーパッドを設けたことから入出力用パッドを外部電気回路基板の回路導体に、ダミーパッドを外部電気回路基板の回路導体や予備に形成したパッドに半田バンプ等を介して接続させ、しかる後、基体と外部電気回路基板に熱が作用した場合、基体と外部電気回路基板との間に両者の線膨張係数の相違に起因する大きな熱応力が発生するものの基体と外部電気回路基板とは前記ダミーパッドによる接続によって強固に固定されているため入出力用パッドが基体より剥離したり半田バンプ等に破断が発生することはほとんどなく、これによって半導体素子と外部電気回路との接続の信頼性を極めて高いものとなすことができる。
【図面の簡単な説明】
【図１】本発明の半導体素子収納用パッケージおよびこの半導体素子収納用パッケージを用いた半導体装置の一実施例を示す断面図である。
【図２】本発明の半導体素子収納用パッケージおよびこの半導体素子収納用パッケージを用いた半導体装置の一実施例を示す下面図である。
【符号の説明】
１・・・・・基体
１ａ・・・・搭載部
２ａ・・・・第１配線導体
２ｂ・・・・グランド配線導体
３ａ・・・・入出力用パッド
３ｂ・・・・グランド用パッド
３ｃ・・・・ダミーパッド
４・・・・・第２配線導体
５・・・・・コネクター
５ａ・・・・線材
５ｂ・・・・外囲体
６・・・・・半導体素子
７・・・・・半導体素子収納用パッケージ
８・・・・・ボンディングワイヤ
１０・・・・蓋体
１１・・・・半導体装置[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor element housing package for housing a semiconductor element for transmitting and receiving high-frequency electrical signals, and a semiconductor device using the semiconductor element housing package.
[0002]
[Prior art]
Conventionally, a semiconductor element housing package for housing a semiconductor element for transmitting and receiving electric signals is generally made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, and an aluminum nitride sintered body, A base on which a mounting portion of a semiconductor element is formed on an upper surface, and a plurality of electrical signals for inputting / outputting and grounding, which are made of a metal material such as tungsten, molybdenum, or manganese, and are attached and derived from the mounting portion of the base to the lower surface. Wiring conductors, a plurality of ground pads and input / output pads formed on the lower surface of the substrate so as to be electrically connected to the wiring conductors, and are led out from the mounting portion of the substrate to the upper surface or the side surface. Of the wire, one end of the wire is connected to the input / output wiring conductor, and the other end is connected to the outside. It is constituted by a connector that has been derived.
[0003]
In such a package for housing a semiconductor element, a semiconductor element for transmitting and receiving an electric signal is bonded and fixed to a mounting portion thereof via a bonding material such as an Au-Sn brazing material or solder, and electrodes of the semiconductor element are connected to an input / output wiring conductor, The semiconductor device is connected to the ground wiring conductor and the input / output wiring conductor via a bonding wire, a connection ribbon, a conductive connecting material such as solder, and then, if necessary, sealing the semiconductor element with a lid or the like. It becomes.
[0004]
Further, the semiconductor device accommodated inside the semiconductor device by connecting the ground pad and the input / output pad formed on the lower surface of the base to the circuit conductor of the external electric circuit board via a solder bump or the like, so that the semiconductor element accommodated therein is connected to the external electric circuit. The semiconductor device and the external device are connected by connecting the external device such as an external communication device to the connector via a coaxial cable or the like at the same time.
[0005]
The semiconductor element used in the semiconductor device has a function of synthesizing a plurality of electric signals and converting it into one electric signal, or separating one electric signal and converting it into a plurality of electric signals. The plurality of electric signals of 5 to 10 GHz input from the external electric circuit via the input / output pad and the first wiring conductor are combined by a semiconductor element to form one electric signal of 40 to 80 GHz, and the electric signal is 40 to 80 GHz. Is transmitted to the connector via the second wiring conductor, is transmitted from the connector to an external device such as an external communication device, and the electric signal of 40 to 80 GHz transmitted from the external device via the connector is a semiconductor. The element converts the electric signal into a plurality of electric signals of 5 to 10 GHz, and each electric signal of 5 to 10 GHz is supplied to an external electric signal through the first wiring conductor and the input / output pad. And thus transmitted to the road.
[0006]
To Also said substrate consisting of sintered aluminum oxide and mullite sintered body such that the linear expansion coefficient of 4 × 10 -6 /℃~7.5×10 -6 / ℃ , external electric circuit The substrate is generally formed of a glass epoxy resin material, and has a coefficient of linear expansion of about 15 × 10 −6 / ° C., so that the input / output pads are solder bumped to the circuit conductors of the external electric circuit board. After the connection between the base and the external electric circuit board, when heat acts on the base and the external electric circuit board, a large stress is generated due to the difference in the amount of thermal expansion between the base and the external electric circuit board. The connection between the semiconductor element and the external electric circuit is broken due to peeling or breakage of the solder bump. Therefore, in this conventional package for housing semiconductor elements, the input / output pads are formed in a circular shape having a diameter of 1 mm or more (a circular area having a plane area of 0.785 mm 2 or more) to increase the bonding strength between the base and the input / output pads. At the same time, the amount of solder bumps and the like connecting the circuit conductors of the external electric circuit board and the input / output pads is increased to prevent breakage.
[0007]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2002-164466
[Problems to be solved by the invention]
However, in this conventional semiconductor element housing package and semiconductor device, the input / output pad connecting the first wiring conductor and the circuit conductor of the external electric circuit board has a circular shape having a diameter of 1 mm or more (0.785 mm in flat area). 2 or more circular shapes), and about 10 times or more larger than the outer dimensions of the first wiring conductor (circular shape with a diameter of about 0.3 mm or more and a plane area of about 0.07 mm 2 or more). The impedance of the pad is lower than that of the first wiring conductor or the circuit conductor of the external electric circuit board. Therefore, when the first wiring conductor is connected to the circuit conductor of the external electric circuit board via the input / output pad and an electric signal of 5 to 10 GHz is transmitted, the electric signal of 5 to 10 GHz is a high-frequency signal. There is a drawback that reflection or the like is caused by an input / output pad having a low impedance, and transmission characteristics are greatly deteriorated.
[0009]
The present invention has been devised in view of the above drawbacks, and has as its object to effectively prevent reflection of high-frequency electric signals at input / output pads, and to provide a first wiring conductor for connecting an external electric circuit to a semiconductor element. It is another object of the present invention to provide a semiconductor device housing package and a semiconductor device having improved transmission characteristics of electric signals at input / output pads.
[0010]
[Means for Solving the Problems]
A semiconductor device housing package according to the present invention includes a base having a mounting portion on which a semiconductor element that transmits and receives an electric signal of 40 GHz to 80 GHz is mounted, and a plurality of ground wirings extending from the mounting portion to a lower surface of the base. A conductor and a first wiring conductor, a plurality of ground pads and input / output pads formed on the lower surface of the base and electrically connected to the ground wiring conductor and the first wiring conductor; and mounting the base. A second wiring conductor extending from the portion to the upper surface or side surface, and a connector comprising a conductive wire and an insulating envelope, wherein the wire is electrically connected to the second wiring conductor. The input / output pad has a flat area of 0.196 mm 2 or less, and the lower surface of the base has a flat area at least twice as large as the input / output pad. A dummy pad is formed.
[0011]
Further, a semiconductor device of the present invention comprises a semiconductor element storage package having the above-described configuration and a semiconductor element for transmitting and receiving an electric signal of 40 GHz to 80 GHz. The semiconductor element is mounted and fixed on a mounting portion of the package, and each of the semiconductor elements is mounted. An electrode is electrically connected to the first wiring conductor and the second wiring conductor.
[0012]
According to the semiconductor element storage package and the semiconductor device of the present invention, the plane area of the input / output pad for connecting the first wiring conductor to the circuit conductor of the external electric circuit board is 0.196 mm 2 or less, and the input / output pad Since the impedance is approximated to the impedance of the first wiring conductor or the circuit conductor of the external electric circuit board, the first wiring conductor is connected to the circuit conductor of the external electric circuit board via the input / output pad, and the frequency of 5 to 10 GHz is connected. Even if a high-frequency electric signal is transmitted, no large reflection or the like is caused on the input / output pad, and the transmission characteristics can be improved.
[0013]
Further, according to the semiconductor element housing package and the semiconductor device of the present invention, the lower surface of the base, that is, the surface on which the input / output pads are formed, is provided with a dummy pad having a plane area more than twice as large as the input / output pads. The input / output pads are connected to the circuit conductors of the external electric circuit board, and the dummy pads are connected to the circuit conductors of the external electric circuit board and the preliminarily formed pads via solder bumps or the like. When heat is applied to the electric circuit board, a large thermal stress is generated between the base and the external electric circuit board due to a difference in coefficient of linear expansion between the base and the external electric circuit board, but the base and the external electric circuit board are connected by the dummy pad. The input / output pads are hardly peeled off from the substrate or the solder bumps are hardly broken because they are firmly fixed. It can be made extremely high reliability of connection between the electric circuit.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 shows one embodiment of the package for housing a semiconductor element of the present invention, wherein 1 is a base, 2a is a first wiring conductor, 2b is a ground wiring conductor, 3a is an input / output pad, 3b is a ground pad, and 4 is The second wiring conductor 5 is a connector. A semiconductor element housing package 7 for housing the semiconductor element 6 by the base 1, the first wiring conductor 2a, the ground wiring conductor 2b, the input / output pad 3a, the ground pad 3b, the second wiring conductor 4 and the connector 5 is provided. Basically configured.
[0015]
The base 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a glass ceramic, an aluminum nitride sintered body. A suitable organic solvent, solvent, plasticizer, and dispersant are added to and mixed with raw material powders such as silicon, magnesium oxide, and calcium oxide to form a slurry, and the slurry is formed by a conventionally known doctor blade method, calender roll method, or the like. A ceramic green sheet (ceramic green sheet) is obtained by forming a sheet by adopting a sheet forming method. Thereafter, the ceramic green sheet is subjected to an appropriate punching process, and a plurality of the green sheets are laminated as necessary. It is manufactured by firing at a high temperature of 1600 ° C.
[0016]
The base 1 is formed with a plurality of first wiring conductors 2a and ground wiring conductors 2b from the mounting portion 1a of the semiconductor element to the lower surface, and each of the wiring conductors 2a and 2b is connected to an electric signal input / output of the semiconductor element. Of the semiconductor element 6 at one end on the side of the mounting portion 1a, and serves as a conductive path for connecting each electrode for grounding and grounding to the input / output pad 3a and the grounding pad 3b. Are electrically connected via a conductive connecting material.
[0017]
The first wiring conductor 2a, the ground wiring conductor 2b, the input / output pad 3a, and the ground pad 3b are made of a metal material such as tungsten, molybdenum, manganese, or the like. It is formed by printing a metal paste obtained by adding a solvent in a predetermined pattern on the surface of a ceramic green sheet serving as the base 1.
[0018]
One ends of the first wiring conductor 2a and the ground wiring conductor 2b on the lower surface side of the base 1 are electrically connected to corresponding input / output pads 3a and ground pads 3b, respectively. By connecting the ground pad 3b to a predetermined signal conductor or a circuit conductor for grounding of the external electric circuit, the electric signal input / output and ground electrodes of the semiconductor element 6 are electrically connected to the external electric circuit. Connected.
[0019]
The base 1 has a second wiring conductor 4 formed from the mounting portion 1a of the semiconductor element to the upper surface, the side surface, and the like. The second wiring conductor 4 connects the electrode of the semiconductor element 6 to the wire 5a of the connector 5. And an electrode of the semiconductor element 6 is electrically connected to one end of the mounting portion 1a via a conductive connecting material 8.
[0020]
The second wiring conductor 4 is made of a metal material such as tungsten or molybdenum similarly to the above-described first wiring conductor 2a or the like. For example, when the second wiring conductor 4 is made of tungsten, an organic solvent or the like is added to tungsten powder. The metal paste is formed by printing a predetermined pattern on the surface of the ceramic green sheet serving as the base 1 by a screen printing method.
[0021]
One end of the second wiring conductor 4 on the outer surface side of the base 1 is electrically connected to a wire 5a of a connector 5, and the connector 5 is connected to an external device such as a communication device via a coaxial cable or the like. Transmission and reception of high-frequency signals are performed between the semiconductor element 6 and an external device.
[0022]
The connector 5 functions as a connector for connecting the second wiring conductor 4 of the semiconductor element housing package 7 to an external device via a coaxial cable or the like, and is, for example, a metal wire such as an iron-nickel-cobalt alloy. 5A has a structure in which the periphery of 5a is surrounded by an insulating outer body 5b such as borosilicate glass.
[0023]
For the connector 5 composed of the wire 5a and the outer body 5b, for example, a wire 5a made of an iron-nickel-cobalt alloy is set at the center of a cylindrical container made of a metal such as an iron-nickel-cobalt alloy, After the glass powder such as borosilicate glass is filled in the container, the glass powder is heated and melted and adhered around the wire 5a.
[0024]
Thus, according to the above-described semiconductor element storage package, the semiconductor element 6 is mounted on the mounting portion 1a of the base 1 and fixed via an adhesive such as glass, resin, brazing material, and the like. The electrodes are connected to the first wiring conductor 2a and the ground wiring conductor 2b via, for example, bonding wires 8, and finally the lid 10 is joined to the upper surface of the base 1 via a sealing material, and the semiconductor element 6 is connected. The semiconductor device 11 is obtained by hermetically sealing.
[0025]
In the semiconductor device 11, input / output pads 3a and ground pads 3b on the lower surface of the base 1 are connected to predetermined signal and ground circuit conductors of an external electric circuit board via external terminals such as solder bumps. Accordingly, the signal and ground electrodes of the semiconductor element 6 are electrically connected to an external electric circuit.
[0026]
In addition, by connecting a conductor for external connection such as a coaxial cable to the wire 5a of the connector 5 attached to the semiconductor device 11, the electrode of the semiconductor element 6 is connected to an external device such as a communication device.
[0027]
The semiconductor device 11 inputs a plurality of electric signals of 5 to 10 GHz supplied from an external electric circuit to the semiconductor element 6 via the input / output pad 3a and the first wiring conductor 2a. The combined electrical signals are combined into an electrical signal of 40 to 80 GHz and output to the connector 5 via the second wiring conductor 4, and external equipment such as an external communication device via the wire 5 a of the connector 5. Or one electrical signal of 40 to 80 GHz transmitted from an external device such as an external communication device is input to the semiconductor element 6 via the wire 5a of the connector 5 and the second wiring conductor 4, and 6 converts the electric signal of 40 to 80 GHz input into a plurality of electric signals of 5 to 10 GHz and converts these individual electric signals into the first wiring conductor 2a and the input / output The supplying to an external electrical circuit through the use pads 3a.
[0028]
In the semiconductor device housing package and the semiconductor device using the same according to the present invention, the plane area of the input / output pad 3a connecting the first wiring conductor 2a and the circuit conductor of the external electric circuit board is set to 0.196 mm 2 or less. This is very important.
[0029]
If the plane area of the input / output pad 3a is 0.196 mm 2 or less, the impedance of the input / output pad 3a approximates the impedance of the first wiring conductor 2a and the circuit conductor of the external electric circuit board. Even if the first wiring conductor 2a is connected to the circuit conductor of the external electric circuit board via the output pad 3a and a high-frequency electric signal of 5 to 10 GHz is transmitted, large reflection occurs at the input / output pad 3a. That is, the transmission characteristics can be extremely excellent.
[0030]
If the plane area of the input / output pad 3a exceeds 0.196 mm 2 , the first wiring conductor 2a and the circuit conductor of the external electric circuit board are connected to each other via the input / output pad 3a. When the high-frequency electric signal is transmitted, the electric signal is reflected at the input / output pad 3a, and the transmission characteristic is greatly deteriorated. Therefore, the input / output pad 3a is specified to have a plane area of 0.196 mm 2 or less.
[0031]
In order to reduce the plane area of the input / output pads 3a to 0.196 mm 2 or less, screen printing is performed when the input / output pads 3a are formed by printing a metal paste on a green sheet serving as the base 1. Is performed by setting the opening of the screen mask at 0.196 mm 2 or less.
[0032]
Further, in the semiconductor element housing package and the semiconductor device of the present invention, as shown in FIG. 2, the lower surface of the base 1 on which the input / output pads 3a are formed, that is, the surface on which the input / output pads 3a are formed. It is important to provide a dummy pad 3c having a plane area at least twice as large as the input / output pad 3a.
[0033]
When a dummy pad 3c having a plane area at least twice as large as the input / output pad 3a is provided on the lower surface of the base 1, the input / output pad 3a is used as a circuit conductor of an external electric circuit board, and the dummy pad 3c is used as an external electric circuit. When connected to the circuit conductors of the board or the pads formed in advance through solder bumps and the like, and thereafter, when heat acts on the base 1 and the external electric circuit board, or when heat acts on the base 1 and the external electric circuit board Although a large thermal stress is generated between the base 1 and the external electric circuit board due to the difference in the coefficient of linear expansion between them, the base 1 and the external electric circuit board are firmly fixed by the connection with the dummy pad 3c. Therefore, even if the plane area of the input / output pad 3a is as small as 0.196 mm 2 or less, the input / output pad 3a is peeled off from the base 1 or the solder bumps are broken. In this case, the reliability of the connection between the semiconductor element 6 and the external electric circuit can be made extremely high.
[0034]
If the plane area of the dummy pad 3c is less than twice the plane area of the input / output pad 3a, the connection strength between the base 1 and the external electric circuit via the dummy pad 3c becomes weak, As a result, the input / output pad 3a may be peeled off by the stress generated between the base 1 and the external electric circuit board due to the difference in the coefficient of linear expansion between the two. Therefore, the dummy pad 3c is specified to have a plane area twice or more the plane area of the input / output pad 3a.
[0035]
The dummy pad 3c is made of tungsten, molybdenum, or the like, and is formed by the same method at the same time as forming the input / output pad 3a on the lower surface of the base 1.
[0036]
Further, when the dummy pad 3c is formed by printing a metal paste on the lower surface of the base 1 in a predetermined pattern by screen printing, the opening of the screen mask in the screen printing is made larger to make the dummy pad 3c smaller than the input / output pad 3a. It is formed in a plane area of twice or more.
[0037]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.
[0038]
【The invention's effect】
According to the semiconductor element storage package and the semiconductor device of the present invention, the plane area of the input / output pad for connecting the first wiring conductor to the circuit conductor of the external electric circuit board is 0.196 mm 2 or less, and the input / output pad Since the impedance is approximated to the impedance of the first wiring conductor or the circuit conductor of the external electric circuit board, the first wiring conductor is connected to the circuit conductor of the external electric circuit board via the input / output pad, and the frequency of 5 to 10 GHz is connected. Even if a high-frequency electric signal is transmitted, no large reflection or the like is caused on the input / output pad, and the transmission characteristics can be improved.
[0039]
Further, according to the semiconductor element housing package and the semiconductor device of the present invention, the lower surface of the base, that is, the surface on which the input / output pads are formed, is provided with a dummy pad having a plane area more than twice as large as the input / output pads. The input / output pads are connected to the circuit conductors of the external electric circuit board, and the dummy pads are connected to the circuit conductors of the external electric circuit board and the preliminarily formed pads via solder bumps or the like. When heat is applied to the electric circuit board, a large thermal stress is generated between the base and the external electric circuit board due to a difference in coefficient of linear expansion between the base and the external electric circuit board, but the base and the external electric circuit board are connected by the dummy pad. The input / output pads are hardly peeled off from the substrate or the solder bumps are hardly broken because they are firmly fixed. It can be made extremely high reliability of connection between the electric circuit.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing one embodiment of a package for housing a semiconductor element of the present invention and a semiconductor device using the package for housing a semiconductor element.
FIG. 2 is a bottom view showing one embodiment of the package for housing a semiconductor element of the present invention and a semiconductor device using the package for housing a semiconductor element.
[Explanation of symbols]
1 Base 1a Mounting part 2a First wiring conductor 2b Ground wiring conductor 3a Input / output pad 3b Ground pad 3c ... Dummy pad 4 ... Second wiring conductor 5 ... Connector 5a ... Wire 5b ... Enclosure 6 ... Semiconductor element 7 ... Semiconductor element storage package 8 Bonding wire 10 Lid 11 Semiconductor device

Claims (2)

４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第１配線導体と、前記基体の下面に形成され、前記グランド配線導体および第１配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面もしくは側面にかけて導出されている第２配線導体と、導電性の線材と絶縁性の外囲体とから成り、線材が前記第２配線導体に電気的に接続されているコネクターとで形成され、前記入出力用パッドの平面積が０．１９６ｍｍ２以下であり、かつ前記基体の下面に前記入出力用パッドよりも２倍以上大きな平面積を有するダミーパッドが形成されていることを特徴とする半導体素子収納用パッケージ。A base having a mounting portion on which a semiconductor element for transmitting and receiving electric signals of 40 GHz to 80 GHz is mounted, a plurality of ground wiring conductors and first wiring conductors extending from the mounting portion of the base to a lower surface; And a plurality of ground pads and input / output pads electrically connected to the ground wiring conductor and the first wiring conductor, and are led out from the mounting portion of the base to the upper surface or the side surface. A second wiring conductor, a conductive wire and an insulating enclosure, wherein the wire is formed by a connector electrically connected to the second wiring conductor, and the plane area of the input / output pad Is 0.196 mm 2 or less, and a dummy pad having a plane area at least twice as large as the input / output pads is formed on the lower surface of the base. Semiconductor device package. 請求項１に記載の半導体素子収納用パッケージと４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子とから成り、前記パッケージの搭載部に半導体素子を搭載固定するとともに該半導体素子の各電極を第１配線導体および第２配線導体に電気的に接続したことを特徴とする半導体装置。2. A semiconductor element storage package according to claim 1, comprising: a semiconductor element for transmitting and receiving an electric signal of 40 GHz to 80 GHz. A semiconductor device electrically connected to a conductor and a second wiring conductor.
JP2002321749A 2002-11-05 2002-11-05 Semiconductor element storage package and semiconductor device using the same Expired - Fee Related JP3847247B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015035531A (en) * 2013-08-09 2015-02-19 キヤノン株式会社 Circuit board and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015035531A (en) * 2013-08-09 2015-02-19 キヤノン株式会社 Circuit board and electronic apparatus

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