JP2004153238A - Method of depositing multiplex high-k gate dielectric for cmos application - Google Patents

Method of depositing multiplex high-k gate dielectric for cmos application Download PDF

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JP2004153238A
JP2004153238A JP2003275027A JP2003275027A JP2004153238A JP 2004153238 A JP2004153238 A JP 2004153238A JP 2003275027 A JP2003275027 A JP 2003275027A JP 2003275027 A JP2003275027 A JP 2003275027A JP 2004153238 A JP2004153238 A JP 2004153238A
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metal oxide
depositing
oxide layer
ald
layer
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JP2003275027A
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JP4133659B2 (en
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Jr John F Conley
エフ． コネリー ジュニア ジョン
Yoshichika Ono
芳睦 大野
Rajendra Solanki
ソランキ レジェンダー
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Sharp Corp
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Sharp Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To form a layer of a high-κ dielectric material on an H termination silicon without forming a low-κ interface layer. <P>SOLUTION: In an integrated circuit, a method of forming the layer of the high-κ dielectric material includes a step of preparing a silicon substrate, a step of depositing a first metal oxide layer by an ALD which uses a metal nitrate precursor, a step of depositing another metal oxide layer by an ALD which uses a metal chloride precursor, and a step of completing the integrated circuit. The preparing step may include a step of forming the H termination surface of the silicon substrate. The forming step may include a step of exposing the silicon surface by HF. The step of depositing the first metal oxide layer may include a step of depositing a metal oxide layer by using an ALD cycle one to five times. <P>COPYRIGHT: (C)2004,JPO

Description

本発明は、集積回路製造、具体的には、トランジスタゲートをソース領域とドレイン領域との間のチャネルから分離するＭＯＳゲート誘電体を製造する方法に関する。   The present invention relates to integrated circuit fabrication, and more particularly to a method of fabricating a MOS gate dielectric that separates a transistor gate from a channel between a source region and a drain region.

シリコン上の熱成長したＳｉＯ２は、ＭＯＳ技術の「心臓」と呼ばれてきた。Ｓｉ／ＳｉＯ２インターフェースは、低い界面およびバルクトラッピング、熱安定性、高い分解などの優良な半導体性質を有する。しかし、ミクロ電子部品技術の連続する世代のそれぞれにおいて、ゲート誘電体の厚さは、スケーリング、例えば、より薄くされる。厚さが、１．５ｎｍ未満にスケーリングされる場合、例えば、直接的なトンネル効果からの漏れに起因する過剰な電力消費、ホウ素貫入、信頼性についての懸念などの問題が生じる。これらの問題により、近い将来、２００５年における８０ｎｍノードと同じくらい早くに、ゲート誘電体としてＳｉＯ２の優勢が衰え、最終的には終わる可能性がある。ＳｉＯ２は、任意の所与のキャパシタンスについて厚さがより厚く、より高い誘電率（κ）の材料にとってかわられる可能性が高い。
Ｃｏｎｌｅｙ，Ｊｒ．らによる「Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ Ｈａｆｎｉｕｍ Ｏｘｉｄｅ Ｕｓｉｎｇ Ａｎｈｙｄｒｏｕｓ Ｈａｆｎｉｕｍ Ｎｉｔｒａｔｅ」（Ｅｌｅｃｔｒｏｃｈｅｍ．ａｎｄ Ｓｏｌ．Ｓｔａｔｅ Ｌｅｔｔ．５（５）２００２年５月） Thermally grown SiO 2 on silicon has been called the “heart” of MOS technology. Si / SiO 2 interface has low interfacial and bulk trapping, thermal stability, a good semiconductor properties such as higher decomposition. However, in each successive generation of microelectronics technology, the thickness of the gate dielectric is scaled, eg, made thinner. When the thickness is scaled below 1.5 nm, problems such as excessive power consumption due to leakage from direct tunneling, boron penetration, reliability concerns, etc., occur. These problems may lead to a decline in the dominance of SiO 2 as the gate dielectric in the near future, as soon as the 80 nm node in 2005, and eventually its termination. SiO 2 is thicker for any given capacitance and is likely to be replaced by higher dielectric constant (κ) materials.
Conley, Jr. "Atomic Layer Deposition of Hafnium Oxide Using Anhydrous Hafnium Nitrate" (Electrochem. And Sol. State Lett. 5 (5) May 2002).

ＳｉＯ２の代用物に対するこのやむにやまれぬ近々の需要にも関わらず、適切な代替品は、依然として発見されていない。この代替的な材料の要件には、低い漏れ電流、低い界面トラップ、低いトラップされた電荷、良好な信頼性、良好な熱安定性、等角な堆積などが含まれる。有望な候補材料には、ＨｆＯ２、ＺｒＯ２などの金属酸化物、および他の金属酸化物が含まれる。 Despite the near-term demand unexpected is mountain in this ceased for the surrogate of SiO 2, a suitable alternative products, not yet been discovered. Requirements for this alternative material include low leakage current, low interfacial traps, low trapped charge, good reliability, good thermal stability, conformal deposition, and the like. The promising candidate materials include metal oxides such as HfO 2, ZrO 2, and other metal oxides.

高κ膜を堆積する場合、低κ界面層を避けることが重要である。なぜなら、非常に薄い低κ界面層でさえ、上に重ねられる高κ材料の利点の殆どを打ち消し得るからである。従って、高κ材料を、Ｈ終端シリコン層の上に直接堆積することが重要である。   When depositing high-κ films, it is important to avoid low-κ interface layers. This is because even a very thin low-κ interface layer can negate most of the advantages of an overlying high-κ material. Therefore, it is important that the high-κ material be deposited directly on the H-terminated silicon layer.

正角性および厚さの制御に対する要件のため、原子層堆積（ＡＬＤ）は、高κ材料の最も有望な堆積技術のうちの１つとして発生した。この技術において、誘電材料は、自己制御式の様態で、層ごとに構築される。すなわち、１つの化学種の単一層のみが所与の表面上に吸着する、堆積現象である。現在では、金属酸化物を堆積するための主要なＡＬＤ前駆物質は、ハロゲン化金属および有機金属である。また、いくつかの実験においては、高κ誘電体前駆物質として無水硝酸金属が用いられてきた。   Due to the requirement for conformality and thickness control, atomic layer deposition (ALD) has emerged as one of the most promising deposition techniques for high-κ materials. In this technique, the dielectric material is built up layer by layer in a self-limiting manner. That is, a deposition phenomenon in which only a single layer of one species adsorbs on a given surface. At present, the main ALD precursors for depositing metal oxides are metal halides and organometallics. Also, in some experiments, anhydrous metal nitrate has been used as a high-κ dielectric precursor.

塩化金属前駆物質、例えば、ＺｒＣｌ４などを用いて堆積されたＺｒＯ２の膜は、高κ誘電率および低い漏れ電流を含む良好な絶縁性質を示してきた。しかし、ＺｒＣｌ４の主な欠点は、Ｈ終端シリコン上に直接滑らかに堆積されないこと、いくつかの「育成」サイクルが必要であること、および均一に開始するためにＳｉＯ２の薄層が必要であることである。これらの問題は、塩化金属前駆物質が製造において用いられ得る前に解決される必要がある。 Films of ZrO 2 deposited using metal chloride precursors, such as ZrCl 4 , have shown good insulating properties, including high κ dielectric constant and low leakage current. However, the main drawbacks of ZrCl 4 are that it does not deposit smoothly directly on H-terminated silicon, requires several “growth” cycles, and requires a thin layer of SiO 2 to start uniformly. There is something. These problems need to be solved before metal chloride precursors can be used in production.

有機金属前駆物質の欠点は、有機的汚染の可能性があることである。Ｈｆ（ＮＯ３）４は、実行可能なＡＬＤ前駆物質であることが示されてきたが、「Ｍｅｔｈｏｄ ｔｏ Ｉｎｉｔｉａｔｅ ｔｈｅ Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ ａ Ｈｉｇｈ Ｄｉｅｌｅｃｔｒｉｃ Ｃｏｎｓｔａｎｔ Ｍａｔｅｒｉａｌ Ｄｉｒｅｃｔｌｙ ｏｎ ａ Ｓｉｌｉｃｏｎ Ｓｕｂｓｔｒａｔｅ」という名称の２００１年６月２８日に出願された米国特許出願第０９／８９４，９４１号、および、Ｃｏｎｌｅｙ，Ｊｒ．らによる「Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ Ｈａｆｎｉｕｍ Ｏｘｉｄｅ Ｕｓｉｎｇ Ａｎｈｙｄｒｏｕｓ Ｈａｆｎｉｕｍ Ｎｉｔｒａｔｅ」（Ｅｌｅｃｔｒｏｃｈｅｍ．ａｎｄ Ｓｏｌ．Ｓｔａｔｅ Ｌｅｔｔ．５（５）２００２年５月）において特定されているように、Ｈｆ（ＮＯ３）４の主な利点は、Ｈ終端シリコン上で直接堆積を開始することを可能にし、均一な薄層が得られることである。この方法は、低κ界面層を避ける可能性を有する。しかし、実験作業によって、Ｈｆ（ＮＯ３）４のＡＬＤを介して堆積されるＨｆＯ２膜は、誘電率が予測されるよりも低いことが示された。これは、恐らくは、酸素が豊富であるという膜の性質のためである。得られる膜の「バルク」誘電性質は、硝酸金属前駆物質が、幅広く用いられるようになるまえに改善される必要がある。 A disadvantage of organometallic precursors is the potential for organic contamination. Although Hf (NO 3 ) 4 has been shown to be a viable ALD precursor, “Method to Initiate the Atomic Layer Deposition of a High Dielectric Constant Material Digital Dir. U.S. patent application Ser. No. 09 / 894,941, filed on Jan. 28, and Conley, Jr. "Atomic Layer Deposition of Hafnium Oxide Using Anhydrous Hafnium Nitrate " as specified in (Electrochem.and Sol.State Lett.5 (5) 5 May 2002), the main advantage of Hf (NO 3) 4 by et al. Is to allow the deposition to be started directly on the H-terminated silicon, resulting in a uniform thin layer. This method has the potential to avoid low-κ interface layers. However, experimental work has shown that HfO 2 films deposited via ALD of Hf (NO 3 ) 4 have lower dielectric constants than expected. This is probably due to the nature of the membrane, which is rich in oxygen. The "bulk" dielectric properties of the resulting films need to be improved before metal nitrate precursors become widely used.

本発明の方法は、集積回路において高κ誘電材料の層を形成する方法であって、シリコン基板を準備する工程と、硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、該集積回路を完成させる工程とを包含し、それによって上記目的を達成する。   The method of the present invention is a method of forming a layer of a high-κ dielectric material in an integrated circuit, comprising the steps of providing a silicon substrate and forming a first metal oxide layer using ALD using a metal nitrate precursor. The method includes the steps of depositing, depositing another metal oxide layer using ALD with a metal chloride precursor, and completing the integrated circuit, thereby achieving the above objectives.

前記準備する工程は、前記シリコン基板のＨ終端表面を形成する工程を含んでもよい。   The preparing step may include a step of forming an H-terminated surface of the silicon substrate.

前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含んでもよい。   The forming may include exposing the silicon surface with HF.

前記第１の金属酸化物の層を堆積する工程は、１〜５回のＡＬＤサイクルを用いて、金属酸化物の層を堆積する工程を含んでもよい。   Depositing the first metal oxide layer may include depositing the metal oxide layer using one to five ALD cycles.

前記他の金属酸化物の層を堆積する工程は、複数のＡＬＤサイクルを用いて、金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程を含んでもよい。   Depositing the other metal oxide layer may include depositing the metal oxide layer using a plurality of ALD cycles to obtain a desired metal oxide layer thickness.

ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含んでもよい。 The metal oxide selected from the group consisting of HfO 2 , ZrO 2 , Gd 2 O 3 , La 2 O 3 , CeO 2 , TiO 2 , Y 2 O 3 , Ta 2 O 5 , and Al 2 O 3 The method may include selecting a metal oxide to be deposited on the silicon substrate.

前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含んでもよい。   Depositing the first metal oxide layer may include depositing an initial metal oxide layer having a thickness between about 0.1 nm and 1.5 nm.

前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含んでもよい。   Depositing the other metal oxide layer may include depositing a metal oxide layer having a thickness between about 3 nm and 10 nm.

本発明の方法は、集積回路において高κ誘電ゲート酸化物の層を形成する方法であって、シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、硝酸金属前駆物質を用いるＡＬＤを１〜５回用いて第１の金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、塩化金属前駆物質を用いるＡＬＤを複数回用いて他の金属酸化物の層を堆積する工程と、該集積回路を完成させる工程とを包含し、それにより上記目的を達成する。   The method of the present invention is a method of forming a layer of a high-κ dielectric gate oxide in an integrated circuit, the method comprising providing a silicon substrate, the method comprising forming an H-terminated surface of the silicon substrate. Depositing a first metal oxide layer using ALD using a metal nitrate precursor one to five times to obtain a desired metal oxide layer thickness, and performing a plurality of ALDs using a metal chloride precursor. A single use of depositing another metal oxide layer and completing the integrated circuit, thereby achieving the above objectives.

前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含んでもよい。   The forming may include exposing the silicon surface with HF.

ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含んでもよい。 The metal oxide selected from the group consisting of HfO 2 , ZrO 2 , Gd 2 O 3 , La 2 O 3 , CeO 2 , TiO 2 , Y 2 O 3 , Ta 2 O 5 , and Al 2 O 3 The method may include selecting a metal oxide to be deposited on the silicon substrate.

前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含んでもよい。   Depositing the first metal oxide layer may include depositing an initial metal oxide layer having a thickness between about 0.1 nm and 1.5 nm.

前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含んでもよい。   Depositing the other metal oxide layer may include depositing a metal oxide layer having a thickness between about 3 nm and 10 nm.

本発明の方法は、集積回路においてＨｆＯ２高κ誘電ゲート酸化物の層を形成する方法であって、シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤを１〜５回用いて第１のＨｆＯ２金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、ＨｆＣｌ４前駆物質を用いるＡＬＤを複数回用いて他のＨｆＯ２の層を堆積する工程と、該集積回路を完成させる工程とを包含し、それにより上記目的を達成する。 The method of the present invention is a method of forming a layer of HfO 2 high-κ dielectric gate oxide in an integrated circuit, the method comprising the steps of providing a silicon substrate and forming an H-terminated surface of the silicon substrate. Depositing a first layer of HfO 2 metal oxide using ALD using a Hf (NO 3 ) 4 precursor one to five times to obtain a desired metal oxide layer thickness; The method includes the steps of depositing another layer of HfO 2 using ALD with the four precursors multiple times and completing the integrated circuit, thereby achieving the above object.

前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含んでもよい。   The forming may include exposing the silicon surface with HF.

前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含んでもよい。   Depositing the first metal oxide layer may include depositing an initial metal oxide layer having a thickness between about 0.1 nm and 1.5 nm.

前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含んでもよい。   Depositing the other metal oxide layer may include depositing a metal oxide layer having a thickness between about 3 nm and 10 nm.

集積回路において、高κ誘電材料の層を形成する方法は、シリコン基板を準備する工程と、硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、集積回路を完成させる工程とを含む。   In an integrated circuit, a method of forming a layer of a high-κ dielectric material includes providing a silicon substrate, depositing a first metal oxide layer using ALD using a metal nitrate precursor, Depositing another metal oxide layer using ALD with a precursor, and completing the integrated circuit.

本発明の目的は、シリコン基板上に金属酸化物高κ層を堆積することである。   It is an object of the present invention to deposit a metal oxide high κ layer on a silicon substrate.

本発明の他の目的は、シリコン基板上に低κ界面層を形成することを必要とせずに、シリコン基板上に金属酸化物高κ層を堆積することである。   Another object of the present invention is to deposit a metal oxide high κ layer on a silicon substrate without the need to form a low κ interface layer on the silicon substrate.

本発明の他の目的は、漏れ電流が低い性質を有する高κ層を提供することである。   It is another object of the present invention to provide a high-κ layer having low leakage current properties.

本発明のこの要旨および目的は、本発明の性質を短時間で理解することを可能にするために提供されている。本発明のより完全な理解は、以下の本発明の好適な実施形態の詳細な説明を、図面とともに参照することによって得ることができる。   This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more complete understanding of the present invention may be obtained by reference to the following detailed description of preferred embodiments of the invention, taken in conjunction with the drawings.

本発明の方法は、Ｈｆ（ＮＯ３）４の１回、または１〜５回までのサイクルで、Ｈ終端シリコン上のＡＬＤ堆積を開始し、その後、ＨｆＣｌ４のような他の前駆物質を用いて、所望の厚さまで、残りの膜のＡＬＤ堆積が続く。本発明の方法によって、最初の低κ界面層が必要なくなるが、依然として、高誘電率の「バルク」膜が達成されるようになる。 The method of the present invention, Hf (NO 3) 4 1 times, or in cycles of up to 5 times, to begin ALD deposition on H-terminated silicon, then using other precursors, such as HfCl 4 Then, ALD deposition of the remaining film continues to the desired thickness. The method of the present invention eliminates the need for an initial low-κ interface layer, but still achieves a high dielectric constant "bulk" film.

本出願は、「Ｍｅｔｈｏｄ ｔｏ Ｉｎｉｔｉａｔｅ ｔｈｅ Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ ａ Ｈｉｇｈ Ｄｉｅｌｅｃｔｒｉｃ Ｃｏｎｓｔａｎｔ Ｍａｔｅｒｉａｌ Ｄｉｒｅｃｔｌｙ ｏｎ ａ Ｓｉｌｉｃｏｎ Ｓｕｂｓｔｒａｔｅ」という名称の２００１年６月２８日に出願された米国特許出願第０９／８９４，９４１号に関連する。   This application claims the benefit of US patent application Ser. No. 08 / 94,200, filed on Apr. 9, U.S.A., filed on Apr. 9, 89, U.S.A., filed on Apr. 8, 89, U.S.A., filed on Apr. 9, U.S.A., filed on Mar. 8, 2004, filed on Apr. 9, U.S.A., filed on Apr. 9, U.S.A., filed on Apr. 9, U.S.A., filed on Mar. 8, 200, U.S.A. .

ゲート形成の最新技術は、高温でのシリコンの酸化を必要とする。ＳｉＯ２が酸化金属、例えば、ＨｆＯ２、ＺｒＯ２などによって代用される可能性が高い。高κ堆積方法が未だ確立されていないにも関わらず、主要な技術は、原子層堆積（ＡＬＤ）である。ＡＬＤは、典型的には、単一の前駆物質、例えば、四塩化金属、有機金属、または無水硝酸金属を用いて行われる。上述したように、これらの前駆物質は、全て、大きな欠点を有する。 State-of-the-art in gate formation requires the oxidation of silicon at high temperatures. There is a high possibility that SiO 2 will be replaced by a metal oxide, for example, HfO 2 , ZrO 2 or the like. The main technique is atomic layer deposition (ALD), even though high-κ deposition methods have not yet been established. ALD is typically performed using a single precursor, for example, a metal tetrachloride, an organic metal, or a metal anhydrous nitrate. As mentioned above, all of these precursors have significant disadvantages.

金属酸化物のＡＬＤについて現在利用可能な主要な前駆物質は、重大な欠点を有するので、本発明の方法は、得られる金属酸化物の膜の質を改善する前駆物質の組合せを含む。前駆物質の組合せは、各前駆物質の利点を利用し、前駆物質の使用に関連する欠点を最小にする。本発明の方法は、Ｈｆ（ＮＯ３）４の１回、または１〜５回までのサイクルで、Ｈ終端シリコン上のＡＬＤ堆積を開始し、その後、ＨｆＣｌ４のような他の前駆物質を用いて、所望の厚さまで、残りの膜のＡＬＤ堆積が続く。本発明の方法によって、最初の低κ界面層が必要なくなるが、依然として、高誘電率の「バルク」膜が達成されるようになる。 Since the main precursors currently available for ALD of metal oxides have significant disadvantages, the method of the present invention includes a combination of precursors that improves the quality of the resulting metal oxide film. Precursor combinations take advantage of each precursor and minimize the disadvantages associated with the use of precursors. The method of the present invention, Hf (NO 3) 4 1 times, or in cycles of up to 5 times, to begin ALD deposition on H-terminated silicon, then using other precursors, such as HfCl 4 Then, ALD deposition of the remaining film continues to the desired thickness. The method of the present invention eliminates the need for an initial low-κ interface layer, but still achieves a high dielectric constant "bulk" film.

本発明の方法は、個々の前駆物質の強度を、組合せで、組み込み、Ｈ終端シリコン上に直接高κ膜を堆積することを達成する。Ｈｆ（ＮＯ３）４前駆物質は、Ｈ終端シリコン上で直接開始することを提供し、ＨｆＣｌ４の前駆物質を用いてさらなるＡＬＤのためのベース層を提供する。 The method of the present invention achieves the incorporation of individual precursor strengths, in combination, to deposit high-κ films directly on H-terminated silicon. The Hf (NO 3 ) 4 precursor provides for starting directly on the H-terminated silicon and provides a base layer for further ALD using a HfCl 4 precursor.

別の前駆物質を用いることは上述されたが、このような別の前駆物質を用いることは、異なる前駆物質を用いて異なる金属酸化物、例えば、ＨｆＯ２−ＺｒＯ２、Ｔａ２Ｏ５−ＨｆＯ２などを挟んで、Ｈ．Ｚｈａｎｇらによる「Ｈｉｇｈ Ｐｅｒｍｉｔｔｉｖｉｔｙ Ｔｈｉｎ Ｆｉｌｍ Ｎａｎｏｌａｍｉｎａｔｅｓ」（Ｊ．Ａｐｐｌ．Ｐｈｙｓ．８７，１９２１（２０００））に記載されているようなナノラミネートを作成することを意味する。複数の堆積サイクルを用いて同じ金属酸化物を堆積する異なる前駆物質の組合せが報告されたということは確認されていない。 The use of different precursors is described above, the use of such an alternative precursor, different metal oxide using different precursors, for example, such as HfO 2 -ZrO 2, Ta2O5-HfO 2 H. Zhang et al., "Making nanolaminates as described in" High Permitivity Thin Film Nanolaminates "(J. Appl. Phys. 87, 1921 (2000)). It has not been determined that different precursor combinations have been reported that deposit the same metal oxide using multiple deposition cycles.

本発明の方法は、ＡＬＤを用いるゲート酸化物堆積の方法を説明する。１回目、または１〜５回目までのＡＬＤ堆積サイクルは、無水硝酸ハフニウム（Ｈｆ（ＮＯ３）４）を前駆物質として用い、残りのサイクルは、前駆物質として、四塩ハフニウム（ＨｆＣｌ４）を用いる。１回のＡＬＤ堆積サイクルは、前駆物質、すなわち、硝酸ハフニウムまたは四塩ハフニウムのパルス、続く窒素パージ、その後の水蒸気のパルス、最終的には、もう１つの窒素パージを含む。 The method of the present invention describes a method for gate oxide deposition using ALD. First, or ALD deposition cycles to 5 th uses a hafnium nitrate anhydrous (Hf (NO 3) 4) as a precursor, the remaining cycles, as a precursor, used Yonshio hafnium (HfCl 4) . One ALD deposition cycle includes a pulse of the precursor, i.e., hafnium nitrate or hafnium tetrasalt, followed by a nitrogen purge, followed by a pulse of water vapor, and finally another nitrogen purge.

図１を参照すると、ゲート酸化物の堆積前の構造は、任意の最新技術による方法によって形成される。このような方法には、シリコン基板１０およびフィールド酸化物領域１２および１４を準備する工程が含まれる。以下の図に示す例は、ゲート処理の代用である。ゲート酸化物の形成前の最後の工程は、シリコン表面をＨＦにより露出させて、Ｈ終端シリコン表面１６を準備することである。   Referring to FIG. 1, the pre-deposition structure of the gate oxide is formed by any state of the art method. Such a method includes providing a silicon substrate 10 and field oxide regions 12 and 14. The example shown in the following figure is a substitute for the gate processing. The final step before forming the gate oxide is to expose the silicon surface with HF to provide an H-terminated silicon surface 16.

図２に、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤを介して堆積されたＨｆＯ２の最初、または第１の層１８を示す。この工程の目的は、「育成」期間またはＳｉＯ２薄層を必要とせずに、Ｈ終端シリコン上に直接堆積を開始することである。最初の層は、約０．１〜１．５ｎｍの間の厚さで形成される。 FIG. 2 shows the first or first layer 18 of HfO 2 deposited via ALD using a Hf (NO 3 ) 4 precursor. The purpose of this step, without requiring a "development" period or SiO 2 thin layer, is to initiate the deposited directly on H-terminated silicon. The first layer is formed with a thickness between about 0.1-1.5 nm.

図３に、ＨｆＣｌ４前駆物質を用いて所望の厚さまで堆積された、他のＨｆＯ２「バルク」層２０を示す。この所望の厚さは、好適な実施形態においては、約３〜１０ｎｍの間の厚さである。この工程の目的は、予測される高誘電率の「バルク」ＨｆＯ２膜を作成することである。 FIG. 3 shows another HfO 2 “bulk” layer 20 deposited to a desired thickness using a HfCl 4 precursor. This desired thickness is between about 3 and 10 nm in a preferred embodiment. The purpose of this step is to create a "bulk" HfO 2 film having a high dielectric constant is expected.

本発明のこの方法の製造プロセスは、エッチングプロセスまたはＣＭＰのいずれかが続く、ゲート材料、例えば、ゲート金属の堆積を進める。残りの工程は、当業者にとって周知の従来の製造プロセスである。本発明の方法は、最初の低κ界面層の必要性をなくし、依然として、高誘電率の膜を達成する。   The manufacturing process of this method of the invention proceeds with the deposition of the gate material, eg, gate metal, followed by either an etching process or CMP. The remaining steps are conventional manufacturing processes well known to those skilled in the art. The method of the present invention eliminates the need for an initial low-κ interface layer and still achieves a high dielectric constant film.

ＨｆＯ２膜Ａが、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤの１回のサイクルを介して堆積され、その後、ＨｆＣｌ４前駆物質を用いるＡＬＤの４０回のサイクルが続いた。比較として、ＨｆＯ２膜Ｂが、１回のサイクルのＨｆ（ＮＯ３）４前駆物質を用いるＡＬＤ工程（ＡＬＤ硝酸工程）なしに、ＨｆＣｌ４前駆物質を用いるＡＬＤの４０回のサイクルのみを用いて堆積された。分光楕円偏光計測定によって、最初のＡＬＤ硝酸工程を用いて堆積されたＨｆＯ２膜Ａは、平均の厚さが８．０ｎｍであり、標準偏差が０．５ｎｍであったことが明らかにされた。ＡＬＤ硝酸工程なしで堆積されたＨｆＯ２膜Ｂは、平均の厚さが４．２ｎｍであり、標準偏差が１．８ｎｍであった。ＨｆＯ２膜ＡがＨｆＯ２膜Ｂよりも滑らかであり、厚いという事実は、本発明の方法の有用性を示している。すなわち、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤの１サイクルによって、後のＨｆＣｌ４前駆物質を用いるＡＬＤの開始層が有効に提供される。ＨｆＯ２膜Ａがより厚いという事実は、ＨｆＣｌ４ＡＬＤの典型的な「育成」期間が必要ないということを示す。 HfO 2 film A was deposited via one cycle of ALD with Hf (NO 3 ) 4 precursor, followed by 40 cycles of ALD with HfCl 4 precursor. As a comparison, the HfO 2 film B was prepared using only 40 ALD cycles using the HfCl 4 precursor without the ALD step using one cycle of the Hf (NO 3 ) 4 precursor (ALD nitric acid step). Deposited. Spectroscopic ellipsometer measurements revealed that the HfO 2 film A deposited using the first ALD nitric acid step had an average thickness of 8.0 nm and a standard deviation of 0.5 nm. . The HfO 2 film B deposited without the ALD nitric acid step had an average thickness of 4.2 nm and a standard deviation of 1.8 nm. The fact that HfO 2 film A is smoother and thicker than HfO 2 film B demonstrates the utility of the method of the present invention. That is, one cycle of ALD using the Hf (NO 3 ) 4 precursor effectively provides a starting layer for ALD using the subsequent HfCl 4 precursor. The fact that the HfO 2 film A is thicker indicates that the typical “growth” period of HfCl 4 ALD is not required.

Ｈｆ（ＮＯ３）４を用いる、１回、または１〜５回までのＡＬＤサイクルで堆積された層は、他の前駆物質、例えば、ＭＩ４、ＭＢｒ４などのハロゲン化金属（Ｍは金属元素を表す）、または、アルコキシド、アセチルアセトネート、ｔ−ブトキシド、エトキシドなどの有機金属を用いるＡＬＤの開始層として用いられ得る。本明細書中に記載のＨｆＯ２処理に加えて、他の金属酸化物、例えば、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、Ａｌ２Ｏ３などが堆積され得る。 Layers deposited in one or up to one to five ALD cycles using Hf (NO 3 ) 4 may be coated with other precursors, for example, metal halides such as MI 4 , MBr 4 (M is a metal element). Or an ALD starting layer using an organic metal such as alkoxide, acetylacetonate, t-butoxide, and ethoxide. In addition to the HfO 2 treatment described herein, other metal oxides such as ZrO 2 , Gd 2 O 3 , La 2 O 3 , CeO 2 , TiO 2 , Y 2 O 3 , Ta 2 O 5 , Al 2 O 3, etc. may be deposited.

集積回路において、高κ誘電材料の層を形成する方法は、シリコン基板を準備する工程と、硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、集積回路を完成させる工程とを含む。 上記のように、ＣＭＯＳアプリケーション用の多重高κゲート誘電体を堆積する方法が開示されてきた。この方法のさらなる変形および改変が、添付の特許請求の範囲に記載の発明の範囲内で行われ得ることが理解される。   In an integrated circuit, a method of forming a layer of a high-κ dielectric material includes providing a silicon substrate, depositing a first metal oxide layer using ALD using a metal nitrate precursor, Depositing another metal oxide layer using ALD with a precursor, and completing the integrated circuit. As described above, methods for depositing multiple high-κ gate dielectrics for CMOS applications have been disclosed. It is understood that further variations and modifications of this method can be made within the scope of the claimed invention.

本発明の方法は、Ｈｆ（ＮＯ３）４の１回、または１〜５回までのサイクルで、Ｈ終端シリコン上のＡＬＤ堆積を開始し、その後、ＨｆＣｌ４のような他の前駆物質を用いて、所望の厚さまで、残りの膜のＡＬＤ堆積が続く。本発明の方法によって、最初の低κ界面層が必要なくなるが、依然として、高誘電率の「バルク」膜が達成されるようになる。 The method of the present invention, Hf (NO 3) 4 1 times, or in cycles of up to 5 times, to begin ALD deposition on H-terminated silicon, then using other precursors, such as HfCl 4 Then, ALD deposition of the remaining film continues to the desired thickness. The method of the present invention eliminates the need for an initial low-κ interface layer, but still achieves a high dielectric constant "bulk" film.

図１は、Ｈ終端シリコン表面を有するシリコン基板を表す図である。FIG. 1 is a diagram illustrating a silicon substrate having an H-terminated silicon surface. 図２は、最初のＨｆＯ２層の堆積後の基板を表す図である。FIG. 2 shows the substrate after the deposition of the first HfO 2 layer. 図３は、第２および最後のＨｆＯ２層の堆積後の構造を表す図である。FIG. 3 shows the structure after the deposition of the second and last HfO 2 layers.

符号の説明Explanation of reference numerals

１０ シリコン基板
１２ フィールド酸化物領域
１４ フィールド酸化物領域
１６ Ｈ終端シリコン表面 Reference Signs List 10 silicon substrate 12 field oxide region 14 field oxide region 16 H-terminated silicon surface

Claims (17)

集積回路において高κ誘電材料の層を形成する方法であって、
シリコン基板を準備する工程と、
硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、
塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、
該集積回路を完成させる工程と
を包含する、方法。 A method of forming a layer of a high-κ dielectric material in an integrated circuit, comprising:
Preparing a silicon substrate;
Depositing a first metal oxide layer using ALD with a metal nitrate precursor;
Depositing a layer of another metal oxide using ALD with a metal chloride precursor;
Completing the integrated circuit. 前記準備する工程は、前記シリコン基板のＨ終端表面を形成する工程を含む、請求項１に記載の方法。   The method of claim 1, wherein the preparing comprises forming an H-terminated surface of the silicon substrate. 前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含む、請求項２に記載の方法。   3. The method of claim 2, wherein said forming comprises exposing said silicon surface with HF. 前記第１の金属酸化物の層を堆積する工程は、１〜５回のＡＬＤサイクルを用いて、金属酸化物の層を堆積する工程を含む、請求項１に記載の方法。   The method of claim 1, wherein depositing the first metal oxide layer comprises depositing the metal oxide layer using 1 to 5 ALD cycles. 前記他の金属酸化物の層を堆積する工程は、複数のＡＬＤサイクルを用いて、金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程を含む、請求項１に記載の方法。 2. The method of claim 1, wherein depositing the other metal oxide layer comprises depositing the metal oxide layer using a plurality of ALD cycles to obtain a desired metal oxide layer thickness. the method of. ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含む、請求項１に記載の方法。 The metal oxide selected from the group consisting of HfO 2 , ZrO 2 , Gd 2 O 3 , La 2 O 3 , CeO 2 , TiO 2 , Y 2 O 3 , Ta 2 O 5 , and Al 2 O 3 The method of claim 1 including selecting a metal oxide to be deposited on a silicon substrate. 前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含む、請求項１に記載の方法。   The method of claim 1, wherein depositing the first metal oxide layer comprises depositing an initial metal oxide layer between about 0.1 nm and 1.5 nm thick. . 前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含む、請求項１に記載の方法。   The method of claim 1, wherein depositing the other metal oxide layer comprises depositing a metal oxide layer between about 3 nm and 10 nm thick. 集積回路において高κ誘電ゲート酸化物の層を形成する方法であって、
シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、
硝酸金属前駆物質を用いるＡＬＤを１〜５回用いて第１の金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、
塩化金属前駆物質を用いるＡＬＤを複数回用いて他の金属酸化物の層を堆積する工程と、
該集積回路を完成させる工程と
を包含する、方法。 A method of forming a layer of a high-κ dielectric gate oxide in an integrated circuit, comprising:
A step of preparing a silicon substrate, comprising the step of forming an H-terminated surface of the silicon substrate;
Depositing a first metal oxide layer using ALD using a metal nitrate precursor one to five times to obtain a desired metal oxide layer thickness;
Depositing another metal oxide layer using ALD with a metal chloride precursor multiple times;
Completing the integrated circuit. 前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含む、請求項９に記載の方法。   The method of claim 9, wherein the forming comprises exposing the silicon surface with HF. ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含む、請求項９に記載の方法。 The metal oxide selected from the group consisting of HfO 2 , ZrO 2 , Gd 2 O 3 , La 2 O 3 , CeO 2 , TiO 2 , Y 2 O 3 , Ta 2 O 5 , and Al 2 O 3 The method of claim 9, comprising selecting a metal oxide to be deposited on a silicon substrate. 前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含む、請求項９に記載の方法。   10. The method of claim 9, wherein depositing the first metal oxide layer comprises depositing an initial metal oxide layer between about 0.1 nm and 1.5 nm thick. . 前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含む、請求項９に記載の方法。   The method of claim 9, wherein depositing the other metal oxide layer comprises depositing a metal oxide layer between about 3 nm and 10 nm thick. 集積回路においてＨｆＯ２高κ誘電ゲート酸化物の層を形成する方法であって、
シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、
Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤを１〜５回用いて第１のＨｆＯ２金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、
ＨｆＣｌ４前駆物質を用いるＡＬＤを複数回用いて他のＨｆＯ２の層を堆積する工程と、
該集積回路を完成させる工程と
を包含する、方法。 A method for forming a layer of HfO 2 high-κ dielectric gate oxide in an integrated circuit, comprising:
A step of preparing a silicon substrate, comprising the step of forming an H-terminated surface of the silicon substrate;
Depositing a first HfO 2 metal oxide layer using ALD using a Hf (NO 3 ) 4 precursor 1 to 5 times to obtain a desired metal oxide layer thickness;
Depositing another layer of HfO 2 using ALD with a HfCl 4 precursor multiple times;
Completing the integrated circuit. 前記形成する工程は、前記シリコン表面をＨＦに露出させる工程を含む、請求項１４に記載の方法。   15. The method of claim 14, wherein said forming comprises exposing said silicon surface to HF. 前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含む、請求項１４に記載の方法。   15. The method of claim 14, wherein depositing the first metal oxide layer comprises depositing a first metal oxide layer between about 0.1 nm and 1.5 nm thick. . 前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含む、請求項１４に記載の方法。   15. The method of claim 14, wherein depositing the other metal oxide layer comprises depositing a metal oxide layer between about 3 nm and 10 nm thick.
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