JP2004134813A - Semiconductor device mounting method and semiconductor device repair method - Google Patents

Semiconductor device mounting method and semiconductor device repair method Download PDF

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JP2004134813A
JP2004134813A JP2004012976A JP2004012976A JP2004134813A JP 2004134813 A JP2004134813 A JP 2004134813A JP 2004012976 A JP2004012976 A JP 2004012976A JP 2004012976 A JP2004012976 A JP 2004012976A JP 2004134813 A JP2004134813 A JP 2004134813A
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hole
semiconductor device
solder ball
heating
terminal
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JP3942596B2 (en
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Takashi Noguchi
野口　高
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device mounting method which can reduce a defect occurrence rate and a semiconductor device repair method which can readily repair the defects at a soldering joint part. <P>SOLUTION: On a substrate 1, a penetrating hole 7 provided with a wiring layer 9 inside is formed, and a soldering ball 6 is so fused to cover the penetrating hole 7. In a mounting process or a repair process, a heating probe 41 is stuck into the soldering ball 6 through the penetrating hole 7 to melt the soldering ball 6, and after that, the heating probe 41 is pulled out and the soldering ball 6 is coagulated. According to this process, only the soldering ball 6 is heated without having any adverse effect on an IC chip 3. Also, in the repair process, the soldering ball 6 can be restored to the initial condition with no inter-metallic compound. <P>COPYRIGHT: (C)2004,JPO

Description

　本発明は、ボールグリッドアレイパッケージ（ＢＧＡ）構造を持つ半導体装置の実装方法及びリペア方法に関するものである。 The present invention relates to a method for mounting and repairing a semiconductor device having a ball grid array package (BGA) structure.

　図２６は、従来のキャビティダウン型（Cavity Down Type）のＢＧＡ構造を持つ半導体装置を概略的に示す断面図である。 FIG. 26 is a cross-sectional view schematically showing a conventional semiconductor device having a cavity down type BGA structure.

　図２６に示されるように、従来の半導体装置は、電気的配線回路が形成された基板１０１と、基板１０１の中央開口部１０１ａ周辺に接着剤で接着された銅板等からなるヒートスラグ１０２とを有する。また、従来の半導体装置は、ヒートスラグ１０２に接着剤で接着されたＩＣチップ１０３と、ＩＣチップ１０３と基板１０１の配線とを電気的に接続する金属細線１０４と、ＩＣチップ１０３及び金属細線１０４を封止するエポキシ樹脂等の封止体１０５と、基板１０１の表面（図２６における下面）に格子状に配列された外部端子としての半田ボール１０６とを有する。基板１０１は、積層された複数枚（図２６には３枚の場合を示す。）の絶縁基板１１１，１１２，１１３と、これら絶縁基板１１１，１１２，１１３の間に挟まれた配線層１１４と、配線層１１４と半田ボール１０６とを電気的に接続する配線１１５とを有する。 As shown in FIG. 26, a conventional semiconductor device includes a substrate 101 on which an electric wiring circuit is formed, and a heat slug 102 made of a copper plate or the like bonded around the central opening 101a of the substrate 101 with an adhesive. Have. Further, a conventional semiconductor device includes an IC chip 103 bonded to a heat slug 102 with an adhesive, a thin metal wire 104 for electrically connecting the IC chip 103 and a wiring of the substrate 101, an IC chip 103 and a thin metal wire 104. And a solder ball 106 as an external terminal arranged in a grid on the surface of the substrate 101 (the lower surface in FIG. 26). The substrate 101 includes a plurality of laminated (three in FIG. 26) insulating substrates 111, 112, and 113, and a wiring layer 114 sandwiched between the insulating substrates 111, 112, and 113. , And a wiring 115 for electrically connecting the wiring layer 114 and the solder ball 106.

　図２７は、図２６の半導体装置の実装工程を示す説明図である。 FIG. 27 is an explanatory view showing a mounting step of the semiconductor device of FIG. 26.

　図２７に示されるように、従来の半導体装置の実装工程においては、プリント基板であるマザーボード１２１の端子（図２７には示さず。）に、半田ペースト（微小な粒状の半田と活性剤（フラックス）とから構成される）（図２７には示さず。）を塗布し、その上に半導体装置の半田ボール１０６を重ね、マザーボード１２１の裏面からヒータプレート１３１で加熱し、マザーボード１２１と半導体装置の間にホットエアー１３２を流し、半田ボール１０６をマザーボード１２１の端子に融着させる。 As shown in FIG. 27, in a conventional semiconductor device mounting process, a terminal (not shown in FIG. 27) of a mother board 121, which is a printed circuit board, is connected to a solder paste (a fine granular solder and an activator (flux). (Not shown in FIG. 27). The solder balls 106 of the semiconductor device are superimposed thereon, and heated from the back surface of the motherboard 121 by the heater plate 131, so that the motherboard 121 and the semiconductor device are heated. Hot air 132 is flowed in between to fuse the solder balls 106 to the terminals of the motherboard 121.

　ところで、ＢＧＡ構造を持つ半導体装置の実装不良率は低いものの、実装不良が生じる場合がある。また、図２８に示されるように、半導体装置の実装後の温度変化（主に、１５０℃以下の範囲内における温度変化）によりに半田接合部に半田ボール１０６の成分であるＳｎと端子（半導体装置の端子１３３及びマザーボードの端子１３４）の成分であるＡｕ及びＮｉとの金属間化合物（例えば、ＡｕＳｎＮｉ）層１０６ａが形成される場合がある。また、金属間化合物層は、時間経過に伴って厚さを増す傾向がある。この金属間化合物は、脆い物質であるため、基板１０１とマザーボード１２１との熱膨張係数の違いによって、半田接合部に応力が集中し、図２９（ａ）及び（ｂ）に示されるように、半田接合部に亀裂１３５や、亀裂がさらに進行した剥がれ１３６が生じる場合がある。 By the way, although a semiconductor device having a BGA structure has a low mounting failure rate, a mounting failure may occur. Further, as shown in FIG. 28, due to a temperature change after the mounting of the semiconductor device (mainly, a temperature change within a range of 150 ° C. or less), Sn as a component of the solder ball 106 and a terminal (semiconductor) are connected to the solder joint. An intermetallic compound (for example, AuSnNi) 106 a with Au and Ni which are components of the terminal 133 of the device and the terminal 134 of the motherboard may be formed. Further, the thickness of the intermetallic compound layer tends to increase with time. Since this intermetallic compound is a brittle substance, stress is concentrated on the solder joint due to a difference in the coefficient of thermal expansion between the substrate 101 and the motherboard 121, and as shown in FIGS. 29 (a) and (b), Cracks 135 and peeling 136 where the cracks have further progressed may occur at the solder joint.

　このような半導体装置（製造段階の性能試験で不合格判定となったものや、製品として出荷した後に不具合が発生したもの）に実施されるリペア方法としては、図２７に示される実装工程と同様の工程により、半田ボール１０６を加熱し、半導体装置を取り外し、マザーボード１２１上の余分な半田を除去し、新しい半導体装置を取り付ける方法が一般的であった。 A repair method performed on such a semiconductor device (one that has been rejected in the performance test at the manufacturing stage or one that has failed after being shipped as a product) is the same as the mounting method shown in FIG. In the above process, the solder ball 106 is heated, the semiconductor device is removed, excess solder on the motherboard 121 is removed, and a new semiconductor device is attached.

　しかしながら、上記した従来の半導体装置の実装工程においては、ホットエアー１３２により半田ボール１０６を溶解させる工程を用いるので、基板や接着剤、封止樹脂に吸湿された水分が高温により爆発（ポップコーン現象）し、封止樹脂にクラックや、チップと封止樹脂との間に剥離を発生させるおそれがある。 However, in the above-described conventional semiconductor device mounting process, a process of dissolving the solder ball 106 with hot air 132 is used, so that moisture absorbed by the substrate, the adhesive, and the sealing resin explodes due to high temperature (popcorn phenomenon). However, there is a possibility that cracks may occur in the sealing resin or separation may occur between the chip and the sealing resin.

　また、上記した従来の半導体装置のリペア方法は、不合格判定がされた又は不具合が発生した半導体装置をマザーボードから取り外し、新しい半導体装置に交換するというものであり、取り外された半導体装置が再利用されていないという問題がある。 Further, the above-described conventional semiconductor device repair method involves removing a failed semiconductor device or a defective semiconductor device from a motherboard and replacing it with a new semiconductor device, and the removed semiconductor device is reused. There is a problem that is not.

　そこで、本発明は上記したような従来技術の課題を解決するためになされたものであり、その目的は、半導体装置の不具合発生率を低減できる半導体装置の実装方法を提供することにある。 Therefore, an object of the present invention is to solve the above-described problems of the related art, and an object of the present invention is to provide a semiconductor device mounting method capable of reducing a failure occurrence rate of the semiconductor device.

　また、本発明の他の目的は、半導体装置を交換することなく、半導体装置の半田接合部の不良を容易に修理することができる半導体装置のリペア方法を提供することにある。 Another object of the present invention is to provide a semiconductor device repair method that can easily repair a defect in a solder joint of a semiconductor device without replacing the semiconductor device.

　本発明に係る半導体装置の実装方法は、
　端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記貫通穴の内表面に備えられた第１の配線層と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールとを有する半導体装置を、前記半田ボールがプリント基板の端子上に載るように、前記プリント基板上に置く工程と、
　加熱装置の加熱プローブを前記第２の面側から前記貫通穴に挿入し、前記半田ボールに突き刺して、前記半田ボールを溶融させる工程と、
　加熱装置の加熱プローブを前記半田ボールから抜き出して、前記半田ボールを凝固させる工程とを有するものである。 The method for mounting a semiconductor device according to the present invention includes:
A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; A first wiring layer connected to the terminal, the first wiring layer provided on the inner surface of the through hole, the first wiring layer connected to the terminal, and the first surface on the first surface. A semiconductor device having a solder ball provided so as to cover the through hole, so that the solder ball rests on a terminal of the printed board, and placing the semiconductor device on the printed board;
Inserting a heating probe of a heating device into the through hole from the second surface side, piercing the solder ball, and melting the solder ball;
Extracting a heating probe of a heating device from the solder ball to solidify the solder ball.

　また、他の発明に係る半導体装置の実装方法は、
　端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールと、前記貫通穴内に形成され、かつ、一端を前記半田ボールに接触させ、他端を外部の加熱装置の発熱部に接触可能なように前記第２の面付近に配置した熱伝導部材とを有する半導体装置を、前記半田ボールがプリント基板の端子上に載るように、前記プリント基板上に置く工程と、
　加熱装置により前記熱伝導部材を加熱して、前記半田ボールを溶融させる工程と、
　加熱装置による前記熱伝導部材の加熱を停止して、前記半田ボールを凝固させる工程とを有するものである。 Further, a mounting method of a semiconductor device according to another invention is as follows.
A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; And a solder ball connected to the terminal and provided on the first surface so as to cover the through hole, and formed in the through hole, and A semiconductor device having a heat conducting member disposed near the second surface such that one end is in contact with the solder ball and the other end is in contact with a heat generating portion of an external heating device. Placing on the printed board so as to be placed on the terminals of the board,
Heating the heat conductive member by a heating device, and melting the solder ball;
Stopping the heating of the heat conducting member by a heating device to solidify the solder balls.

　また、他の発明に係る半導体装置のリペア方法は、
　端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記貫通穴の内表面に備えられた第１の配線層と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールとを有する半導体装置であって、プリント基板の端子に前記半田ボールを融着させた前記半導体装置のリペア方法であって、
　加熱装置の加熱プローブを前記第２の面側から前記貫通穴に挿入し、前記半田ボールに突き刺して、前記半田ボールを溶融させる工程と、
　加熱装置の加熱プローブを前記半田ボールから抜き出して、前記半田ボールを凝固させる工程とを有するものである。 Further, a method for repairing a semiconductor device according to another invention includes:
A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; A first wiring layer connected to the terminal, the first wiring layer provided on the inner surface of the through hole, the first wiring layer connected to the terminal, and the first surface on the first surface. A solder ball provided so as to cover the through-hole, a method for repairing the semiconductor device, wherein the solder ball is fused to a terminal of a printed circuit board,
Inserting a heating probe of a heating device into the through hole from the second surface side, piercing the solder ball, and melting the solder ball;
Extracting a heating probe of a heating device from the solder ball to solidify the solder ball.

　また、他の発明に係る半導体装置のリペア方法は、
　端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールと、前記貫通穴内に形成され、かつ、一端を前記半田ボールに接触させ、他端を外部の加熱装置の発熱部に接触可能なように前記第２の面付近に配置した熱伝導部材とを有する半導体装置であって、プリント基板の端子に前記半田ボールを融着させた前記半導体装置のリペア方法であって、
　加熱装置により前記熱伝導部材を加熱して、前記半田ボールを溶融させる工程と、
　加熱装置による前記熱伝導部材の加熱を停止して、前記半田ボールを凝固させる工程とを有するものである。 Further, a method for repairing a semiconductor device according to another invention includes:
A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; And a solder ball connected to the terminal and provided on the first surface so as to cover the through hole, and formed in the through hole, and A heat conductive member disposed near the second surface such that one end is in contact with the solder ball and the other end is capable of contacting a heating portion of an external heating device. A method for repairing the semiconductor device, wherein the solder balls are fused to terminals,
Heating the heat conductive member by a heating device, and melting the solder ball;
Stopping the heating of the heat conducting member by a heating device to solidify the solder balls.

　本発明に係る半導体装置の実装方法によれば、半導体装置の実装に伴う不具合発生率を低減できる。 According to the method of mounting a semiconductor device according to the present invention, it is possible to reduce the rate of occurrence of defects accompanying the mounting of the semiconductor device.

　また、本発明に係る半導体装置のリペア方法によれば、半導体装置を交換することなく、半導体装置の半田接合部の不良を容易に修理することができる。 According to the method of repairing a semiconductor device according to the present invention, it is possible to easily repair a defect in a solder joint of the semiconductor device without replacing the semiconductor device.

　また、半導体装置の貫通穴に充填部を備えた場合には、異物の侵入に起因する半田接合部の劣化を防止できる。 In addition, in the case where the filling portion is provided in the through hole of the semiconductor device, it is possible to prevent the deterioration of the solder joint portion due to the invasion of foreign matter.

　また、貫通穴に固定プローブを備えた場合には、半田ボールの加熱装置の構成を簡素化できる。 In addition, when the fixed probe is provided in the through hole, the configuration of the solder ball heating device can be simplified.

　また、貫通穴に固定プローブを備え、端部を基板側面に露出させた場合には、半導体基板を重ねて実装する３次元実装が可能になる。 In the case where the fixed probe is provided in the through hole and the end is exposed on the side surface of the substrate, three-dimensional mounting in which semiconductor substrates are stacked and mounted becomes possible.

≪第１の実施形態≫
＜第１の実施形態に係る半導体装置の構造＞
　図１は、本発明の第１の実施形態に係る半導体装置の上面（ヒートシンク２を備えた面）を概略的に示す平面図であり、図２は、図１の半導体装置をＳ２−Ｓ２線で切る面を概略的に示す断面図であり、図３は、図１の半導体装置の下面（半田ボール６を備えた面）を概略的に示す平面図である。また、図４は、図１の半導体装置の上面の貫通穴７付近を拡大して示す平面図であり、図５は、図１の半導体装置の端子８と半田ボール６の接合部を拡大して示す断面図である。 << 1st Embodiment >>
<Structure of Semiconductor Device According to First Embodiment>
1, the upper surface of the semiconductor device according to a first embodiment of the present invention (the surface having the heat sink 2) is a plan view schematically illustrating, FIG. 2, the semiconductor device of FIG. 1 S 2 -S FIG. 3 is a cross-sectional view schematically showing a surface cut by two lines, and FIG. 3 is a plan view schematically showing a lower surface (a surface provided with solder balls 6) of the semiconductor device of FIG. FIG. 4 is an enlarged plan view showing the vicinity of the through hole 7 on the upper surface of the semiconductor device of FIG. 1, and FIG. 5 is an enlarged view of a joint between the terminal 8 and the solder ball 6 of the semiconductor device of FIG. FIG.

　図１から図３までに示されるように、第１の実施形態に係る半導体装置は、電気的配線回路が形成された基板１を有する。基板１は、積層された複数枚（図２には３枚の場合を示す。）の絶縁基板１１，１２，１３と、これら絶縁基板１１，１２，１３の間に挟まれた配線層１４とを有する。ただし、絶縁基板の枚数は３枚に限定されず、絶縁基板の形状も四角形に限定されない。 As shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment has a substrate 1 on which an electric wiring circuit is formed. The substrate 1 includes a plurality of (three in FIG. 2) insulating substrates 11, 12 and 13 stacked, and a wiring layer 14 sandwiched between these insulating substrates 11, 12, and 13. Having. However, the number of insulating substrates is not limited to three, and the shape of the insulating substrate is not limited to a square.

　また、図１から図３までに示されるように、第１の実施形態に係る半導体装置は、基板１の上面１ｃ（図２における上側の面）の中央開口部１ａ周辺に接着剤で接着された銅板等からなるヒートスラグ２と、ヒートスラグ２に接着剤で接着されたＩＣチップ３と、ＩＣチップ３と基板１の配線とを電気的に接続（即ち、ワイヤーボンド）する金属細線４と、ＩＣチップ３及び金属細線４を封止するエポキシ樹脂等の封止体５と、基板１の下面１ｂ（図２における下側の面）に格子状に配列された外部端子としての複数の半田ボール６とを有する。このように、第１の実施形態に係る半導体装置は、放熱性を向上させたキャビティダウン型の構造を持つ。ただし、半導体装置の構造は、キャビティアップ型等のような他の構造であってもよい。また、半田ボール６の配列及び数も、図示のものに限定されない。 As shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment is bonded to the periphery of the central opening 1a of the upper surface 1c (the upper surface in FIG. 2) of the substrate 1 with an adhesive. A heat slug 2 made of a copper plate or the like, an IC chip 3 adhered to the heat slug 2 with an adhesive, and a thin metal wire 4 for electrically connecting (that is, wire bonding) the IC chip 3 to the wiring of the substrate 1. , A sealing body 5 such as an epoxy resin for sealing the IC chip 3 and the thin metal wires 4, and a plurality of solders as external terminals arranged in a grid on the lower surface 1 b (the lower surface in FIG. 2) of the substrate 1. And a ball 6. As described above, the semiconductor device according to the first embodiment has a cavity-down type structure with improved heat dissipation. However, the structure of the semiconductor device may be another structure such as a cavity-up type. Also, the arrangement and number of the solder balls 6 are not limited to those shown in the figure.

　さらに、図１から図５までに示されるように、第１の実施形態に係る半導体装置は、基板１の上面１ｃと下面１ｂとを繋ぐように、基板１に形成された貫通穴７と、基板１の下面１ｂの端子８に接続され、貫通穴７の内表面に備えられた配線層９とを有する。貫通穴７は、金型を用いた打ち抜き加工又はドリルによるミーリング加工により形成される。端子８は、例えば、下層（基板１側）から上層に向けてＣｕ層、Ｎｉ層、Ａｕ層を順に積層させた構造を持つ。配線層９は、例えば、メッキ工程によって形成されたＣｕ配線層である。また、図５に示されるように、半田ボール６は、端子８に融着されており、基板１の下面１ｂ上に貫通穴７を覆うように配置されている。なお、半田ボール６と端子８との融着は、端子８上に活性剤（フラックス）を塗布し、それに半田ボール８を重ね、加熱するという手順で実行される。 Further, as shown in FIGS. 1 to 5, the semiconductor device according to the first embodiment has a through hole 7 formed in the substrate 1 so as to connect the upper surface 1c and the lower surface 1b of the substrate 1, A wiring layer connected to the terminal on the lower surface of the substrate and provided on the inner surface of the through hole; The through-hole 7 is formed by punching using a die or milling using a drill. The terminal 8 has, for example, a structure in which a Cu layer, a Ni layer, and an Au layer are sequentially stacked from a lower layer (substrate 1 side) to an upper layer. The wiring layer 9 is, for example, a Cu wiring layer formed by a plating process. As shown in FIG. 5, the solder balls 6 are fused to the terminals 8 and are arranged on the lower surface 1b of the substrate 1 so as to cover the through holes 7. The fusion of the solder ball 6 with the terminal 8 is performed by applying an activator (flux) on the terminal 8, stacking the solder ball 8 on the activator, and heating.

　なお、図には、貫通穴７が基板１の表面に垂直な方向に延びている場合を示しているが、貫通穴７の方向を基板１の表面に対して傾斜させることも可能である。貫通穴７の方向及び形状は、後述する加熱装置の加熱プローブが貫通穴７を通して半田ボール６に接触可能なものであれば、いかなる方向及び形状であってもよい。 Although the drawing shows a case where the through-hole 7 extends in a direction perpendicular to the surface of the substrate 1, the direction of the through-hole 7 can be inclined with respect to the surface of the substrate 1. The direction and shape of the through hole 7 may be any direction and shape as long as a heating probe of a heating device described later can contact the solder ball 6 through the through hole 7.

＜第１の実施形態に係る半導体装置のリペア方法＞
　図６から図８までは、プリント回路としてのマザーボード２１に搭載された第１の実施形態に係る半導体装置のリペア工程（その１〜３）を示す断面図である。また、図９（ａ）及び（ｂ）のそれぞれは、リペア工程を実施する前と後の半田ボール６の状態を示す説明図である。 <Repair method of semiconductor device according to first embodiment>
FIGS. 6 to 8 are cross-sectional views illustrating repair steps (Nos. 1 to 3) of the semiconductor device according to the first embodiment mounted on the motherboard 21 as a printed circuit. FIGS. 9A and 9B are explanatory diagrams showing states of the solder balls 6 before and after the repair process is performed.

　第１の実施形態に係るリペア方法が適用される半導体装置は、図６に示されるように、マザーボード２１の端子（図９の符号２２）に半導体装置の半田ボール６を重ね、融着させたものである。融着の方法は、例えば、図２７に示される従来の方法、後述する図１１から図１３までによって説明される実装方法のいずれでもよい。リペアの実施対象となる半導体装置は、製造段階における性能試験において不合格判定された半導体装置と、製品として出荷した後に不具合が発生した半導体装置とがある。 As shown in FIG. 6, in the semiconductor device to which the repair method according to the first embodiment is applied, the solder balls 6 of the semiconductor device are overlaid on terminals (reference numeral 22 in FIG. 9) of the motherboard 21 and fused. Things. For example, the fusion method may be any of the conventional method shown in FIG. 27 and the mounting method described later with reference to FIGS. Semiconductor devices to be repaired include semiconductor devices that have been rejected in a performance test in a manufacturing stage and semiconductor devices that have failed after being shipped as a product.

　第１の実施形態に係るリペア方法においては、図６に示されるような、半田ボール６を加熱するための加熱装置を使用する。加熱装置は、加熱プローブ４１の端部４１ｂを保持する発熱部４２と、発熱部４２を水平方向に移動及び垂直方向に移動（昇降）させるを移動機構４３とを有する。加熱プローブ４１は、熱伝導性が良好で、半田ボール６との濡れ性が良好な材料で構成される。好適な材料としては、銅、銀、白金等の金属、Ｚｒ−Ｃｕ、Ｆｅ−Ｃｕ、Ｎｉ−Ｃｕ等の銅合金、４２アロイ（４２％Ｎｉ―Ｆｅ）等の鉄合金等がある。また、加熱プローブ４１の先端は、図６に符号４１ａで示されるように、鋭角に形成されているが、先端を球状又は平坦に形成してもよい。 In the repair method according to the first embodiment, a heating device for heating the solder balls 6 as shown in FIG. 6 is used. The heating device has a heating unit 42 that holds the end 41 b of the heating probe 41 and a moving mechanism 43 that moves the heating unit 42 in the horizontal direction and the vertical direction (elevation). The heating probe 41 is made of a material having good thermal conductivity and good wettability with the solder ball 6. Suitable materials include metals such as copper, silver and platinum, copper alloys such as Zr-Cu, Fe-Cu and Ni-Cu, and iron alloys such as 42 alloy (42% Ni-Fe). The tip of the heating probe 41 is formed at an acute angle as shown by reference numeral 41a in FIG. 6, but may be formed spherical or flat.

　第１の実施形態に係るリペア方法は以下のとおりである。先ず、図６に示される加熱装置の加熱プローブ４１を加熱し（１８０℃〜３５０℃程度の範囲内の所定温度であり、半田ボール６の組成等によって異なる。また、通常は、約２４０℃である。）を、半導体装置の貫通穴７の上部から下降させて、貫通穴７に挿入し、図７に示されるように、半田ボール６に突き刺して、半田ボール６を溶融させる。その後、図８に示されるように、加熱装置の加熱プローブ４１を半田ボール６から抜き出し、半田ボール６を凝固させる。なお、このリペア工程において、図２７に示されるように、ホットプレート１３１及びエアブロー１３２の少なくとも一方を併用してもよい。 リ The repair method according to the first embodiment is as follows. First, the heating probe 41 of the heating device shown in FIG. 6 is heated (a predetermined temperature in a range of about 180 ° C. to 350 ° C., which varies depending on the composition of the solder ball 6 and the like. Is lowered from above the through hole 7 of the semiconductor device and inserted into the through hole 7, and pierces the solder ball 6, as shown in FIG. 7, to melt the solder ball 6. Thereafter, as shown in FIG. 8, the heating probe 41 of the heating device is extracted from the solder ball 6, and the solder ball 6 is solidified. In this repair step, at least one of the hot plate 131 and the air blow 132 may be used together as shown in FIG.

　このリペア工程により、図９（ａ）に示されるような半田ボール６の金属間化合物層６ａが破壊されて、図９（ｂ）に示されるように金属間化合物層が消滅した半田接合部となる。このため、脆い金属間化合物層６ａの存在に起因する半田ボール６と端子８又は２２との接触不良が解消される。 By this repair process, the intermetallic compound layer 6a of the solder ball 6 as shown in FIG. 9A is broken, and as shown in FIG. Become. Therefore, poor contact between the solder ball 6 and the terminal 8 or 22 due to the presence of the brittle intermetallic compound layer 6a is eliminated.

　なお、加熱プローブ４１の突き刺し及び抜き出しによって、半田ボール６の半田量が減少する場合には、加熱プローブ４１の挿入前に貫通穴７の上部からから粒状又は溶融した半田材料を追加してもよい。 When the solder amount of the solder ball 6 is reduced by piercing and extracting the heating probe 41, a granular or molten solder material may be added from above the through hole 7 before the heating probe 41 is inserted. .

　以上説明したように、第１の実施形態に係るリペア方法によれば、半導体装置を新しい半導体装置に交換することなく、半導体装置の半田ボール６の接合部の不良箇所を容易に修理することができる。また、加熱プローブ４１は、半田ボール６のみを加熱するので、他の部分（特に、ＩＣチップ３）に悪影響を与えることがない。 As described above, according to the repair method according to the first embodiment, it is possible to easily repair a defective portion of the joint portion of the solder ball 6 of the semiconductor device without replacing the semiconductor device with a new semiconductor device. it can. Further, since the heating probe 41 heats only the solder balls 6, it does not adversely affect other parts (in particular, the IC chip 3).

＜第１の実施形態に係る半導体装置の実装方法＞
　図１０は、第１の実施の形態に係る実装方法が適用される半導体装置を概略的に示す断面図である。 <Method of Mounting Semiconductor Device According to First Embodiment>
FIG. 10 is a cross-sectional view schematically showing a semiconductor device to which the mounting method according to the first embodiment is applied.

　図１０に示されるように、第１の実施形態に係る実装方法が適用される半導体装置は、基板１の端子８上にフラックスを塗布し、その上に半田ボール６を置き、加熱炉（図示せず）を通過させて半田ボール６の表面を部分的に溶融させて、半田ボール６を端子８に融着させたものである。 As shown in FIG. 10, in the semiconductor device to which the mounting method according to the first embodiment is applied, a flux is applied on the terminals 8 of the substrate 1, the solder balls 6 are placed thereon, and a heating furnace (FIG. (Not shown), the surface of the solder ball 6 is partially melted, and the solder ball 6 is fused to the terminal 8.

　図１１から図１３までは、第１の実施形態に係る半導体装置をマザーボード２１に実装する工程（その１〜３）を示す断面図である。 FIGS. 11 to 13 are cross-sectional views showing steps (Nos. 1 to 3) of mounting the semiconductor device according to the first embodiment on the motherboard 21. FIGS.

　第１の実施形態に係る半導体装置の実装方法においては、上記リペア方法で使用したものと同じ加熱装置を使用する。第１の実施形態に係る実装方法は、以下のとおりである。先ず、図１１に示されるように、マザーボード２１の端子上にフラックス（図示せず）を塗布し、次に、半田ボール６がマザーボード２１のフラックスが塗布された端子上に載るように、図１０の半導体装置をマザーボード２１上に置く。次に、加熱装置の加熱プローブ４１を加熱し（１８０℃〜３５０℃程度の範囲内の所定温度であり、半田ボール６の組成等によって異なる。また、通常は、約２４０℃である。）を、半導体装置の貫通穴７の上部から下降させて、貫通穴７に挿入し、図１２に示されるように、半田ボール６に突き刺して、半田ボール６を溶融させる。その後、図１３に示されるように、加熱装置の加熱プローブ４１を半田ボール６から抜き出し、半田ボール６を凝固させる。以上の工程により、半田ボール６は、マザーボード２１の端子に半田付けされる。なお、この実装工程において、図２７に示されるように、ホットプレート１３１及びエアブロー１３２の少なくとも一方を併用してもよい。 In the semiconductor device mounting method according to the first embodiment, the same heating device as that used in the repair method is used. The mounting method according to the first embodiment is as follows. First, as shown in FIG. 11, a flux (not shown) is applied to the terminals of the motherboard 21, and then, the solder balls 6 are placed on the terminals of the motherboard 21 to which the flux is applied, as shown in FIG. Is placed on the motherboard 21. Next, the heating probe 41 of the heating device is heated (a predetermined temperature in the range of about 180 ° C. to 350 ° C., which varies depending on the composition of the solder balls 6, etc., and is usually about 240 ° C.). Then, the semiconductor device is lowered from above the through hole 7 of the semiconductor device, inserted into the through hole 7, and pierces the solder ball 6, as shown in FIG. Thereafter, as shown in FIG. 13, the heating probe 41 of the heating device is extracted from the solder ball 6, and the solder ball 6 is solidified. Through the above steps, the solder balls 6 are soldered to the terminals of the motherboard 21. In this mounting step, at least one of the hot plate 131 and the air blow 132 may be used together as shown in FIG.

　なお、加熱プローブ４１の突き刺し及び抜き出しによって、半田ボール６の半田量が減少する場合には、加熱プローブ４１の挿入前に貫通穴７の上部からから粒状又は溶融した半田材料を追加してもよい。 When the solder amount of the solder ball 6 is reduced by piercing and extracting the heating probe 41, a granular or molten solder material may be added from above the through hole 7 before the heating probe 41 is inserted. .

　以上説明したように、第１の実施形態に係る実装方法によれば、加熱プローブ４１は、半田ボール６のみを加熱するので、他の部分（特に、ＩＣチップ３）に悪影響を与えることがない。このため、半導体装置の不具合発生率を低減させることができる。 As described above, according to the mounting method according to the first embodiment, since the heating probe 41 heats only the solder balls 6, it does not adversely affect other parts (in particular, the IC chip 3). . For this reason, the failure occurrence rate of the semiconductor device can be reduced.

＜第１の実施形態の変形例＞
　図１４は、半導体装置の貫通穴７にジェル状樹脂を充填した充填部１５を設けた第１の実施形態の変形例を示す断面図である。ジェル状樹脂としては、シリコーン系樹脂（例えば、東レ社製「ＪＣＲ６１１０」）やポリイミド系樹脂（例えば、日立化成社製「ＰＩＸ８２００」）を用いることができる。充填部１５は、貫通穴７の上部開口部からジェル状樹脂を注入することによって形成される。図１４に示すように、貫通穴７内に充填部１５を設けることによって、端子８や、半田ボール６の接合部の腐食等に起因する不具合や、外部からの異物（ゴミ等）の侵入に起因する不具合の発生を無くすることができる。 <Modification of First Embodiment>
FIG. 14 is a cross-sectional view showing a modification of the first embodiment in which the filling portion 15 in which the gel resin is filled in the through hole 7 of the semiconductor device is provided. As the gel resin, a silicone resin (for example, “JCR6110” manufactured by Toray Industries, Inc.) or a polyimide resin (for example, “PIX8200” manufactured by Hitachi Chemical Co., Ltd.) can be used. The filling portion 15 is formed by injecting a gel resin from an upper opening of the through hole 7. As shown in FIG. 14, the provision of the filling portion 15 in the through hole 7 prevents defects caused by corrosion of the terminal 8 and the joint portion of the solder ball 6 and entry of foreign matter (dust and the like) from the outside. It is possible to eliminate the occurrence of inconvenience.

　なお、図１４に示される半導体装置のリペア工程においては、加熱プローブ４１を充填部１５に突き刺し、半田ボール６まで到達させ、半田ボール６にプローブ４１を突き刺し、その後、加熱プローブ４１を抜き出す。このリペア工程によってジェル状樹脂が減少した場合には、貫通穴７の開口部からジェル状樹脂を補充する。 In the repairing process of the semiconductor device shown in FIG. 14, the heating probe 41 is pierced into the filling portion 15 to reach the solder ball 6, the probe 41 is pierced into the solder ball 6, and then the heating probe 41 is extracted. When the amount of the gel-like resin is reduced by the repair process, the gel-like resin is replenished from the opening of the through hole 7.

≪第２の実施形態≫
　図１５は、本発明の第２の実施形態に係る半導体装置に関するものであり、同図（ａ）は、半導体装置の貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、貫通穴付近を拡大して示す平面図である。 << 2nd Embodiment >>
FIGS. 15A and 15B relate to a semiconductor device according to a second embodiment of the present invention. FIG. 15A is a cross-sectional view schematically showing the vicinity of a through hole of the semiconductor device, and FIG. FIG. 4 is an enlarged plan view showing the vicinity of a through hole.

　第２の実施形態に係る半導体装置は、貫通穴７内に、貫通穴７を半円柱状にする電極部材１６を備えた点のみが、上記第１の実施形態の半導体装置と相違する。電極部材１６の形成方法としては、半円柱状の貫通穴を有する部材を製造して、基板１に形成された貫通穴に差し込む方法がある。第２の実施形態の半導体装置によれば、半田ボール６と電極部材１６とが接合されるので、接合面積が増加し、半田ボール６の接続強度が確保できる。その結果、半田ボール６の亀裂や剥がれが生じにくくなる。 The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment only in that the semiconductor device according to the second embodiment is provided with an electrode member 16 that makes the through hole 7 semi-cylindrical in the through hole 7. As a method for forming the electrode member 16, there is a method in which a member having a semi-cylindrical through hole is manufactured and inserted into the through hole formed in the substrate 1. According to the semiconductor device of the second embodiment, since the solder ball 6 and the electrode member 16 are joined, the joining area increases, and the connection strength of the solder ball 6 can be secured. As a result, cracks and peeling of the solder balls 6 are less likely to occur.

　第２の実施形態に係る半導体装置のリペア方法及び実装方法は、上記第１の実施形態の方法と同じである。なお、上記以外の点においては、第２の実施形態は、上記第１の実施形態と同じである。 リ The repair method and the mounting method of the semiconductor device according to the second embodiment are the same as those of the first embodiment. Except for the above points, the second embodiment is the same as the first embodiment.

　図１６は、本発明の第２の実施形態に係る半導体装置の変形例に関するものであり、同図（ａ）は、半導体装置の貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、貫通穴付近を拡大して示す平面図である。 FIG. 16 relates to a modification of the semiconductor device according to the second embodiment of the present invention, and FIG. 16A is a cross-sectional view schematically showing the vicinity of a through hole of the semiconductor device. (b) is an enlarged plan view showing the vicinity of the through hole.

　図１６の半導体装置は、半円柱状の貫通穴７にジェル状樹脂を充填した充填部１７を設けた点のみが、上記図１５の半導体装置と相違する。なお、充填部１７の材質及び役割は、上記第１の実施形態の充填部１５と同じである。 半導体 The semiconductor device of FIG. 16 differs from the semiconductor device of FIG. 15 only in that a filling portion 17 in which the semi-cylindrical through hole 7 is filled with a gel resin is provided. The material and role of the filling section 17 are the same as those of the filling section 15 of the first embodiment.

≪第３の実施形態≫
　図１７は、本発明の第３の実施形態に係る半導体装置に関するものであり、同図（ａ）は、貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、基板１の端子３１を示す平面図である。 << 3rd Embodiment >>
FIGS. 17A and 17B relate to a semiconductor device according to a third embodiment of the present invention. FIG. 17A is a cross-sectional view schematically showing the vicinity of a through hole, and FIG. 3 is a plan view showing a terminal 31 of FIG.

　第３の実施形態に係る半導体装置は、端子３１の開口部３１ａを半円状にした点のみが、上記第１の実施形態の半導体装置と相違する。第３の実施形態の半導体装置によれば、半田ボール６と端子３１とが接合されるので、接合面積が増加し、半田ボール６の接続強度が確保できる。その結果、半田ボール６の亀裂や剥がれが生じにくくなる。 The semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment only in that the opening 31a of the terminal 31 is formed in a semicircular shape. According to the semiconductor device of the third embodiment, since the solder ball 6 and the terminal 31 are bonded, the bonding area increases, and the connection strength of the solder ball 6 can be secured. As a result, cracks and peeling of the solder balls 6 are less likely to occur.

　第３の実施形態に係る半導体装置のリペア方法及び実装方法は、上記第１の実施形態の方法と同じである。なお、上記以外の点においては、第３の実施形態は、上記第１の実施形態と同じである。 リ The repair method and the mounting method of the semiconductor device according to the third embodiment are the same as those of the first embodiment. Except for the above, the third embodiment is the same as the first embodiment.

　また、図１７の半導体装置の貫通穴７にジェル状樹脂を充填した充填部を設けてもよい。 Also, a filling portion filled with a gel resin may be provided in the through hole 7 of the semiconductor device of FIG.

≪第４の実施形態≫
　図１８は、本発明の第４の実施形態に係る半導体装置に関するものであり、同図（ａ）は、貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、基板１の端子３２を示す平面図である。 << 4th Embodiment >>
FIGS. 18A and 18B relate to a semiconductor device according to a fourth embodiment of the present invention. FIG. 18A is a cross-sectional view schematically showing the vicinity of a through hole, and FIG. 3 is a plan view showing the terminal 32 of FIG.

　第４の実施形態に係る半導体装置は、端子３２の開口部３２ａを、貫通穴７の中心と同心に配置され、かつ、貫通穴７の内径よりも小径にした点のみが、上記第１の実施形態の半導体装置と相違する。第４の実施形態の半導体装置によれば、半田ボール６と端子３２とが接合されるので、接合面積が増加し、半田ボール６の接続強度が確保できる。その結果、半田ボール６の亀裂や剥がれが生じにくくなる。また、加熱プローブ４１を半田ボール６に突き刺すときに、端子３２の開口部３２ａにより半田ボール６の中心に加熱プローブ４１がガイドされるので、半田ボール６を均一に加熱することができ、実装工程後又はリペア工程後における接合状態を良好にすることができる。また、開口部３２ａを貫通穴７側を大径にし、半田ボール６側を小径にしたテーパー状に形成してもよく、この場合には、加熱プローブ４１の挿入のための位置決めが容易になる。 The semiconductor device according to the fourth embodiment is different from the first embodiment only in that the opening 32a of the terminal 32 is arranged concentrically with the center of the through hole 7 and has a smaller diameter than the inner diameter of the through hole 7. This is different from the semiconductor device of the embodiment. According to the semiconductor device of the fourth embodiment, since the solder ball 6 and the terminal 32 are bonded, the bonding area increases, and the connection strength of the solder ball 6 can be secured. As a result, cracks and peeling of the solder balls 6 are less likely to occur. Further, when the heating probe 41 is pierced into the solder ball 6, the heating probe 41 is guided to the center of the solder ball 6 by the opening 32a of the terminal 32, so that the solder ball 6 can be uniformly heated, and the mounting process can be performed. The bonding state after or after the repair step can be improved. Further, the opening 32a may be formed in a tapered shape in which the diameter of the through hole 7 is made large and the diameter of the solder ball 6 is made small. In this case, positioning for inserting the heating probe 41 becomes easy. .

　第４の実施形態に係る半導体装置のリペア方法及び実装方法は、上記第１の実施形態の方法と同じである。なお、上記以外の点においては、第４の実施形態は、上記第１の実施形態と同じである。 リ The repair method and the mounting method of the semiconductor device according to the fourth embodiment are the same as the method of the first embodiment. Except for the above points, the fourth embodiment is the same as the first embodiment.

　また、図１８の半導体装置の貫通穴７にジェル状樹脂を充填した充填部を設けてもよい。 Also, a filling portion filled with a gel resin may be provided in the through hole 7 of the semiconductor device of FIG.

≪第５の実施形態≫
　図１９は、本発明の第５の実施形態に係る半導体装置に関するものであり、同図（ａ）は、貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、基板１の端子３３を示す平面図である。 << 5th Embodiment >>
FIGS. 19A and 19B relate to a semiconductor device according to a fifth embodiment of the present invention. FIG. 19A is a cross-sectional view schematically showing the vicinity of a through hole, and FIG. 3 is a plan view showing a terminal 33 of FIG.

　第５の実施形態に係る半導体装置は、図１９（ｂ）に示されるように、端子３３が十字形部３３ａを有し、４個の扇形開口部３３ｂを形成している点のみが、上記第１の実施形態の半導体装置と相違する。第５の実施形態に係る半導体装置によれば、半田ボール６と端子３３とが接合されるので、接合面積が増加し、半田ボール６の接続強度が確保できる。また、端子と半田ボール６の接合部の形状が点対称となり、接合部の接続強度が安定する。その結果、半田ボール６の亀裂や剥がれが生じにくくなる。 The semiconductor device according to the fifth embodiment is different from the semiconductor device according to the fifth embodiment only in that the terminal 33 has a cross-shaped portion 33a and forms four fan-shaped openings 33b, as shown in FIG. This is different from the semiconductor device of the first embodiment. According to the semiconductor device of the fifth embodiment, since the solder ball 6 and the terminal 33 are joined, the joining area increases, and the connection strength of the solder ball 6 can be secured. In addition, the shape of the joint between the terminal and the solder ball 6 becomes point symmetric, and the connection strength of the joint is stabilized. As a result, cracks and peeling of the solder balls 6 are less likely to occur.

　第５の実施形態に係る半導体装置のリペア方法及び実装方法は、上記第１の実施形態の方法と同じである。加熱プローブ４１は、開口部３３ｂを通して半田ボール６に突き刺す。なお、上記以外の点においては、第５の実施形態は、上記第１の実施形態と同じである。 リ The repair method and the mounting method of the semiconductor device according to the fifth embodiment are the same as those of the first embodiment. The heating probe 41 pierces the solder ball 6 through the opening 33b. In other respects, the fifth embodiment is the same as the first embodiment.

　また、図１９の半導体装置の貫通穴７にジェル状樹脂を充填した充填部を設けてもよい。 In addition, a filling portion filled with a gel resin may be provided in the through hole 7 of the semiconductor device of FIG.

≪第６の実施形態≫
　図２０は、本発明の第６の実施形態に係る半導体装置を概略的に示す断面図である。 << Sixth Embodiment >>
FIG. 20 is a sectional view schematically showing a semiconductor device according to the sixth embodiment of the present invention.

　第６の実施形態に係る半導体装置は、図２０に示されるように、貫通穴７内に、一端を半田ボール６に接触させ、他端を外部の加熱装置の発熱部５１に接触可能なように上面１ｃ上に突出させた半田ボール加熱用の熱伝導部材（固定プローブ）４４を備えた点のみが、上記第１の実施形態の半導体装置と相違する。固定プローブ４４は、貫通穴７に差し込んだ後に、研磨工程により同じ高さに揃えられる。固定プローブ４４は、熱伝導性が良好で、半田ボール６との濡れ性が良好な材料で構成される。好適な材料としては、銅、銀、白金等の金属、Ｚｒ−Ｃｕ、Ｆｅ−Ｃｕ、Ｎｉ−Ｃｕ等の銅合金、４２アロイ（４２％Ｎｉ―Ｆｅ）等の鉄合金等がある。 As shown in FIG. 20, the semiconductor device according to the sixth embodiment has one end in contact with the solder ball 6 and the other end in the through hole 7 so as to be able to contact the heat generating portion 51 of the external heating device. The semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment only in that a heat conductive member (fixed probe) 44 for heating a solder ball protruding above the upper surface 1c is provided. After being inserted into the through-hole 7, the fixed probe 44 is adjusted to the same height by a polishing process. The fixed probe 44 is made of a material having good thermal conductivity and good wettability with the solder ball 6. Suitable materials include metals such as copper, silver and platinum, copper alloys such as Zr-Cu, Fe-Cu and Ni-Cu, and iron alloys such as 42 alloy (42% Ni-Fe).

　第６の実施形態に係る半導体装置のリペア方法及び実装方法は、加熱装置の発熱体５１（例えば、板状）を加熱してから固定プローブ４４の端部４４ａに接触させて（又は接触してから加熱して）半田ボール６を加熱し、加熱装置の発熱体５１を、固定プローブ４４の端部４４ａから離して（又は発熱を停止させて）に半田ボール６を冷却することによって実行される。第６の実施形態によれば、半田ボール６を均一に加熱することができる。なお、この実装工程において、図２７に示されるように、ホットプレート１３１及びエアブロー１３２の少なくとも一方を併用してもよい。また、実装工程においては、半田ペースト（微小な粒状の半田と活性剤（フラックス）とから構成される）をマザーボードの端子上に塗布し、その上に半田ボール６を置き、加熱装置の発熱体５１による固定プローブ４４の加熱を行う。 The repair method and the mounting method of the semiconductor device according to the sixth embodiment are such that the heating element 51 (for example, a plate) of the heating device is heated and then brought into contact with (or in contact with) the end 44 a of the fixed probe 44. The heating is performed by heating the solder ball 6 and cooling the solder ball 6 by separating the heating element 51 of the heating device from the end 44 a of the fixed probe 44 (or by stopping the heat generation). . According to the sixth embodiment, the solder balls 6 can be uniformly heated. In this mounting step, at least one of the hot plate 131 and the air blow 132 may be used together as shown in FIG. In the mounting step, a solder paste (comprising fine-granular solder and an activator (flux)) is applied to the terminals of the motherboard, and solder balls 6 are placed on the solder paste. The fixed probe 44 is heated by 51.

　また、上記以外の点においては、第６の実施形態は、上記第１の実施形態と同じである。 Other than the above, the sixth embodiment is the same as the first embodiment.

　また、図２０の半導体装置の貫通穴７の隙間にジェル状樹脂を充填した充填部を設けてもよい。 In addition, a filling portion filled with a gel resin may be provided in the gap between the through holes 7 of the semiconductor device of FIG.

　図２１は、本発明の第６の実施形態に係る半導体装置の変形例を概略的に示す断面図である。 FIG. 21 is a sectional view schematically showing a modification of the semiconductor device according to the sixth embodiment of the present invention.

　図２１の半導体装置は、固定プローブ４５の端部４５ａが基板１の表面１ｃを同じ高さである点のみが、上記図２０の半導体装置と相違する。この場合には、加熱装置の発熱部５２に固定プローブ４５の端部４５ａに接触できる凸部を備えればよい。 半導体 The semiconductor device of FIG. 21 differs from the semiconductor device of FIG. 20 only in that the end 45 a of the fixed probe 45 has the same height as the surface 1 c of the substrate 1. In this case, the heat generating portion 52 of the heating device may be provided with a convex portion that can contact the end portion 45a of the fixed probe 45.

　図２２は、本発明の第６の実施形態に係る半導体装置の変形例を概略的に示す断面図である。 FIG. 22 is a sectional view schematically showing a modification of the semiconductor device according to the sixth embodiment of the present invention.

　図２２の半導体装置は、固定プローブ４６の端部４６ａが基板１の表面１ｃより低くなっている点のみが、上記図２０の半導体装置と相違する。この場合には、加熱装置の発熱部５３に固定プローブ４６の端部４６ａに接触できる凸部を備えればよい。 The semiconductor device of FIG. 22 differs from the semiconductor device of FIG. 20 only in that the end 46a of the fixed probe 46 is lower than the surface 1c of the substrate 1. In this case, the heating portion 53 of the heating device may be provided with a convex portion that can contact the end 46a of the fixed probe 46.

≪第７の実施形態≫
　図２３は、本発明の第７の実施形態に係る半導体装置を概略的に示す断面図である。 << Seventh embodiment >>
FIG. 23 is a sectional view schematically showing a semiconductor device according to the seventh embodiment of the present invention.

　第７の実施形態に係る半導体装置は、図２３に示されるように、基板１の下面１ｂと側面１ｄとを繋ぐように、基板１に形成された貫通穴６０と、貫通穴内６０に一端を半田ボール６に接触させ、他端を加熱装置の発熱部に接触可能なように側面１ｄ付近に配置した半田ボール加熱用の熱伝導部材（固定プローブ）６１とを有する点のみが、上記第１の実施形態の半導体装置と相違する。固定プローブ６１の製造方法としては、基板１の製造段階において、板状の銅製部材を絶縁基板間に挟み込んでおく方法がある。固定プローブ６１は、熱伝導性が良好で、半田ボール６との濡れ性が良好な材料で構成される。好適な材料としては、銅、銀、白金等の金属、Ｚｒ−Ｃｕ、Ｆｅ−Ｃｕ、Ｎｉ−Ｃｕ等の銅合金、４２アロイ（４２％Ｎｉ―Ｆｅ）等の鉄合金等がある。 As shown in FIG. 23, the semiconductor device according to the seventh embodiment has a through hole 60 formed in the substrate 1 and one end in the through hole 60 so as to connect the lower surface 1b and the side surface 1d of the substrate 1. The only point having the heat conductive member (fixed probe) 61 for heating the solder ball, which is arranged in the vicinity of the side surface 1d so as to be in contact with the solder ball 6 and the other end can be brought into contact with the heating portion of the heating device, is the first type. It is different from the semiconductor device of the embodiment. As a method for manufacturing the fixed probe 61, there is a method in which a plate-shaped copper member is sandwiched between insulating substrates in the manufacturing stage of the substrate 1. The fixed probe 61 is made of a material having good thermal conductivity and good wettability with the solder ball 6. Suitable materials include metals such as copper, silver and platinum, copper alloys such as Zr-Cu, Fe-Cu and Ni-Cu, and iron alloys such as 42 alloy (42% Ni-Fe).

　第７の実施形態に係る半導体装置のリペア方法及び実装方法は、加熱装置の発熱体（図示せず）を加熱してから固定プローブ６１の端部６１ａに接触させて（又は接触してから加熱して）半田ボール６を加熱し、加熱装置の発熱体を、固定プローブ６１の端部６１ａから離して（又は発熱を停止させて）に半田ボール６を冷却することによって実行される。第７の実施形態によれば、半田ボール６を均一に加熱することができる。また、図２３の構造を高さ方向に重ねて実装する、いわゆる３次元実装が可能となる。なお、この実装工程において、図２７に示されるように、ホットプレート１３１及びエアブロー１３２の少なくとも一方を併用してもよい。また、実装工程においては、半田ペースト（微小な粒状の半田と活性剤（フラックス）とから構成される）をマザーボードの端子上に塗布し、その上に半田ボール６を置き、加熱装置の発熱体５１による固定プローブ６１の加熱を行う。 The method for repairing and mounting the semiconductor device according to the seventh embodiment includes heating a heating element (not shown) of a heating device and then contacting (or heating after contacting) the end 61 a of the fixed probe 61. This is performed by heating the solder ball 6 and cooling the solder ball 6 while keeping the heating element of the heating device away from the end 61 a of the fixed probe 61 (or by stopping the heat generation). According to the seventh embodiment, the solder balls 6 can be uniformly heated. In addition, so-called three-dimensional mounting, in which the structure of FIG. 23 is stacked in the height direction and mounted, becomes possible. In this mounting step, at least one of the hot plate 131 and the air blow 132 may be used together as shown in FIG. In the mounting step, a solder paste (composed of fine-grained solder and an activator (flux)) is applied onto the terminals of the motherboard, and solder balls 6 are placed thereon, and the heating element of the heating device is heated. The fixed probe 61 is heated by 51.

　なお、上記以外の点においては、第７の実施形態は、上記第１の実施形態と同じである。 ７Except for the points described above, the seventh embodiment is the same as the first embodiment.

　また、図２３の半導体装置の貫通穴７の隙間にジェル状樹脂を充填した充填部を設けてもよい。 In addition, a filling portion filled with a gel resin may be provided in the gap between the through holes 7 of the semiconductor device of FIG.

　図２４は、本発明の第７の実施形態に係る半導体装置の変形例を概略的に示す断面図である。 FIG. 24 is a sectional view schematically showing a modification of the semiconductor device according to the seventh embodiment of the present invention.

　図２４の半導体装置は、固定プローブ６２の端部６２ａが基板１の側面１ｄと同じ高さである点のみが、上記図２３の半導体装置と相違する。この場合には、加熱装置の発熱部に固定プローブ６２の端部６２ａに接触できる凸部を備えればよい。 半導体 The semiconductor device of FIG. 24 differs from the semiconductor device of FIG. 23 only in that the end 62 a of the fixed probe 62 has the same height as the side surface 1 d of the substrate 1. In this case, the heating portion of the heating device may be provided with a convex portion that can contact the end portion 62a of the fixed probe 62.

　図２５は、本発明の第７の実施形態に係る半導体装置の変形例を概略的に示す断面図である。 FIG. 25 is a sectional view schematically showing a modification of the semiconductor device according to the seventh embodiment of the present invention.

　図２５の半導体装置は、固定プローブ６３の端部６３ａが基板１の側面１ｄより低くなっている点のみが、上記図２３の半導体装置と相違する。この場合には、加熱装置の発熱部に固定プローブ６３の端部６３ａに接触できる凸部を備えればよい。 半導体 The semiconductor device of FIG. 25 differs from the semiconductor device of FIG. 23 only in that the end 63 a of the fixed probe 63 is lower than the side surface 1 d of the substrate 1. In this case, the heating portion of the heating device may be provided with a convex portion that can contact the end 63a of the fixed probe 63.

本発明の第１の実施形態に係る半導体装置の上面（ヒートシンクを備えた面）を概略的に示す平面図である。FIG. 2 is a plan view schematically showing an upper surface (a surface provided with a heat sink) of the semiconductor device according to the first embodiment of the present invention. 図１（又は図３）の半導体装置をＳ２−Ｓ２線で切る面を概略的に示す断面図である。The semiconductor device of FIG. 1 (or Fig. 3) the surfaces cut by S 2 -S 2 line is a sectional view schematically showing. 第１の実施形態に係る半導体装置の下面（半田ボールを備えた面）を概略的に示す平面図である。FIG. 2 is a plan view schematically showing a lower surface (a surface provided with solder balls) of the semiconductor device according to the first embodiment. 第１の実施形態に係る半導体装置の上面の貫通穴付近を拡大して示す平面図である。FIG. 2 is an enlarged plan view showing the vicinity of a through hole on the upper surface of the semiconductor device according to the first embodiment. 第１の実施形態に係る半導体装置の端子と半田ボールの接合部を拡大して示す断面図である。FIG. 2 is an enlarged cross-sectional view illustrating a joint between a terminal and a solder ball of the semiconductor device according to the first embodiment. マザーボードに搭載された第１の実施形態に係る半導体装置のリペア工程（その１）を示す断面図である。FIG. 5 is a cross-sectional view illustrating a repair process (part 1) of the semiconductor device according to the first embodiment mounted on a motherboard. マザーボードに搭載された第１の実施形態に係る半導体装置のリペア工程（その２）を示す断面図である。FIG. 5 is a cross-sectional view illustrating a repair step (part 2) of the semiconductor device according to the first embodiment mounted on a motherboard. マザーボードに搭載された第１の実施形態に係る半導体装置のリペア工程（その３）を示す断面図である。FIG. 6 is a cross-sectional view illustrating a repair step (part 3) of the semiconductor device according to the first embodiment mounted on a motherboard. （ａ）及び（ｂ）のそれぞれは、図６から図８までのリペア工程を実施する前と後の半田ボールの状態を示す説明図である。(A) and (b) are explanatory views showing states of solder balls before and after performing the repair process of FIGS. 6 to 8. 第１の実施の形態に係る実装方法が適用される半導体装置を概略的に示す断面図である。FIG. 2 is a cross-sectional view schematically showing a semiconductor device to which the mounting method according to the first embodiment is applied. 第１の実施形態に係る半導体装置をマザーボードに実装する工程（その１）を示す断面図である。FIG. 6 is a cross-sectional view illustrating a step (part 1) of mounting the semiconductor device according to the first embodiment on a motherboard. 第１の実施形態に係る半導体装置をマザーボードに実装する工程（その２）を示す断面図である。FIG. 5 is a cross-sectional view illustrating a step (part 2) of mounting the semiconductor device according to the first embodiment on a motherboard. 第１の実施形態に係る半導体装置をマザーボードに実装する工程（その３）を示す断面図である。FIG. 5 is a cross-sectional view illustrating a step (No. 3) of mounting the semiconductor device according to the first embodiment on a motherboard. 半導体装置の貫通穴を封止体で封止した第１の実施形態の変形例を示す断面図である。It is sectional drawing which shows the modification of 1st Embodiment which sealed the through-hole of the semiconductor device with the sealing body. （ａ）は、本発明の第２の実施形態に係る半導体装置の貫通穴付近を概略的に示す断面図であり、（ｂ）は、貫通穴付近を拡大して示す平面図である。(A) is a sectional view schematically showing the vicinity of a through hole of a semiconductor device according to a second embodiment of the present invention, and (b) is an enlarged plan view showing the vicinity of the through hole. （ａ）は、半導体装置の貫通穴を充填部で充填した第２の実施形態の変形例を示す断面図であり、（ｂ）は、貫通穴付近を拡大して示す平面図である。(A) is sectional drawing which shows the modification of 2nd Embodiment which filled the through-hole of the semiconductor device with the filling part, (b) is a top view which expands and shows the vicinity of a through-hole. 本発明の第３の実施形態に係る半導体装置に関するものであり、同図（ａ）は、貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、基板の端子を示す平面図である。FIG. 4A is a cross-sectional view schematically showing a vicinity of a through hole, and FIG. 4B is a plan view showing terminals of a substrate, which relates to a semiconductor device according to a third embodiment of the present invention. FIG. 本発明の第４の実施形態に係る半導体装置に関するものであり、同図（ａ）は、貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、基板の端子を示す平面図である。FIG. 6A is a cross-sectional view schematically showing a vicinity of a through hole, and FIG. 6B is a plan view showing terminals of a substrate, which relates to a semiconductor device according to a fourth embodiment of the present invention. FIG. 本発明の第５の実施形態に係る半導体装置に関するものであり、同図（ａ）は、貫通穴付近を概略的に示す断面図であり、同図（ｂ）は、基板の端子を示す平面図である。FIG. 8A is a cross-sectional view schematically showing a vicinity of a through hole, and FIG. 8B is a plan view showing terminals of a substrate, which relates to a semiconductor device according to a fifth embodiment of the present invention. FIG. 本発明の第６の実施形態に係る半導体装置を概略的に示す断面図である。FIG. 14 is a sectional view schematically showing a semiconductor device according to a sixth embodiment of the present invention. 第６の実施形態の変形例を概略的に示す断面図である。It is sectional drawing which shows the modification of 6th Embodiment schematically. 第６の実施形態の他の変形例を概略的に示す断面図である。It is sectional drawing which shows the other modification of 6th Embodiment schematically. 本発明の第７の実施形態に係る半導体装置を概略的に示す断面図である。FIG. 15 is a sectional view schematically showing a semiconductor device according to a seventh embodiment of the present invention. 第７の実施形態の変形例を概略的に示す断面図である。It is sectional drawing which shows the modification of 7th Embodiment schematically. 第８の実施形態の他の変形例を概略的に示す断面図である。It is sectional drawing which shows the other modification of 8th Embodiment schematically. マザーボードに搭載された従来の半導体装置の構成を概略的に示す断面図である。FIG. 11 is a cross-sectional view schematically showing a configuration of a conventional semiconductor device mounted on a motherboard. 従来の半導体装置をマザーボードに実装する工程を示す説明図である。It is an explanatory view showing a step of mounting a conventional semiconductor device on a motherboard. 従来の半導体装置の問題点の発生原理を示す説明図である。FIG. 11 is an explanatory diagram showing the principle of generation of a problem of a conventional semiconductor device. （ａ）及び（ｂ）のそれぞれは、従来の半導体装置における半田接合部の亀裂及び剥がれを示す断面図である。(A) and (b) are cross-sectional views showing cracks and peeling of solder joints in a conventional semiconductor device.

符号の説明Explanation of reference numerals

　１　基板
　１ａ　中央開口部
　１ｂ　下面
　１ｃ　上面
　１ｄ　側面
　２　ヒートスラグ
　３　ＩＣチップ
　４　金属細線
　５　封止体
　６　半田ボール
　６ａ　金属間化合物
　７　貫通穴
　８　基板の端子
　９　配線層
　１１，１２，１３　絶縁基板
　１４　配線層
　１５，１７　充填部
　１６　電極部材
　２１　マザーボード
　２２　マザーボードの端子
　３１，３２，３３　基板の端子
　３１ａ，３２ａ，３３ｂ　端子の開口部
　３３ａ　十字形部
　４１　加熱プローブ
　４１ａ　加熱プローブの先端
　４１ｂ　加熱プローブの端部
　４２　発熱体
　４３　移動機構
　４４，４５，４６　固定プローブ
　４４ａ，４５ａ，４６ａ　固定プローブの端部
　５１，５２，５３　発熱体
　６０　Ｌ字状の貫通穴
　６１，６２，６３　固定プローブ
　６１ａ，６２ａ，６３ａ　固定プローブの端部 DESCRIPTION OF SYMBOLS 1 Substrate 1a Central opening 1b Lower surface 1c Upper surface 1d Side surface 2 Heat slug 3 IC chip 4 Fine metal wire 5 Sealing body 6 Solder ball 6a Intermetallic compound 7 Through hole 8 Terminal of board 9 Wiring layer 11, 12, 13 Insulating substrate 14 Wiring layer 15, 17 Filling portion 16 Electrode member 21 Motherboard 22 Motherboard terminal 31, 32, 33 Terminal 31a, 32a, 33b Terminal opening 33a Cross-shaped portion 41 Heating probe 41a Heating probe tip 41b Heating probe end Part 42 Heating element 43 Moving mechanism 44, 45, 46 Fixed probe 44a, 45a, 46a Fixed probe end 51, 52, 53 Heating element 60 L-shaped through hole 61, 62, 63 Fixed probe 61a, 62a, 63a Fixed probe end

Claims (14)

　端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記貫通穴の内表面に備えられた第１の配線層と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールとを有する半導体装置を、前記半田ボールがプリント基板の端子上に載るように、前記プリント基板上に置く工程と、
　加熱装置の加熱プローブを前記第２の面側から前記貫通穴に挿入し、前記半田ボールに突き刺して、前記半田ボールを溶融させる工程と、
　加熱装置の加熱プローブを前記半田ボールから抜き出して、前記半田ボールを凝固させる工程と
　を有することを特徴とする半導体装置の実装方法。 A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; A first wiring layer connected to the terminal, the first wiring layer provided on the inner surface of the through hole, the first wiring layer connected to the terminal, and the first surface on the first surface. A semiconductor device having a solder ball provided so as to cover the through hole, so that the solder ball rests on a terminal of the printed board, and placing the semiconductor device on the printed board;
Inserting a heating probe of a heating device into the through hole from the second surface side, piercing the solder ball, and melting the solder ball;
Extracting a heating probe of a heating device from the solder ball to solidify the solder ball. 　前記端子が、前記貫通穴に重なる半円状の開口部を有することを特徴とする請求項１に記載の半導体装置の実装方法。 The method according to claim 1, wherein the terminal has a semicircular opening overlapping the through hole. 　前記端子が、前記貫通穴に重なる複数の扇形開口部を含むことを特徴とする請求項１に記載の半導体装置の実装方法。 The method according to claim 1, wherein the terminal includes a plurality of fan-shaped openings overlapping the through hole. 　前記端子が、前記貫通穴の中心と同心に配置され、前記貫通穴の内径よりも小径の開口部を有することを特徴とする請求項１に記載の半導体装置の実装方法。 The method according to claim 1, wherein the terminal is disposed concentrically with a center of the through hole, and has an opening having a diameter smaller than an inner diameter of the through hole. 　前記貫通穴内に、前記貫通穴を半円柱状にする電極部材を備えたことを特徴とする請求項１に記載の半導体装置の実装方法。 4. The method according to claim 1, further comprising: an electrode member in the through hole, the electrode member making the through hole semi-cylindrical. 　前記貫通穴内に、前記貫通穴を塞ぐジェル状樹脂からなる充填部を備えたことを特徴とする請求項１から５までのいずれかに記載の半導体装置の実装方法。 6. The method of mounting a semiconductor device according to claim 1, further comprising: a filling portion made of a gel-like resin that closes the through hole in the through hole. 　端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールと、前記貫通穴内に形成され、かつ、一端を前記半田ボールに接触させ、他端を外部の加熱装置の発熱部に接触可能なように前記第２の面付近に配置した熱伝導部材とを有する半導体装置を、前記半田ボールがプリント基板の端子上に載るように、前記プリント基板上に置く工程と、
　加熱装置により前記熱伝導部材を加熱して、前記半田ボールを溶融させる工程と、
　加熱装置による前記熱伝導部材の加熱を停止して、前記半田ボールを凝固させる工程と
　を有することを特徴とする半導体装置の実装方法。 A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; And a solder ball connected to the terminal and provided on the first surface so as to cover the through hole, and formed in the through hole, and A semiconductor device having a heat conducting member disposed near the second surface such that one end is in contact with the solder ball and the other end is in contact with a heat generating portion of an external heating device. Placing on the printed board so as to be placed on the terminals of the board,
Heating the heat conductive member by a heating device, and melting the solder ball;
Stopping the heating of the heat conducting member by a heating device to solidify the solder balls. 　端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記貫通穴の内表面に備えられた第１の配線層と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールとを有する半導体装置であって、プリント基板の端子に前記半田ボールを融着させた前記半導体装置のリペア方法であって、
　加熱装置の加熱プローブを前記第２の面側から前記貫通穴に挿入し、前記半田ボールに突き刺して、前記半田ボールを溶融させる工程と、
　加熱装置の加熱プローブを前記半田ボールから抜き出して、前記半田ボールを凝固させる工程と
　を有することを特徴とする半導体装置のリペア方法。 A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; A first wiring layer connected to the terminal, the first wiring layer provided on the inner surface of the through hole, the first wiring layer connected to the terminal, and the first surface on the first surface. A solder ball provided so as to cover the through-hole, a method for repairing the semiconductor device, wherein the solder ball is fused to a terminal of a printed circuit board,
Inserting a heating probe of a heating device into the through hole from the second surface side, piercing the solder ball, and melting the solder ball;
Extracting a heating probe of a heating device from the solder ball to solidify the solder ball. 　前記端子が、前記貫通穴に重なる半円状の開口部を有することを特徴とする請求項８に記載の半導体装置のリペア方法。 The method according to claim 8, wherein the terminal has a semicircular opening overlapping the through hole. 　前記端子が、前記貫通穴に重なる複数の扇形開口部を含むことを特徴とする請求項８に記載の半導体装置のリペア方法。 The method according to claim 8, wherein the terminal includes a plurality of fan-shaped openings overlapping the through hole. 　前記端子が、前記貫通穴の中心と同心に配置され、前記貫通穴の内径よりも小径の開口部を有することを特徴とする請求項８に記載の半導体装置のリペア方法。 9. The method according to claim 8, wherein the terminal is disposed concentrically with a center of the through hole, and has an opening having a diameter smaller than an inner diameter of the through hole. 　前記貫通穴内に、前記貫通穴を半円柱状にする電極部材を備えたことを特徴とする請求項８に記載の半導体装置のリペア方法。 9. The method according to claim 8, further comprising an electrode member in the through hole, the electrode member making the through hole semi-cylindrical. 　前記貫通穴内に、前記貫通穴を塞ぐジェル状樹脂からなる充填部を備えたことを特徴とする請求項８から１２までのいずれかに記載の半導体装置のリペア方法。 13. The method of repairing a semiconductor device according to claim 8, wherein a filling portion made of a gel resin for closing the through hole is provided in the through hole. 端子を備えた第１の面と前記第１の面の反対側の第２の面とを有する基板と、前記基板に搭載された半導体チップと、前記第１の面と前記第２の面とを繋ぐように、前記基板に形成された貫通穴と、前記端子に接続され、前記第１の面上に前記貫通穴を覆うように備えられた半田ボールと、前記貫通穴内に形成され、かつ、一端を前記半田ボールに接触させ、他端を外部の加熱装置の発熱部に接触可能なように前記第２の面付近に配置した熱伝導部材とを有する半導体装置であって、プリント基板の端子に前記半田ボールを融着させた前記半導体装置のリペア方法であって、
　加熱装置により前記熱伝導部材を加熱して、前記半田ボールを溶融させる工程と、
　加熱装置による前記熱伝導部材の加熱を停止して、前記半田ボールを凝固させる工程と
　を有することを特徴とする半導体装置のリペア方法。 A substrate having a first surface provided with terminals and a second surface opposite to the first surface, a semiconductor chip mounted on the substrate, the first surface and the second surface; And a solder ball connected to the terminal and provided on the first surface so as to cover the through hole, and formed in the through hole, and A heat conductive member disposed near the second surface such that one end is in contact with the solder ball and the other end is capable of contacting a heating portion of an external heating device. A method for repairing the semiconductor device, wherein the solder balls are fused to terminals,
Heating the heat conductive member by a heating device, and melting the solder ball;
Stopping the heating of the heat conducting member by a heating device to solidify the solder balls.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012195452A (en) * 2011-03-16 2012-10-11 Fujitsu Ltd Electronic component and electronic component assembly apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012195452A (en) * 2011-03-16 2012-10-11 Fujitsu Ltd Electronic component and electronic component assembly apparatus

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