JP2004006971A - Circuit forming board - Google Patents

Circuit forming board Download PDF

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JP2004006971A
JP2004006971A JP2003284812A JP2003284812A JP2004006971A JP 2004006971 A JP2004006971 A JP 2004006971A JP 2003284812 A JP2003284812 A JP 2003284812A JP 2003284812 A JP2003284812 A JP 2003284812A JP 2004006971 A JP2004006971 A JP 2004006971A
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circuit
land
diameter
substrate
insulating
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Toshihiro Nishii
西井　利浩
Shinji Nakamura
中村　眞治
Toshiaki Takenaka
竹中　敏昭
Sadao Mitamura
三田村　貞雄
Kunio Kishimoto
岸本　邦雄
Seiichi Nakatani
中谷　誠一
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To make a pattern of a circuit finer and to make the dimensions of through holes and lands small for achieving a high-density circuit board. <P>SOLUTION: The through holes are tapered such that the diameter of the through holes is large on one surface of an insulating board and small on the other surface. A first land is provided on the one surface, a second land is provided on the other surface, and the first land is made larger than the second land. <P>COPYRIGHT: (C)2004,JPO

Description

　本発明は、回路形成基板および回路形成基板の製造方法に関するものである。 The present invention relates to a circuit formation substrate and a method for manufacturing the circuit formation substrate.

　近年の電子機器の小型化・高密度化に伴って、電子部品を搭載する基板も従来の片面基板から両面、多層基板の採用が進み、より多くの回路を基板上に集積可能な基板の開発が行われている。 In recent years, with the miniaturization and high density of electronic devices, the use of multi-layer boards, rather than the conventional single-sided boards, has been progressing, so that more circuits can be integrated on the boards. Has been done.

　両面、多層基板の開発に伴って層間の接続方法も、従来の貫通スルーホールから、接続すべき層間にのみスルーホールを設けるＩＶＨ（インタスティシャルビアホール）の検討が行われている。 With the development of double-sided and multi-layer substrates, as for the connection method between layers, an IVH (interstitial via hole) in which a through hole is provided only between the layers to be connected from a conventional through hole is being studied.

　以下に従来の回路形成基板について図面を参照しながら説明する。 Hereinafter, a conventional circuit forming substrate will be described with reference to the drawings.

　図５は従来の回路形成基板を示す断面図である。絶縁基板１ａ、１ｂ、１ｃの両面に回路２ａ、２ｂ、２ｃが形成されており、回路２ａと回路２ｂおよび回路２ｂと回路２ｃはＩＶＨ４内の導電性ペースト３によって電気的に接続されている。 FIG. 5 is a sectional view showing a conventional circuit forming substrate. Circuits 2a, 2b, and 2c are formed on both surfaces of the insulating substrates 1a, 1b, and 1c. The circuits 2a and 2b and the circuits 2b and 2c are electrically connected to each other by the conductive paste 3 in the IVH 4.

　回路２ａ、２ｂ、２ｃのＩＶＨ４に接する部分はランド５と呼ばれ、通常は略円形のパターンを用いる。ランド５を部品実装用の端子として用いる場合には、ランド５の形状は長方形が用いられる。表層に設けたＩＶＨ４は特にブラインドビアホールと呼ばれる。 部分 A portion of the circuits 2a, 2b, and 2c that is in contact with the IVH 4 is called a land 5, and generally uses a substantially circular pattern. When the land 5 is used as a component mounting terminal, the land 5 has a rectangular shape. IVH4 provided on the surface layer is particularly called a blind via hole.

　図６（ａ）〜（ｆ）は、従来の回路形成基板の製造法を示す工程図である。まず同図（ａ）に示すように、絶縁基板１ｂに貫通孔６を形成する。絶縁基板１ｂの材質としてはガラス繊維織布にエポキシ樹脂を含浸させ、樹脂をＢステージと呼ばれる半硬化状態にした、一般にプリプレグと呼ばれるものが用いられる。 FIGS. 6A to 6F are process diagrams showing a conventional method for manufacturing a circuit-formed substrate. First, as shown in FIG. 1A, a through hole 6 is formed in an insulating substrate 1b. As a material of the insulating substrate 1b, a so-called prepreg, which is a glass fiber woven fabric impregnated with an epoxy resin and the resin is in a semi-cured state called a B stage, is used.

　貫通孔６の形成法としては、通常はドリルによる機械加工あるいはレーザー加工が用いられる。 機械 As a method of forming the through-hole 6, usually, machining with a drill or laser processing is used.

　次に同図（ｂ）に示すように、印刷等を用いて導電性ペースト３を貫通孔６内に充填する。 Next, as shown in FIG. 3B, the conductive paste 3 is filled into the through holes 6 by printing or the like.

　その後同図（ｃ）に示すように、絶縁基板１の両面に金属箔７を接着し、導電性ペースト３を硬化させて金属箔との電気的接続を持たせる。 (4) Thereafter, as shown in FIG. 5 (c), a metal foil 7 is adhered to both sides of the insulating substrate 1, and the conductive paste 3 is cured to have an electrical connection with the metal foil.

　さらに、金属箔７をエッチングして同図（ｄ）に示すように所望の回路２ｂ、２ｃを形成し両面基板を完成する。 (4) Further, the metal foil 7 is etched to form desired circuits 2b and 2c as shown in FIG.

　ランド５ｂ、５ｃの直径は貫通孔６の孔径が２００μｍの場合には約４００μｍ程度が用いられる。 The diameter of the lands 5b and 5c is about 400 μm when the diameter of the through hole 6 is 200 μm.

　以上のような、導電性ペーストを用いてＩＶＨを形成する方法は各種検討がなされている（例えば、特許文献１参照）。 方法 Various studies have been made on the method of forming an IVH using a conductive paste as described above (for example, see Patent Document 1).

　さらに多層の回路形成基板を製作する場合には、同図（ｅ）に示すように導電性ペースト３を充填した絶縁基板１ａ、１ｂで、同図（ｄ）の両面基板を挟み込み、上に述べたような工程を繰り返すことで同図（ｆ）に示す様な多層基板を実現できる。 Further, when a multilayer circuit forming substrate is manufactured, the double-sided substrate shown in FIG. 4D is sandwiched between insulating substrates 1a and 1b filled with the conductive paste 3 as shown in FIG. By repeating such steps, a multilayer substrate as shown in FIG.

　図７は、めっきによる層間接続を行った従来の回路形成基板の製造法を示す工程図である。 FIG. 7 is a process chart showing a conventional method for manufacturing a circuit-formed substrate in which interlayer connection is performed by plating.

　まず図中（ａ）に示すように回路２ｂを形成した絶縁基板１ｂに絶縁基板１ａを接着したものに、ドリルあるいはレーザー加工法にてＩＶＨ４を形成する。 {Circle around (1)} First, an IVH4 is formed on a substrate obtained by bonding the insulating substrate 1a to the insulating substrate 1b on which the circuit 2b is formed as shown in FIG.

　次に同図（ｂ）に示すように、無電解あるいは電解めっきによって銅めっき層８を形成する。 (4) Next, as shown in FIG. 3B, a copper plating layer 8 is formed by electroless or electrolytic plating.

　さらに同図（ｃ）に示すように、銅めっき層８の上にレジスト９を塗布し、通常良く用いられるフォトプロセスで回路のパターンニングを行なう。 (4) As shown in FIG. 3 (c), a resist 9 is applied on the copper plating layer 8, and patterning of the circuit is performed by a commonly used photo process.

　最後にレジスト９を剥離して同図（ｄ）に示すようなＩＶＨを持つ基板を完成する。工程内でレジスト９の密着が良くなかった場合には、パターンニング時にＩＶＨ４内の銅メッキ層８がエッチングされてしまい、同図（ｄ）に図示するような欠陥ＦがＩＶＨ４内に発生する。 (4) Finally, the resist 9 is peeled off to complete a substrate having an IVH as shown in FIG. If the adhesion of the resist 9 is not good in the process, the copper plating layer 8 in the IVH 4 is etched at the time of patterning, and a defect F as shown in FIG.

　このような現象を改善するために、例えば特開平１−２４８６９４号公報に記載のように保護用のペーストを充填する方法等が行われている。
特開平４−３３８６９５号公報 In order to improve such a phenomenon, for example, a method of filling a protective paste as described in Japanese Patent Application Laid-Open No. 1-248694 is performed.
JP-A-4-338895

　しかし、より高密度な回路形成基板を実現するためには回路のパターン形成をより微細にすると共に、貫通孔、ランドの寸法を小さくすることが必要である。 However, in order to realize a higher-density circuit-forming substrate, it is necessary to make the circuit pattern finer and to reduce the dimensions of the through-holes and lands.

　しかしながら貫通孔の孔径を小さくすると導電性ペーストの充填が困難になるため、貫通孔の小径化には限界があり、当然のことながらランドの寸法も小さくすることは困難となる。 However, when the diameter of the through-hole is reduced, it becomes difficult to fill the conductive paste with the hole. Therefore, there is a limit in reducing the diameter of the through-hole, and it is naturally difficult to reduce the dimension of the land.

　また、導電性ペーストの代わりに金属材料をメッキして絶縁基板両面の接続を行なうとしても、孔径が有る程度以上に小さいとメッキ液のつきまわり性などが悪くなるため接続の信頼性が低下する。 Also, even if a metal material is plated instead of the conductive paste to connect the two surfaces of the insulating substrate, if the hole diameter is smaller than a certain degree, the throwing power of the plating solution is deteriorated, and the connection reliability is reduced. .

　また、パターンニング時にＩＶＨ内の保護のために絶縁ペーストを充填する際にも孔径が小さくなるに従って作業性は悪くなる。金属粉をエポキシ樹脂に混入した導電性ペーストを用いた実験では２００μｍ以下の孔径の貫通孔においては充填量のばらつきが大きく、ＩＶＨの層間接続抵抗は安定しなかった。 に も Also, when filling the insulating paste for protection in the IVH at the time of patterning, the workability becomes worse as the hole diameter becomes smaller. In an experiment using a conductive paste in which a metal powder was mixed into an epoxy resin, the through hole having a hole diameter of 200 μm or less had a large variation in the filling amount, and the IVH interlayer connection resistance was not stable.

　本発明はこのような課題を解決するものであり、回路形成基板の高密度化に貢献できうるものである。 The present invention solves such a problem, and can contribute to a higher density of a circuit forming substrate.

　上記目的を達成するために、本発明の回路形成基板および回路形成基板の製造方法は、貫通孔の孔径にテーパーを持たせる、あるいはランドの寸法を貫通孔の口径に合わせて絶縁基板の一方の面と他方の面で異なるものとした構成を用いるものである。 In order to achieve the above object, a circuit forming substrate and a method of manufacturing a circuit forming substrate according to the present invention may be configured such that the diameter of the through-hole is tapered, or the size of the land is adjusted to the diameter of the through-hole, and one of the insulating substrates is formed. A different configuration is used between the surface and the other surface.

　本発明によれば、絶縁基板両面の回路間を接続する導電性ペースト等の充填あるいはメッキ等の工程を微細な貫通孔に対しても容易なものとし、ランド寸法を小さくできることによって回路形成基板に形成する回路を高密度化出来るものである。 According to the present invention, a process such as filling or plating of a conductive paste or the like for connecting between circuits on both surfaces of an insulating substrate can be easily performed even for fine through holes, and a land size can be reduced. It is possible to increase the density of a circuit to be formed.

　以下、本発明の実施例について同一機能を有するものには同一番号を付して詳しい説明を省略し、相違する点について説明する。 Hereafter, in the embodiments of the present invention, those having the same functions are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be described.

　（実施例１）
　図１は本発明の第１の実施例の回路形成基板を示す断面図である。従来例と同じく絶縁基板１ａ、１ｂ、１ｃの両面に回路２ａ、２ｂ、２ｃが形成されており、テーパ形状のＩＶＨ４内の導電ペースト３によって、回路２ａ、２ｂ、２ｃは電気的に接続されている。 (Example 1)
FIG. 1 is a sectional view showing a circuit forming substrate according to a first embodiment of the present invention. Circuits 2a, 2b, 2c are formed on both sides of the insulating substrates 1a, 1b, 1c as in the conventional example, and the circuits 2a, 2b, 2c are electrically connected by the conductive paste 3 in the tapered IVH 4. I have.

　図２（ａ）〜（ｆ）は、図１に示す回路形成基板の製造方法を示す工程図である。 2 (a) to 2 (f) are process diagrams showing a method for manufacturing the circuit formation substrate shown in FIG.

　まず、同図（ａ）に示すように絶縁基板１ｂにテーパ−形状の貫通孔６を形成する。貫通孔６は図中に示すように、絶縁基板１ｂの上面でその直径が大きく下面で直径が小さくなるように貫通方向にテーパーがつけられている。 {Circle around (1)} First, a tapered through hole 6 is formed in the insulating substrate 1b as shown in FIG. As shown in the figure, the through-hole 6 is tapered in the penetrating direction so that the diameter is large on the upper surface of the insulating substrate 1b and smaller on the lower surface.

　レーザー加工法を用いて貫通孔６を形成すると、通常このようなテーパーが僅かに発生するが、絶縁基板１ｂにガラス繊維織布プリプレグを用いた発明者の実験では、エキシマレーザーを用いてレーザーパルスのエネルギーやパルス長あるいは焦点距離等の加工条件をコントロールすることで、貫通孔６の絶縁基板１ｂ上面での直径（以後上面径と記述）と下面での直径（以後下面径）の比（以後直径比）が０．３から０．９５程度にすることが出来た。 When the through hole 6 is formed by using a laser processing method, such a taper is usually slightly generated. By controlling processing conditions such as energy, pulse length, and focal length, the ratio of the diameter of the through hole 6 on the upper surface of the insulating substrate 1b (hereinafter referred to as the upper surface diameter) to the diameter of the lower surface (hereinafter referred to as the lower surface diameter) (hereinafter, the lower surface diameter). (Diameter ratio) could be made about 0.3 to 0.95.

　アラミド繊維織布プリプレグを用いた実験では、ＣＯ2 レーザーを用いて同様の加工が出来た。勿論不織布プリプレグを用いることも可能である。 In an experiment using aramid fiber woven prepreg, the same processing was performed using a CO2 laser. Of course, it is also possible to use a nonwoven fabric prepreg.

　ただし、直径比０．３以下の加工は、下面径が加工条件に対して非常に大きく変動し加工条件の設定が困難であった。また、直径比０．９５以上のほとんど上面径と下面径が同じになるような加工は、レーザーを用いた実験では不可能であった。 However, in the processing with a diameter ratio of 0.3 or less, the diameter of the lower surface fluctuated greatly with respect to the processing conditions, and it was difficult to set the processing conditions. Further, it was not possible to perform processing in which the upper surface diameter and the lower surface diameter having a diameter ratio of 0.95 or more were almost the same in an experiment using a laser.

　次に同図（ｂ）に示すように、貫通孔６に導電性ペースト３を充填する。貫通孔６の上面径が約２００μｍ、下面径が約７０μｍのサンプルを用いた実験では、充填はばらつき無く行われ、作業性は従来例と比較して非常に向上した。 Next, as shown in FIG. 3B, the conductive paste 3 is filled in the through holes 6. In an experiment using a sample in which the upper surface diameter of the through hole 6 was about 200 μm and the lower surface diameter was about 70 μm, the filling was performed without variation, and the workability was greatly improved as compared with the conventional example.

　また、貫通孔６が下方に行くほど小さくなる形状のため充填後に導電性ペースト３が下方に抜け落ちる現象も全く起こらなかった。 (4) Since the shape of the through-hole 6 becomes smaller as it goes downward, the phenomenon that the conductive paste 3 falls down after filling does not occur at all.

　さらに同図（ｃ）に示すように絶縁基板１ｂの両面に金属箔７を接着し、同図（ｄ）に示すように回路２ｂ、２ｃを形成した。このときランド５ｂの直径は４００μｍ、ランド５ｃの直径は２００μｍとした。 Furthermore, as shown in FIG. 3C, metal foils 7 were bonded to both surfaces of the insulating substrate 1b to form circuits 2b and 2c as shown in FIG. At this time, the diameter of the land 5b was 400 μm, and the diameter of the land 5c was 200 μm.

　従来例と比較して、回路２ｃはランド径２００μｍで設計できるため、回路パターンの高密度化が図れた。通常の多層基板では電源、グランド層と信号層に各層の役割が分けられており、信号層の方が回路パターンの高密度化が要求される。従って本実施例の場合では回路２ｂを電源層、回路２ｃを信号層に用いれば良い。 (4) Since the circuit 2c can be designed with a land diameter of 200 μm as compared with the conventional example, the density of the circuit pattern can be increased. In a general multilayer substrate, the roles of each layer are divided into a power supply, a ground layer, and a signal layer, and the signal layer is required to have a higher circuit pattern density. Therefore, in the case of this embodiment, the circuit 2b may be used for the power supply layer, and the circuit 2c may be used for the signal layer.

　完成後の回路形成基板についてＩＶＨの層間接続抵抗を評価し、従来例と比較した結果を図３に示す。 (4) The IVH interlayer connection resistance of the completed circuit formation substrate was evaluated, and the result of comparison with the conventional example is shown in FIG.

　絶縁基板にはガラス繊維織布プリプレグを用い、従来例と本実施例の回路形成基板を各々１００枚ずつ試作した。 ガ ラ ス Glass fiber woven prepreg was used as the insulating substrate, and 100 circuit-forming substrates of the conventional example and the present example were each prototyped.

　従来例はストレート形状の１８０μｍ径のＩＶＨに導電性ペーストを充填したものでああり、１０００個のＩＶＨが直列につながるような回路パターンとし、その両端の電気抵抗を測定したところ、図３に示すように測定値は最小約２Ωから最大５Ωとばらつき、１００枚のサンプル中１枚はオープン不良が発生した。 In the conventional example, a straight-shaped IVH having a diameter of 180 μm is filled with a conductive paste. A circuit pattern in which 1,000 IVHs are connected in series is measured. The electric resistance at both ends is shown in FIG. As described above, the measured value varied from a minimum of about 2Ω to a maximum of 5Ω, and one out of 100 samples had an open defect.

　次に本実施例に基づき、上面径２００μｍ下面径７０μｍのテーパーを設けたＩＶＨについて同様の評価を行うと、図中に示すように測定値は約２Ω近辺に安定した。 Next, based on the present example, when the same evaluation was performed on an IVH having a taper having an upper surface diameter of 200 μm and a lower surface diameter of 70 μm, the measured value was stabilized at about 2Ω as shown in the figure.

　テーパー無し１８０μｍ径のＩＶＨを用いて回路形成基板を設計した従来構造の場合と、２００から７０μｍにテーパーを設けたＩＶＨを用いて設計した本実施例の場合を比較すると、後者の方が同じ電気回路を基板化した場合に基板サイズを小さくすることが可能で、ＩＶＨの層間接続の信頼性と回路形成基板の高密度化を両立することができる。 Comparing the case of the conventional structure in which a circuit forming substrate is designed using an IVH having a diameter of 180 μm without a taper and the case of the present embodiment designed using an IVH having a taper of 200 to 70 μm, the latter has the same electric power. When a circuit is formed on a substrate, the substrate size can be reduced, and both the reliability of the IVH interlayer connection and the increase in the density of the circuit forming substrate can be achieved.

　（実施例２）
　図４はめっきによる層間接続を行った本発明の第２の実施例の回路形成基板の製造法を示す工程図である。 (Example 2)
FIG. 4 is a process chart showing a method of manufacturing a circuit-formed substrate according to a second embodiment of the present invention in which interlayer connection is performed by plating.

　従来例と同様に、ドリルあるいはレーザー加工法にて貫通孔を形成し、無電解あるいは電解めっきによって層間を接続する。ただし、ＩＶＨ４にテーパーがつけられているためにめっきのつきまわり性が良く、またレジスト９が銅メッキ層８にＩＶＨ４内でも良く密着し、従来例に見られたようなＩＶＨ４内に欠陥が生じることは無かった。 (4) As in the conventional example, a through hole is formed by a drill or a laser processing method, and the layers are connected by electroless or electrolytic plating. However, since the IVH 4 is tapered, the throwing power of the plating is good, and the resist 9 adheres well to the copper plating layer 8 even in the IVH 4, causing a defect in the IVH 4 as seen in the conventional example. There was nothing.

　特開平１−２４８６９４のように保護用樹脂ペーストを充填した場合でも、ＩＶＨ４にテーパーを設けたため作業性は極めて良好であった。 で も Even when the protective resin paste was filled as in JP-A-1-248694, the workability was extremely good because the IVH4 was tapered.

　なお、実施例中ではＩＶＨ加工法としてレーザーを用いた例を示したが、ドリル等を用いた機械加工においても工具形状の検討により、ＩＨＶをテーパー形状とする本発明は適用でき、金属箔の代わりに銅ペースト等を印刷、焼成した厚膜導体あるいは蒸着等により形成した回路を用いることも可能である。 Although an example using a laser as the IVH processing method is shown in the examples, the present invention in which the IHV is tapered can be applied to the machining using a drill or the like by examining the tool shape. Instead, a thick film conductor printed with copper paste or the like and fired, or a circuit formed by vapor deposition or the like can be used.

　また絶縁基板の材料としてはガラス繊維あるいはアラミド繊維を用いたプリプレグの例を示したが、ポリイミド等のフィルム、セラミック等の無機系の基板材料などにおいて同様の効果を得ることができる。 Although the example of the prepreg using the glass fiber or the aramid fiber as the material of the insulating substrate has been described, the same effect can be obtained with a film such as a polyimide or an inorganic substrate material such as a ceramic.

　本発明にかかる回路形成基板は、ランドの直径を貫通孔口径が小さくなった面では、回路形成の微細化が図れるという優れた効果を有し、電子部品を搭載する片面、両面、多層配線基板等として有用である。 The circuit-forming board according to the present invention has an excellent effect that the circuit can be miniaturized on the surface where the diameter of the land is smaller than the diameter of the through-hole, and is a single-sided, double-sided, multi-layer wiring board on which electronic components are mounted. It is useful as such.

本発明の回路形成基板の一実施例の構成を示す断面図Sectional drawing which shows the structure of one Example of the circuit formation board | substrate of this invention. 同実施例基板の製造方法の一例を示す工程図Process chart showing an example of the method for manufacturing a substrate of the example. 同実施例基板のＩＶＨ層間接続抵抗分布図IVH interlayer connection resistance distribution diagram of the same example substrate 本発明の回路形成基板の製造方法の一実施例を示す工程図Process chart showing one embodiment of a method for manufacturing a circuit forming substrate of the present invention. 従来の回路形成基板の断面図Sectional view of conventional circuit board 従来の回路形成基板の製造方法の工程図Process drawing of a conventional method for manufacturing a circuit-formed substrate 従来の他の回路形成基板の製造方法の工程図Process drawing of another conventional method for manufacturing a circuit-formed substrate

符号の説明Explanation of reference numerals

　１ａ，１ｂ，１ｃ　　絶縁基板
　２ａ，２ｂ，２ｃ　　回路
　３　　導電性ペースト
　４　　ＩＶＨ
　５，５ｂ，５ｃ　　ランド
　６　　貫通孔
　７　　銅箔
　８　　銅めっき層
　９　　レジスト 1a, 1b, 1c Insulating substrate 2a, 2b, 2c Circuit 3 Conductive paste 4 IVH
5, 5b, 5c Land 6 Through hole 7 Copper foil 8 Copper plating layer 9 Resist

Claims (8)

貫通孔を設けた一枚あるいは二枚以上積層した絶縁基板と、前記絶縁基板の両面あるいは積層した絶縁基板の層間に形成された少なくとも二層以上の回路と、前記貫通孔を通じて前記回路を前記絶縁基板の両面間あるいは層間で電気的に接続する接続手段と、前記貫通孔の孔径が絶縁基板の一方の面でその直径が大きく他方の面で直径が小さくなるように貫通方向にテーパーを備え、前記一方の面に第１のランドが設けられ、前記他方の面に第２のランドが設けられ、前記第１のランドが前記第２のランドよりも大きい回路形成基板。 One or two or more insulating substrates provided with through holes, at least two layers of circuits formed on both surfaces of the insulating substrate or between layers of the stacked insulating substrates, and insulating the circuit through the through holes; A connection means for electrically connecting between both surfaces or between layers of the substrate, and a diameter of the through hole is provided with a taper in a penetrating direction so that the diameter is large on one surface of the insulating substrate and small on the other surface, A circuit forming substrate, wherein a first land is provided on the one surface, and a second land is provided on the other surface, and the first land is larger than the second land. 絶縁基板が少なくとも二枚以上積層された回路形成基板であって、最外層の絶縁基板に設けられた貫通孔の孔径の直径の小さい方が前記回路形成基板の表層となるようにテーパーを備えている請求項１記載の回路形成基板。 A circuit forming substrate in which at least two or more insulating substrates are stacked, and provided with a taper such that the smaller one of the diameters of the through holes provided in the outermost insulating substrate is the surface layer of the circuit forming substrate. The circuit forming substrate according to claim 1. 少なくとも三枚以上積層した絶縁基板と、内層の絶縁基板に設けられた貫通孔と、前記内層の絶縁基板の両側に形成され、前記貫通孔によって電気的に接続された回路と、を備え、
　前記貫通孔の孔径が絶縁基板の一方の面でその直径が大きく他方の面で直径が小さくなるように貫通方向にテーパーを備え、前記一方の面に第１のランドが設けられ、前記他方の面に第２のランドが設けられ、前記第１のランドが前記第２のランドよりも大きい回路形成基板。 At least three or more laminated insulating substrates, a through-hole provided in the inner-layer insulating substrate, and a circuit formed on both sides of the inner-layer insulating substrate and electrically connected by the through-hole,
The diameter of the through hole is tapered in a penetrating direction so that the diameter is large on one surface of the insulating substrate and is small on the other surface, and a first land is provided on the one surface, and the other land is provided with a first land. A circuit forming substrate, wherein a second land is provided on a surface, and the first land is larger than the second land. 回路が金属箔をパターンニングして形成されたことを特徴とする請求項１〜３のいずれかに記載の回路形成基板。 4. The circuit forming substrate according to claim 1, wherein the circuit is formed by patterning a metal foil. 絶縁基材に樹脂を含浸し硬化させた絶縁基板を用いたことを特徴とする請求項１〜３のいずれかに記載の回路形成基板。 The circuit-forming substrate according to any one of claims 1 to 3, wherein an insulating substrate obtained by impregnating the insulating base material with a resin and curing the resin is used. ガラス繊維織布あるいはガラス繊維不織布に熱硬化性樹脂を含浸し硬化させた絶縁基板を用いたことを特徴とする請求項５記載の回路形成基板。 6. The circuit forming substrate according to claim 5, wherein an insulating substrate obtained by impregnating a thermosetting resin into a glass fiber woven fabric or a glass fiber nonwoven fabric and curing the resin is used. アラミド繊維織布あるいはアラミド繊維不織布に熱硬化性樹脂を含浸し硬化させた絶縁基板を用いたことを特徴とする請求項５記載の回路形成基板。 6. The circuit-forming substrate according to claim 5, wherein an insulating substrate obtained by impregnating a thermosetting resin into a woven aramid fabric or a nonwoven fabric of aramid fiber and curing the resin is used. 絶縁基板の一方の面における貫通孔口径と、他方の面における貫通孔口径の比が０．３から０．９５であることを特徴とする請求項１から３のいずれに記載の回路形成基板。 4. The circuit forming substrate according to claim 1, wherein a ratio of a diameter of the through hole on one surface of the insulating substrate to a diameter of the through hole on the other surface is 0.3 to 0.95.
JP2003284812A 1994-08-25 2003-08-01 Circuit forming board Pending JP2004006971A (en)

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JP20065494 1994-08-25
JP2003284812A JP2004006971A (en) 1994-08-25 2003-08-01 Circuit forming board

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006114741A (en) * 2004-10-15 2006-04-27 Ibiden Co Ltd Multilayer core substrate and manufacturing method thereof
JP2010087429A (en) * 2008-10-02 2010-04-15 Denso Corp Multilayered circuit board and its manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006114741A (en) * 2004-10-15 2006-04-27 Ibiden Co Ltd Multilayer core substrate and manufacturing method thereof
JP4551730B2 (en) * 2004-10-15 2010-09-29 イビデン株式会社 Multilayer core substrate and manufacturing method thereof
US7905014B2 (en) 2004-10-15 2011-03-15 Ibiden Co., Ltd. Manufacturing method of multilayer core board
JP2010087429A (en) * 2008-10-02 2010-04-15 Denso Corp Multilayered circuit board and its manufacturing method

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