JP2003347507A - Semiconductor power device - Google Patents
Semiconductor power deviceInfo
- Publication number
- JP2003347507A JP2003347507A JP2002152665A JP2002152665A JP2003347507A JP 2003347507 A JP2003347507 A JP 2003347507A JP 2002152665 A JP2002152665 A JP 2002152665A JP 2002152665 A JP2002152665 A JP 2002152665A JP 2003347507 A JP2003347507 A JP 2003347507A
- Authority
- JP
- Japan
- Prior art keywords
- conductive paste
- semiconductor
- power device
- insulating substrate
- igbt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えばＩＧＢＴ
（Insulated Gate Bipolar Transistor)とＦＷＤ（Free
Wheeling Diode ）を組合せたパワーモジュールなどを
対象とする半導体パワーデバイスに関し、詳しくはその
組立構造に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention
(Insulated Gate Bipolar Transistor) and FWD (Free
More specifically, the present invention relates to an assembly structure of a semiconductor power device for a power module or the like in which a wheeling diode is combined.
【０００２】[0002]
【従来の技術】先ず、ＩＧＢＴとＦＷＤを組合せたパワ
ーモジュールを例に、その従来における基本的な組立構
造を図４(a),(b) に示す。図において、１は放熱用の金
属ベース板（銅板）、２は金属ベース板１の上に搭載し
た半導体素子実装用の絶縁基板、３はＩＧＢＴ、４はＦ
ＷＤ、５は外囲ケース、６，７，８はそれぞれ外部導出
端子としてのコレクタ端子，エミッタ端子，ゲート端子
である。2. Description of the Related Art First, taking a power module combining an IGBT and an FWD as an example, FIGS. 4 (a) and 4 (b) show a conventional basic assembly structure. In the figure, 1 is a metal base plate (copper plate) for heat dissipation, 2 is an insulating substrate for mounting a semiconductor element mounted on the metal base plate 1, 3 is an IGBT, 4 is F
WD, 5 is an outer case, and 6, 7, and 8 are a collector terminal, an emitter terminal, and a gate terminal, respectively, as external leading terminals.
【０００３】ここで、絶縁基板２としては、伝熱性に優
れたセラミック板の両面に導体（銅箔）を接合したDire
ct Bonding Copper 基板などが用いられ、その下面側の
導体２ａを金属ベース板１の上面に重ねて半田接合して
いる。また、絶縁基板２の上面側導体には、ＩＧＢＴ３
のコレクタ，エミッタおよびゲートに対応する配線パタ
ーン２ｂ，２ｃおよび２ｄがパターン形成されており、
ＩＧＢＴ３はコレクタ電極を下面に向けて配線パターン
２ｂに半田マウントし、上面側のエミッタ電極，ゲート
電極は、それぞれアルミワイヤ９を超音波ボンディング
して絶縁基板上の配線パターン２ｃ，２ｄと電気的に接
続している。一方、ＦＷＤ４はカソード電極を下に向け
てＩＧＢＴ３の側方に並べて前記の配線パターン２ｂに
半田マウントし、その上面のアノード電極と配線パター
ン２ｃとの間にアルミワイヤ９を超音波ボンディングし
てＩＧＢＴ３に並列接続している。また、コレクタ端子
６，エミッタ端子７，ゲート端子８はその脚部をそれぞ
れ配線パターン２ｂ，２ｃ，２ｄに半田付けして外囲ケ
ース５から外部に引き出している。なお、１０は半田付
け部を表している。また、ＩＧＢＴ３，ＦＷＤ４は外囲
ケース５の内部に充填したシリコーンゲルなどで封止さ
れている。[0003] Here, as the insulating substrate 2, a conductive (copper foil) bonded to both surfaces of a ceramic plate having excellent heat conductivity is used.
A ct-bonding copper substrate or the like is used, and the conductor 2a on the lower surface side is overlapped with the upper surface of the metal base plate 1 and soldered. In addition, IGBT3 is provided on the upper surface side conductor of the insulating substrate 2.
Wiring patterns 2b, 2c and 2d corresponding to the collector, emitter and gate of
The IGBT 3 is solder-mounted on the wiring pattern 2b with the collector electrode facing downward, and the emitter electrode and the gate electrode on the upper surface are electrically connected to the wiring patterns 2c and 2d on the insulating substrate by ultrasonic bonding aluminum wires 9, respectively. Connected. On the other hand, the FWD 4 is arranged on the side of the IGBT 3 with the cathode electrode facing downward and solder-mounted on the wiring pattern 2b, and the aluminum wire 9 is ultrasonically bonded between the anode electrode on the upper surface thereof and the wiring pattern 2c by ultrasonic bonding. Are connected in parallel. The legs of the collector terminal 6, the emitter terminal 7, and the gate terminal 8 are soldered to the wiring patterns 2b, 2c, and 2d, respectively, and are drawn out of the surrounding case 5. Reference numeral 10 denotes a soldered portion. The IGBT 3 and the FWD 4 are sealed with a silicone gel or the like filled in the outer case 5.
【０００４】[0004]
【発明が解決しようとする課題】前記した半導体パワー
モジュールは、インバータなどの電力用変換機器として
電気車両，電気自動車のモータ駆動電源に使用されるこ
とから、小形，軽量化が求められている。かかる点、前
記した従来構造の半導体パワーデバイスでは、パワー半
導体チップに発生する熱を効率よく外部に放熱するため
に、ＩＧＢＴ３，ＦＷＤ４を絶縁基板２の上に平面的に
配置していることから、絶縁基板２も大形となってデバ
イスの面積，重量が増加する。Since the above-mentioned semiconductor power module is used as a power conversion device such as an inverter for an electric vehicle or a motor drive power supply of an electric vehicle, it is required to be small and light. In this regard, in the semiconductor power device having the conventional structure described above, the IGBTs 3 and the FWDs 4 are arranged in a plane on the insulating substrate 2 in order to efficiently radiate heat generated in the power semiconductor chip to the outside. The insulating substrate 2 also becomes large, and the area and weight of the device increase.
【０００５】また、ＩＧＢＴ３，ＦＷＤ４などの半導体
チップに生じた熱損失は、チップの下面から絶縁基板
２，金属ベース板１を伝熱し、金属ベース板１に取付け
た放熱フィンなどから外部に放熱して除熱されるのに対
して、半導体チップの上面側からの放熱は、細いアルミ
ワイヤ９の熱伝導によるだけで、その放熱効果は殆ど期
待できないのみならず、半導体チップの上面側電極にア
ルミワイヤ９を超音波ボンデイングすると、チップにダ
メージを与えるおそれがある。すなわち、超音波ワイヤ
ーボンデイングでは、アルミワイヤーと半導体チップと
を加圧しながら超音波を印加してアルミワイヤを接合し
ているが、良好な接合を得るためには大きな加圧力と大
きな超音波パワーが必要であり、これが半導体チップに
ダメージを与えるおそれがある。さらに、アルミワイヤ
９がヒートサイクルによる熱応力で断線するおそれもあ
る。The heat loss generated in the semiconductor chips such as IGBT3 and FWD4 is transmitted to the insulating substrate 2 and the metal base plate 1 from the lower surface of the chip, and is radiated to the outside through radiation fins attached to the metal base plate 1. On the other hand, the heat radiation from the upper surface side of the semiconductor chip is only due to the heat conduction of the thin aluminum wire 9 and the heat radiation effect is hardly expected. If ultrasonic bonding is performed on 9, the chip may be damaged. In other words, in the ultrasonic wire bonding, the aluminum wire is bonded by applying ultrasonic waves while pressing the aluminum wire and the semiconductor chip. However, in order to obtain good bonding, a large pressing force and a large ultrasonic power are required. Required, which may damage the semiconductor chip. Further, there is a possibility that the aluminum wire 9 is disconnected due to thermal stress due to a heat cycle.
【０００６】一方、前記問題の対応策として、特開２０
００−１６４８００号公報には、ＩＧＢＴチップとＦＷ
Ｄチップを上下に積み重ねて絶縁基板上に実装した上
で、上下に積み重ねた半導体チップの間にボンディング
ワイヤに代わる幅広な接続導体（銅板）を挟んで半導体
チップの電極と導電性接着剤により接合した構造が開示
されている。On the other hand, as a countermeasure for the above-mentioned problem,
No. 00-164800 discloses an IGBT chip and a FW
D chips are stacked on top of each other and mounted on an insulating substrate. Then, a wide connection conductor (copper plate) instead of a bonding wire is sandwiched between the semiconductor chips stacked on top of each other and joined to the electrodes of the semiconductor chip with a conductive adhesive. A disclosed structure is disclosed.
【０００７】この構成によれば、図４に示したデバイス
の組立構造と比べて、絶縁基板，金属ベース板の所要面
積を大幅に縮減してデバイスの小形化，軽量化が図れる
ほか、パワー半導体チップに生じた熱の放熱性も改善さ
れる利点があるものの、内部配線部品として幅広の接続
導体（銅板）を要するほか、この接続導体を導電性接着
剤で半導体チップに接合するために、部品，工数が増え
てデバイスの製作費がコスト高となる。According to this structure, the required area of the insulating substrate and the metal base plate can be greatly reduced as compared with the assembly structure of the device shown in FIG. 4, so that the size and weight of the device can be reduced. Although it has the advantage of improving the heat dissipation of the heat generated in the chip, it requires a wide connection conductor (copper plate) as an internal wiring component, and the connection conductor is bonded to the semiconductor chip with a conductive adhesive, Therefore, the number of steps is increased, and the manufacturing cost of the device is increased.
【０００８】本発明は上記の点に鑑みなされたものであ
り、その目的はデバイスの小形，軽量化と併せて、放熱
性の向上，並びに製作コストの低減化が図れるように組
立構造を改良した半導体パワーデバイスを提供すること
にある。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to improve the assembly structure so that the heat dissipation and the manufacturing cost can be reduced in addition to the reduction in size and weight of the device. It is to provide a semiconductor power device.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、外囲ケースに組合せた金属ベース
板を放熱板として、該金属ベース板上に接合した絶縁基
板の上に第１のパワー半導体チップと第２のパワー半導
体チップを組にして搭載し、各パワー半導体チップの電
極とその電極に対応する絶縁基板の配線パターンとの間
を電気的に接続した上で、各配線パターンから外部導出
端子を引出した半導体パワーデバイスにおいて、前記第
１のパワー半導体チップと第２のパワー半導体チップを
上下に積み重ねてその電極の間を導電性ペーストで接合
するとともに、該接合部の導電性ペーストを含めて各パ
ワー半導体チップの上面側電極とその電極に対応する絶
縁基板の配線パターンとの間に導電性ペーストを延設し
て電気的および伝熱的に接続するようにする（請求項
１）。According to the present invention, in order to achieve the above object, according to the present invention, a metal base plate combined with an outer case is used as a heat radiating plate on an insulating substrate joined to the metal base plate. A first power semiconductor chip and a second power semiconductor chip are mounted as a set, and an electrode of each power semiconductor chip is electrically connected to a wiring pattern of an insulating substrate corresponding to the electrode. In a semiconductor power device having an external lead-out terminal drawn out from a wiring pattern, the first power semiconductor chip and the second power semiconductor chip are vertically stacked, and the electrodes thereof are joined with a conductive paste. The conductive paste is extended between the upper electrode of each power semiconductor chip, including the conductive paste, and the wiring pattern of the insulating substrate corresponding to the electrode to provide electrical and Manner so as to connect (claim 1).
【００１０】上記の構成によれば、絶縁基板，金属ベー
ス板の面積縮減によるデバイスの小形，軽量化と併せ
て、導電性ペーストがパワー半導体チップ間の接合、パ
ワー半導体チップの電極と絶縁基板の配線パターンとの
間の電気的な接続導体、および伝熱体としての機能を果
たすことになる。これにより、ワイヤボンディングが不
要となり、安価で信頼性の高い半導体パワーデバイスを
提供できる。According to the above-described structure, the size and weight of the device are reduced by reducing the area of the insulating substrate and the metal base plate, and at the same time, the conductive paste is bonded between the power semiconductor chips and the electrodes of the power semiconductor chip are connected to the insulating substrate. It functions as an electrical connection conductor between the wiring pattern and a heat conductor. As a result, wire bonding becomes unnecessary, and a low-cost and highly reliable semiconductor power device can be provided.
【００１１】また、前記の半導体パワーデバイスは、次
記のような実施態様で構成することができる。
(1) 導電性ペーストの延設経路に沿って、導電性ペース
トと電気的な接続が不要な部分との間を絶縁性ペースト
で絶縁する（請求項２）。
(2) 絶縁基板から引き出す外部導出端子の脚部を導電性
ペーストの上に重ねて接合する（請求項３）。The above-mentioned semiconductor power device can be constituted by the following embodiments. (1) The conductive paste is insulated from the portion that does not require electrical connection with an insulating paste along the conductive paste extending path (claim 2). (2) The legs of the external lead-out terminals drawn from the insulating substrate are overlapped and joined on the conductive paste.
【００１２】(3) 前記した第１のパワー半導体チップを
ＩＧＢＴ、第２のパワー半導体チップがＩＧＢＴに並列
接続するＦＷＤとして（請求項４）、ＩＧＢＴはコレク
タ電極を下面に向けて絶縁基板の配線パターンにマウン
トし、上面のエミッタ電極の上に導電性ペーストを介し
てＦＷＤをそのアノード電極を下向きで接合する（請求
項５）。(3) The first power semiconductor chip is an IGBT, and the second power semiconductor chip is an FWD connected in parallel to the IGBT (claim 4). The FWD is mounted on the pattern, and the FWD is bonded to the emitter electrode on the upper surface with the anode electrode facing down via a conductive paste.
【００１３】(4) 前項(3) とは逆に、ＩＧＢＴはエミッ
タ電極，ゲート電極を下面に向けて絶縁基板の配線パタ
ーンにマウントし、上面のコレクタ電極の上に導電性ペ
ーストを介してＦＷＤをそのカソード電極を下向気で接
合する（請求項６）。(4) Contrary to the above (3), the IGBT is mounted on a wiring pattern on an insulating substrate with the emitter electrode and the gate electrode facing downward, and the FWD is placed on the collector electrode on the upper surface via a conductive paste. Is joined with its cathode electrode in a downward direction (claim 6).
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態を図１
〜図３に示す実施例で説明する。なお、各実施例の図中
で図４に対応する部材には同じ符号を付してその説明は
省略する。〔実施例１〕図１(a),(b) は本発明の請求項
１，２，４，５に対応する実施例を示すものである。こ
の実施例においては、金属ベース板１および絶縁基板２
の所要面積を縮減するために、ＩＧＢＴ３とＦＷＤ４を
上下に積み重ねて次記のように基板上に実装する。すな
わち、ＩＧＢＴ３はコレクタ電極を下面に向けて絶縁基
板２に形成した配線パターン２ｂに半田マウントし、こ
のＩＧＢＴ３の上面側のエミッタ電極の上に導電性ペー
スト１１を介してＦＷＤ４がアノード電極を下に向けて
接合されている。さらに、この導電性ペースト１１はチ
ップの間から側方に伸ばして絶縁基板２の配線パターン
２ｃとの間に延在するように塗布し、この導電性ペース
ト１１を介して半導体チップと絶縁基板の配線パターン
との間を電気的，および伝熱的に接続している。また、
ＩＧＢＴ３のゲート電極と絶縁基板上に形成した配線パ
ターン２ｄとの間、およびＦＷＤ４の上面側のカソード
電極と配線パターン２ｂとの間も、前記と同様に導電性
ペースト１１を塗布して電気的，伝熱的に接続する。な
お、この実施例においては、外部導出端子としてのコレ
クタ端子６，エミッタ端子７およびゲート端子８は絶縁
基板２の配線パターン２ｂ，３ｃ，３ｄの上に半田付け
して接合されている。FIG. 1 is a block diagram showing an embodiment of the present invention.
3 will be described with reference to the embodiment shown in FIG. In the drawings of each embodiment, the members corresponding to those in FIG. Embodiment 1 FIGS. 1A and 1B show an embodiment corresponding to claims 1, 2, 4, and 5 of the present invention. In this embodiment, a metal base plate 1 and an insulating substrate 2
In order to reduce the required area, the IGBT 3 and the FWD 4 are vertically stacked and mounted on a substrate as described below. That is, the IGBT 3 is solder-mounted on the wiring pattern 2b formed on the insulating substrate 2 with the collector electrode facing down, and the FWD 4 is placed on the emitter electrode on the upper surface side of the IGBT 3 via the conductive paste 11 with the anode electrode down. It is joined toward. Further, the conductive paste 11 is applied so as to extend laterally from between the chips and to extend between the wiring pattern 2 c of the insulating substrate 2, and the semiconductor chip and the insulating substrate are applied through the conductive paste 11. The wiring pattern is electrically and thermally connected. Also,
Similarly, the conductive paste 11 is applied between the gate electrode of the IGBT 3 and the wiring pattern 2d formed on the insulating substrate, and between the cathode electrode on the upper surface side of the FWD 4 and the wiring pattern 2b. Connect thermally. In this embodiment, the collector terminal 6, the emitter terminal 7, and the gate terminal 8 as the external lead terminals are soldered and joined on the wiring patterns 2b, 3c, 3d of the insulating substrate 2.
【００１５】ここで、前記の導電性ペースト１１は、樹
脂を主体とするバインダに銀などの導電性フィラーを多
量に配合して高い導電性，伝熱性を付与したペーストで
あり、ディスペンサを使って所定の箇所に塗布するよう
にする。なお、導電性ペーストには紫外線硬化型，ある
いは熱硬化型など知られており、ペーストを塗布した半
導体チップには不要な加圧力を加えずに接合することが
可能である。Here, the conductive paste 11 is a paste having high conductivity and heat conductivity obtained by blending a large amount of a conductive filler such as silver in a binder mainly composed of a resin, and using a dispenser. It is applied to a predetermined location. The conductive paste is known to be an ultraviolet-curing type or a thermosetting type, and can be joined to a semiconductor chip coated with the paste without applying unnecessary pressure.
【００１６】また、導電性ペースト１１との接触が不要
な部分には、図示のように絶縁性ペースト１２を塗布
し、この絶縁性ペースト１２を下地としてその上に塗布
した導電性ペーストと絶縁するようにしている。また、
量産化に当たっては、絶縁性が問題となる半導体チップ
に対して、導電性ペースト１１を塗布する電極面の周縁
にガードリングとして図示のように絶縁性ペースト（ポ
リイミド樹脂など）１３をあらかじめ塗布しておくこと
により、導電性ペースト１１を塗布する際に電極面域か
ら外側にはみ出しなく塗布できる。An insulating paste 12 is applied to portions that do not need to be in contact with the conductive paste 11 as shown in the figure, and the insulating paste 12 is used as a base to insulate the conductive paste applied thereon. Like that. Also,
In mass production, an insulating paste (polyimide resin or the like) 13 is applied in advance as shown in the figure as a guard ring to the periphery of the electrode surface on which the conductive paste 11 is applied to a semiconductor chip having an insulating property. By doing so, when the conductive paste 11 is applied, it can be applied without protruding outside from the electrode surface area.
【００１７】上記の構成によれば、導電性ペースト１１
がＩＧＢＴ３とＦＷＤ４とを導電接合するほか、半導体
チップの電極とこれに対応する絶縁基板２の配線パター
ンとの間の電気的な接続体、および半導体チップの発生
熱を絶縁基板２に導く伝熱体としても機能する。したが
って、図４のボンディングワイヤ９による内部配線、さ
らには先記した特開２０００−１６４８００号公報に開
示のデバイスに採用している幅広な接続導体（銅板）を
省いて半導体パワーデバイスを組立てることができる。According to the above configuration, the conductive paste 11
Electrically connects the IGBT 3 and the FWD 4 to each other, electrically connects the electrodes of the semiconductor chip to the corresponding wiring patterns of the insulating substrate 2, and transfers heat generated by the semiconductor chip to the insulating substrate 2. It also functions as a body. Therefore, it is possible to assemble the semiconductor power device by omitting the internal wiring by the bonding wire 9 in FIG. 4 and the wide connection conductor (copper plate) used in the device disclosed in the aforementioned Japanese Patent Application Laid-Open No. 2000-164800. it can.
【００１８】〔実施例２〕図２(a),(b) は本発明の請求
項３に対応する応用実施例を示すものであり、その組立
構造は、基本的に先記実施例１と同様であるが、絶縁基
板２の配線パターン２ａ〜２ｃから引出した外部導出電
極としてのコレクタ端子６，エミッタ端子７およびゲー
ト端子８は配線パターン上に半田付けする代わりに、そ
の脚部６ａ，７ａ，８ａを同じ配線パターン上に塗布し
た導電性ペースト１１の上に重ね合わせて接合してい
る。この構成によれば、実施例１の組立構造と比べて外
部導出端子６〜８の半田付け工程が不要となる。[Embodiment 2] FIGS. 2 (a) and 2 (b) show an applied embodiment corresponding to claim 3 of the present invention. Similarly, collector terminals 6, emitter terminals 7, and gate terminals 8 as external lead-out electrodes drawn from the wiring patterns 2a to 2c of the insulating substrate 2 have their legs 6a, 7a instead of being soldered on the wiring pattern. , 8a are overlapped and joined on the conductive paste 11 applied on the same wiring pattern. According to this configuration, a soldering step of the external lead-out terminals 6 to 8 is not required as compared with the assembly structure of the first embodiment.
【００１９】〔実施例３〕次に、本発明の請求項６に対
応する実施例を図３(a),(b) に示す。この実施例におい
ては、先記実施例１，２と比べて、ＩＧＢＴ４とＦＷＤ
４の向きを上下反転して絶縁基板２の上に実装してお
り、ＩＧＢＴ３はエミッタ電極とゲート電極を下面に向
けて絶縁基板２の配線パターン２ｃと２ｄに跨がって半
田マウントし、その上面側のコレクタ電極の上に導電性
ペースト１１を介してカソード電極を下向きにＦＷＤ４
を積み重ねて接合した上で、ＩＧＢＴ３のコレクタ電極
と配線パターン２ｂとの間、およびＦＷＤ４の上面側の
アノード電極と配線パターン２ｃとの間に導電性ペース
ト１１を塗布して電気的および伝熱的に接続するように
している。[Embodiment 3] Next, an embodiment corresponding to claim 6 of the present invention is shown in FIGS. In this embodiment, the IGBT 4 and the FWD are compared with the first and second embodiments.
The IGBT 3 is mounted on the insulating substrate 2 with the emitter electrode and the gate electrode facing the lower surface so as to straddle the wiring patterns 2c and 2d of the insulating substrate 2 by reversing the direction of 4 and mounting it on the insulating substrate 2. The cathode electrode is placed downward on the collector electrode on the upper surface side with the conductive paste 11
Are stacked and joined, and a conductive paste 11 is applied between the collector electrode of the IGBT 3 and the wiring pattern 2b and between the anode electrode on the upper surface side of the FWD 4 and the wiring pattern 2c to provide electrical and heat transfer. To connect to.
【００２０】この組立構造によれば、先記実施例１，２
と比べて、ＩＧＢＴ３のゲート電極と絶縁基板２の配線
パターン２ｄとの間に塗布する導電性ペースト１１，絶
縁性ペースト１２を省略できる。According to this assembling structure, the first and second embodiments are used.
In comparison with the above, the conductive paste 11 and the insulating paste 12 applied between the gate electrode of the IGBT 3 and the wiring pattern 2d of the insulating substrate 2 can be omitted.
【００２１】[0021]
【発明の効果】以上述べたように、本発明の構成によれ
ば、外囲ケースに組合せた金属ベース板を放熱板とし
て、該金属ベース板上に接合した絶縁基板の上に第１の
パワー半導体チップ（ＩＧＢＴ）と第２のパワー半導体
チップ（ＦＷＤ）を組にして搭載し、各パワー半導体チ
ップの電極とその電極に対応する絶縁基板の配線パター
ンとの間を電気的に接続した上で、各配線パターンから
外部導出端子を引出した半導体パワーデバイスにおい
て、前記第１のパワー半導体チップと第２のパワー半導
体チップを上下に重ねてその電極の間を導電性ペースト
で接合するとともに、該接合部の導電性ペーストを含め
て各パワー半導体チップの上面側電極とその電極に対応
する絶縁基板の配線パターンとの間に導電性ペーストを
延設して電気的および伝熱的に接続したことにより、絶
縁基板，金属ベース板の面積縮減による半導体パワーデ
バイスの小形，軽量化と併せて、上下に積み重ねたパワ
ー半導体チップ間の接合，半導体チップの各電極と基板
の配線パターンとの間の電気的な接続および伝熱を導電
性ペーストを介して行うことができ、これによりボンデ
ィングワイヤによる内部配線を不要として、信頼性の高
い半導体パワーデバイスを安価に提供することができ
る。As described above, according to the structure of the present invention, the first power is placed on the insulating substrate joined to the metal base plate by using the metal base plate combined with the surrounding case as the heat sink. A semiconductor chip (IGBT) and a second power semiconductor chip (FWD) are mounted as a set, and an electrode of each power semiconductor chip is electrically connected to a wiring pattern of an insulating substrate corresponding to the electrode. A first power semiconductor chip and a second power semiconductor chip are vertically stacked on a semiconductor power device in which an external lead terminal is drawn out of each wiring pattern; The conductive paste is extended between the upper surface side electrode of each power semiconductor chip including the conductive paste of the portion and the wiring pattern of the insulating substrate corresponding to the electrode, thereby providing electrical and electrical Due to the thermal connection, the size and weight of the semiconductor power device can be reduced by reducing the area of the insulating substrate and the metal base plate, as well as bonding between power semiconductor chips stacked one above the other, and wiring between the electrodes of the semiconductor chip and the substrate. Electrical connection and heat transfer with the pattern can be made via the conductive paste, thereby eliminating the need for internal wiring using bonding wires and providing a highly reliable semiconductor power device at low cost. .
【図１】本発明の実施例１に対応する半導体パワーデバ
イスの組立構造図で、(a),(b)はそれぞれ縦断側面図，
および横断平面図FIG. 1 is an assembly structural view of a semiconductor power device corresponding to a first embodiment of the present invention, wherein (a) and (b) are longitudinal side views,
And cross section plan
【図２】本発明の実施例２に対応する半導体パワーデバ
イスの組立構造図で、(a),(b)はそれぞれ縦断側面図，
および横断平面図FIGS. 2A and 2B are structural views of a semiconductor power device according to a second embodiment of the present invention, in which FIGS.
And cross section plan
【図３】本発明の実施例３に対応する半導体パワーデバ
イスの組立構造図で、(a),(b)はそれぞれ縦断側面図，
および横断平面図FIG. 3 is an assembly structure diagram of a semiconductor power device corresponding to a third embodiment of the present invention, wherein (a) and (b) are longitudinal side views,
And cross section plan
【図４】従来における半導体パワーデバイスの組立構造
図で、(a),(b) はそれぞれ縦断側面図，および横断平面
図4A and 4B are longitudinal sectional side views and cross-sectional plan views, respectively, of a conventional semiconductor power device assembly structure diagram.
１ 金属ベース板 ２ 絶縁基板 ２ｂ，２ｃ，２ｄ 配線パターン ３ ＩＧＢＴ（第１のパワー半導体チップ） ４ ＦＷＤ（第２のパワー半導体チップ） ５ 外囲ケース ６ コレクタ端子（外部接続端子） ７ エミッタ端子（外部接続端子） ８ ゲート端子（外部接続端子） ６ａ，７ａ，８ａ 脚部 １１ 導電性ペースト １２ 絶縁性ペースト 1 Metal base plate 2 Insulating substrate 2b, 2c, 2d Wiring pattern 3 IGBT (first power semiconductor chip) 4 FWD (second power semiconductor chip) 5 Outer case 6 Collector terminal (external connection terminal) 7 Emitter terminal (external connection terminal) 8 Gate terminal (external connection terminal) 6a, 7a, 8a Legs 11 conductive paste 12 Insulating paste
Claims (6)
板として、該金属ベース板上に接合した絶縁基板の上に
第１のパワー半導体チップと第２のパワー半導体チップ
を組にして搭載し、各パワー半導体チップの電極とその
電極に対応する絶縁基板の配線パターンとの間を電気的
に接続した上で、各配線パターンから外部導出端子を引
出した半導体パワーデバイスにおいて、 前記第１のパワー半導体チップと第２のパワー半導体チ
ップを上下に積み重ねてその電極の間を導電性ペースト
で接合するとともに、該接合部の導電性ペーストを含め
て各パワー半導体チップの上面側電極とその電極に対応
する絶縁基板の配線パターンとの間に導電性ペーストを
延設して電気的および伝熱的に接続したことを特徴とす
る半導体パワーデバイス。1. A first power semiconductor chip and a second power semiconductor chip are mounted as a set on an insulating substrate joined to the metal base plate, using the metal base plate combined with the surrounding case as a heat sink. A semiconductor power device in which an electrode of each power semiconductor chip is electrically connected to a wiring pattern of an insulating substrate corresponding to the electrode, and an external lead-out terminal is drawn out of each wiring pattern; The power semiconductor chip and the second power semiconductor chip are stacked one on top of the other, and the electrodes thereof are joined with a conductive paste. A semiconductor power device wherein a conductive paste is extended and electrically and thermally conductively connected to a wiring pattern of a corresponding insulating substrate.
いて、導電性ペーストの延設経路に沿って、導電性ペー
ストと電気的な接続が不要な部分との間を絶縁性ペース
トで絶縁隔離したことを特徴とする半導体パワーデバイ
ス。2. The semiconductor power device according to claim 1, wherein an insulating paste is provided between the conductive paste and a portion that does not need to be electrically connected with the conductive paste along an extending path of the conductive paste. A semiconductor power device characterized by the above-mentioned.
いて、絶縁基板上で外部導出端子の脚部を導電性ペース
トの上に重ねて接合したことを特徴とする半導体パワー
デバイス。3. The semiconductor power device according to claim 1, wherein the legs of the external lead-out terminal are overlapped and joined on the conductive paste on the insulating substrate.
いて、第１のパワー半導体チップがＩＧＢＴ、第２のパ
ワー半導体チップがＩＧＢＴに並列接続するＦＷＤであ
ることを特徴とする半導体パワーデバイス。4. The semiconductor power device according to claim 1, wherein the first power semiconductor chip is an IGBT and the second power semiconductor chip is an FWD connected to the IGBT in parallel.
いて、ＩＧＢＴはコレクタ電極を下面にして絶縁基板の
配線パターンにマウントした上で、上面のエミッタ電極
の上に導電性ペーストを介してＦＷＤをそのアノード電
極を下向きで接合したことを特徴とする半導体パワーデ
バイス。5. The semiconductor power device according to claim 4, wherein the IGBT is mounted on a wiring pattern of an insulating substrate with the collector electrode facing downward, and the FWD is mounted on the emitter electrode on the upper surface via a conductive paste. A semiconductor power device having an anode electrode joined downward.
いて、ＩＧＢＴはエミッタ電極，ゲート電極を下面に向
けて絶縁基板の配線パターンにマウントした上で、上面
のコレクタ電極の上に導電性ペーストを介してＦＷＤを
そのカソード電極を下向きで接合したことを特徴とする
半導体パワーデバイス。6. The semiconductor power device according to claim 4, wherein the IGBT is mounted on the wiring pattern of the insulating substrate with the emitter electrode and the gate electrode facing the lower surface, and the conductive paste is interposed on the collector electrode on the upper surface. A semiconductor power device wherein the FWD is joined with its cathode electrode facing downward.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002152665A JP2003347507A (en) | 2002-05-27 | 2002-05-27 | Semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002152665A JP2003347507A (en) | 2002-05-27 | 2002-05-27 | Semiconductor power device |
Publications (1)
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| JP2003347507A true JP2003347507A (en) | 2003-12-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016136457A1 (en) * | 2015-02-25 | 2016-09-01 | 三菱電機株式会社 | Power module |
| KR20160109573A (en) * | 2015-03-12 | 2016-09-21 | 제엠제코(주) | Semiconductor chip package using clip and manufacturing method for the same |
| CN111162057A (en) * | 2020-01-06 | 2020-05-15 | 珠海格力电器股份有限公司 | Semiconductor power device and power processing assembly for semiconductor power device |
-
2002
- 2002-05-27 JP JP2002152665A patent/JP2003347507A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016136457A1 (en) * | 2015-02-25 | 2016-09-01 | 三菱電機株式会社 | Power module |
| JPWO2016136457A1 (en) * | 2015-02-25 | 2017-06-15 | 三菱電機株式会社 | Power module |
| CN107210238A (en) * | 2015-02-25 | 2017-09-26 | 三菱电机株式会社 | Power model |
| US10559538B2 (en) | 2015-02-25 | 2020-02-11 | Mitsubishi Electric Corporation | Power module |
| KR20160109573A (en) * | 2015-03-12 | 2016-09-21 | 제엠제코(주) | Semiconductor chip package using clip and manufacturing method for the same |
| KR101669902B1 (en) * | 2015-03-12 | 2016-10-28 | 제엠제코(주) | Semiconductor chip package using clip and manufacturing method for the same |
| CN111162057A (en) * | 2020-01-06 | 2020-05-15 | 珠海格力电器股份有限公司 | Semiconductor power device and power processing assembly for semiconductor power device |
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