JP2003347488A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2003347488A JP2003347488A JP2002151764A JP2002151764A JP2003347488A JP 2003347488 A JP2003347488 A JP 2003347488A JP 2002151764 A JP2002151764 A JP 2002151764A JP 2002151764 A JP2002151764 A JP 2002151764A JP 2003347488 A JP2003347488 A JP 2003347488A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- groove
- conductive material
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、放熱性能を向上さ
せた半導体装置およびその製造方法に関するもので、特
に、支持基板上に半導体層が積層されてなる半導体装置
およびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having improved heat radiation performance and a method of manufacturing the same, and more particularly to a semiconductor device having a semiconductor layer laminated on a supporting substrate and a method of manufacturing the same. .
【０００２】[0002]
【従来の技術】半導体素子の高速化や高集積化のため
に、ＳＯＩ（Silicon On Insulator）技術が用いられて
いる。ＳＯＩは、絶縁性基体上に半導体層を形成し、そ
の半導体層に半導体素子を形成するものである。2. Description of the Related Art SOI (Silicon On Insulator) technology is used to increase the speed and integration of semiconductor devices. In the SOI, a semiconductor layer is formed on an insulating substrate, and a semiconductor element is formed on the semiconductor layer.
【０００３】また、高速化・高集積化が進んだ半導体チ
ップの実装方法として、フリップチップ実装が行われて
いる。フリップチップ実装は、半導体素子を形成した半
導体チップの主面に半田バンプを設け、その半田バンプ
により、半導体チップの主面と当該チップを搭載する配
線基板を向かい合わせて接続する構造である。フリップ
チップ実装は、配線遅延を低減することができ、またパ
ッケージを小型にできるので、前記ＳＯＩ技術による半
導体チップの高速化・高集積化と相性の良い実装方法で
ある。このフリップチップ実装においては、近年、さら
なる小型化を目的として、前記配線基板の大きさを半導
体チップの大きさにほぼ等しくした、ＣＳＰ（Chip Siz
e Package）構造の検討が行われている。[0003] As a method of mounting a semiconductor chip with higher speed and higher integration, flip chip mounting is performed. The flip-chip mounting is a structure in which a solder bump is provided on a main surface of a semiconductor chip on which a semiconductor element is formed, and the main surface of the semiconductor chip and a wiring board on which the chip is mounted face-to-face and connected by the solder bump. Flip chip mounting is a mounting method that is compatible with high-speed and high-integration of a semiconductor chip by the SOI technology, because wiring delay can be reduced and a package can be reduced in size. In this flip-chip mounting, in recent years, for the purpose of further miniaturization, the size of the wiring board has been made substantially equal to the size of a semiconductor chip, and a CSP (Chip Siz
e Package) structure is being studied.
【０００４】[0004]
【発明が解決しようとする課題】前記ＳＯＩ技術により
高速化、高集積化が進められた半導体素子においては、
動作中において発生する熱が、熱伝導性の低い支持基板
の存在により、半導体装置の外に放熱され難いという問
題点がある。SUMMARY OF THE INVENTION In a semiconductor device whose speed and integration have been advanced by the SOI technology,
There is a problem that heat generated during operation is hard to be radiated outside the semiconductor device due to the presence of the supporting substrate having low thermal conductivity.
【０００５】また、フリップチップ実装においても、従
来の半導体チップ裏面を配線基板に貼り付ける実装方法
に比較して、放熱能力は低下しており、特にＣＳＰ構造
において厳しくなっている。Also, in the flip-chip mounting, the heat radiation ability is lower than that of the conventional mounting method in which the back surface of the semiconductor chip is attached to a wiring board, and the CSP structure is particularly severe.
【０００６】このため、高速化・高集積化が進められた
前記半導体装置においては、素子特性の変化、配線抵抗
の増大、半田バンプの融解、熱応力による保護膜剥離と
いった問題が発生しやすい。For this reason, in the semiconductor device which has been advanced in speed and integration, problems such as changes in element characteristics, increase in wiring resistance, melting of solder bumps, and peeling of the protective film due to thermal stress are likely to occur.
【０００７】そこで本発明の目的は、ＳＯＩ技術による
半導体素子の高速化・高集積化と、フリップチップ実装
によるパッケージの小型化を阻害することなく、放熱性
能を向上させた半導体装置およびその製造方法を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having improved heat dissipation performance without impeding high-speed and high-integration of a semiconductor element by SOI technology and miniaturization of a package by flip-chip mounting, and a method of manufacturing the same. Is to provide.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、請求項１に記載の発明は、支持基板上に半導体層が
積層されてなる半導体装置において、半導体層側の第１
表面に半導体素子が形成され、支持基板側の第２表面か
ら前記半導体層へ向けて溝が形成され、当該溝内に支持
基板より熱伝導率の大きな高熱伝導材料が埋め込まれる
ことを特徴としている。According to a first aspect of the present invention, there is provided a semiconductor device in which a semiconductor layer is laminated on a supporting substrate.
A semiconductor element is formed on the surface, a groove is formed from the second surface on the support substrate side toward the semiconductor layer, and a high heat conductive material having a higher thermal conductivity than the support substrate is embedded in the groove. .
【０００９】これによれば、支持基板の溝内に埋め込ま
れた高熱伝導材料を介して、半導体素子の動作中に半導
体層側の第１表面で発生した熱が、すばやく支持基板側
の第２表面に伝達し、そこから放熱される。従って、半
導体装置の放熱性能が向上し、動作中の半導体素子の温
度上昇を低減することができるため、温度上昇による素
子の特性変化も低減することができる。According to this, the heat generated on the first surface on the semiconductor layer side during the operation of the semiconductor element is quickly transferred to the second surface on the support substrate side through the high thermal conductive material embedded in the groove of the support substrate. Transfers to the surface, from which heat is dissipated. Therefore, the heat dissipation performance of the semiconductor device is improved, and the temperature rise of the semiconductor element during operation can be reduced, so that a change in the characteristics of the element due to the temperature rise can be reduced.
【００１０】請求項２に記載の発明は、支持基板が、少
なくとも一方の表面に絶縁層が形成された半導体基板で
あり、前記半導体層が当該絶縁層の上に積層されること
を特徴としている。これによれば、半導体基板の内部に
酸化膜等の絶縁層を有する、いわゆるＳＯＩ構造の半導
体基板において、半導体素子の温度上昇を防止すること
ができる。According to a second aspect of the present invention, the support substrate is a semiconductor substrate having an insulating layer formed on at least one surface, and the semiconductor layer is laminated on the insulating layer. . According to this, in a semiconductor substrate having a so-called SOI structure having an insulating layer such as an oxide film inside the semiconductor substrate, a temperature rise of the semiconductor element can be prevented.
【００１１】請求項３に記載の発明は、半導体素子が発
熱量の大きな発熱素子であり、前記溝が当該発熱素子の
直下に形成されることを特徴としている。これによれ
ば、発熱素子の発生する熱を、発熱素子の直下に形成し
た溝内に埋め込まれた高熱伝導材料を介して、すばやく
直下の第２表面に伝達することができる。このため、発
熱素子の発生する熱が同じ半導体層内で発熱素子の周囲
に形成された他の素子へ伝達するのを抑制することがで
き、発熱素子の熱の広がりを抑えて他の素子への熱影響
を低減することができる。The invention according to claim 3 is characterized in that the semiconductor element is a heating element having a large heat value, and the groove is formed immediately below the heating element. According to this, the heat generated by the heating element can be quickly transmitted to the second surface immediately below via the high heat conductive material embedded in the groove formed immediately below the heating element. For this reason, it is possible to suppress the heat generated by the heating element from being transmitted to other elements formed around the heating element in the same semiconductor layer, and to suppress the spread of heat of the heating element to other elements. Can reduce the thermal effect of
【００１２】請求項４に記載の発明は、前記溝が、第２
表面に向かって広がる順テーパ形状に形成されることを
特徴としている。これによれば、溝形状を順テーパ形状
にすることで、前記高熱伝導材料の溝内への埋め込み性
を良くすることができるので、熱の伝達性が向上して、
半導体装置の放熱性能が向上する。[0012] According to a fourth aspect of the present invention, the groove is a second groove.
It is characterized by being formed in a forward tapered shape spreading toward the surface. According to this, by making the groove shape a forward taper shape, the embedding property of the high thermal conductive material in the groove can be improved, so that the heat transfer property is improved,
The heat radiation performance of the semiconductor device is improved.
【００１３】請求項５に記載の発明は、高熱伝導材料
が、銅、アルミニウム、銀、金、銅合金、アルミニウム
合金、銀合金、金合金のいずれかであることを特徴とし
ている。これによれば、これらの高熱伝導材料はいずれ
も熱伝導率が大きく、前記の半導体装置において、素子
で発生した熱をすばやく支持基板側の第２表面に伝達
し、放熱することができる。The invention according to claim 5 is characterized in that the high heat conductive material is any of copper, aluminum, silver, gold, copper alloy, aluminum alloy, silver alloy, and gold alloy. According to this, each of these high heat conductive materials has a high thermal conductivity, and in the above-described semiconductor device, heat generated in the element can be quickly transmitted to the second surface on the support substrate side and radiated.
【００１４】請求項６に記載の発明は、高熱伝導材料
が、第２表面上にも連結して形成されることを特徴とし
ている。これによれば、第２表面上に連結して形成され
る高熱伝導材料により、第２表面に伝達された熱の放熱
性能をより高めることができる。The invention according to claim 6 is characterized in that the high heat conductive material is formed so as to be connected also on the second surface. According to this, the heat dissipation performance of the heat transmitted to the second surface can be further improved by the high heat conductive material formed by being connected on the second surface.
【００１５】請求項７に記載の発明は、高熱伝導材料に
当接して、放熱部材が配置されることを特徴としてい
る。これによれば、高熱伝導材料に当接して配置された
放熱部材により、第２表面に伝達された熱の放熱性能
を、さらに高めることができる。According to a seventh aspect of the present invention, a heat radiating member is disposed in contact with the high heat conductive material. According to this, the heat dissipating member arranged in contact with the high heat conductive material can further enhance the heat dissipating performance of the heat transmitted to the second surface.
【００１６】請求項８に記載したように、本発明は、半
導体層側の第１表面に半田バンプが形成され、半田バン
プを配線基板に接続する、いわゆるフリップチップ実装
に適用して効果的である。フリップチップ実装において
は、実装構造上、放熱に対しては不利であるが、本発明
を適用することでその不利を解消することができ、必要
な放熱性能を確保することができる。The present invention is effective when applied to a so-called flip chip mounting in which a solder bump is formed on a first surface on a semiconductor layer side and the solder bump is connected to a wiring board. is there. In flip-chip mounting, it is disadvantageous for heat radiation due to the mounting structure. However, by applying the present invention, the disadvantage can be solved and necessary heat radiation performance can be secured.
【００１７】また請求項９に記載したように、本発明
は、配線基板が支持基板とほぼ同じサイズである、いわ
ゆるＣＳＰに適用して効果的である。配線基板が支持基
板とほぼ同じで、フリップチップ実装の中でも放熱にお
いて非常に厳しい構造となっているＣＳＰにおいても、
本発明により、必要な放熱性能を確保することができ
る。Further, as described in claim 9, the present invention is effective when applied to a so-called CSP in which the wiring substrate has substantially the same size as the support substrate. Even in CSPs, where the wiring substrate is almost the same as the support substrate and has a very severe structure for heat dissipation in flip chip mounting,
According to the present invention, necessary heat radiation performance can be secured.
【００１８】請求項１０〜１２に記載した発明は、上述
した半導体装置の製造方法に関するものである。The invention according to claims 10 to 12 relates to a method for manufacturing the above-described semiconductor device.
【００１９】その作用効果は同様であるので詳細説明は
省略するが、請求項１０に記載した第２表面から半導体
層へ向けて溝を形成する第２工程は、第１表面に半導体
素子を形成する第１工程の前に行ってもよいし、第１工
程の後に行ってもよい。第３工程は第２工程の後に行う
が、高熱伝導材料の耐熱性が低い場合には、第３工程は
第１工程と第２工程の後に行い、耐熱性が高い場合に
は、第２工程と第３工程を第１工程の前に行うこともで
きる。Since the operation and effect are the same, detailed description is omitted, but the second step of forming a groove from the second surface to the semiconductor layer according to claim 10 forms a semiconductor element on the first surface. May be performed before the first step to be performed, or may be performed after the first step. The third step is performed after the second step. When the heat resistance of the high heat conductive material is low, the third step is performed after the first step and the second step. When the heat resistance is high, the second step is performed. And the third step can be performed before the first step.
【００２０】さらに、請求項１１に記載したように、半
導体素子が発熱量の大きな発熱素子である場合には、溝
を発熱素子の直下に選択的に形成して、周りの半導体素
子への熱の影響を選択的に抑制することができる。ま
た、請求項１２に記載したように、エッチングで溝を順
テーパ形状に形成して、高熱伝導材料の埋め込み性と熱
の伝達性を向上することができる。Further, when the semiconductor element is a heating element having a large amount of heat generation, the groove is selectively formed directly below the heating element to provide heat to the surrounding semiconductor elements. Can be selectively suppressed. In addition, as described in the twelfth aspect, the grooves are formed in a forward tapered shape by etching, so that the embedding property of the high heat conductive material and the heat transfer property can be improved.
【００２１】[0021]
【発明の実施の形態】（第１の実施形態）以下、本発明
の実施形態を、図に基づいて説明する。(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.
【００２２】図１（ａ）は、本発明の第１実施形態にお
ける半導体装置を示す断面模式図であり、図１（ｂ）
は、当該半導体装置の配線基板への搭載状態を示す断面
図である。FIG. 1A is a schematic sectional view showing a semiconductor device according to the first embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a state where the semiconductor device is mounted on a wiring board.
【００２３】図１（ａ）に示す半導体装置１０１は、支
持基板１１と、支持基板１１上に積層された半導体層１
０からなり、支持基板１１と半導体層１０が半導体チッ
プ１２を構成している。半導体層１０側の表面７０に
は、半導体素子８１，８２，８３が形成されている。ま
た、支持基板１１側の表面７１には半導体層１０に向か
う複数の溝２が形成され、溝２内には支持基板１１より
熱伝導率の大きな高熱伝導材料３が埋め込まれている。A semiconductor device 101 shown in FIG. 1A has a support substrate 11 and a semiconductor layer 1 laminated on the support substrate 11.
The support substrate 11 and the semiconductor layer 10 constitute a semiconductor chip 12. Semiconductor elements 81, 82, and 83 are formed on the surface 70 on the semiconductor layer 10 side. A plurality of grooves 2 are formed in the surface 71 on the support substrate 11 side toward the semiconductor layer 10, and the high heat conductive material 3 having a higher thermal conductivity than the support substrate 11 is embedded in the grooves 2.
【００２４】図１（ｂ）に示す半導体装置１０１の配線
基板５への搭載では、半導体素子８１，８２，８３を形
成した半導体層１０側の表面７０に半田バンプ４が形成
されており、半田バンプ４を介して半導体チップ１２が
配線基板５に接続されている。図１（ｂ）に示す半導体
チップ１２の実装方法は、素子の形成された半導体チッ
プ１２の主面７０と配線基板５が対向して接続される、
いわゆるフリップチップと呼ばれる実装方法である。When the semiconductor device 101 is mounted on the wiring board 5 shown in FIG. 1B, the solder bumps 4 are formed on the surface 70 on the side of the semiconductor layer 10 on which the semiconductor elements 81, 82 and 83 are formed. The semiconductor chip 12 is connected to the wiring board 5 via the bump 4. In the mounting method of the semiconductor chip 12 shown in FIG. 1B, the main surface 70 of the semiconductor chip 12 on which elements are formed and the wiring board 5 are connected to face each other.
This is a so-called flip chip mounting method.
【００２５】半導体装置１０１における支持基板１１
は、金属や半導体のような導電性基体であってもよい
が、支持基板１１が絶縁性基体の場合には、半導体チッ
プ１２はＳＯＩ（Silicon On Insulator）と呼ばれる。
ＳＯＩ基板を用いると、半導体層１０に形成される各半
導体素子８１，８２，８３を高速化・高集積化すること
ができる。一方、ＳＯＩ基板に用いられる絶縁性基体１
１は、熱伝導性が良くない。このため、ＳＯＩにより半
導体素子が高集積化される程、動作中に発生する熱で各
半導体素子が温度上昇し、素子特性に悪影響が及ぶ。Support substrate 11 in semiconductor device 101
May be a conductive substrate such as a metal or a semiconductor, but when the support substrate 11 is an insulating substrate, the semiconductor chip 12 is called an SOI (Silicon On Insulator).
When an SOI substrate is used, each of the semiconductor elements 81, 82, and 83 formed in the semiconductor layer 10 can be operated at high speed and with high integration. On the other hand, the insulating substrate 1 used for the SOI substrate
No. 1 has poor thermal conductivity. For this reason, as semiconductor elements are highly integrated by SOI, the temperature of each semiconductor element rises due to heat generated during operation, which adversely affects the element characteristics.
【００２６】また、図１（ｂ）に示すフリップチップ実
装は、従来の半導体チップの裏面側７１を配線基板５に
貼り付けワイヤボンディングにより配線接続する方法と
比較し、半田バンプ４による接続のみで長いリード線が
不要となるため、配線遅延を低減することができる。ま
たパッケージを小型にできるので、ＳＯＩを用いた半導
体チップの高集積化・高速化にも対応した実装方法であ
る。このフリップチップ実装においては、近年、小型化
を目的として、配線基板５の大きさを半導体チップ１
２，１６の大きさにほぼ等しくした、ＣＳＰ（Chip Siz
e Package）の検討が進められている。The flip-chip mounting shown in FIG. 1B is different from the conventional method in which the back side 71 of the semiconductor chip is attached to the wiring board 5 and connected by wire bonding, and only the connection by the solder bumps 4 is used. Since long lead wires are not required, wiring delay can be reduced. Further, since the package can be reduced in size, it is a mounting method corresponding to high integration and high speed of a semiconductor chip using SOI. In the flip chip mounting, in recent years, the size of the wiring board 5 has been
CSP (Chip Siz) which is almost equal to the size of 2,16
e Package) is under consideration.
【００２７】フリップチップ実装は、従来の半導体チッ
プ裏面側７１の全体が配線基板５に貼り付けられる実装
方法と比較し、半導体層１０において素子の動作中に発
生する熱が配線基板５に伝達しにくいため、構造上は放
熱に対して不利である。In flip-chip mounting, heat generated during operation of the element in the semiconductor layer 10 is transmitted to the wiring substrate 5 as compared with the conventional mounting method in which the entire back side 71 of the semiconductor chip is attached to the wiring substrate 5. This is disadvantageous for heat radiation because of its difficulty.
【００２８】本発明の図１（ａ），（ｂ）の半導体装置
１０１においては、半導体素子８１，８２，８３の動作
中に発生する熱を、支持基板１１の溝２に埋め込まれた
高熱伝導材料３を介して迅速に支持基板１１の表面７１
に伝達し、表面７１から放熱することができる。高熱伝
導材料３としてはできるだけ熱伝導率が大きな金属が望
ましく、特に、銅（Ｃｕ）、アルミニウム（Ａｌ）、銀
（Ａｇ）、金（Ａｕ）、銅合金、アルミニウム合金、銀
合金、金合金のいずれかの金属が好ましい。このように
して、図１（ａ），（ｂ）の半導体装置１０１において
は、ＳＯＩにより高集積化され多量の熱が発生する半導
体装置１０１であっても、半導体素子８１，８２，８３
の温度上昇を抑制することができ、素子特性の変化を低
減することができる。In the semiconductor device 101 of FIGS. 1A and 1B according to the present invention, the heat generated during the operation of the semiconductor elements 81, 82, 83 is transferred to the high thermal conductivity embedded in the groove 2 of the support substrate 11. The surface 71 of the support substrate 11 is quickly slid through the material 3.
And heat can be dissipated from the surface 71. As the high thermal conductive material 3, a metal having a thermal conductivity as large as possible is desirable. In particular, copper (Cu), aluminum (Al), silver (Ag), gold (Au), copper alloy, aluminum alloy, silver alloy, and gold alloy are preferable. Either metal is preferred. In this manner, in the semiconductor device 101 of FIGS. 1A and 1B, even if the semiconductor device 101 is highly integrated by SOI and generates a large amount of heat, the semiconductor elements 81, 82, 83
Can be suppressed, and a change in element characteristics can be reduced.
【００２９】また、本発明の半導体装置１０１において
は、半導体チップの裏面側である支持基板１１の表面７
１を放熱面とし、素子で発生した熱を支持基板１１の溝
２に埋め込まれた高熱伝導材料３を介して迅速に表面７
１に伝達している。このため、フリップチップ実装にお
いても、必要な放熱性能を確保することができ、素子特
性の変化、配線抵抗の増大、半田バンプの融解、熱応力
による保護膜剥離といった問題の発生を抑制することが
できる。Further, in the semiconductor device 101 of the present invention, the front surface 7 of the support substrate 11, which is the back side of the semiconductor chip,
1 is a heat-dissipating surface, and the heat generated by the element is quickly transferred to the surface 7 through the high heat conductive material 3 embedded in the groove 2 of the support substrate 11.
To one. Therefore, even in flip-chip mounting, necessary heat radiation performance can be secured, and the occurrence of problems such as changes in element characteristics, increase in wiring resistance, melting of solder bumps, and peeling of the protective film due to thermal stress can be suppressed. it can.
【００３０】以上のように、本発明は、ＳＯＩによる半
導体素子の高速化・高集積化と、フリップチップ実装に
よるパッケージの小型化を阻害することなく、放熱性能
を向上させることができる。As described above, according to the present invention, the heat dissipation performance can be improved without impeding the high speed and high integration of the semiconductor element by the SOI and the miniaturization of the package by the flip chip mounting.
【００３１】図２（ａ）〜（ｅ）は、図１（ａ），
（ｂ）に示した半導体装置１０１の製造工程を示す工程
別の断面図である。半導体装置１０１の製造は、以下の
とおりである。FIGS. 2A to 2E show FIGS.
FIG. 9 is a cross-sectional view illustrating a manufacturing step of the semiconductor device 101 illustrated in FIG. The manufacture of the semiconductor device 101 is as follows.
【００３２】図２（ａ）に示すように、最初に、シリコ
ン基板（ウェハ）と支持基板１１を用意し、加熱により
両者を貼り合わせて、貼り合わせ基板を形成する。その
後、貼り合わされたシリコン基板を研磨して、１０μｍ
厚程度のシリコン半導体層１０に加工する。As shown in FIG. 2A, first, a silicon substrate (wafer) and a support substrate 11 are prepared, and both are bonded by heating to form a bonded substrate. Then, the bonded silicon substrate is polished to 10 μm
It is processed into a silicon semiconductor layer 10 having a thickness of approximately.
【００３３】次に、図２（ｂ）に示すように、所定の工
程を用いて、半導体層１０の表面７０に、半導体素子８
１，８２，８３を形成する。Next, as shown in FIG. 2B, the semiconductor element 8 is formed on the surface 70 of the semiconductor layer 10 by using a predetermined process.
1, 82 and 83 are formed.
【００３４】次に、図２（ｃ）に示すように、基板を反
転し、支持基板１１の表面７１に所定の開口部を有する
マスクを配置して、支持基板１１を表面７１からほぼ垂
直にドライエッチングし、溝２を形成する。溝２の形成
には、ウェットエッチングや機械的なドリル加工を用い
てもよい。Next, as shown in FIG. 2C, the substrate is turned upside down, a mask having a predetermined opening is arranged on the surface 71 of the support substrate 11, and the support substrate 11 is placed almost vertically from the surface 71. The groove 2 is formed by dry etching. The grooves 2 may be formed by wet etching or mechanical drilling.
【００３５】次に、図２（ｄ）に示すように、溝２が形
成された支持基板１１に、高熱伝導材料３を埋め込む。
高熱伝導材料３は、前記したように、Ｃｕ、Ａｌ、Ａ
ｇ、Ａｕ、Ｃｕ合金、Ａｌ合金、Ａｇ合金、Ａｕ合金が
好ましい。これら金属による溝３の埋め込みは、スパッ
タ等の物理的気相成長、またはＣＶＤ等の化学的気相成
長により行うことができる。高熱伝導材料３により溝２
を埋め込んだ後、表面に残った高熱伝導材料３を化学機
械研磨でエッチバックし、表面を平らにする。Next, as shown in FIG. 2D, the high heat conductive material 3 is embedded in the support substrate 11 in which the grooves 2 are formed.
As described above, the high thermal conductive material 3 is made of Cu, Al, A
g, Au, Cu alloy, Al alloy, Ag alloy and Au alloy are preferred. The filling of the groove 3 with these metals can be performed by physical vapor deposition such as sputtering or chemical vapor deposition such as CVD. Groove 2 made of high thermal conductive material 3
After embedding, the high heat conductive material 3 remaining on the surface is etched back by chemical mechanical polishing to flatten the surface.
【００３６】次に、図２（ｅ）に示すように、半導体層
１０側の表面７０に半田バンプ４を形成し、基板をカッ
トして半導体チップ１２とする。最後に、半導体チップ
１２に形成した半田バンプ４を配線基板５に接合して、
半導体装置１０１が完成する。Next, as shown in FIG. 2E, the solder bumps 4 are formed on the surface 70 on the semiconductor layer 10 side, and the substrate is cut into semiconductor chips 12. Finally, the solder bumps 4 formed on the semiconductor chip 12 are joined to the wiring board 5,
The semiconductor device 101 is completed.
【００３７】尚、図２（ａ）〜（ｅ）に示した製造工程
では、最初に図２（ｂ）の半導体素子形成工程を行った
後、図２（ｃ）の溝形成工程を行った。しかしながら、
最初に図２（ｃ）の溝形成工程を行った後、図２（ｂ）
の半導体素子形成工程を行ってもよい。特に、高熱伝導
材料３が前記したＣｕ、Ａｌ、Ａｇ、Ａｕ、Ｃｕ合金、
Ａｌ合金、Ａｇ合金、Ａｕ合金のように耐熱性が低い場
合には、最初に図２（ｂ）の半導体素子形成工程を行っ
た後、図２（ｃ）の溝形成工程と図２（ｄ）の溝埋め込
み工程を行うのがよい。一方、特に、高熱伝導材料３が
タングステン（Ｗ）、モリブデン（Ｍｏ）、白金（Ｐ
ｔ）のように耐熱性が高い場合には、最初に図２（ｃ）
の溝形成工程と図２（ｄ）の溝埋め込み工程を行った
後、図２（ｂ）の半導体素子形成工程を行うこともでき
る。In the manufacturing steps shown in FIGS. 2A to 2E, first, the semiconductor element forming step of FIG. 2B is performed, and then the groove forming step of FIG. 2C is performed. . However,
After performing the groove forming step of FIG. 2C first, FIG.
May be performed. In particular, when the high heat conductive material 3 is Cu, Al, Ag, Au, Cu alloy,
When the heat resistance is low like Al alloy, Ag alloy and Au alloy, first, the semiconductor element forming step of FIG. 2B is performed, and then the groove forming step of FIG. It is preferable to carry out the groove filling step of ()). On the other hand, particularly, the high thermal conductive material 3 is made of tungsten (W), molybdenum (Mo), platinum (P).
In the case where the heat resistance is high as in t), first, FIG.
After performing the groove forming step and the groove filling step in FIG. 2D, the semiconductor element forming step in FIG. 2B can be performed.
【００３８】上述したように、本実施形態では、支持基
板１１全体を熱伝導性の優れた材料から構成するのでは
なく、その支持基板１１に発熱部である半導体素子８
１，８２，８３が形成される半導体層１０に向けて溝２
を形成し、その溝２内にのみ高熱伝導材料３を埋め込
む。従って、一つの半導体素子が発生した熱は、支持基
板１１において横方向に伝えられることなく、速やか
に、高熱伝導材料３を介して、支持基板１１の表面から
放熱される。このため、本実施形態における放熱構造に
よれば、半導体層１０に複数の半導体素子が形成されて
も、それぞれの発熱の影響が相互に作用しにくくするこ
とができる。As described above, in the present embodiment, the whole of the support substrate 11 is not made of a material having excellent heat conductivity, and the
Groove 2 toward semiconductor layer 10 where 1, 82 and 83 are formed
Is formed, and the high thermal conductive material 3 is embedded only in the groove 2. Therefore, the heat generated by one semiconductor element is quickly dissipated from the surface of the support substrate 11 via the high heat conductive material 3 without being transmitted laterally in the support substrate 11. For this reason, according to the heat dissipation structure in the present embodiment, even when a plurality of semiconductor elements are formed in the semiconductor layer 10, the influence of each heat generation can be made less likely to interact.
【００３９】（第２の実施形態）第１の実施形態では、
絶縁性の支持基板１１と半導体層１０からＳＯＩ基板を
形成した。第２の実施形態は、近年よく用いられる、２
枚の半導体基板を絶縁層を介して貼り合わせ、ＳＯＩ基
板を形成するものである。以下、本実施形態について図
に基づいて説明する。(Second Embodiment) In the first embodiment,
An SOI substrate was formed from the insulating support substrate 11 and the semiconductor layer 10. The second embodiment has been widely used in recent years.
In this method, two semiconductor substrates are bonded to each other with an insulating layer interposed therebetween to form an SOI substrate. Hereinafter, the present embodiment will be described with reference to the drawings.
【００４０】図３（ａ）は、本実施形態における半導体
装置１０２を示す断面模式図であり、図３（ｂ）は、当
該半導体装置１０２の配線基板５への搭載状態を示す断
面図である。尚、図３（ａ），（ｂ）において、図１
（ａ），（ｂ）に示した半導体装置１０１と同様の部分
については同一の符号を付け、その説明を省略する。FIG. 3A is a schematic cross-sectional view showing the semiconductor device 102 according to the present embodiment, and FIG. 3B is a cross-sectional view showing a state where the semiconductor device 102 is mounted on the wiring board 5. . 3A and 3B, FIG.
The same parts as those of the semiconductor device 101 shown in (a) and (b) are denoted by the same reference numerals, and description thereof will be omitted.
【００４１】２枚の半導体基板を貼り合わせて形成する
ＳＯＩ基板は、片面を表面酸化した半導体基板と、もう
１枚の表面酸化を行わない半導体基板を準備し、表面酸
化した半導体の酸化表面と表面酸化を行わない半導体基
板を対向させて貼り合わせた後、一方の半導体基板を研
磨して形成される。図３（ａ）において、半導体層１０
は研磨されたほうの半導体基板であり、符号１３が研磨
されていないほうの半導体基板である。また符合１４は
絶縁層で、表面酸化した半導体基板の表面酸化膜からな
っている。As an SOI substrate formed by bonding two semiconductor substrates, a semiconductor substrate with one surface oxidized and another semiconductor substrate without surface oxidation are prepared, and the oxidized surface of the oxidized semiconductor is prepared. After the semiconductor substrates that are not subjected to surface oxidation are bonded to each other, they are formed by polishing one of the semiconductor substrates. In FIG. 3A, the semiconductor layer 10
Denotes a polished semiconductor substrate, and reference numeral 13 denotes an unpolished semiconductor substrate. Reference numeral 14 denotes an insulating layer made of a surface oxide film of a semiconductor substrate whose surface has been oxidized.
【００４２】図３（ａ）に示す半導体装置１０２におい
ては、図１（ａ）の半導体装置１０１に対応して、表面
酸化膜１４と半導体基板１３が支持基板１５に相当し、
支持基板１５に形成された表面酸化膜からなる絶縁層１
４上に、半導体層１０が積層された構造となっている。
従って、図３（ａ）に示す半導体チップ１６は、半導体
基板１３と半導体層１０の間に絶縁層１４が埋め込まれ
た構造になっている。図３（ａ）の半導体装置１０２に
おいて、図１（ａ）の半導体装置１０１と同様に半導体
層１０には半導体素子８１，８２，８３が形成されてい
るが、各半導体素子８１，８２，８３は埋め込み絶縁分
離溝９１，９２により完全に分離されている。この埋め
込み絶縁分離溝９１，９２による素子分離により、各半
導体素子８１，８２，８３をより高集積化することがで
き、また高速化することができる。In the semiconductor device 102 shown in FIG. 3A, the surface oxide film 14 and the semiconductor substrate 13 correspond to the support substrate 15, corresponding to the semiconductor device 101 in FIG.
Insulating layer 1 made of surface oxide film formed on supporting substrate 15
The semiconductor device has a structure in which a semiconductor layer 10 is stacked on the semiconductor device 4.
Accordingly, the semiconductor chip 16 shown in FIG. 3A has a structure in which the insulating layer 14 is embedded between the semiconductor substrate 13 and the semiconductor layer 10. In the semiconductor device 102 of FIG. 3A, semiconductor elements 81, 82, and 83 are formed in the semiconductor layer 10 similarly to the semiconductor device 101 of FIG. Are completely separated by buried insulating separation grooves 91 and 92. By the element isolation by the buried insulating isolation grooves 91 and 92, the semiconductor elements 81, 82 and 83 can be more highly integrated and can be operated at higher speed.
【００４３】図３（ａ）の半導体装置１０２において
も、図１（ａ）の半導体装置１０１と同様に、支持基板
１５に溝２０が形成され、溝２０内には支持基板１５を
構成する半導体基板１３と絶縁層１４の熱伝導率より大
きな高熱伝導材料３が埋め込まれている。尚、図３
（ａ）の半導体装置１０２においては、溝２０が絶縁層
１４に到達する深さまで形成されている。溝２０の深さ
は、放熱性能の面で深いほど望ましいが、必ずしも絶縁
層１４に到達する必要はなく、必要な放熱性能が得られ
る深さで支持基板１５内に形成すればよい。In the semiconductor device 102 of FIG. 3A, similarly to the semiconductor device 101 of FIG. 1A, a groove 20 is formed in the support substrate 15, and the semiconductor constituting the support substrate 15 is formed in the groove 20. A high thermal conductive material 3 larger than the thermal conductivity of the substrate 13 and the insulating layer 14 is embedded. Note that FIG.
In the semiconductor device 102 of (a), the groove 20 is formed to a depth that reaches the insulating layer 14. The depth of the groove 20 is preferably as deep as possible in terms of heat radiation performance, but it is not always necessary to reach the insulating layer 14 and the groove 20 may be formed in the support substrate 15 at a depth at which the required heat radiation performance is obtained.
【００４４】図３（ｂ）に示す半導体装置１０２の配線
基板５への搭載は、図１（ｂ）に示す半導体装置１０１
の配線基板５への搭載と同様の、フリップチップ実装で
ある。The mounting of the semiconductor device 102 shown in FIG. 3B on the wiring board 5 is performed by using the semiconductor device 101 shown in FIG.
This is the same flip chip mounting as the mounting on the wiring board 5.
【００４５】図３（ａ）に示した半導体装置１０２の製
造は、前記したように、表面酸化したシリコン基板（ウ
ェハ）ともう１枚の表面酸化していないシリコン基板
（ウェハ）を貼り合わせた基板を用いて行う。最初に、
貼り合わせた一方のシリコン基板を研磨して、１０μｍ
厚程度のシリコン半導体層１０に加工する。次に、所定
の工程を用いて、半導体層１０に埋め込み絶縁分離溝９
１，９２とを形成する。次の半導体素子８１，８２，８
３の形成以後は、図２（ｂ）〜（ｅ）に示した第１実施
形態の半導体装置１０１の製造工程と同様に行う。In the manufacture of the semiconductor device 102 shown in FIG. 3A, as described above, a silicon substrate (wafer) whose surface has been oxidized and another silicon substrate (wafer) whose surface has not been oxidized have been bonded together. This is performed using a substrate. At first,
Polish one of the bonded silicon substrates to 10 μm
It is processed into a silicon semiconductor layer 10 having a thickness of approximately. Next, the insulating isolation trench 9 embedded in the semiconductor layer 10 is formed by using a predetermined process.
1, 92 are formed. Next semiconductor elements 81, 82, 8
After the formation of No. 3, it is performed in the same manner as the manufacturing process of the semiconductor device 101 of the first embodiment shown in FIGS. 2B to 2E.
【００４６】図３（ａ）に示す半導体装置１０２におい
ては、図１（ａ）に示す半導体装置１０１と比較し、埋
め込み絶縁分離溝９１，９２が形成されているため半導
体層１０において横方向への熱が逃げにくい構造となっ
ている。本実施形態の図３（ａ），（ｂ）に示す半導体
装置１０２においては、第１実施形態と同様に、半導体
素子８１，８２，８３の発生する熱を、溝２０に埋め込
まれた高熱伝導材料３を介して表面７１からすばやく放
熱することができる。従って、図３（ｂ）に示すフリッ
プチップ実装においても、半導体素子８１，８２，８３
の発熱による相互影響を一層低減できるとともに、各半
導体素子８１，８２，８３の温度上昇を抑制することが
でき、素子特性の変化、配線抵抗の増大、半田バンプの
融解、熱応力による保護膜剥離といった問題の発生を抑
制することができる。In the semiconductor device 102 shown in FIG. 3A, compared with the semiconductor device 101 shown in FIG. The structure makes it difficult for heat to escape. In the semiconductor device 102 of the present embodiment shown in FIGS. 3A and 3B, similarly to the first embodiment, the heat generated by the semiconductor elements 81, 82, and 83 is transferred to the high thermal conductivity embedded in the groove 20. Heat can be quickly radiated from the surface 71 through the material 3. Accordingly, even in the flip chip mounting shown in FIG.
Of the semiconductor elements 81, 82, 83 can be suppressed, the element characteristics change, the wiring resistance increases, the solder bumps melt, and the protective film peels due to thermal stress. Can be suppressed.
【００４７】（第３の実施形態）第２の実施形態では、
貼り合わせ基板に半導体素子を形成し、高熱伝導材料を
埋め込んだ溝により放熱性を高めた半導体装置につい
て、構造およびその製造方法を示した。第３の実施形態
は、複数の半導体素子のうち１つが特に発熱量の大きな
発熱素子である場合に、高熱伝導材料を埋め込んだ溝が
その発熱素子の直下に形成された半導体装置に関する。
以下、本実施形態について図に基づいて説明する。(Third Embodiment) In the second embodiment,
The structure and manufacturing method of a semiconductor device in which a semiconductor element is formed on a bonded substrate and heat dissipation is improved by a groove in which a high heat conductive material is embedded are described. The third embodiment relates to a semiconductor device in which, when one of a plurality of semiconductor elements is a heating element that generates a particularly large amount of heat, a groove in which a high thermal conductive material is embedded is formed immediately below the heating element.
Hereinafter, the present embodiment will be described with reference to the drawings.
【００４８】図４（ａ）は、本実施形態における半導体
装置１０３を示す断面模式図であり、図４（ｂ）は、当
該半導体装置１０３の下面図であり、図３（ｃ）は、当
該半導体装置１０３の配線基板５への搭載状態を示す断
面図である。尚、図４（ａ），（ｂ），（ｃ）におい
て、図３（ａ），（ｂ）に示した半導体装置１０２と同
様の部分については同一の符号を付け、その説明を省略
する。FIG. 4A is a schematic sectional view showing a semiconductor device 103 according to the present embodiment, FIG. 4B is a bottom view of the semiconductor device 103, and FIG. FIG. 5 is a cross-sectional view showing a state where the semiconductor device 103 is mounted on the wiring board 5. In FIGS. 4A, 4B, and 4C, the same parts as those of the semiconductor device 102 shown in FIGS. 3A and 3B are denoted by the same reference numerals, and description thereof will be omitted.
【００４９】図４（ａ）に示す半導体装置１０３におい
ては、図２（ａ）の半導体装置１０２と同様に半導体層
１０には半導体素子８４，８５，８６が形成されている
が、半導体素子８５は他の半導体素子８４，８６と比べ
て、特に発熱量の大きな発熱素子である。この発熱素子
８４に対して、高熱伝導材料３を埋め込んだ溝２１が、
発熱素子８５の直下に、集中的に形成されている。In the semiconductor device 103 shown in FIG. 4A, semiconductor elements 84, 85 and 86 are formed in the semiconductor layer 10 as in the semiconductor device 102 of FIG. Is a heat generating element that generates a particularly large amount of heat as compared with the other semiconductor elements 84 and 86. The groove 21 in which the high thermal conductive material 3 is embedded is formed in the heating element 84.
Immediately below the heating element 85, they are formed intensively.
【００５０】この様な構造をとることにより、発熱素子
８５の発生する熱を、発熱素子８５の直下に形成した溝
２１内に埋め込まれた高熱伝導材料３を介して、すばや
く表面７１に伝達することができる。このため、発熱素
子８５の発生する熱が同じ半導体層１０内で発熱素子８
５の周囲に形成された他の半導体素子８４，８６へ伝達
するのを抑制することができ、発熱素子８５の熱の広が
りを抑えて他の半導体素子８４，８６への熱影響を低減
することができる。By adopting such a structure, the heat generated by the heating element 85 is quickly transmitted to the surface 71 via the high heat conductive material 3 embedded in the groove 21 formed immediately below the heating element 85. be able to. Therefore, the heat generated by the heating element 85 is generated within the same semiconductor layer 10 by the heating element 8.
5 can be suppressed from being transmitted to the other semiconductor elements 84 and 86 formed around the element 5, and the heat spread of the heating element 85 can be suppressed to reduce the thermal influence on the other semiconductor elements 84 and 86. Can be.
【００５１】図４（ａ），（Ｂ），（ｃ）に示した半導
体装置１０３の製造は、前記の第２実施形態と同様であ
るので詳細説明は省略するが、本発明による半導体装置
の製造方法によれば、図４（ａ），（Ｂ），（ｃ）の半
導体装置１０３で示したように、放熱したい半導体素子
８５の直下に集中的に放熱構造を形成できる利点があ
る。The manufacture of the semiconductor device 103 shown in FIGS. 4A, 4B, and 4C is the same as that of the second embodiment described above, and a detailed description thereof will be omitted. According to the manufacturing method, as shown in the semiconductor device 103 of FIGS. 4A, 4B, and 4C, there is an advantage that a heat radiation structure can be formed intensively immediately below the semiconductor element 85 to which heat is to be radiated.
【００５２】また、各素子の発熱量に応じた密度で、高
熱伝導材料を配置してもよい。すなわち、相対的に発熱
量が大きい素子の直下には、高密度に高熱伝導材料を配
置し、相対的に発熱量の小さい素子の直下には、低密度
に高熱伝導材料を配置してもよい。このように各素子の
発熱量に応じた密度で基板に溝を形成して、その内部に
高熱伝導材料を埋め込んだ放熱構造を採用することによ
り、基板各部の放熱特性を任意に調節することができ
る。Further, a high heat conductive material may be arranged at a density corresponding to the heat value of each element. That is, a high heat conductive material may be disposed at a high density immediately below an element having a relatively large calorific value, and a high thermal conductive material may be disposed at a low density under a relatively small element having a relatively small calorific value. . By adopting a heat dissipation structure in which grooves are formed in the board at a density corresponding to the heat value of each element and a high thermal conductive material is embedded inside, grooves can be arbitrarily adjusted to the heat dissipation characteristics of each part of the board. it can.
【００５３】（第４の実施形態）第１の実施形態で示し
た半導体装置は、支持基板の表面からほぼ垂直に溝を形
成し、溝内に高熱伝導材料３を埋め込んだ半導体装置で
あった。第４の実施形態は、溝を順テーパ形状に形成
し、高熱伝導材料を支持基板の表面上にも連結して形成
した半導体装置に関する。以下、本実施形態について図
に基づいて説明する。(Fourth Embodiment) The semiconductor device shown in the first embodiment is a semiconductor device in which a groove is formed almost vertically from the surface of a supporting substrate, and a high heat conductive material 3 is embedded in the groove. . The fourth embodiment relates to a semiconductor device in which a groove is formed in a forward tapered shape, and a high heat conductive material is also connected to a surface of a supporting substrate. Hereinafter, the present embodiment will be described with reference to the drawings.
【００５４】図５は、本実施形態における半導体装置１
０４の配線基板５への搭載状態を示す断面図である。
尚、図５において、図１（ｂ）に示した半導体装置１０
１と同様の部分については同一の符号を付け、その説明
を省略する。FIG. 5 shows a semiconductor device 1 according to this embodiment.
FIG. 4 is a cross-sectional view showing a mounting state of the circuit board No. 04 on a wiring board 5.
In FIG. 5, the semiconductor device 10 shown in FIG.
The same parts as those in 1 are denoted by the same reference numerals, and description thereof will be omitted.
【００５５】図５に示す半導体装置１０４においては、
図１（ｂ）の半導体装置１０１と比較し、溝２２が支持
基板１１側の表面７１に向かって広がる順テーパ形状に
形成されている。また、高熱伝導材料３は、溝２２を埋
め込むだけでなく、支持基板１１の表面上にも連結して
形成されている。In the semiconductor device 104 shown in FIG.
As compared with the semiconductor device 101 of FIG. 1B, the groove 22 is formed in a forward tapered shape that extends toward the surface 71 on the support substrate 11 side. The high thermal conductive material 3 is formed not only to fill the groove 22 but also to be connected to the surface of the support substrate 11.
【００５６】溝２２の形状を順テーパ形状にすること
で、高熱伝導材料３の溝２２内への埋め込み性を良くす
ることができるので、熱の伝達性が向上して、半導体装
置１０４の放熱性能が向上する。また、高熱伝導材料３
を支持基板１１の表面上にも連結して形成することで、
表面にも高熱伝導材料３があるため、支持基板１１側の
表面７１に伝達された熱の放熱をより高めることができ
る。By forming the groove 22 into a forward tapered shape, the embedding property of the high thermal conductive material 3 into the groove 22 can be improved, so that the heat transfer is improved and the heat dissipation of the semiconductor device 104 is improved. Performance is improved. In addition, high heat conductive material 3
Is also connected to the surface of the support substrate 11 to form
Since the high heat conductive material 3 is also present on the surface, the heat radiation of the heat transmitted to the surface 71 on the support substrate 11 side can be further enhanced.
【００５７】図５に示した半導体装置１０４の順テーパ
形状の溝２２形成は、第１実施形態で示した図２（ｃ）
の溝形成工程において、テーパエッチングを用いて行え
ばよい。本発明による半導体装置の製造方法によれば、
図５の半導体装置１０４で示したように任意の溝形状を
用いることができ、放熱に適した高熱伝導材料の埋め込
み形状とすることができる。また、図２（ｄ）の溝埋め
込み工程において、スパッタやＣＶＤにより高熱伝導材
料３を溝２２を埋め込んだ後、化学機械研磨によるエッ
チバックを行わなければ、支持基板１１の表面に高熱伝
導材料３を溝２２と連結して残すことができる。The formation of the forward tapered groove 22 of the semiconductor device 104 shown in FIG. 5 is the same as that of the first embodiment shown in FIG.
May be performed using taper etching. According to the method of manufacturing a semiconductor device according to the present invention,
As shown in the semiconductor device 104 of FIG. 5, an arbitrary groove shape can be used, and a buried shape of a high heat conductive material suitable for heat radiation can be obtained. In the groove filling step of FIG. 2D, after the groove 22 is filled with the high thermal conductive material 3 by sputtering or CVD, if the etch back by chemical mechanical polishing is not performed, the high thermal conductive material 3 Can be left in connection with the groove 22.
【００５８】（第５の実施形態）第４の実施形態で示し
た半導体装置は、溝を順テーパ形状に形成し、高熱伝導
材料を支持基板の表面上にも連結して形成した半導体装
置であった。第５の実施形態は、さらに、高熱伝導材料
に放熱部材を当接して配置した半導体装置に関する。以
下、本実施形態について図に基づいて説明する。(Fifth Embodiment) The semiconductor device shown in the fourth embodiment is a semiconductor device in which a groove is formed in a forward tapered shape, and a high heat conductive material is also connected on the surface of a supporting substrate. there were. The fifth embodiment further relates to a semiconductor device in which a heat radiating member is disposed in contact with a high heat conductive material. Hereinafter, the present embodiment will be described with reference to the drawings.
【００５９】図６は、本実施形態における半導体装置１
０５の配線基板５への搭載状態を示す断面図である。
尚、図６において、図５に示した半導体装置１０４と同
様の部分については同一の符号を付け、その説明を省略
する。FIG. 6 shows a semiconductor device 1 according to this embodiment.
FIG. 5 is a cross-sectional view showing a state of mounting on a wiring substrate of No. 05.
In FIG. 6, the same components as those of the semiconductor device 104 shown in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.
【００６０】図６に示すように、高熱伝導材料３に当接
して放熱部材３０を配置することにより、半導体素子８
１，８２，８３で発生し、高熱伝導材料３を介して表面
７１に伝達された熱の放熱を、さらに高めることができ
る。As shown in FIG. 6, by disposing the heat radiating member 30 in contact with the high heat conductive material 3, the semiconductor element 8
The heat radiation of the heat generated at 1, 82, 83 and transmitted to the surface 71 via the high heat conductive material 3 can be further enhanced.
【００６１】（他の実施形態）上記各実施形態において
は、フリップチップ実装を行った半導体装置を示した。
これに限らず、本発明の半導体装置の配線基板への実装
は、従来の半導体チップの裏面側を配線基板に貼り付け
る方法と同様に、支持基板側を配線基板に貼り付けても
よい。これによっても、溝に埋め込んだ高熱伝導材料を
介して、半導体素子で発生した熱を配線基板にすばやく
逃がすことができ、本発明は効果的である。(Other Embodiments) In each of the above embodiments, the semiconductor device on which flip-chip mounting has been performed has been described.
However, the present invention is not limited to this. For mounting the semiconductor device of the present invention on a wiring board, the support substrate may be attached to the wiring board in the same manner as the conventional method of attaching the back surface of a semiconductor chip to the wiring board. This also allows the heat generated in the semiconductor element to be quickly released to the wiring board via the high thermal conductive material embedded in the groove, and the present invention is effective.
【図１】（ａ）は、本発明の第１実施形態における半導
体装置の断面図であり、（ｂ）は、当該半導体装置の配
線基板への搭載状態を示す断面図である。FIG. 1A is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view showing a state where the semiconductor device is mounted on a wiring board.
【図２】（ａ）〜（ｅ）は、本発明の第１実施形態にお
ける半導体装置の製造工程を示す工程別の断面図であ
る。FIGS. 2A to 2E are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, which are process-specific.
【図３】（ａ）は、本発明の第２実施形態における半導
体装置の断面図であり、（ｂ）は、当該半導体装置の配
線基板への搭載状態を示す断面図である。FIG. 3A is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, and FIG. 3B is a cross-sectional view showing a state where the semiconductor device is mounted on a wiring board.
【図４】（ａ）は、本発明の第３実施形態における半導
体装置の断面図であり、（ｂ）は、当該半導体装置の下
面図であり、（ｃ）は、当該半導体装置の配線基板への
搭載状態を示す断面図である。4A is a sectional view of a semiconductor device according to a third embodiment of the present invention, FIG. 4B is a bottom view of the semiconductor device, and FIG. 4C is a wiring board of the semiconductor device; FIG. 4 is a cross-sectional view showing a state of being mounted on a hologram.
【図５】本発明の第４実施形態における半導体装置の配
線基板への搭載状態を示す断面図である。FIG. 5 is a sectional view showing a state in which a semiconductor device according to a fourth embodiment of the present invention is mounted on a wiring board.
【図６】本発明の第５実施形態における半導体装置の配
線基板への搭載状態を示す断面図である。FIG. 6 is a sectional view showing a state in which a semiconductor device according to a fifth embodiment of the present invention is mounted on a wiring board.
１０１〜１０５ 半導体装置 １０ 半導体層 １３ 半導体基板 １４ 絶縁層 １１，１５ 支持基板 １２，１６ 半導体チップ ２，２０，２１，２２ 溝 ３ 高熱伝導材料 ４ 半田バンプ ５ 配線基板 ６ 放熱部材 101-105 Semiconductor device 10 Semiconductor layer 13 Semiconductor substrate 14 Insulating layer 11,15 Support substrate 12,16 semiconductor chips 2,20,21,22 grooves 3 High thermal conductive materials 4 Solder bump 5 Wiring board 6 Heat dissipation member
Claims (12)
半導体装置において、 前記半導体層側の第１表面に半導体素子が形成され、 前記支持基板側の第２表面から前記半導体層へ向けて溝
が形成され、 前記溝内に、前記支持基板より熱伝導率の大きな高熱伝
導材料が埋め込まれることを特徴とする半導体装置。1. A semiconductor device having a semiconductor layer laminated on a support substrate, wherein a semiconductor element is formed on a first surface on the semiconductor layer side, and from a second surface on the support substrate side to the semiconductor layer. A semiconductor device, wherein a groove is formed, and a high thermal conductive material having a higher thermal conductivity than the support substrate is embedded in the groove.
に絶縁層が形成された半導体基板であり、前記半導体層
が前記絶縁層の上に積層されることを特徴とする請求項
１に記載の半導体装置。2. The method according to claim 1, wherein the supporting substrate is a semiconductor substrate having an insulating layer formed on at least one surface, and the semiconductor layer is stacked on the insulating layer. Semiconductor device.
子であり、前記溝が前記発熱素子の直下に形成されるこ
とを特徴とする請求項１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein said semiconductor element is a heating element having a large amount of generated heat, and said groove is formed immediately below said heating element.
る順テーパ形状に形成されることを特徴とする請求項１
乃至３のいずれか１項に記載の半導体装置。4. The device according to claim 1, wherein the groove is formed in a forward tapered shape extending toward the second surface.
The semiconductor device according to any one of claims 3 to 3.
ム、銀、金、銅合金、アルミニウム合金、銀合金、金合
金のいずれかであることを特徴とする請求項１乃至４の
いずれか１項に記載の半導体装置。5. The high thermal conductive material is any one of copper, aluminum, silver, gold, copper alloy, aluminum alloy, silver alloy, and gold alloy. 3. The semiconductor device according to claim 1.
も連結して形成されることを特徴とする請求項１乃至５
のいずれか１項に記載の半導体装置。6. The high thermal conductive material is also formed on the second surface so as to be connected thereto.
The semiconductor device according to claim 1.
が配置されることを特徴とする請求項１乃至６のいずれ
か１項に記載の半導体装置。7. The semiconductor device according to claim 1, wherein a heat radiating member is disposed in contact with said high heat conductive material.
前記半田バンプを配線基板に接続して、 前記半導体装置を前記配線基板に搭載したことを特徴と
する請求項１乃至７のいずれか１項に記載の半導体装
置。8. A solder bump is formed on the first surface,
The semiconductor device according to claim 1, wherein the solder bump is connected to a wiring board, and the semiconductor device is mounted on the wiring board.
じサイズであることを特徴とする請求項８に記載の半導
体装置。9. The semiconductor device according to claim 8, wherein said wiring substrate has substantially the same size as said support substrate.
る半導体装置の製造方法において、 前記半導体層側の第１表面に半導体素子を形成する第１
工程と、 前記支持基板側の第２表面から前記半導体層へ向けて溝
を形成する第２工程と、 前記溝内に、前記支持基板より熱伝導率の大きな高熱伝
導材料を埋め込む第３工程とを有することを特徴とする
半導体装置の製造方法。10. A method for manufacturing a semiconductor device comprising a semiconductor layer laminated on a supporting substrate, wherein a semiconductor element is formed on a first surface on the semiconductor layer side.
A step of forming a groove from the second surface on the support substrate side toward the semiconductor layer; and a third step of embedding a high heat conductive material having a higher thermal conductivity than the support substrate in the groove. A method for manufacturing a semiconductor device, comprising:
素子であり、前記溝を当該発熱素子の直下に形成するこ
とを特徴とする請求項１０に記載の半導体装置の製造方
法。11. The method according to claim 10, wherein the semiconductor element is a heating element that generates a large amount of heat, and the groove is formed immediately below the heating element.
２表面に向かって広がる順テーパ形状に形成することを
特徴とする請求項１０または１１に記載の半導体装置の
製造方法。12. The method of manufacturing a semiconductor device according to claim 10, wherein said groove is formed by etching into a forward tapered shape extending toward said second surface.
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|---|---|---|---|
| JP2002151764A JP3791459B2 (en) | 2002-05-27 | 2002-05-27 | Semiconductor device and manufacturing method thereof |
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|---|---|---|---|
| JP2002151764A JP3791459B2 (en) | 2002-05-27 | 2002-05-27 | Semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN107710609A (en) * | 2015-07-13 | 2018-02-16 | 追踪有限公司 | With component derived from improved heat |
| US11303263B2 (en) | 2015-07-13 | 2022-04-12 | Qualcomm Incorporated | Component with improved heat dissipation |
| KR102667425B1 (en) * | 2015-07-13 | 2024-05-17 | 스냅트랙, 인코포레이티드 | Components with improved heat dissipation |
| CN111554586A (en) * | 2020-06-12 | 2020-08-18 | 厦门通富微电子有限公司 | Preparation method of chip packaging body |
| CN111554644A (en) * | 2020-06-12 | 2020-08-18 | 厦门通富微电子有限公司 | Chip, chip package and wafer |
| CN111554586B (en) * | 2020-06-12 | 2022-04-01 | 厦门通富微电子有限公司 | Preparation method of chip packaging body |
| CN111952197A (en) * | 2020-08-25 | 2020-11-17 | 济南南知信息科技有限公司 | Semiconductor device and packaging method thereof |
| CN111952197B (en) * | 2020-08-25 | 2022-05-27 | 青岛融合装备科技有限公司 | Semiconductor device and packaging method thereof |
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