JP2003298167A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JP2003298167A JP2003298167A JP2002094148A JP2002094148A JP2003298167A JP 2003298167 A JP2003298167 A JP 2003298167A JP 2002094148 A JP2002094148 A JP 2002094148A JP 2002094148 A JP2002094148 A JP 2002094148A JP 2003298167 A JP2003298167 A JP 2003298167A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- optical semiconductor
- metal
- optical
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
- H01L2224/17051—Bump connectors having different shapes
Abstract
Description
【０００１】[0001]
【発明の属する技術の分野】本発明は発光素子または受
光素子から構成される光半導体素子を配線基板に搭載す
る光半導体装置に係り、特に前記光半導体素子を電気配
線層と光配線層を有する前記配線基板上にフリップチッ
プ実装する光半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device in which an optical semiconductor element composed of a light emitting element or a light receiving element is mounted on a wiring board, and in particular, the optical semiconductor element has an electric wiring layer and an optical wiring layer. The present invention relates to an optical semiconductor device which is flip-chip mounted on the wiring board.
【０００２】[0002]
【従来の技術】近年、長距離・大容量の光ファイバー伝
送システムは急速に普及して、現在では、ギガビットか
らテラビットの光伝送技術の研究開発が多く行われてい
る。特に、ＦＴＴＨ（Ｆｉｂｅｒ Ｔｏ Ｔｈｅ Ｈｏ
ｍｅ）における、センター局から一般家庭まで光ファイ
バーを用いて情報を伝送する光加入者系システムに関し
ては多くの研究が行われている。具体的には、この光加
入者系システム用の光デバイスモジュールを汎用化させ
るために、製造コストを低減させることが求められてお
り、その製造コストを低減するための手段として、例え
ば、特開平１１−２７４４４６号公報に記載されるシリ
コンプラットホーム基板にＶ溝形成して光ファイバーと
の位置合わせを容易化する方法などのパッシブアライメ
ント法を用いた光デバイスと光ファイバーの結合技術の
提案が多く行われている。一方、シリコンＬＳＩにおい
ても高集積化のための研究開発は多く行われており、そ
の動作速度と集積規模は著しく向上される方向にある。
この性能向上を行う上での課題が信号配線における転送
速度および信号配線の実装密度である。すなわち、トラ
ンジスタなどの機能素子の性能向上が行われても、信号
配線における信号転送速度と信号配線の高密度化が行わ
なければ、これらが律速となり、モジュール性能向上の
実現は困難である。また、一般に電気信号配線には信号
伝達のための遅延が存在するため、これも上記の性能向
上を阻害する要因となっている。さらに、信号転送速度
の高速化と信号配線の高密度化を行った場合にはＥＭＩ
（Ｅｌｅｃｔｒｏｍａｇｎｅｔｉｃ Ｉｎｔｅｒｆｅｒ
ｅｎｃｅ）の影響が顕著になるため、その対策を十分に
講じる必要もある。2. Description of the Related Art In recent years, long-distance, large-capacity optical fiber transmission systems have rapidly spread, and nowadays, much research and development is being carried out on optical transmission technology from gigabit to terabit. In particular, FTTH (Fiber To The Ho
Much research has been conducted on the optical subscriber system for transmitting information from the center station to general households by using optical fibers. Specifically, in order to generalize the optical device module for the optical subscriber system, it is required to reduce the manufacturing cost. As a means for reducing the manufacturing cost, for example, Japanese Patent Laid-Open No. Many proposals have been made for a technique for coupling an optical device and an optical fiber using a passive alignment method such as a method for forming a V groove on a silicon platform substrate described in JP-A 11-274446 to facilitate alignment with an optical fiber. There is. On the other hand, much research and development for high integration is also performed on silicon LSIs, and the operating speed and the scale of integration are significantly improved.
The issues in improving this performance are the transfer rate of the signal wiring and the packaging density of the signal wiring. That is, even if the performance of a functional element such as a transistor is improved, unless the signal transfer speed of the signal wiring and the density of the signal wiring are increased, these become the rate-determining factors and it is difficult to improve the module performance. Further, in general, the electric signal wiring has a delay for signal transmission, which is also a factor that hinders the above performance improvement. Furthermore, when the signal transfer speed is increased and the signal wiring density is increased, EMI
(Electromagnetic Interferer
ence) will be significant, so it is necessary to take sufficient measures.
【０００３】このような電気信号配線における問題を解
決するものとして、例えば、電子情報通信学会論文誌Ｖ
ｏｌ．Ｊ８４−Ｃ，Ｎｏ．９，ｐｐ７３６−７４３，２
０００に公開される光インターコネクション技術が最近
の技術として有力になっている。現在、この光インター
コネクション技術は、電子機器間、電子機器内ボード
間、あるいはボード内チップ間など、多くの用途に適用
可能と考えられており、例えば、電子機器間の光インタ
ーコネクションとして、コア径が大きく接続の容易なプ
ラスティック光ファイバーを用いた光リンクの利用、電
子機器内の光インターコネクションとしては、フレキシ
ブルな光導波路を使用した光リンクの利用、ボード内チ
ップ間の光インターコネクションとして、光導波路また
はフリースペースによる光配線などの利用が提案されて
いる。したがって、上記に記載したＦＴＴＨにおける光
加入者系システムも広義において光インターコネクショ
ン技術の１つとすることができる。As a solution to such a problem in electric signal wiring, for example, the Institute of Electronics, Information and Communication Engineers
ol. J84-C, No. 9, pp736-743,2
The optical interconnection technology, which is open to the public in 000, has become a powerful technology in recent years. At present, this optical interconnection technology is considered to be applicable to many applications such as between electronic devices, between boards in an electronic device, or between chips in a board. For example, as an optical interconnection between electronic devices, Use of an optical link using a plastic optical fiber with a large diameter and easy connection, use of an optical link using a flexible optical waveguide as an optical interconnection in an electronic device, and optical interconnection between chips on a board. The use of optical wiring by a waveguide or free space has been proposed. Therefore, the optical subscriber system in FTTH described above can also be one of the optical interconnection technologies in a broad sense.
【０００４】光インターコネクションの具体例として、
電子情報通信学会論文誌Ｖｏｌ．Ｊ８４−Ｃ，Ｎｏ．
９，ｐｐ７９３−７９９には、ボード内チップ間接続と
しての光バンプインターフェイスが公開されている。こ
の技術は、発光素子と受光素子を搭載した光パッケージ
と電子機器ボード間の光インターフェイスとして、両者
にマイクロレンズを形成して、その空間をコリメート光
で接続するもので、ＳＭＴ（Ｓｕｒｆａｃｅ Ｍｏｕｎ
ｔ ｔｅｃｈｎｏｌｏｇｙ）の搭載位置ずれを許容でき
る大きなビーム径で接続するものである。この技術によ
れば、これまで高い精度が必要となっていた光デバイス
と光ファイバー間のアライメントを容易に緩和できるだ
けでなく、ボード上での光ファイバー収納、コネクタ接
続作業も不要になるため、結果として低コストで光イン
ターコネクションモジュールを実現できる特徴を有して
いる。As a concrete example of the optical interconnection,
IEICE Transactions Vol. J84-C, No.
9, pp 793-799 discloses an optical bump interface as inter-chip chip connection. This technology forms a microlens as an optical interface between an optical package equipped with a light emitting element and a light receiving element and an electronic device board, and connects the space with collimated light. SMT (Surface Mount)
The connection is performed with a large beam diameter that allows the mounting position deviation of the t technology). This technology not only eases the alignment between the optical device and the optical fiber, which previously required high precision, but also eliminates the need for optical fiber storage and connector connection on the board, resulting in low It has the feature that an optical interconnection module can be realized at low cost.
【０００５】[0005]
【発明が解決しようとする課題】以上のように、高密度
・高速通信技術の次世代技術として有効な光インターコ
ネクション技術では、光を発生するレーザダイオードの
ような発光素子、光を受信するフォトダイオードなどの
受光素子が必要とされるが、このような発光素子または
受光素子（受発光素子）のうち、光の発信方向または受
信方向が基板に対して垂直な方向の面型受発光素子は、
各素子を２次元的に集積できることから、特に、前記光
インターコネクション技術に適応される光素子として有
効であり、その光ファイバーとの結合方法を考慮した受
発光素子の実装方法には多くの提案が行われている。例
えば、特開２０００−２７７８４４号公報の従来の技術
には、面発光レーザの一般的な実装方法が記載されてい
る。具体的には，ＬＥＤ（発光ダイオード）の実装に用
いられる汎用の台座に搭載する方法が記載されている。
この方法によれば、この面発光レーザは不活性ガス雰囲
気中に搭載されているため、表面の酸化によって素子劣
化が発生せず、かつ面発光レーザの光が基板と垂直方向
に出射することから、上面に光を出す電気光変換素子を
小型に簡便に作製することができるものである。さら
に、特開２０００−２８４１５１号公報には，面発光レ
ーザ素子を２次元アレイ状に配列した面発光レーザアレ
イに対して、金属プレートに搭載したフェルールを用い
て光ファイバーとの接続を実現するモジュール構造が公
開されている。As described above, in the optical interconnection technology which is effective as the next-generation technology of the high-density and high-speed communication technology, the light-emitting element such as a laser diode that emits light and the photo-receiver that receives the light are used. A light receiving element such as a diode is required. Among such light emitting elements or light receiving elements (light receiving and emitting elements), the surface type light receiving and emitting element whose light emitting direction or light receiving direction is perpendicular to the substrate is ,
Since each element can be two-dimensionally integrated, it is particularly effective as an optical element adapted to the optical interconnection technology, and many proposals have been made for a mounting method of a light emitting / receiving element in consideration of the coupling method with the optical fiber. Has been done. For example, a conventional technique disclosed in Japanese Patent Laid-Open No. 2000-277844 describes a general mounting method for a surface emitting laser. Specifically, a method of mounting on a general-purpose pedestal used for mounting an LED (light emitting diode) is described.
According to this method, since the surface emitting laser is mounted in an inert gas atmosphere, element deterioration does not occur due to surface oxidation, and the surface emitting laser light is emitted in the direction perpendicular to the substrate. The electro-optical conversion element that emits light on the upper surface can be easily manufactured in a small size. Further, Japanese Patent Application Laid-Open No. 2000-284151 discloses a module structure for connecting a surface emitting laser array in which surface emitting laser elements are arranged in a two-dimensional array to an optical fiber by using a ferrule mounted on a metal plate. Has been published.
【０００６】また、受光素子の実装方法に関しては、例
えば、特開平５−３７００４号公報と特開平５−１２９
６３８号公報に、光ファイバーと良好な光結合が容易な
フリップチップ型の受光素子の実装構造が公開されてい
る。この方法は、半導体基板の表面に形成され、裏面側
から入射した光を受光して電流に変換する受光部と、半
導体基板の裏面側の受光部に対応する部分に受光部に光
を導く光ファイバーの先端部を収納するように形成され
ている凹部を備えることを特徴とするもので、光結合す
べき光ファイバーを単に凹部に挿入するだけで、その端
面から出射される光信号を正確に光吸収層に導くことが
できるものである。Regarding the mounting method of the light receiving element, for example, Japanese Patent Application Laid-Open Nos. 5-37004 and 5-129.
Japanese Laid-Open Patent Publication No. 638 discloses a mounting structure of a flip-chip type light receiving element, which facilitates good optical coupling with an optical fiber. This method consists of a light-receiving part formed on the front surface of the semiconductor substrate, which receives the light incident from the back surface side and converts it into an electric current, and an optical fiber which guides the light to the light-receiving part on the back surface side of the semiconductor substrate. It is characterized by having a recess formed so as to accommodate the tip of the optical fiber. By simply inserting the optical fiber to be optically coupled into the recess, the optical signal emitted from the end face is accurately absorbed. It can lead to layers.
【０００７】しかしながら、これらの実装方法は、光素
子をマイクロオプティック的にブロック状に配列する同
軸型のモジュール実装構成であるため、低コスト化を実
現する、複数の光素子を同一配線基板上に配列する光Ｓ
ＭＴ技術には適していない。具体的には、光ＳＭＴは、
例えばシリコンプラットホーム基板上にＬＤ、ＰＤ、導
波路、合分波器、光ファイバーなどを配置する構成で、
半導体プロセス技術を用いてシリコン基板上に導波路、
合分波器、光ファイバー用のＶ溝を一括形成すること
で、製作コストと実装コストの低減及び実装面積の高密
度化を実現するものであるが、上記に記載した受発光素
子の実装方法では、光ファイバーが配線基板の空間方向
に対して垂直方向に結合されるため、光ＳＭＴ技術の基
本的な必須構造である配線基板上の表面実装ができない
問題を有している。However, these mounting methods are coaxial-type module mounting configurations in which optical elements are arranged in a block shape in a micro-optical manner, so that a plurality of optical elements can be realized on the same wiring board to realize cost reduction. Light S to be arranged
Not suitable for MT technology. Specifically, the optical SMT is
For example, a configuration in which LDs, PDs, waveguides, multiplexers / demultiplexers, optical fibers, etc. are arranged on a silicon platform substrate,
Waveguide on silicon substrate using semiconductor process technology,
By collectively forming the V-grooves for the multiplexer / demultiplexer and the optical fiber, the manufacturing cost and the mounting cost can be reduced and the mounting area can be increased. However, in the mounting method of the light emitting / receiving element described above, Since the optical fibers are coupled in the direction perpendicular to the spatial direction of the wiring board, there is a problem that surface mounting on the wiring board, which is a basic essential structure of the optical SMT technology, cannot be performed.
【０００８】上記のような問題を部分的に解決する方法
として、上記に記載した電子情報通信学会論文誌Ｖｏ
ｌ．Ｊ８４−Ｃ，Ｎｏ．９ｐｐ７９３−７９９，２００
０に公開される光バンプインターフェイス構造が挙げら
れる。図９に示すように、この方法によれば、はんだボ
ールのセルフアライメント効果を光ファイバーとの光結
合に利用しており、さらに、面発光レーザアレイ素子を
搭載する光パッケージ構造も光ＳＭＴに適した構造が実
現できるが、パッケージ内部の面発光レーザアレイ素子
はワイヤーボンディングで接続しているため、面発光レ
ーザアレイ素子としての高密度化には限界があった。な
お、図９において、４１は光電気配線基板、４２はポリ
マー導波路、４３は４５度ミラー、４４は面発光レーザ
アレイ素子、４５はホトダイオード、４６は送信信号制
御ＬＳＩ、４７は受信信号制御ＬＳＩ、４８は制御ＬＳ
Ｉ、４９はマイクロレンズアレイ、５０ははんだボール
である。As a method for partially solving the above problems, the above-mentioned journal of the Institute of Electronics, Information and Communication Engineers Vo
l. J84-C, No. 9 pp 793-799, 200
There is an optical bump interface structure which is open to public. As shown in FIG. 9, according to this method, the self-alignment effect of the solder balls is used for optical coupling with the optical fiber, and the optical package structure mounting the surface emitting laser array element is also suitable for optical SMT. Although the structure can be realized, since the surface emitting laser array elements inside the package are connected by wire bonding, there is a limit to increase the density of the surface emitting laser array elements. In FIG. 9, 41 is an opto-electric wiring board, 42 is a polymer waveguide, 43 is a 45 degree mirror, 44 is a surface emitting laser array element, 45 is a photodiode, 46 is a transmission signal control LSI, and 47 is a reception signal control LSI. 48 are control LS
I and 49 are microlens arrays, and 50 is a solder ball.
【０００９】また、上記に記載した面発光レーザアレイ
では、図８に示すように、各面発光レーザ素子６４の近
傍に形成された電極部に個別に接続される電気信号配線
６３を、各素子の間を通して、面発光レーザアレイ素子
６２の周囲に配置されるＩ／Ｏ電極６１に接続する必要
がある。このＩ／Ｏ電極６１は、ワイヤーボンディング
法で配線基板の電極端子と接続されるのが一般的であ
る。ところが、このような構成では、各面発光レーザ素
子６４の個別の電極部に接続される電気信号の配線が複
雑になり、電気信号配線６３の配線密度が向上するた
め、高速変調特性の劣化が生じるなどの問題があった。
さらに、このように面発光レーザアレイ素子６２のチッ
プ周囲に電気配線のためのＩ／Ｏ電極６１を配置する
と、面発光レーザ素子の集積を行っても、Ｉ／Ｏ電極の
配置密度が律速となり、結果として面発光レーザアレイ
素子を高密度化できない問題があった。Further, in the surface emitting laser array described above, as shown in FIG. 8, the electric signal wiring 63 individually connected to the electrode portion formed in the vicinity of each surface emitting laser element 64 is provided in each element. It is necessary to connect to the I / O electrode 61 arranged around the surface emitting laser array element 62 through the space. This I / O electrode 61 is generally connected to an electrode terminal of a wiring board by a wire bonding method. However, in such a configuration, the wiring of electric signals connected to the individual electrode portions of each surface emitting laser element 64 becomes complicated, and the wiring density of the electric signal wiring 63 is improved, so that the high speed modulation characteristic is deteriorated. There were problems such as occurrence.
Further, when the I / O electrodes 61 for electrical wiring are arranged around the chip of the surface-emission laser array element 62 as described above, the arrangement density of the I / O electrodes becomes rate-determining even when the surface-emission laser elements are integrated. As a result, there is a problem that the surface emitting laser array element cannot be densified.
【００１０】このため、各面発光レーザ素子に接続され
る電極部にバンプ電極を形成して、面発光レーザアレイ
素子をフリップチップ実装する方法が考えられるが、こ
の方法では、フリップチップ実装する面発光レーザアレ
イ素子と配線基板の熱膨張係数の相違に起因する歪がバ
ンプ電極の破壊を発生させることになり、光インターコ
ネクションモジュールとしての信頼性を確保するには多
くの問題があった。この問題は、特に発熱量の大きな面
発光レーザ素子などを配線基板上にフリップチップ実装
する場合に顕著なものである。したがって、例えば、フ
リップチップ実装する面発光レーザアレイ素子と配線基
板の間に封止樹脂を配置することでバンプ応力歪を緩和
することも考えられるが、このように封止樹脂を配置す
る方法では、封止樹脂が面発光レーザ素子の発光部にま
で配置されることから、光受信部に十分な光強度を到達
させられない問題も発生していた。Therefore, a method is conceivable in which bump electrodes are formed on the electrode portions connected to each surface emitting laser element and the surface emitting laser array element is flip-chip mounted. In this method, the surface to be flip-chip mounted is used. Strain caused by the difference in thermal expansion coefficient between the light emitting laser array element and the wiring substrate causes the destruction of the bump electrode, and there are many problems in securing the reliability as the optical interconnection module. This problem is particularly noticeable when a surface emitting laser device having a large amount of heat is flip-chip mounted on a wiring board. Therefore, for example, it is conceivable to reduce the bump stress strain by disposing the sealing resin between the surface emitting laser array element to be flip-chip mounted and the wiring substrate. However, in the method of disposing the sealing resin in this way, Since the sealing resin is disposed even in the light emitting portion of the surface emitting laser element, there has been a problem that a sufficient light intensity cannot be reached in the light receiving portion.
【００１１】本発明は上記の問題を鑑みてなされたもの
であり、特に発光素子または受光素子をから構成される
面型の光半導体素子を、電気配線層と光配線層を有する
配線基板に高い接続信頼性でフリップチップ実装する光
半導体装置を実現するものである。The present invention has been made in view of the above problems, and in particular, a surface type optical semiconductor element including a light emitting element or a light receiving element is applied to a wiring board having an electric wiring layer and an optical wiring layer. The present invention realizes a flip-chip mounted optical semiconductor device with connection reliability.
【００１２】[0012]
【課題を解決するための手段】本発明は上記課題を解決
するため、少なくとも１つの発光素子または受光素子を
有する光半導体素子を、電気絶縁部と電気伝送部からな
る電気配線層および光絶縁部と光伝送部からなる光配線
層を有する配線基板上に搭載する光半導体装置におい
て、前記光半導体素子上に配置される前記発光素子また
は受光素子は、前記各素子周囲に配置される第１の電極
上に形成された環状電極により、前記配線基板に主面が
対向して接続されていることを特徴とするものである。
さらに、前記光半導体素子上には、前記発光素子または
受光素子と接続される第２の電極が前記各素子に対応し
て形成されており、前記第２の電極上に、内部に第１の
金属とその周囲に第２の金属を配置したバンプ電極が形
成されており、前記バンプ電極を構成する前記第１の金
属の融点は前記第２の金属の融点よりも高く、前記光半
導体素子は前記バンプ電極により、前記配線基板に主面
が対向して接続されていることを特徴とするものであ
る。In order to solve the above problems, the present invention provides an optical semiconductor element having at least one light emitting element or light receiving element, an electrical wiring layer including an electrical insulation section and an electrical transmission section, and an optical insulation section. In an optical semiconductor device mounted on a wiring substrate having an optical wiring layer including an optical transmission part, the light emitting element or the light receiving element arranged on the optical semiconductor element is arranged around each of the first element. The main surface is connected to the wiring board so as to face the wiring board by an annular electrode formed on the electrode.
Further, a second electrode connected to the light emitting element or the light receiving element is formed on the optical semiconductor element so as to correspond to each element, and a first electrode is internally formed on the second electrode. A bump electrode in which a metal and a second metal is arranged around the metal is formed, the melting point of the first metal forming the bump electrode is higher than the melting point of the second metal, and the optical semiconductor element is The main surface is connected to the wiring board so as to face the wiring board by the bump electrode.
【００１３】さらに、前記光半導体素子裏面上には、前
記発光素子または受光素子と接続される第３の電極が形
成されており、前記第３の電極は前記光半導体素子より
も大きい寸法と熱伝導性を有する導電性材料板が接続さ
れており、前記導電性材料板には、内部に第１の金属と
その周囲に第２の金属を配置したバンプ電極が形成され
ており、前記バンプ電極を構成する前記第１の金属の融
点は前記第２の金属の融点よりも高く、前記バンプ電極
の高さ寸法は前記光半導体素子の厚み寸法と前記環状電
極の高さ寸法との総和以上の寸法を有することを特徴と
するものである。さらに、前記第１の電極上に形成する
環状電極と、前記バンプ電極を構成する第２の金属は、
Ｐｂ，Ｓｎ，Ａｇ，Ｓｂ，Ｉｎ，Ｂｉから選択される金
属またはこれら金属を主成分とする合金であって、前記
バンプ電極を構成する第１の金属は、Ａｌ，Ａｕ，Ｗ，
Ｃｕ，Ｎｉ，Ｃｒ，Ｐｔ，Ｐｄから選択される金属また
はこれら金属を主成分とする合金であることを特徴とす
るものである。さらに、前記発光素子は面発光型レーザ
であって、前記受光素子はフォトダイオードであり、前
記発光素子または受光素子と前記配線基板が作る隙間に
は樹脂が封止されていることを特徴とするものである。Further, a third electrode connected to the light emitting element or the light receiving element is formed on the back surface of the optical semiconductor element, and the third electrode has a larger size and a smaller heat than the optical semiconductor element. A conductive material plate having conductivity is connected to the conductive material plate, and a bump electrode having a first metal and a second metal arranged around the first metal is formed inside the conductive material plate. The melting point of the first metal constituting the above is higher than the melting point of the second metal, and the height dimension of the bump electrode is not less than the sum of the thickness dimension of the optical semiconductor element and the height dimension of the annular electrode. It is characterized by having dimensions. Furthermore, the annular electrode formed on the first electrode and the second metal forming the bump electrode are
A metal selected from Pb, Sn, Ag, Sb, In, and Bi or an alloy containing these metals as a main component, and the first metal forming the bump electrode is Al, Au, W,
It is characterized by being a metal selected from Cu, Ni, Cr, Pt, Pd or an alloy containing these metals as a main component. Further, the light emitting element is a surface emitting laser, the light receiving element is a photodiode, and a resin is sealed in a gap formed by the light emitting element or the light receiving element and the wiring board. It is a thing.
【００１４】本発明によれば、これまでの技術では実現
が困難であったアレイ型の光半導体素子のフリップチッ
プ実装を容易に実現できる。したがって、本発明によれ
ば、光半導体素子の主面の受発光素子配置領域上に光半
導体素子と接続する第２電極を形成することができるた
め、これまでの技術のように、アレイ型の光半導体素子
をワイヤーボンディングで接続する場合に必要となって
いたチップ周囲でのＩ／Ｏ電極配置に必要な電気信号配
線が不要になり、さらにＩ／Ｏ電極で律速となっていた
光半導体素子の高集積化も可能になり、結果として光半
導体素子の小型化が実現できる。特に、本発明のように
受発光素子部を接続する第１電極上に環状電極をはんだ
などを形成して、光半導体素子をフリップチップ実装す
ることにより、受発光素子を近接配置した場合でも、信
号伝送を行う光を環状電極内部に完全に閉じ込めること
ができるため、クロストークなどの問題も解決すること
ができる。According to the present invention, it is possible to easily realize flip-chip mounting of an array type optical semiconductor element, which has been difficult to realize by the conventional techniques. Therefore, according to the present invention, since it is possible to form the second electrode connected to the optical semiconductor element on the light receiving and emitting element disposition region on the main surface of the optical semiconductor element, it is possible to form an array type electrode as in the conventional techniques. An optical semiconductor element, which is necessary when arranging optical semiconductor elements by wire bonding, eliminates the need for electric signal wiring required for arranging I / O electrodes around the chip, and is rate-controlled by the I / O electrodes. It is possible to achieve high integration, and as a result, miniaturization of the optical semiconductor element can be realized. In particular, even when the annular electrode is formed on the first electrode connecting the light emitting and receiving element portion with solder or the like as in the present invention, and the optical semiconductor element is flip-chip mounted, even when the light emitting and receiving elements are arranged close to each other, Since light for signal transmission can be completely confined inside the annular electrode, problems such as crosstalk can be solved.
【００１５】さらに本発明によれば、光半導体素子と接
続する第２電極上に、内部に銅などの高融点金属を配置
して、その周囲にはんだなどの低融点金属を配置してバ
ンプ電極を構成しているため、第１電極上に形成する環
状電極だけでは困難であった、光半導体素子と配線基板
の作る隙間寸法を厳密に制御することができる。特に、
第１金属周囲に配置した、はんだなどの第２金属によ
り、光半導体素子の配線基板に対するセルフアライメン
ト効果が効率的に向上するため、光半導体素子と配線基
板の光導波路などの位置合わせ精度が向上して、受発光
素子と光導波路との結合効率も極めて向上させることが
可能になる。Further, according to the present invention, a high melting point metal such as copper is disposed inside the second electrode connected to the optical semiconductor element, and a low melting point metal such as solder is disposed around the bump electrode. Therefore, it is possible to strictly control the size of the gap between the optical semiconductor element and the wiring board, which is difficult only with the annular electrode formed on the first electrode. In particular,
The second metal such as solder disposed around the first metal efficiently improves the self-alignment effect of the optical semiconductor element with respect to the wiring board, and thus improves the alignment accuracy of the optical semiconductor element and the optical waveguide of the wiring board. Then, the coupling efficiency between the light emitting / receiving element and the optical waveguide can be significantly improved.
【００１６】また、このバンプ電極は、熱伝導性の高い
金属を第１の金属とすることで光半導体素子からの熱を
配線基板に効率的に放熱させることもできる。なお、こ
の光半導体素子と配線基板の作る隙間寸法制御構造、お
よび光半導体素子からの放熱構造は、光半導体素子裏面
に光半導体素子寸法よりも大きい寸法を有する第３の電
極を形成した構造においても同様の作用を発揮する。The bump electrode can also efficiently dissipate the heat from the optical semiconductor element to the wiring board by using a metal having high thermal conductivity as the first metal. The gap size control structure formed by the optical semiconductor element and the wiring board and the heat dissipation structure from the optical semiconductor element are the same as those in the structure in which the third electrode having a size larger than the optical semiconductor element size is formed on the back surface of the optical semiconductor element. Also has the same effect.
【００１７】さらに、本発明によれば、第１の電極上に
形成する環状電極により、光半導体素子と配線基板の作
る隙間部分に封止樹脂を配置しても、受発光素子部に封
止樹脂が流入することがなくなるため、封止樹脂による
光強度劣化などの問題を効果的に解決することができ
る。この作用は、光半導体素子の熱膨張係数と配線基板
の熱膨張係数を考慮した封止樹脂として、石英フィラな
どを含有する封止樹脂を容易に用いることができる点で
特に効果的である。Further, according to the present invention, the annular electrode formed on the first electrode seals the light receiving and emitting element portion even if the sealing resin is arranged in the gap between the optical semiconductor element and the wiring substrate. Since the resin does not flow in, problems such as deterioration of light intensity due to the sealing resin can be effectively solved. This action is particularly effective in that a sealing resin containing a quartz filler or the like can be easily used as the sealing resin in consideration of the thermal expansion coefficient of the optical semiconductor element and the thermal expansion coefficient of the wiring board.
【００１８】[0018]
【発明の実施の形態】以下，本発明の実施形態につき、
図１、図２、図３、図４、図５、図６、図７に示す本発
明の実施例を基に説明する。図１は本発明に係る光半導
体装置にフリップチップ実装される光半導体素子の第１
の実施例を示す平面図であり、図２は本発明に係る光半
導体装置の第１の実施例を示す第１の部分拡大断面図で
あり、図３は本発明に係る光半導体装置の第１の実施例
を示す部分拡大平面図であり、図４は本発明に係る光半
導体装置の第１の実施例を示す第２の部分拡大断面図で
あり、図５は本発明に係る光半導体装置の第２の実施例
を示す第１の部分拡大断面図であり、図６は本発明に係
る光半導体装置の第２の実施例を示す第２の部分拡大断
面図、図７は本発明の変形例を示す断面図である。BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention will be described below.
The embodiment of the present invention shown in FIGS. 1, 2, 3, 4, 5, 6, and 7 will be described. FIG. 1 shows a first optical semiconductor element flip-chip mounted on an optical semiconductor device according to the present invention.
2 is a plan view showing an embodiment of the present invention, FIG. 2 is a first partial enlarged sectional view showing a first embodiment of an optical semiconductor device according to the present invention, and FIG. 3 is a view showing an optical semiconductor device according to the present invention. 1 is a partially enlarged plan view showing the first embodiment, FIG. 4 is a second partially enlarged cross-sectional view showing the first embodiment of the optical semiconductor device according to the present invention, and FIG. 5 is an optical semiconductor according to the present invention. FIG. 6 is a first partial enlarged cross-sectional view showing a second embodiment of the device, FIG. 6 is a second partial enlarged cross-sectional view showing a second embodiment of the optical semiconductor device according to the present invention, and FIG. 7 is the present invention. It is sectional drawing which shows the modification.
【００１９】図１から図７において、１は光半導体素
子、２は面型発光素子、３は発光部、４はバンプ電極で
（第１の金属：９）、５は環状電極、６は第１の電極、
７は第２の電極、８は光入力部、１０は第２の金属、１
１は光配線層、１２は電気配線層、１３は配線基板、１
４は光伝送部、１５は第３の金属である。1 to 7, 1 is an optical semiconductor element, 2 is a planar light emitting element, 3 is a light emitting portion, 4 is a bump electrode (first metal: 9), 5 is an annular electrode, and 6 is a first electrode. One electrode,
7 is a second electrode, 8 is a light input part, 10 is a second metal, 1
1 is an optical wiring layer, 12 is an electrical wiring layer, 13 is a wiring board, 1
4 is an optical transmission part, and 15 is a third metal.
【００２０】以下、本発明に係る半導体装置の実施例の
製造方法を図１から図４を用いて説明する。まず図１に
おいて、面型発光素子として基板に対して垂直方向にレ
ーザ光を出射する面発光レーザ素子がアレイ状に配置さ
れた面発光レーザアレイ素子を用意する。この面発光レ
ーザ素子は本発明の主旨から一般的なものであり、例え
ば、特開２０００−２９４８７４号公報、特開２０００
−１２４５４５号公報に記載される方法で製造すること
ができるが、本発明では説明のため、例えば、ｎｏｎ−
ｄｏｐｅのＧａＡｓからなる活性層（活性領域）をｎ型
ＧａＡｌＡｓ，ｐ型ＧａＡｌＡｓからなる２つのクラッ
ド層で挟み、ｎ型ＧａＡｌＡｓ層の外面、ｐ型ＧａＡｌ
Ａｓ層の外面にそれぞれ多層膜からなる反射鏡を設けた
構成で、この２つの反射鏡の間でレーザ発振を起こさせ
ることによりクラッド層及び活性層の積層方向にレーザ
光を出力する構造の面発光レーザ素子を用いた。したが
って、面発光レーザ素子の光が出射される主面には、ｐ
型コンタクトのための電極が配置されている。この素子
電極は、本発明の趣旨から、凹部となる光出射部を囲む
環状電極の形状を有している。さらに、本発明での面発
光レーザアレイ素子は、上記の発光素子が、１００μｍ
ピッチで、１ｍｍ×１ｍｍのチップ上に、８×８のレイ
アウトで配置されている。なお、この発光素子レイアウ
トと電極材料などは限定されるものではないが、本発明
では、説明のため８×８のレイアウトとして、電極材料
には、Ａｕ／Ｎｉ／Ｔｉを用いた。なお、レーザアレイ
素子は、面発光素子に限るものではない。A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. First, as shown in FIG. 1, a surface emitting laser array element, in which surface emitting laser elements for emitting laser light in a direction perpendicular to a substrate are arranged in an array, is prepared as a surface emitting element. This surface emitting laser element is general from the point of the present invention, and is disclosed in, for example, Japanese Patent Laid-Open Nos. 2000-294874 and 2000.
Although it can be produced by the method described in Japanese Patent Publication No. 124545, in the present invention, for the purpose of explanation, for example, non-
The active layer (active region) made of dope GaAs is sandwiched between two cladding layers made of n-type GaAlAs and p-type GaAlAs, and the outer surface of the n-type GaAlAs layer and p-type GaAl
A surface having a structure in which reflecting mirrors each made of a multilayer film are provided on the outer surface of the As layer and outputting laser light in the stacking direction of the clad layer and the active layer by causing laser oscillation between the two reflecting mirrors. A light emitting laser device was used. Therefore, on the main surface from which the light of the surface emitting laser element is emitted, p
An electrode is arranged for the mold contact. For the purpose of the present invention, this element electrode has the shape of an annular electrode that surrounds the light emitting portion that is a recess. Further, in the surface emitting laser array element according to the present invention, the above light emitting element is 100 μm thick.
Pitches are arranged in a layout of 8 × 8 on a chip of 1 mm × 1 mm. Although the light emitting element layout and the electrode material are not limited, Au / Ni / Ti is used as the electrode material in the present invention with an 8 × 8 layout for the purpose of explanation. The laser array element is not limited to the surface emitting element.
【００２１】さらに、図２に示す配線基板は以下に記載
する方法で製造することができる。具体的には、光配線
層は、石英ガラス基板上に設けられた厚さ数十ミクロン
のＳｉＯ２（酸化ケイ素）で製造することができる。さ
らに具体的には、この光配線層は、光絶縁部中に光伝送
部が直径５０μｍ，ピッチ１５０μｍで形成され、必要
に応じて曲部が設けられている。Further, the wiring board shown in FIG. 2 can be manufactured by the method described below. Specifically, the optical wiring layer can be manufactured from SiO 2 (silicon oxide) having a thickness of several tens of microns provided on a quartz glass substrate. More specifically, in this optical wiring layer, an optical transmission portion is formed in the optical insulating portion with a diameter of 50 μm and a pitch of 150 μm, and a curved portion is provided as necessary.
【００２２】この光配線層における光絶縁部と光伝送部
はＳｉＯ２中に含有される不純物濃度による光の屈折率
の相違により分離でき、光伝送部の方が、光絶縁部より
も屈折率が大きくなるようにＳｉＯ２中の不純物濃度を
調整してある。これにより、光は光伝送部と光絶縁部の
境界で全反射して、光伝送部の中を伝達していくことに
なっている。The optical insulation part and the optical transmission part in this optical wiring layer can be separated by the difference in the refractive index of light due to the concentration of impurities contained in SiO 2 , and the optical transmission part has a higher refractive index than the optical insulation part. The impurity concentration in SiO 2 is adjusted so that As a result, light is totally reflected at the boundary between the optical transmission section and the optical insulation section, and is transmitted through the optical transmission section.
【００２３】さらに、この光配線層は必要に応じて多層
構造になっており、異なる光配線層間の光伝送部は、例
えば４５度ミラーなどを有するコンタクトホールで結合
され、このコンタクトホールの材料組成は、上記に記載
した光伝送部と同一材料で構成されている。この光配線
層の表面に露出されるコンタクトホールが光入力部とな
り、配線基板上に搭載される面発光レーザ素子の光出力
部と対向して、第１電極が直径３０μｍで構成されてい
る。この配線基板の光入力部と面発光レーザ素子の光出
力部は、図２に示すように、内径３０μｍ、外形５０μ
ｍ、高さ５０μｍ寸法のはんだ（Ｐｂ／Ｓｎ＝３７／６
３）から構成される環状電極で接続されている。したが
って、面発光レーザ素子から出射された光信号は、直接
またははんだ環状電極の内壁に反射され、光入力部であ
るコンタクトホールに向かい、光伝送部により光伝送さ
れる。なお、このはんだ環状電極の中空部を伝送、また
は内壁で反射する光信号は、光伝送部での光伝送または
反射と異なり減衰が大きくなるが、その距離が数十μｍ
であるため、その伝送特性が問題になることは殆どな
い。なお、この環状電極の材料組成に関しては、特に限
定されるものではないが、基本的には、Ｐｂ，Ｓｎ，Ａ
ｇ，Ｓｂ，Ｉｎ，Ｂｉから選択される金属またはこれら
金属を主成分とする合金であることが好ましいため、本
発明における実施例では、説明のため，Ｐｂ／Ｓｎ＝６
３／３７はんだを用いた。Further, this optical wiring layer has a multi-layered structure as required, and the optical transmission parts between different optical wiring layers are connected by a contact hole having, for example, a 45-degree mirror, and the material composition of this contact hole. Is made of the same material as that of the optical transmission section described above. The contact hole exposed on the surface of the optical wiring layer serves as a light input portion, and faces the light output portion of the surface emitting laser element mounted on the wiring substrate, and the first electrode is formed with a diameter of 30 μm. As shown in FIG. 2, the light input portion of this wiring board and the light output portion of the surface emitting laser element have an inner diameter of 30 μm and an outer diameter of 50 μm.
m, 50 μm height solder (Pb / Sn = 37/6
They are connected by an annular electrode composed of 3). Therefore, the optical signal emitted from the surface-emission laser device is directly or reflected by the inner wall of the solder annular electrode, heads for the contact hole as the light input portion, and is transmitted by the light transmitting portion. The optical signal transmitted through the hollow portion of the solder annular electrode or reflected by the inner wall has large attenuation unlike the optical transmission or reflection at the optical transmission portion, but the distance is several tens of μm.
Therefore, its transmission characteristics hardly cause any problem. The material composition of the annular electrode is not particularly limited, but basically Pb, Sn, A
Since a metal selected from g, Sb, In, and Bi or an alloy containing these metals as a main component is preferable, Pb / Sn = 6 is set for the sake of description in the embodiments of the present invention.
3/37 solder was used.
【００２４】さらに、配線基板の内部には、第２の電極
と接続される電気配線層が電気絶縁層と電気伝送部から
構成されている。この第２の電極は、図２に示すよう
に、バンプ電極で面発光レーザ素子の主面に露出させた
電流供給電極に接続されている。したがって、面発光レ
ーザ素子の主面に形成したバンプ電極に接続される電極
端子は、通常はｎ型コンタクトになっている。なお、こ
の第２電極上に接続されるバンプ電極の寸法は、本発明
の趣旨から特に限定されるものではないが、本発明にお
ける実施例では、２５μｍφの銅から構成される第１の
金属を中心に配置して、その周囲をはんだ（Ｐｂ／Ｓｎ
＝６３／３７）から構成される第２の金属で囲んで、全
体寸法としては５０μｍ高さと、５０μｍφの寸法を有
するバンプ電極を形成した。Further, inside the wiring board, an electric wiring layer connected to the second electrode is composed of an electric insulating layer and an electric transmission section. As shown in FIG. 2, this second electrode is connected to a current supply electrode exposed on the main surface of the surface emitting laser element by a bump electrode. Therefore, the electrode terminals connected to the bump electrodes formed on the main surface of the surface emitting laser element are usually n-type contacts. The size of the bump electrode connected to the second electrode is not particularly limited from the spirit of the present invention, but in the embodiment of the present invention, the first metal made of 25 μmφ copper is used. Place it in the center and solder around it (Pb / Sn
= 63/37), a bump electrode having an overall size of 50 μm height and a size of 50 μmφ was formed.
【００２５】なお、この第１の金属材料と第２の金属材
料組成に関しても、特に限定されるものではないが、基
本的には、第１の金属材料としては、Ａｌ，Ａｕ，Ｗ，
Ｃｕ，Ｎｉ，Ｃｒ，Ｐｔ，Ｐｄから選択される金属また
はこれらを主成分とする合金であることが好ましく、第
２の金属組成としては、Ｐｂ，Ｓｎ，Ａｇ，Ｓｂ，Ｉ
ｎ，Ｂｉから選択される金属またはこれら金属を主成分
とする合金であることが好ましいため、本発明における
実施例では、説明のため，第１の金属としてＣｕ、第２
の金属としてＰｂ／Ｓｎ＝６３／３７はんだを用いた。The compositions of the first metal material and the second metal material are not particularly limited, but basically, the first metal material is Al, Au, W,
A metal selected from Cu, Ni, Cr, Pt, and Pd or an alloy containing these as the main components is preferable, and the second metal composition includes Pb, Sn, Ag, Sb, and I.
Since a metal selected from n and Bi or an alloy containing these metals as a main component is preferable, Cu is used as the first metal and
As the metal of Pb / Sn = 63/37 solder was used.
【００２６】図３は、はんだ環状電極とバンプ電極の部
分平面図である。なお、本発明の実施例に記載するよう
に、環状電極とバンプ電極のレイアウトとしては、環状
電極を４隅とした場合の中心部にバンプ電極を配置する
方法が実装密度的には最も有利である。FIG. 3 is a partial plan view of the solder annular electrode and the bump electrode. As described in the embodiments of the present invention, as the layout of the ring electrodes and the bump electrodes, the method of arranging the bump electrodes at the center when the ring electrodes are four corners is the most advantageous in terms of mounting density. is there.
【００２７】さらに、これらの第１の電極上と第２の電
極上に配置される環状電極とバンプ電極の製造方法につ
いても、本発明の趣旨から特に限定されるものではない
が、公知の技術である電気めっき法の中でも厚膜レジス
トをめっきマスクとした、公知の技術であるパターンめ
っき法を用いて、配線基板側に形成することが製造プロ
セス的には有利である。これは、面発光レーザ素子を形
成する基板材料が一般的に酸に対して溶解性の高い材料
を使用しているのに対して、配線基板の構成材料は酸耐
性が一般的に高い材料を任意に選択できるためである。Further, the manufacturing method of the annular electrode and the bump electrode arranged on the first electrode and the second electrode is not particularly limited from the point of the present invention, but it is a known technique. Among the electroplating methods described in (1) above, it is advantageous in terms of the manufacturing process to use the thick film resist as a plating mask to form on the wiring board side by using the known technique of pattern plating. This is because the substrate material forming the surface-emission laser device generally uses a material highly soluble in acid, while the constituent material of the wiring substrate is a material generally high in acid resistance. This is because it can be arbitrarily selected.
【００２８】なお、面発光レーザ素子と配線基板とのフ
リップチップ実装接続は、例えば以下のような方法を用
いることができる。具体的には、公知の技術であるハー
フミラーを有して位置合せを行うフリップチップボンダ
ーを用いて、面発光レーザアレイ素子と、環状電極及び
バンプ電極の形成された配線基板の位置合せを行う。こ
の位置合せは、面発光レーザアレイ素子に形成された電
極端子と、配線基板上に形成された環状電極及びバンプ
電極で行うことが製造的には容易である。なお、この面
発光レーザアレイ素子は、加熱機構を有するコレットに
保持され、３５０℃の窒素雰囲気中で予備加熱されてい
る。For the flip-chip mounting connection between the surface emitting laser element and the wiring board, for example, the following method can be used. Specifically, using a flip-chip bonder that has a known half mirror and performs alignment, the surface-emission laser array element is aligned with the wiring substrate on which the annular electrodes and bump electrodes are formed. . It is easy in terms of manufacturing that this alignment is performed using the electrode terminals formed on the surface-emission laser array element and the annular electrodes and bump electrodes formed on the wiring board. The surface emitting laser array element is held by a collet having a heating mechanism and preheated in a nitrogen atmosphere at 350 ° C.
【００２９】次いで，面発光レーザアレイ素子と、配線
基板の環状電極及びバンプ電極が接触された状態で、コ
レットをさらに下方移動して、圧力３０ｋｇ／ｍｍ２を
加え、面発光レーザアレイ素子と配線基板を機械的圧力
が加わった状態で接触させる。さらにこの状態で温度を
３７０℃まで上昇させて環状電極とバンプ電極を構成す
るはんだを溶融させ、面発光レーザアレイ素子と配線基
板を接続する。このように面発光レーザアレイ素子と配
線基板をはんだ接続することにより、公知の技術である
セルフアライメント効果で、面発光レーザアレイ素子と
配線基板は正確な位置合せが実現され、面発光レーザ素
子の光出力部と配線基板の光入力部は、概ね±１μｍ〜
２μｍの誤差精度で接続することが可能になった。さら
に、バンプ電極に配置した第１の金属のスタンドオフ効
果で、面発光レーザアレイ素子と配線基板の高さばらつ
きを、第１の金属高さである，５０μｍ±２μｍ程度ま
で小さくすることも可能になった。Next, while the surface emitting laser array element is in contact with the ring electrode and the bump electrode of the wiring board, the collet is further moved downward and a pressure of 30 kg / mm 2 is applied to the surface emitting laser array element and the wiring. The substrates are brought into contact with each other under mechanical pressure. Further, in this state, the temperature is raised to 370 ° C. to melt the solder forming the annular electrode and the bump electrode, and the surface emitting laser array element and the wiring board are connected. By solder-connecting the surface-emission laser array element and the wiring board in this way, the surface-emission laser array element and the wiring board can be accurately aligned by the self-alignment effect which is a well-known technique. The optical output part and the optical input part of the wiring board are approximately ± 1 μm
It became possible to connect with an error accuracy of 2 μm. Furthermore, the stand-off effect of the first metal arranged on the bump electrode can reduce the height variation between the surface emitting laser array element and the wiring board to the first metal height of about 50 μm ± 2 μm. Became.
【００３０】さらに、図４に示すように、必要に応じ
て、面発光レーザアレイ素子と配線基板の作る隙間部分
に公知技術である、封止樹脂を配置することも可能であ
る。封止する樹脂としては特に限定されるものではない
が、例えば、ビスフェノール系エポキシとイミダゾール
効果触媒、酸無水物硬化剤と球状の石英フィラを重量比
で４５ｗｔ％含有するエポキシ樹脂などを用いることが
できる。したがって、例えばクレゾールノボラックタイ
プのエポキシ樹脂（ＥＣＯＮ−１９５ＸＬ；住友化学社
製）１００重量部、硬化剤としてのフェノール樹脂５４
重量部、充填剤としての熔融シリカ１００重量部、触媒
としてのベンジルジメチルアミン０．５重量部、その他
添加剤としてカーボンブラック３重量部、シランカップ
リング剤３重量部を粉砕、混合、溶融したエポキシ樹脂
溶融体などを用いることもできる。Further, as shown in FIG. 4, it is possible to dispose a sealing resin, which is a known technique, in the gap formed by the surface emitting laser array element and the wiring board, if necessary. Although the resin to be sealed is not particularly limited, for example, an epoxy resin containing bisphenol-based epoxy and an imidazole effect catalyst, an acid anhydride curing agent and spherical silica filler in a weight ratio of 45 wt% is used. it can. Therefore, for example, 100 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.) and a phenol resin 54 as a curing agent.
Parts by weight, 100 parts by weight of fused silica as a filler, 0.5 parts by weight of benzyldimethylamine as a catalyst, 3 parts by weight of carbon black as an additive, and 3 parts by weight of a silane coupling agent are crushed, mixed and melted epoxy A resin melt or the like can also be used.
【００３１】図５は、本発明に係る第２の実施例を示す
部分断面構成図である。この図において、面発光レーザ
アレイ素子及び面発光レーザアレイ素子を搭載する配線
基板については、第１の実施例で用いたものと、本発明
の目的とする範囲において基本的に相違する部分はない
が、第２の実施例で用いた面発光レーザアレイ素子は、
ｎ型電極がチップ裏面に全体的に配置されている。さら
に、第２の実施例に記載する面発光レーザアレイ素子裏
面には、第３の電極が配置されており、この第３の電極
には、面発光レーザアレイ素子の厚み寸法である３００
μｍとはんだ環状電極の厚み寸法である５０μｍの総和
である３５０μｍ高さのバンプ電極が形成され、配線基
板内部の電気配線層と接続される第２電極と電気的に接
続されている。なお、第３の金属の材料組成としては、
熱伝導性と導電性を有していれば特に限定されるもので
はないが、本発明では説明のため、バンプ電極の接続部
分のみがレジスト開口され、その表面にＡｕ／Ｎｉ薄膜
が被覆された銅板を用いた。さらに図６に示すように、
必要に応じて，面発光レーザアレイ素子及び第３の金属
が配線基板と作る隙間部分に第１の実施例の場合と同様
に、公知の技術である封止樹脂を配置することも可能で
ある。この封止樹脂の組成に関しても、第１の実施例の
場合と同様に、配線基板の熱膨張係数および面発光レー
ザアレイ素子の熱膨張係数を考慮した値であれば、特に
限定されるものではないため、本発明における第２の実
施例では、第１の実施例に記載した封止樹脂と同一組成
の封止樹脂を用いた。FIG. 5 is a partial cross sectional view showing a second embodiment according to the present invention. In this figure, the surface emitting laser array element and the wiring board on which the surface emitting laser array element is mounted are basically the same as those used in the first embodiment within the scope of the present invention. However, the surface emitting laser array element used in the second embodiment is
The n-type electrode is entirely arranged on the back surface of the chip. Further, a third electrode is arranged on the back surface of the surface emitting laser array element described in the second embodiment, and the third electrode has a thickness dimension of 300 of the surface emitting laser array element.
A bump electrode having a height of 350 μm, which is the sum of μm and the thickness of the solder annular electrode, which is 50 μm, is formed and electrically connected to the second electrode connected to the electric wiring layer inside the wiring board. The material composition of the third metal is
The present invention is not particularly limited as long as it has thermal conductivity and electrical conductivity, but for the purpose of explanation in the present invention, only the connection portion of the bump electrode is opened with a resist, and the surface thereof is covered with an Au / Ni thin film. A copper plate was used. Further, as shown in FIG.
If necessary, it is possible to dispose a sealing resin, which is a known technique, in the gap formed by the surface emitting laser array element and the third metal with the wiring board, as in the case of the first embodiment. . The composition of this sealing resin is not particularly limited as long as it is a value that takes into account the thermal expansion coefficient of the wiring board and the thermal expansion coefficient of the surface emitting laser array element, as in the case of the first embodiment. Therefore, in the second embodiment of the present invention, the sealing resin having the same composition as the sealing resin described in the first embodiment was used.
【００３２】なお、本発明はその趣旨から、光半導体素
子としては，上記に記載する面発光レーザ素子と同様
に、公知の技術で製造される面型受光素子を用いること
も可能である。したがって、詳細には記載しないが、こ
の場合の受光素子としては、例えば，以下のようなもの
を用いることが可能である。具体的には、受光素子は、
ｎ＋−ＩｎＰ基板上に受光部となるＰＩＮホトダイオー
ドを有しているもので、この受光部はメサ部と周辺部と
から構成され、これらは基板側から１．５μｍの厚さ
で、ｎ＝１０１５ｃｍ−３のｎ−ＩｎＰバッファ層と、
１．９μｍの厚さでｎ＝１０１５ｃｍ−３であるｎ−Ｇ
ａ０．４７Ｉｎ０．５３Ａｓの光吸収層と１．０μｍの
厚さでｐ＝１０１６ｃｍ−３のＩｎＰ層の積層構造とな
っているものである。From the spirit of the present invention, it is also possible to use, as the optical semiconductor element, a surface-type light receiving element manufactured by a known technique, like the surface emitting laser element described above. Therefore, although not described in detail, the following can be used as the light receiving element in this case, for example. Specifically, the light receiving element is
An n + -InP substrate has a PIN photodiode serving as a light receiving portion, and the light receiving portion is composed of a mesa portion and a peripheral portion, and these have a thickness of 1.5 μm from the substrate side, and n = An n-InP buffer layer of 10 15 cm −3 ,
N-G with a thickness of 1.9 μm and n = 10 15 cm −3
a 0.47 In 0.53 As light absorption layer and a laminated structure of an InP layer with a thickness of 1.0 μm and p = 10 16 cm −3 .
【００３３】また、上記実施例では光配線層が１層の例
について説明したが、たとえば、図７に示すように多層
構造にしても良く、さらに、波長の異なる面発光レーザ
素子を複数設けても良い。In the above embodiment, an example in which the optical wiring layer is one layer has been described. However, for example, a multilayer structure may be used as shown in FIG. 7, and a plurality of surface emitting laser elements having different wavelengths may be provided. Is also good.
【００３４】次に，以上の様に製造した本発明による光
半導体装置の性能を評価したところ以下の結果を得るこ
とができた。まず、上記に記載した面発光レーザ素子を
８×８配置でレイアウトした面発光レーザアレイ素子に
おいて、従来までの技術によりチップ周囲にワイヤーボ
ンディングするためのＩ／Ｏ電極を配置した場合の面発
光レーザアレイ素子のチップ寸法は，１ｍｍ×１ｍｍで
あったが、本発明に記載する方法では、Ｉ／Ｏ電極をチ
ップ周囲に配置するための信号配線が不要になり、さら
に、チップ寸法もＩ／Ｏ電極により律速されることがな
くなり、結果として１ｍｍ×１ｍｍの面発光レーザアレ
イ素子が実現でき、光半導体素子の小型化が実現でき
た。Next, when the performance of the optical semiconductor device according to the present invention manufactured as described above was evaluated, the following results were obtained. First, in a surface emitting laser array element in which the surface emitting laser elements described above are laid out in an 8 × 8 arrangement, a surface emitting laser in which an I / O electrode for wire bonding is arranged around a chip by a conventional technique The chip size of the array element was 1 mm × 1 mm, but the method described in the present invention eliminates the need for signal wiring for arranging the I / O electrodes around the chip, and further, the chip size is I / O. The electrodes do not control the rate, and as a result, a surface emitting laser array element of 1 mm × 1 mm can be realized, and the optical semiconductor element can be downsized.
【００３５】さらに、本発明による構造では、面発光レ
ーザ素子からの光出力部と配線基板上の光入力部との間
がはんだ環状電極により完全に覆われているため、従来
までの方法では、約−５ｄＢ程度あったクロストークは
本発明では確認されなかった。またこ、の光入出力部に
おける光結合損失は約０．２ｄＢ程度であり、光インタ
ーコネクション技術として用いるには問題のない値であ
った。さらにまた、本発明による構造の放熱特性を評価
した結果、面発光レーザアレイ素子と配線基板との熱抵
抗は、第１の実施例では約２０Ｗ／℃、第２の実施例で
は１５Ｗ／℃であり、従来までの技術での熱抵抗が３０
Ｗ／℃であったことと比較すると、その放熱特性が極め
て向上されていることが確認された。Further, in the structure according to the present invention, the space between the light output portion from the surface emitting laser element and the light input portion on the wiring board is completely covered by the solder annular electrode. Crosstalk of about -5 dB was not confirmed in the present invention. Also, the optical coupling loss in the optical input / output section is about 0.2 dB, which is a value that is not a problem for use as an optical interconnection technique. Furthermore, as a result of evaluating the heat dissipation characteristics of the structure according to the present invention, the thermal resistance between the surface emitting laser array element and the wiring board is about 20 W / ° C. in the first embodiment and 15 W / ° C. in the second embodiment. Yes, the thermal resistance of conventional technology is 30
It was confirmed that the heat dissipation characteristics were extremely improved as compared with the case of W / ° C.
【００３６】さらに、本発明による光半導体装置の信頼
性評価を行ったところ次のような結果を得た。なお、信
頼性試験評価は本発明の第１の実施例に記載した光半導
体装置で行った。そして、面発光レーザ素子を光入力部
とした６４個の環状電極とそれに対応する６４個のバン
プ電極の合計１２８個において、１箇所でも接続がオー
プンになった場合を不良にして評価した。サンプル数は
１０００個を評価して、温度サイクル条件は（−５５℃
（３０ｍｉｎ）〜２５℃（５ｍｉｎ）〜１２５℃（３０
ｍｉｎ）〜２５℃（５ｍｉｎ））で行った。評価の結
果、封止樹脂を配置しない構造では、１０００サイクル
で接続不良が発生して２０００サイクルで接続不良が１
００％になった。ところが封止樹脂を配置した構造で
は、３５００サイクルまで接続不良は発生せず、光半導
体素子のフリップチップ実装の接続信頼性が極めて向上
することが確認された。Further, when the reliability of the optical semiconductor device according to the present invention was evaluated, the following results were obtained. The reliability test evaluation was performed on the optical semiconductor device described in the first embodiment of the present invention. Then, in a total of 128 annular electrodes including 64 annular electrodes using the surface emitting laser element as an optical input portion and 64 bump electrodes corresponding thereto, a case where the connection was opened even at one place was evaluated as defective. Evaluating 1000 samples, the temperature cycle condition is (-55 ℃
(30 min) to 25 ° C (5 min) to 125 ° C (30
min) to 25 ° C. (5 min)). As a result of the evaluation, in the structure in which the sealing resin is not arranged, the connection failure occurs at 1000 cycles and the connection failure becomes 1 at 2000 cycles.
It became 00%. However, it was confirmed that in the structure in which the sealing resin is arranged, the connection failure does not occur up to 3500 cycles, and the connection reliability of the flip-chip mounting of the optical semiconductor element is significantly improved.
【００３７】以上の結果から、本発明による光半導体装
置は、発光素子または受光素子を有する光半導体素子に
対して、配線基板と光結合効率が高く、光半導体素子の
小型化が可能なフリップチップ実装構造の光半導体装置
を、放熱特性と接続信頼性を確保しながら容易に実現で
きる、これまでの問題を解決できる有効性の高いもので
あることが確認された。なお、本発明は上記実施例に限
定されるものではなく、その要旨を逸脱しない範囲で種
々に変更可能である。例えば、本実施例中では搭載され
る配線基板は，石英基板に対して記載したが、ポリマー
導波路を有するガラスエポキシ基板から構成される構造
の配線基板を用いても良く、さらに、光半導体素子に搭
載される受発光素子数とその材料構成についても特に限
定されるものではない。したがって、当然ながら、光半
導体素子として、同一チップ上に発光素子と受光素子が
搭載される集積型の光半導体素子を用いても良く、さら
に、光半導体素子と配線基板が作る隙間部分に封止する
樹脂、配線基板と接続する環状電極数とその環状電極の
平面的な断面形状などについても限定されるものではな
い。以上説明したように、本発明の実施例によれば、こ
れまでの技術では実現が困難であった接続信頼性の高い
アレイ型の光半導体素子のフリップチップ実装を容易に
実現できる。さらに、光半導体素子の主面の受発光素子
配置領域上に光半導体素子と接続する第２電極を形成す
ることができるため、アレイ型の光半導体素子をワイヤ
ーボンディングで接続する場合に必要となっていたチッ
プ周囲のＩ／Ｏ電極配置に必要な電気信号配線が不要に
なり、Ｉ／Ｏ電極で律速となっていた光半導体素子の高
集積化も可能になることから、結果として光半導体素子
の小型化が実現できる。From the above results, the optical semiconductor device according to the present invention has a high efficiency of optical coupling with the wiring board and an optical semiconductor device having a light emitting element or a light receiving element, and a flip chip capable of miniaturizing the optical semiconductor element. It has been confirmed that an optical semiconductor device having a mounting structure can be easily realized while ensuring heat dissipation characteristics and connection reliability, and that it is highly effective in solving the problems so far. The present invention is not limited to the above-described embodiments, but can be variously modified without departing from the scope of the invention. For example, although the wiring substrate to be mounted is described as a quartz substrate in this embodiment, a wiring substrate having a structure made of a glass epoxy substrate having a polymer waveguide may be used. There is no particular limitation on the number of light emitting / receiving elements mounted on the device and the material configuration thereof. Therefore, as a matter of course, as the optical semiconductor element, an integrated type optical semiconductor element in which a light emitting element and a light receiving element are mounted on the same chip may be used, and further, the optical semiconductor element is sealed in a gap formed by the optical semiconductor element and the wiring board. The resin used, the number of annular electrodes connected to the wiring board, and the planar sectional shape of the annular electrodes are not limited. As described above, according to the embodiments of the present invention, it is possible to easily realize flip-chip mounting of an array-type optical semiconductor element having high connection reliability, which has been difficult to achieve by the conventional technology. Further, since the second electrode connected to the optical semiconductor element can be formed on the light emitting / receiving element arrangement region of the main surface of the optical semiconductor element, it is necessary when connecting the array type optical semiconductor element by wire bonding. The electric signal wiring required for disposing the I / O electrodes around the chip, which has been required, becomes unnecessary, and the high integration of the optical semiconductor element, which has been the rate-determining factor for the I / O electrodes, can be realized, resulting in the optical semiconductor element. Can be made smaller.
【００３８】特に、本発明では、受発光素子部を接続す
る第１電極上に環状電極をはんだなどを形成して、光半
導体素子をフリップチップ実装するため、受発光素子を
光半導体チップ上で近接配置した場合でも、信号伝送を
行う光を環状電極内部に完全に閉じ込めることができる
ことから、クロストークなどの問題も解決することがで
きる。In particular, according to the present invention, since the annular electrode is formed on the first electrode connecting the light emitting and receiving element portion with solder or the like and the optical semiconductor element is flip-chip mounted, the light receiving and emitting element is mounted on the optical semiconductor chip. Even when they are arranged close to each other, the light for signal transmission can be completely confined inside the annular electrode, so that problems such as crosstalk can be solved.
【００３９】さらに本発明の実施例によれば、光半導体
素子と接続する第２電極上に、内部に銅などの高融点金
属を配置して、その周囲にはんだなどの低融点金属を配
置してバンプ電極を構成しているため、第１電極上に形
成する環状電極だけでは困難であった、光半導体素子と
配線基板の作る隙間寸法を厳密に制御することができ
る。特に、第１金属周囲に配置した、はんだなどの第２
金属により、光半導体素子の配線基板に対するセルフア
ライメント効果が効率的に向上するため、光半導体素子
と配線基板の光導波路などの位置合わせ精度が向上し
て、受発光素子と光導波路との結合効率も極めて向上さ
せることができる。なお、このバンプ電極は、熱伝導性
の高い金属を第１の金属とすることで光半導体素子から
の熱を配線基板に効率的に放熱させることもできる。Further, according to the embodiment of the present invention, a refractory metal such as copper is disposed inside the second electrode connected to the optical semiconductor element, and a low melting point metal such as solder is disposed around the refractory metal. Since the bump electrode is configured by using the bump electrode, it is possible to strictly control the size of the gap between the optical semiconductor element and the wiring board, which is difficult only with the annular electrode formed on the first electrode. In particular, a second metal such as solder is arranged around the first metal.
The metal effectively improves the self-alignment effect of the optical semiconductor element with respect to the wiring board, so that the alignment accuracy of the optical semiconductor element and the optical waveguide of the wiring board is improved, and the coupling efficiency between the light emitting / receiving element and the optical waveguide is improved. Can also be significantly improved. The bump electrode can also efficiently dissipate the heat from the optical semiconductor element to the wiring board by using a metal having high thermal conductivity as the first metal.
【００４０】さらに、本発明の実施例によれば、第１の
電極上に形成する環状電極により、光半導体素子と配線
基板の作る隙間部分に接続信頼性を向上させる封止樹脂
を配置しても、受発光素子部に封止樹脂が流入すること
がなくなるため、封止樹脂による光強度劣化などの問題
を効果的に解決することができる。なお、この効果は、
光半導体素子の熱膨張係数と配線基板の熱膨張係数を考
慮した封止樹脂として、石英フィラなどを含有する封止
樹脂を容易に用いることができる点で特に効果的であ
る。Furthermore, according to the embodiment of the present invention, the annular electrode formed on the first electrode disposes the sealing resin for improving the connection reliability in the gap between the optical semiconductor element and the wiring board. However, since the sealing resin does not flow into the light emitting / receiving element portion, it is possible to effectively solve problems such as deterioration of light intensity due to the sealing resin. This effect is
As a sealing resin considering the thermal expansion coefficient of the optical semiconductor element and the thermal expansion coefficient of the wiring board, a sealing resin containing a quartz filler or the like can be easily used, which is particularly effective.
【００４１】[0041]
【発明の効果】本発明によれば、発光素子または受光素
子をから構成される面型の光半導体素子を、電気配線層
と光配線層を有する配線基板に高い接続信頼性でフリッ
プチップ実装する光半導体装置を実現することができ
る。According to the present invention, a surface-type optical semiconductor element including a light emitting element or a light receiving element is flip-chip mounted on a wiring board having an electric wiring layer and an optical wiring layer with high connection reliability. An optical semiconductor device can be realized.
【図１】 本発明に係る光半導体装置の第１の実施例を
示す平面図。FIG. 1 is a plan view showing a first embodiment of an optical semiconductor device according to the present invention.
【図２】 本発明に係る光半導体装置の第１の実施例を
示す第１の部分拡大断面図。FIG. 2 is a first partial enlarged cross-sectional view showing a first embodiment of an optical semiconductor device according to the present invention.
【図３】 本発明に係る光半導体装置の第１の実施例を
示す部分拡大平面図。FIG. 3 is a partially enlarged plan view showing a first embodiment of an optical semiconductor device according to the present invention.
【図４】 本発明に係る光半導体装置の第１の実施例を
示す第２の部分拡大断面図。FIG. 4 is a second partial enlarged cross-sectional view showing the first embodiment of the optical semiconductor device according to the present invention.
【図５】 本発明に係る光半導体装置の第２の実施例を
示す第１の部分拡大断面図。FIG. 5 is a first partial enlarged sectional view showing a second embodiment of the optical semiconductor device according to the present invention.
【図６】 本発明に係る光半導体装置の第２の実施例を
示す第２の部分拡大断面図。FIG. 6 is a second partial enlarged cross-sectional view showing a second embodiment of the optical semiconductor device according to the present invention.
【図７】 本発明に係る光半導体装置の変形例を示す断
面図。FIG. 7 is a cross-sectional view showing a modified example of the optical semiconductor device according to the present invention.
【図８】 従来の技術を説明するための図FIG. 8 is a diagram for explaining a conventional technique.
【図９】 従来の技術を説明するための図FIG. 9 is a diagram for explaining a conventional technique.
１ 光半導体素子 ２ 面型発光素子 ３ 発光部 ４ バンプ電極 ５ 環状電極 ６ 第１の電極 ７ 第２の電極 ８ 光入力部 ９ 第１の金属 １０ 第２の金属 １１ 光配線層 １２ 電気配線層 １３ 配線基板 １４ 光伝送部 １５ 第３の金属 １６ 封止樹脂 1 Optical semiconductor element Two-sided light emitting device 3 light emitting part 4 bump electrodes 5 ring electrodes 6 First electrode 7 Second electrode 8 Optical input section 9 First metal 10 Second metal 11 Optical wiring layer 12 Electric wiring layer 13 wiring board 14 Optical transmission unit 15 Third metal 16 Sealing resin
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 31/12 Ｈ０１Ｌ 21/92 ６０２Ｃ ６０２Ｐ Ｆターム(参考） 5F073 AB02 AB16 BA09 EA27 FA15 FA30 5F088 AA01 BA03 BA15 BA16 BB10 EA02 JA09 JA14 5F089 AA06 AB20 AC02 AC07 GA10Front page continuation (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 31/12 H01L 21/92 602C 602P F term (reference) 5F073 AB02 AB16 BA09 EA27 FA15 FA30 5F088 AA01 BA03 BA15 BA16 BB10 EA02 JA09 JA14 5F089 AA06 AB20 AC02 AC07 GA10
Claims (5)
を有する光半導体素子を、電気絶縁部と電気伝送部から
なる電気配線層および光絶縁部と光伝送部からなる光配
線層を有する配線基板上に搭載する光半導体装置におい
て、前記光半導体素子上に配置される前記発光素子また
は受光素子は、前記各素子周囲に配置される第１の電極
上に形成された環状電極により、前記配線基板に主面が
対向して接続されていることを特徴とする光半導体装
置。1. An optical semiconductor element having at least one light emitting element or light receiving element, on a wiring board having an electric wiring layer composed of an electric insulation part and an electric transmission part and an optical wiring layer composed of an optical insulation part and an optical transmission part. In the optical semiconductor device mounted on the optical semiconductor device, the light emitting element or the light receiving element arranged on the optical semiconductor element is mounted on the wiring board by an annular electrode formed on a first electrode arranged around each element. An optical semiconductor device characterized in that main surfaces thereof are connected so as to face each other.
たは受光素子と接続される第２の電極が前記各素子に対
応して形成されており、前記第２の電極上には、内部に
第１の金属とその周囲に第２の金属を配置したバンプ電
極が形成されており、前記バンプ電極を構成する前記第
１の金属は前記第２の金属の融点よりも高い材料で構成
され、前記光半導体素子は前記バンプ電極により、前記
配線基板に主面が対向して接続されていることを特徴と
請求項１記載の光半導体装置。2. A second electrode connected to the light emitting element or the light receiving element is formed on the optical semiconductor element so as to correspond to each element, and an internal electrode is formed on the second electrode. A bump electrode in which a first metal and a second metal are arranged around the first metal, and the first metal forming the bump electrode is made of a material having a melting point higher than that of the second metal. 2. The optical semiconductor device according to claim 1, wherein the optical semiconductor element is connected to the wiring board so that its main surface faces the bump electrode by the bump electrode.
子または受光素子と接続される第３の電極が形成されて
おり、前記第３の電極は前記光半導体素子よりも大きい
寸法と熱伝導性を有する導電性材料板が接続されてお
り、前記導電性材料板には、内部に第１の金属とその周
囲に第２の金属を配置したバンプ電極が形成れており、
前記バンプ電極を構成する前記第１の金属は前記第２の
金属の融点よりも高い材料で構成され、前記バンプ電極
の高さ寸法は前記光半導体素子の厚み寸法と前記環状電
極の高さ寸法との総和以上の寸法を有することを特徴と
する請求項１記載の光半導体装置。3. A third electrode connected to the light emitting element or the light receiving element is formed on the back surface of the optical semiconductor element, and the third electrode has a larger size and a smaller heat than the optical semiconductor element. A conductive material plate having conductivity is connected to the conductive material plate, and a bump electrode having a first metal and a second metal arranged around the first metal is formed inside the conductive material plate.
The first metal forming the bump electrode is made of a material higher than the melting point of the second metal, and the height dimension of the bump electrode is the thickness dimension of the optical semiconductor element and the height dimension of the annular electrode. The optical semiconductor device according to claim 1, wherein the optical semiconductor device has a dimension not less than the sum of
前記バンプ電極を構成する第２の金属は、Ｐｂ，Ｓｎ，
Ａｇ，Ｓｂ，Ｉｎ，Ｂｉから選択される金属またはこれ
ら金属を主成分とする合金から構成され、前記バンプ電
極を構成する第１の金属は，Ａｌ，Ａｕ，Ｗ，Ｃｕ，Ｎ
ｉ，Ｃｒ，Ｐｔ，Ｐｄから選択される金属またはこれら
金属を主成分とする合金で構成されていることを特徴と
する請求項２または３記載の光半導体装置。4. An annular electrode formed on the first electrode,
The second metal forming the bump electrode is Pb, Sn,
The first metal, which is composed of a metal selected from Ag, Sb, In, Bi or an alloy containing these metals as a main component, and which constitutes the bump electrode, is Al, Au, W, Cu, N.
4. The optical semiconductor device according to claim 2, wherein the optical semiconductor device is made of a metal selected from i, Cr, Pt, and Pd or an alloy containing these metals as a main component.
前記受光素子はフォトダイオードであり、前記発光素子
または受光素子と前記配線基板とで構成される隙間には
樹脂が封止されていることを特徴とする請求項１記載の
光半導体装置。5. The light emitting element is a surface emitting laser,
The optical semiconductor device according to claim 1, wherein the light receiving element is a photodiode, and a resin is sealed in a gap formed between the light emitting element or the light receiving element and the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002094148A JP4104889B2 (en) | 2002-03-29 | 2002-03-29 | Optical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002094148A JP4104889B2 (en) | 2002-03-29 | 2002-03-29 | Optical semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003298167A true JP2003298167A (en) | 2003-10-17 |
| JP4104889B2 JP4104889B2 (en) | 2008-06-18 |
Family
ID=29386909
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002094148A Expired - Fee Related JP4104889B2 (en) | 2002-03-29 | 2002-03-29 | Optical semiconductor device |
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| Country | Link |
|---|---|
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| US7968801B2 (en) | 2005-07-28 | 2011-06-28 | Sharp Kabushiki Kaisha | Solder mounting structure, method for manufacturing such solder mounting structure and use of such solder mounting structure |
| JP2007242686A (en) * | 2006-03-06 | 2007-09-20 | Ricoh Co Ltd | Surface light emitting laser array and image forming device having same |
| US8027553B2 (en) | 2006-08-24 | 2011-09-27 | Hitachi Cable, Ltd. | Connected body and optical transceiver module |
| JP2008091916A (en) * | 2006-09-29 | 2008-04-17 | Osram Opto Semiconductors Gmbh | Semiconductor laser and its manufacturing method |
| JP2016040822A (en) * | 2014-08-11 | 2016-03-24 | 株式会社リコー | Surface emitting laser device and manufacturing method of the same |
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