JP2001013377A - Optical wiring device - Google Patents
Optical wiring deviceInfo
- Publication number
- JP2001013377A JP2001013377A JP11182741A JP18274199A JP2001013377A JP 2001013377 A JP2001013377 A JP 2001013377A JP 11182741 A JP11182741 A JP 11182741A JP 18274199 A JP18274199 A JP 18274199A JP 2001013377 A JP2001013377 A JP 2001013377A
- Authority
- JP
- Japan
- Prior art keywords
- optical
- photoelectric conversion
- conversion element
- integrated circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Optical Couplings Of Light Guides (AREA)
- Semiconductor Lasers (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、集積回路を高速実
装するための光配線装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical wiring device for mounting an integrated circuit at high speed.
【０００２】[0002]
【従来の技術】バイポーラトランジスタや電界効果トラ
ンジスタ等の電子デバイスの性能向上により、ＬＳＩは
飛躍的な高速動作が可能になってきている。しかしなが
ら、ＬＳＩの内部動作は高速化されているものの、ＬＳ
Ｉチップを実装したプリント基板レベルやこのプリント
基板を装着したラックでの動作速度はＬＳＩの動作速度
より低く抑えられている。この理由は、プリント基板や
ラックでは、動作周波数を上昇させると電気配線の伝送
損失や雑音、電磁障害が増大するため、特に信号を劣化
させないために長い配線ほど動作周波数を下げる必要が
でてくるためである。従って、電気配線装置では、能動
素子であるＬＳＩの動作速度を向上させても、プリント
基板やラックにおける問題のために動作速度を向上でき
ないという問題がある。一方、上述のような電気配線装
置の問題を鑑み、ＬＳＩ間を光で接続する光配線装置が
いくつか提案されている。光による配線の特徴は、直流
から数十ＧＨｚ以上の周波数領域で損失等の周波数依存
性が殆ど無く、また、配線経路の電磁障害や接地電位変
動雑音が無いため数十Ｇｂｐｓの配線が可能である。こ
の光配線装置を実現するためには光導波路を用いた配線
が必要となる。一般に光導波路の接続は平板光導波路基
板の突き合わせや光ファイバの突き合わせで行われ、電
気の配線方法に比し汎用性が少ない。このため、光配線
装置は電気配線装置に比し一般的ではなく、極限られた
特殊装置でのみ用いられている。2. Description of the Related Art With the improvement of the performance of electronic devices such as bipolar transistors and field effect transistors, LSIs have become able to operate at a remarkably high speed. However, although the internal operation of the LSI has been accelerated,
The operating speed at the level of the printed circuit board on which the I-chip is mounted or the rack on which the printed circuit board is mounted is suppressed to be lower than the operating speed of the LSI. The reason for this is that, in the case of a printed circuit board or rack, increasing the operating frequency increases transmission loss, noise, and electromagnetic interference of electric wiring, and in particular, it is necessary to lower the operating frequency for longer wiring so as not to deteriorate the signal. That's why. Therefore, in the electric wiring device, there is a problem that even if the operation speed of the LSI as an active element is improved, the operation speed cannot be improved due to a problem in a printed circuit board or a rack. On the other hand, in view of the above-described problem of the electric wiring device, some optical wiring devices for connecting between LSIs with light have been proposed. The feature of wiring by light is that there is almost no frequency dependence such as loss in the frequency range from DC to several tens of GHz, and wiring of several tens of Gbps is possible because there is no electromagnetic interference or ground potential fluctuation noise in the wiring path. is there. In order to realize this optical wiring device, wiring using an optical waveguide is required. In general, the connection of the optical waveguide is performed by butting of the flat optical waveguide substrate or butting of the optical fiber, and is less versatile than the electric wiring method. For this reason, the optical wiring device is less common than the electrical wiring device, and is used only in a very limited special device.
【０００３】[0003]
【発明が解決しようとする課題】本発明は、上記問題点
を解決し、ＬＳＩを汎用的に光配線実装するための光配
線線装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an optical wiring line apparatus for mounting an LSI on an optical wiring in a general-purpose manner.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、基板と、この基板上に配置された集積回
路と、前記基板上に設けられ、前記集積回路と電気信号
のやり取りをする光電変換素子と、前記基板の一部に設
けられた貫通孔と、この貫通孔に配置され、前記光電変
換素子と対向する曲面を有する光端子とを具備し、前記
集積回路への入力は、前記光端子を介して前記光電変換
素子へ光信号を入力し、前記光電変換素子が前記光信号
を電気信号に変換し、この電気信号を前記集積回路に入
力することによって行われることを特徴とする光配線装
置を提供する。また、本発明は、基板と、この基板上に
配置された集積回路と、前記基板上に設けられ、前記集
積回路と電気信号のやり取りをする光電変換素子と、前
記基板の一部に設けられた貫通孔と、この貫通孔に配置
され、前記光電変換素子と対向する曲面を有する光端子
とを具備し、前記集積回路からの出力は、前記集積回路
から電気信号を前記光電変換素子へ出力し、この電気信
号により前記光電変換素子が光信号に変換し、この光信
号を前記光端子を介して出力することによって行われる
ことを特徴とする光配線装置を提供する。In order to achieve the above object, the present invention provides a substrate, an integrated circuit disposed on the substrate, and exchange of electric signals with the integrated circuit provided on the substrate. A photoelectric conversion element, a through-hole provided in a part of the substrate, and an optical terminal disposed in the through-hole and having a curved surface facing the photoelectric conversion element. Is performed by inputting an optical signal to the photoelectric conversion element via the optical terminal, the photoelectric conversion element converts the optical signal into an electric signal, and inputs the electric signal to the integrated circuit. An optical wiring device is provided. In addition, the present invention provides a substrate, an integrated circuit provided on the substrate, a photoelectric conversion element provided on the substrate, for exchanging electric signals with the integrated circuit, and provided on a part of the substrate. And an optical terminal disposed in the through-hole and having a curved surface facing the photoelectric conversion element. The output from the integrated circuit outputs an electric signal from the integrated circuit to the photoelectric conversion element. Further, an optical wiring device is provided in which the photoelectric conversion element is converted into an optical signal by the electric signal, and the optical signal is output through the optical terminal.
【０００５】また、前記基板に設けられた貫通孔は傾斜
側面を有し、この傾斜側面によって前記光端子が位置決
めされることを特徴とする光配線装置を提供する。ま
た、パッケージ基板と、このパッケージ基板上に対向配
置された集積回路と、前記基板上に設けられ、前記集積
回路と電気信号のやり取りをする光電変換素子と、前記
パッケージ基板の一部に設けられた貫通孔と、この貫通
孔に配置され、前記光電変換素子と対向する曲面を有す
る光端子と、前記光端子を介し前記パッケージ基板と対
向配置された光配線基板とを具備し、前記集積回路への
入力は、前記光端子を介して前記光電変換素子へ光信号
を入力し、前記光電変換素子が前記光信号を電気信号に
変換し、この電気信号を前記集積回路に入力することに
よって行われることを特徴とする光配線装置を提供す
る。また、パッケージ基板と、このパッケージ基板上に
対向配置された集積回路と、前記基板上に設けられ、前
記集積回路と電気信号のやり取りをする光電変換素子
と、前記パッケージ基板の一部に設けられた貫通孔と、
この貫通孔に配置され、前記光電変換素子と対向する曲
面を有する光端子と、前記光端子を介し前記パッケージ
基板と対向配置された光配線基板とを具備し、前記集積
回路からの出力は、前記集積回路から電気信号を前記光
電変換素子へ出力し、この電気信号により前記光電変換
素子が光信号に変換し、この光信号を前記光端子を介し
て出力することによって行われることを特徴とする光配
線装置を提供する。[0005] Further, the present invention provides an optical wiring device, wherein the through hole provided in the substrate has an inclined side surface, and the optical terminal is positioned by the inclined side surface. Further, a package substrate, an integrated circuit opposed to the package substrate, a photoelectric conversion element provided on the substrate to exchange electric signals with the integrated circuit, and a photoelectric conversion element provided on a part of the package substrate. The integrated circuit, comprising: a through hole; an optical terminal disposed in the through hole, the optical terminal having a curved surface facing the photoelectric conversion element; and an optical wiring substrate facing the package substrate via the optical terminal. Input to the photoelectric conversion element through the optical terminal, the photoelectric conversion element converts the optical signal into an electric signal, and inputs the electric signal to the integrated circuit. An optical wiring device is provided. Further, a package substrate, an integrated circuit opposed to the package substrate, a photoelectric conversion element provided on the substrate to exchange electric signals with the integrated circuit, and a photoelectric conversion element provided on a part of the package substrate. Through holes,
An optical terminal having a curved surface facing the photoelectric conversion element, the optical terminal being disposed in the through-hole and facing the package substrate via the optical terminal, wherein an output from the integrated circuit is: Outputting an electric signal from the integrated circuit to the photoelectric conversion element, converting the electric signal into an optical signal by the electric signal, and outputting the optical signal through the optical terminal, is performed. To provide an optical wiring device.
【０００６】また、前記パッケージ基板に設けられた貫
通孔は傾斜側面を有し、前記光配線基板の前記光結合さ
れた部分は傾斜側面を持った凹部が設けられ、これらの
傾斜側面によって前記光端子、前記光導波路、前記光電
変換素子が光結合するように位置決めされることを特徴
とする光配線装置を提供する。また、前記光端子による
光結像位置を前記凹部底面より深い位置とし、この位置
に前記光導波路を位置させることによって、前記光導波
路を前記光配線基板の表面に露出させないことを特徴と
する光配線装置を提供する。本発明の骨子は、集積回路
（ＬＳＩ）パッケージ内部にＬＳＩ及び光半導体素子を
搭載するパッケージ基板を設け、そのパッケージ基板に
設けられた貫通孔により、光半導体素子と先端が半球又
は先端が球テーパ形状の光入出力端子の光軸のアライメ
ントを行うことである。また、光配線基板の光入出力部
に凹部を設け、前記光入出力端子を機械的に固定すると
共にパッケージ基板と光配線基板を位置合わせし、光入
出力端子のレンズの焦点を光配線基板内部にある光導波
路におくものである。また、集積回路の電源および低速
信号端子は電気接続ピンを通して電気的に接続し、高速
信号は光電変換素子、光端子、光導波路を通して行うも
のである。このようにして集積回路内の電子素子に電源
を与え、かつ高速信号は光信号によって行えるので、ボ
ードレベルでの信号の劣化を防ぐことができる。The through hole provided in the package substrate has an inclined side surface, and the optically coupled portion of the optical wiring board is provided with a concave portion having an inclined side surface. An optical wiring device is provided, wherein a terminal, the optical waveguide, and the photoelectric conversion element are positioned so as to be optically coupled. Further, the optical imaging position by the optical terminal is set to a position deeper than the bottom surface of the concave portion, and the optical waveguide is located at this position, so that the optical waveguide is not exposed on the surface of the optical wiring substrate. Provide a wiring device. The gist of the present invention is to provide a package substrate on which an LSI and an optical semiconductor element are mounted inside an integrated circuit (LSI) package. The purpose is to perform alignment of the optical axis of the optical input / output terminal having the shape. Also, a concave portion is provided in the optical input / output section of the optical wiring board, the optical input / output terminal is mechanically fixed, the package substrate and the optical wiring board are aligned, and the focal point of the lens of the optical input / output terminal is adjusted. It is placed in an optical waveguide inside. In addition, the power supply and the low-speed signal terminal of the integrated circuit are electrically connected through electric connection pins, and the high-speed signal is transmitted through a photoelectric conversion element, an optical terminal, and an optical waveguide. In this manner, power is supplied to the electronic elements in the integrated circuit, and a high-speed signal can be generated by an optical signal, so that signal degradation at the board level can be prevented.
【０００７】本発明によれば、光電変換素子と光導波路
の光軸調整を、光電変換素子と光入出力端子との調整、
光入出力端子と光導波路との調整、に分離するため、Ｌ
ＳＩパッケージ、配線基板実装といった通常のＬＳＩ実
装と同様な工程分離が可能である。従って、ＬＳＩパッ
ケージと配線基板の作製が独立に行え、光配線基板の作
製に光電変換素子の実装がないため光配線基板の大型化
が容易となる。また、ＬＳＩパッケージは、予め光端子
を設けたパッケージ基板を用いることで光電変換素子搭
載といった最小限の工程追加で通常のＬＳＩパッケージ
工程に投入できる。更に、光配線基板実装においては電
気端子の位置合わせ程度の精度で光端子を機械的に勘合
させることが可能であり、個別の光軸合わせが不要なた
め他の電子素子等と同時の実装が可能となる。また、光
端子の焦点位置を光配線基板の内部に位置させるため、
光配線基板の表面汚染の制限が緩和され、その取扱いが
容易となる。このように本発明の光配線パッケージ及び
光配線装置に依れば、光配線固有の工程が最小限に抑え
られ、一般的な電子素子実装の手法が適用可能となるた
め、実装コストを大幅に上昇させることなく光配線実装
が可能となり、ボードレベル、ラックレベルで高速動作
可能なシステムを安価に構築できるという効果を奏す
る。According to the present invention, the optical axis adjustment of the photoelectric conversion element and the optical waveguide is performed by adjusting the photoelectric conversion element and the optical input / output terminal.
To separate the optical input / output terminal and the optical waveguide,
Process separation similar to that of ordinary LSI mounting such as SI package and wiring board mounting is possible. Therefore, the LSI package and the wiring board can be manufactured independently, and since the photoelectric conversion element is not mounted in the manufacturing of the optical wiring board, the size of the optical wiring board can be easily increased. Further, the LSI package can be put into a normal LSI package process by using a package substrate provided with an optical terminal in advance and adding a minimum number of steps such as mounting a photoelectric conversion element. Furthermore, in the optical wiring board mounting, it is possible to mechanically fit the optical terminals with an accuracy equivalent to the alignment of the electric terminals, and since individual optical axis alignment is unnecessary, mounting at the same time as other electronic elements can be performed. It becomes possible. Also, in order to position the focal position of the optical terminal inside the optical wiring board,
Restrictions on surface contamination of the optical wiring substrate are eased, and handling thereof is facilitated. As described above, according to the optical wiring package and the optical wiring device of the present invention, the process peculiar to the optical wiring is minimized, and a general electronic element mounting method can be applied. The optical wiring can be mounted without raising, and an effect that a system capable of high-speed operation at a board level or a rack level can be constructed at a low cost can be obtained.
【０００８】[0008]
【発明の実施の形態】以下、図面を参照しながら本発明
の詳細を説明する。図１は、本発明の光配線パッケージ
の斜視図である。パッケージ基板３上に、ＬＳＩチップ
１が、フリップチップ実装されている。ＬＳＩチップ１
の脇には光電変換素子アレイ２が形成され、ＬＳＩチッ
プとは電気的に信号のやり取りを行う。パッケージ基板
３上には電気内部配線４が形成され、電気端子６とワイ
ヤーボンディング５で接続されている。これら電気的配
線はＬＳＩの電源や低速信号と接続されている。ＬＳＩ
チップ１、光電変換素子アレイ２、内部配線４、パッケ
ージ基板３ワイヤーボンディング５と電気端子６の一部
は、モールド樹脂７によってモールドされパッケージ化
されている。光電変換素子アレイ２と光端子は、パッケ
ージ基板３に形成された貫通孔を介して光結合されてい
るが、具体的構成については後述する。このような光配
線装置出は、ＬＳＩチップ１の電源配線及び動作モード
制御信号等の低速信号は内部配線４及びボンディングワ
イヤ５を通じて電気端子６に接続される。一方、クロッ
ク信号やデータ等の高速信号は同様な内部配線または５
と同様なボンディングワイヤにより光電変換素子アレイ
２に接続され、光信号としてパッケージ基板３外部に接
続される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a perspective view of an optical wiring package of the present invention. The LSI chip 1 is flip-chip mounted on the package substrate 3. LSI chip 1
A photoelectric conversion element array 2 is formed beside the device, and electrically exchanges signals with the LSI chip. The electric internal wiring 4 is formed on the package substrate 3, and is connected to the electric terminals 6 by wire bonding 5. These electrical wirings are connected to the power supply and low-speed signal of the LSI. LSI
A part of the chip 1, the photoelectric conversion element array 2, the internal wiring 4, the package substrate 3, the wire bonding 5, and the electric terminals 6 are molded by a molding resin 7 and packaged. The photoelectric conversion element array 2 and the optical terminal are optically coupled via a through hole formed in the package substrate 3, and a specific configuration will be described later. In such an optical wiring device, a low-speed signal such as a power supply wiring and an operation mode control signal of the LSI chip 1 is connected to an electric terminal 6 through an internal wiring 4 and a bonding wire 5. On the other hand, high-speed signals such as clock signals and data are transmitted through similar internal wiring or 5
Is connected to the photoelectric conversion element array 2 by the same bonding wire as described above, and is connected to the outside of the package substrate 3 as an optical signal.
【０００９】このパッケージ基板３の作製工程の例とし
ては、まず、光端子及び内部配線を形成したパッケージ
基板３にＬＳＩチップ１と光電変換素子アレイ２を搭載
する。このとき、ＬＳＩチップ１及び光電変換素子２を
フリップチップ実装すれば、ＬＳＩチップ１とパッケー
ジ基板３の内部配線４や光電変換素子アレイ２との電気
接続は同時に行われる。または、それぞれワイヤボンデ
ィング５で接続しても構わない。また、光端子の形成
と、ＬＳＩチップ１や光電変換素子アレイ２の搭載が逆
の順序であっても構わない。次に、リードフレーム６へ
のワイヤ接続（ボンディングワイヤ５の形成）を行い、
全体をエポキシ樹脂等の樹脂によりモールドし、リード
（電気端子６）の切断と整形を行ってパッケージが完成
する。このとき、後述するように光端子の先端はモール
ド樹脂の外部に露出するよう、金型を加工しておく。図
２は、図１で示した本発明の光配線装置の構成例を示す
断面図である。パッケージ基板３の傾斜側面を有する貫
通孔が形成された部分には、光電変換素子アレイ２の光
電変換素子能動部２００が対向するように配置され、キ
ャップ部をフリップチップ実装用の半田ボールで形成し
ている。As an example of the manufacturing process of the package substrate 3, first, the LSI chip 1 and the photoelectric conversion element array 2 are mounted on the package substrate 3 on which optical terminals and internal wirings are formed. At this time, if the LSI chip 1 and the photoelectric conversion element 2 are flip-chip mounted, the electrical connection between the LSI chip 1 and the internal wiring 4 of the package substrate 3 and the photoelectric conversion element array 2 is performed simultaneously. Alternatively, they may be connected by wire bonding 5, respectively. Further, the order of forming the optical terminal and mounting the LSI chip 1 and the photoelectric conversion element array 2 may be reversed. Next, a wire connection (formation of the bonding wire 5) to the lead frame 6 is performed,
The whole is molded with a resin such as epoxy resin, and the leads (electric terminals 6) are cut and shaped to complete the package. At this time, the die is processed so that the tip of the optical terminal is exposed outside the mold resin as described later. FIG. 2 is a sectional view showing a configuration example of the optical wiring device of the present invention shown in FIG. In the portion of the package substrate 3 where the through hole having the inclined side surface is formed, the photoelectric conversion element active section 200 of the photoelectric conversion element array 2 is disposed so as to face the portion, and the cap section is formed by solder balls for flip chip mounting. are doing.
【００１０】この貫通後部には傾斜側面に収まるように
球状レンズ（光端子）８が形成されている。貫通孔内部
および光電変換素子アレイ２とパッケージ基板３とのギ
ャップ部には透明樹脂９が充填されている。７は前記モ
ールド樹脂である。この光配線装置は、パッケージ基板
３の表面に光電変換素子２搭載用の配線及び半田ボール
１０が形成されており、光電変換素子アレイ２を載せた
後、熱処理により半田溶融を行うことで半田ボール１０
が形成される。このとき、半田ボール１０の表面張力に
より光電変換素子アレイ２が所定位置に移動するため、
初期の光電変換素子アレイ２の搭載は例えば±１０μｍ
といった比較的低精度の位置合わせでも良く、半田張力
による所謂フリップチップボンディングによって最終的
に１μｍ以下の精度が実現される。また、パッケージ基
板３は、例えば異方性エッチングにより高精度に形成し
た貫通口を有するＳｉ基板を用いてもよい。ここに球レ
ンズ８を勘合させ、前述のフリップチップボンディング
と合わせることで、光電変換素子アレイ２と球レンズ８
の光軸を機械的に高精度に合わせることができる。球レ
ンズ８は透明樹脂９で仮固定しておき、パッケージのモ
ールド樹脂７により最終的な固定を行う。[0010] A spherical lens (optical terminal) 8 is formed in the rear portion of the through hole so as to fit on the inclined side surface. A transparent resin 9 is filled in the through hole and in the gap between the photoelectric conversion element array 2 and the package substrate 3. 7 is the mold resin. In this optical wiring device, the wiring for mounting the photoelectric conversion element 2 and the solder ball 10 are formed on the surface of the package substrate 3. After the photoelectric conversion element array 2 is mounted, the solder ball is melted by heat treatment. 10
Is formed. At this time, since the photoelectric conversion element array 2 moves to a predetermined position due to the surface tension of the solder ball 10,
The initial mounting of the photoelectric conversion element array 2 is, for example, ± 10 μm.
A relatively low precision alignment may be used, and an accuracy of 1 μm or less is finally achieved by so-called flip chip bonding using solder tension. Further, as the package substrate 3, for example, a Si substrate having a through hole formed with high precision by anisotropic etching may be used. Here, the spherical lens 8 is fitted and combined with the above-described flip chip bonding, so that the photoelectric conversion element array 2 and the spherical lens 8
Can be mechanically aligned with high precision. The spherical lens 8 is temporarily fixed with a transparent resin 9 and finally fixed with the mold resin 7 of the package.
【００１１】作製工程としては、まず、パッケージ基板
３に光電変換素子アレイ２の搭載を行い、例えば半田ボ
ール１０をＡｕＳｎ共晶として不活性ガス雰囲気中で３
００℃の熱処理を行う。次に、パッケージ基板３の貫通
口に透明樹脂９として、例えば光電変換素子アレイ２に
かかる応力を考慮して、シリコーン系樹脂を注入し、続
いて球レンズ８を装着する。次に、この透明樹脂９を熱
処理により硬化させた後、全体を樹脂モールドする。こ
のとき、予め光電変換素子アレイ２と球レンズの間には
透明樹脂９が充填されているためモールド樹脂７が光路
に進入することはなく、モールド樹脂７の光学特性は特
段考慮する必要がなく、逆に外界からの光の侵入を防ぐ
意味からも光吸収特性の高い樹脂にしてもよい。また、
モールド樹脂は通常のＬＳＩのパッケージ樹脂を用いる
ことができ、例えば、ガラスフィラーを添加して熱膨張
率調整したエポキシ樹脂等を用いれば良い。勿論、モー
ルドする際の金型をモールド樹脂が光端子８の先端に被
らないよう設定しておく。図３は、本発明の光配線装置
を示す断面図であり、図２で示した光配線装置を光配線
基板上に搭載したものである。図３に示すように、１１
は光配線基板、１２は光導波路、１３は光結合のための
光端子勘合部（凹部）、１４は透明樹脂であり、１４の
透明樹脂は光配線パッケージの仮固定と光経路の保護材
を兼ねている。In the manufacturing process, first, the photoelectric conversion element array 2 is mounted on the package substrate 3, and for example, the solder balls 10 are converted into AuSn eutectics in an inert gas atmosphere.
A heat treatment at 00 ° C. is performed. Next, a silicone resin is injected into the through hole of the package substrate 3 as the transparent resin 9 in consideration of, for example, the stress applied to the photoelectric conversion element array 2, and then the spherical lens 8 is mounted. Next, after the transparent resin 9 is cured by heat treatment, the whole is resin-molded. At this time, since the space between the photoelectric conversion element array 2 and the spherical lens is filled with the transparent resin 9 in advance, the mold resin 7 does not enter the optical path, and the optical characteristics of the mold resin 7 do not need to be particularly considered. Conversely, a resin having high light absorption characteristics may be used from the viewpoint of preventing light from entering from the outside. Also,
As the mold resin, a normal LSI package resin can be used. For example, an epoxy resin or the like whose glass material is added to adjust the coefficient of thermal expansion may be used. Of course, the mold used for molding is set so that the mold resin does not cover the tip of the optical terminal 8. FIG. 3 is a sectional view showing the optical wiring device of the present invention, in which the optical wiring device shown in FIG. 2 is mounted on an optical wiring board. As shown in FIG.
Is an optical wiring board, 12 is an optical waveguide, 13 is an optical terminal fitting portion (recess) for optical coupling, 14 is a transparent resin, and 14 transparent resin is used for temporary fixing of an optical wiring package and a protective material for an optical path. Also serves as.
【００１２】光配線基板１１は、石英、多成分ガラス等
の所謂ガラス系光導波路基板や、ポリメチルメタクリレ
ート（ＰＭＭＡ）、弗化ポリイミド、ポリカーボネート
（ＰＣ）等の所謂樹脂系光導波路基板を用いることがで
きる。この実施例では、光導波路が水平方向に光伝播す
る形態のものであり、光導波路端部（光入出力部、基板
凹部）において光路直交変換の４５°加工が施されてい
る。これは、回折格子による結合や内部ミラーによるも
の等でも構わず、また、基板垂直方向に光伝播する形態
の場合には、特に直交変換等の構成は不要である。この
実施例の実装工程例としては、まず、光配線基板１１の
光入出力部１３に透明樹脂又は透明樹脂接着剤１４を塗
布し、光配線パッケージの搭載と透明樹脂１４による固
定を行う。透明樹脂１４は、例えばシリコーン樹脂やエ
ポキシ樹脂等の透明樹脂を用いれば良い。但し、一般の
透明樹脂だけでは充填剤にはなるものの、後の工程で位
置ずれを起こすため空スペースに接着剤を併用しても良
い。また、アクリル系やエポキシ系の透明接着剤を用い
れば光配線パッケージの固定も同時に行え、この時、紫
外線硬化樹脂等を用いれば短時間に固定することができ
る。この工程は、一般のＬＳＩパッケージの実装で用い
られる位置決めと接着剤による仮固定の工程に相当し、
必ずしも光配線装置固有の付加工程ではない。As the optical wiring substrate 11, a so-called glass-based optical waveguide substrate such as quartz or multi-component glass, or a so-called resin-based optical waveguide substrate such as polymethyl methacrylate (PMMA), fluorinated polyimide or polycarbonate (PC) is used. Can be. In this embodiment, the optical waveguide has a form in which light propagates in the horizontal direction, and 45 ° processing of optical path orthogonal transformation is performed at the end of the optical waveguide (light input / output portion, substrate recess). This may be a coupling by a diffraction grating, an internal mirror, or the like. In the case of a form in which light propagates in a direction perpendicular to the substrate, a configuration such as orthogonal transformation is not particularly required. As an example of a mounting process in this embodiment, first, a transparent resin or a transparent resin adhesive 14 is applied to the optical input / output unit 13 of the optical wiring board 11, and mounting of the optical wiring package and fixing with the transparent resin 14 are performed. As the transparent resin 14, a transparent resin such as a silicone resin or an epoxy resin may be used. However, although a general transparent resin alone can serve as a filler, an adhesive may be used in an empty space in order to cause displacement in a later step. Further, if an acrylic or epoxy transparent adhesive is used, the optical wiring package can be fixed at the same time. At this time, if an ultraviolet curable resin or the like is used, the optical wiring package can be fixed in a short time. This step corresponds to a positioning and temporary fixing step using an adhesive used in mounting an ordinary LSI package.
It is not necessarily an additional process unique to the optical wiring device.
【００１３】次に、他のパッケージや電子素子等も仮固
定し、光配線基板１１を半田リフロー工程にかけ、電気
端子の半田接続を行う。この工程は、一般的ＬＳＩ実装
と同様である。このように、本発明実施例の光配線装置
では、一般のＬＳＩ実装とほぼ同等の工程で実装でき、
光入出力端子部分に充填する樹脂材料の変更だけで通常
の実装方法が適用できる。また、光導波路１２が光配線
基板１１の表面に露出していないため、配線基板の洗浄
工程なども通常のＬＳＩ実装基板と同様の工程で扱うこ
とができ、洗浄液残差が多少あっても、光の焦点が基板
内部にあるためその影響は小さい。これはコンパクトデ
ィスク等の光ディスクがレコード等に比し取り扱い易く
なっている効果と同様の効果である。図４は、本発明の
光配線パッケージの他の例である。この実施例の特徴
は、図２の１０（半田バンプ）の代りに通常の接続半田
１０’を用いることと、光電変換素子能動部２００をパ
ッケージ基板３の貫通口に挿入し、その外形部を機械的
に貫通口に当てて位置合わせすることである。この例の
利点は、半田バンプ形成のためのパッシベーション膜や
数十μｍといった厚い半田の形成が不要となることであ
り、また、半田バンプのためのリフロー工程が不要とな
るため、材料費、加工費の低減と工程時間の短縮が可能
なことである。Next, other packages, electronic elements and the like are temporarily fixed, and the optical wiring board 11 is subjected to a solder reflow process to perform solder connection of electric terminals. This step is the same as that of general LSI mounting. As described above, the optical wiring device according to the embodiment of the present invention can be mounted in a process substantially the same as a general LSI mounting.
A normal mounting method can be applied only by changing the resin material filled in the optical input / output terminal portion. Further, since the optical waveguide 12 is not exposed on the surface of the optical wiring substrate 11, the cleaning process of the wiring substrate and the like can be handled in the same process as that of a normal LSI mounting substrate. The influence is small because the focal point of the light is inside the substrate. This is the same effect as that an optical disk such as a compact disk is easier to handle than a record or the like. FIG. 4 shows another example of the optical wiring package of the present invention. This embodiment is characterized in that ordinary connection solder 10 ′ is used instead of 10 (solder bump) in FIG. 2 and that the photoelectric conversion element active section 200 is inserted into the through hole of the package substrate 3, and its outer shape is removed. That is, positioning is performed by mechanically hitting the through hole. The advantage of this example is that a passivation film for forming a solder bump and the formation of a thick solder having a thickness of several tens of μm are not required, and a reflow process for the solder bump is not required. It is possible to reduce cost and process time.
【００１４】図２、図３の実施例にもちいる光半導体素
子の例を図５、図６に示す。図５は発光電変換素子（ア
レイ）、図６は受光電変換素子（アレイ）であり、図５
には発光電変換素子の例として垂直ＤＢＲ（Ｄｉｓｔｉ
ｂｕｔｅｄ Ｂｒａｇｇ Ｒｅｆｒｅｃｔｏｒ）型半導
体レーザ、図６には受光電変換素子の例としてｐｉｎ型
フォトダオード（ＰＩＮ−ＰＤ）を示している。図５の
２０１は半導体基板、２０２は下部積層ミラー、２０３
は活性層、２０４は上部積層ミラー、２０５はモード制
御部、２０６は表面パッシベーション、２０７は配線電
極（上部用）である。発振波長の例として０．７８μｍ
帯の場合、半導体基板２０１がＧａＡｓ、積層ミラー２
０２、２０４がＡｌＡｓとＡｌＧａＡｓのλ／４膜、活
性層２０３がＧａＡｌＡｓか所謂量子井戸としての薄膜
ＧａＡｓ、表面パッシベーション膜２０６はＳｉＯ２膜
やＳｉＮｘ膜等の誘電膜等を用いれば良い。モード制御
部２０５は例えばＧａＡｓを埋め込み成長し、高次横モ
ードや不要輻射光を除外する。この効果は、光端子の出
力光に高角度の迷光が混入しないようにすることであ
り、光配線基板の本来の光入出力部以外に入る光を抑制
し、クロストーク等の弊害を生じさせないようにするた
めのものである。FIGS. 5 and 6 show examples of optical semiconductor elements used in the embodiments shown in FIGS. 2 and 3. FIG. FIG. 5 shows a light emitting element (array), and FIG. 6 shows a light receiving element (array).
Has a vertical DBR (Disti) as an example of a light emitting element.
FIG. 6 shows a pin-type photodiode (PIN-PD) as an example of a photodetector device. 5. In FIG. 5, 201 is a semiconductor substrate, 202 is a lower laminated mirror, and 203 is
Is an active layer, 204 is an upper laminated mirror, 205 is a mode control unit, 206 is surface passivation, and 207 is a wiring electrode (for upper). 0.78 μm as an example of oscillation wavelength
In the case of a band, the semiconductor substrate 201 is made of GaAs,
02 and 204 may be λ / 4 films of AlAs and AlGaAs, the active layer 203 may be GaAlAs or a thin film GaAs as a so-called quantum well, and the surface passivation film 206 may be a dielectric film such as a SiO 2 film or a SiNx film. The mode control unit 205 buries and grows, for example, GaAs, and excludes higher-order transverse modes and unnecessary radiation. This effect is to prevent stray light at a high angle from being mixed into the output light of the optical terminal, and to suppress light that enters the optical wiring board other than the original optical input / output portion, and does not cause adverse effects such as crosstalk. That's what we do.
【００１５】図６の２０１は半導体基板、２０８は光吸
収層、２０９は上部ウィンドウ層、２１０は不純物拡散
領域である。上述の図５の例に合わせて、０．７８μｍ
帯の受光の場合、２０１が高キャリア濃度のＧａＡｓ、
２０８が低キャリア濃度のＧａＡｓ、２０９が高キャリ
ア濃度のＡｌＧａＡｓとし、２１０には半導体基板２０
１と逆の導伝型の不純物を熱拡散等で導入する。この素
子にｐｎ逆バイアスを印可すると、２０８の低キャリア
濃度層が空乏化して光吸収によるキャリアのドリフトを
生じる。この結果、高速の応答が可能になり、数ＧＨｚ
以上の高速応答が可能になる。尚、受光波長が０．７８
μｍ帯の場合、Ｓｉを用いることができ、同様のキャリ
ア濃度構造で全てＳｉを材料とすれば同等の機能が得ら
れる。図５、図６の発光電変換素子、受光電変換素子は
図に示すように能動部をメサ化加工し、配線電極２０７
によりメサ下部に電極を延長している。これにより、図
４のような機械的位置合わせの光配線パッケージにも適
用できるようになる。この様子を図７に斜視図で示す。
図７の２１１は接地電極であり、素子能動部２０４の配
線電極２０７とはずれた位置に形成している。In FIG. 6, 201 is a semiconductor substrate, 208 is a light absorption layer, 209 is an upper window layer, and 210 is an impurity diffusion region. 0.78 μm according to the example of FIG.
In the case of light reception in the band, 201 is GaAs having a high carrier concentration,
208 is GaAs having a low carrier concentration, 209 is AlGaAs having a high carrier concentration, and 210 is a semiconductor substrate 20.
A conductive impurity opposite to 1 is introduced by thermal diffusion or the like. When a pn reverse bias is applied to this element, the low carrier concentration layer 208 is depleted, causing a carrier drift due to light absorption. As a result, a high-speed response becomes possible, and several GHz
The above high-speed response is possible. The light receiving wavelength is 0.78
In the case of the μm band, Si can be used, and the same function can be obtained by using Si as the material with the same carrier concentration structure. 5 and 6, the active portion is formed into a mesa as shown in FIG.
The electrode is extended below the mesa. Thus, the present invention can be applied to an optical wiring package having mechanical alignment as shown in FIG. This is shown in a perspective view in FIG.
In FIG. 7, reference numeral 211 denotes a ground electrode, which is formed at a position separated from the wiring electrode 207 of the element active part 204.
【００１６】図１乃至図６においては接地電極について
特に触れていなかったが、これは基板２０１の下面から
一括して配線しても良いが、図７のように個別に設け、
パッケージ基板３上で配線電極２０７と同時に接続する
こともできる。その際、パッケージ配線が２０７から光
電変換素子のアレイ配列方向と垂直の方向に引き出され
るため、接地電極２１１はその空間を避けて設けてい
る。これにより、接地電極と信号電極間の浮遊容量を低
減することが可能である。尚、図５乃至図７の実施例
で、発光電変換素子は発光ダイオードでも良く、受光電
変換素子は金属半導体接触型素子でも良い。また、発光
波長等は用いる光配線装置の設計や用いる材料等により
変更可能であり、適宜変更、変形が可能である。図８は
本発明の光配線パッケージの他の実施例であり、図２、
図４で示した実施例の光配線端子の変形例である。この
実施例の特徴は、光端子１５がガラスや樹脂の透明ロッ
ドからなり、パッケージ基板３に集積素子や光電変換素
子１５を搭載する以前に光端子を形成しておけるという
ことにある。このため、図８の実施例では、パッケージ
工程が集積素子及び光電変換素子の搭載、透明樹脂９の
充填の後、即座に樹脂モールド工程に移る。従って、光
端子数に応じたレンズの装着工程が無く、一般のＬＳＩ
パッケージとほぼ同等の工程が適用でき、光配線パッケ
ージの工程が大幅に簡略化できる。Although the ground electrode is not particularly mentioned in FIGS. 1 to 6, it may be wired collectively from the lower surface of the substrate 201. However, as shown in FIG.
The connection can be made simultaneously with the wiring electrode 207 on the package substrate 3. At this time, since the package wiring is drawn out from 207 in the direction perpendicular to the array direction of the photoelectric conversion elements, the ground electrode 211 is provided so as to avoid the space. Thereby, the stray capacitance between the ground electrode and the signal electrode can be reduced. In the embodiments shown in FIGS. 5 to 7, the light-emitting element may be a light-emitting diode, and the light-receiving element may be a metal-semiconductor contact element. The emission wavelength and the like can be changed depending on the design of the optical wiring device to be used, the material to be used, and the like, and can be appropriately changed and modified. FIG. 8 shows another embodiment of the optical wiring package of the present invention.
9 is a modification of the optical wiring terminal of the embodiment shown in FIG. The feature of this embodiment is that the optical terminal 15 is made of a transparent rod made of glass or resin, and the optical terminal can be formed before the integrated element or the photoelectric conversion element 15 is mounted on the package substrate 3. For this reason, in the embodiment of FIG. 8, after the mounting of the integrated device and the photoelectric conversion device and the filling of the transparent resin 9, the package process immediately proceeds to the resin molding process. Therefore, there is no lens mounting process corresponding to the number of optical terminals, and a general LSI
A process almost equivalent to that of the package can be applied, and the process of the optical wiring package can be greatly simplified.
【００１７】図８の例では先球テーパーの光端子ロッド
を用いているが、これは先端が半球の物でも良い。先球
テーパーと半球の使い分けは、光学的な結合の設計や、
光配線基板との勘合設計により使い分ければ良いもので
ある。図９は、図８の実施例に用いる光電変換素子の例
であり、図７と異なる点は配線電極２０７が素子表面側
にあり、そのため接地電極２１１もダミーのメサ上に形
成して表面側に形成している点である。この場合、ダミ
ーメサのスペースが必要なため、配線電極２０７の引き
出し電極が接地電極２１１の基板面部分で交差するが、
メサの高さ分だけ空間的に離れているため、比較的浮遊
容量も小さくできる。尚、図８の実施例においても、図
７の光電変換素子を用いることができる。また図２、図
４の実施例に図９の光電変換素子を用いることができ
る。これらはパッケージ基板３及び光電変換素子の形状
の変更で対応可能である。また上記実施例では、光電変
換素子アレイ２と半導体集積回路を別に実装し電気的配
線にて接続したが、半導体光電変換素子を半導体集積回
路に集積化して用いてもよい。In the example shown in FIG. 8, a tapered optical terminal rod is used, but this may be a hemispherical tip. The choice between using a hemisphere taper and a hemisphere depends on the design of the optical coupling,
What is necessary is just to use properly by fitting design with an optical wiring board. FIG. 9 shows an example of the photoelectric conversion element used in the embodiment of FIG. 8. The difference from FIG. 7 is that the wiring electrode 207 is on the element surface side, so that the ground electrode 211 is also formed on the dummy mesa and This is the point that is formed. In this case, since a space for a dummy mesa is required, the extraction electrodes of the wiring electrodes 207 intersect at the substrate surface portion of the ground electrode 211.
Since they are spatially separated by the height of the mesa, the stray capacitance can be made relatively small. Note that the photoelectric conversion element shown in FIG. 7 can also be used in the embodiment shown in FIG. Further, the photoelectric conversion element shown in FIG. 9 can be used in the embodiments shown in FIGS. These can be dealt with by changing the shapes of the package substrate 3 and the photoelectric conversion element. In the above embodiment, the photoelectric conversion element array 2 and the semiconductor integrated circuit are separately mounted and connected by electric wiring. However, the semiconductor photoelectric conversion element may be integrated with the semiconductor integrated circuit and used.
【００１８】[0018]
【発明の効果】以上述べたように、本発明によれば一般
的な電子素子の実装手法により光配線が可能となり、実
装コストを大幅に上昇させることなく、ボードレベル、
ラックレベルで高速動作可能なシステムを安価に構築で
きるという効果を奏する。As described above, according to the present invention, optical wiring can be performed by a general electronic element mounting method, and the board level can be reduced without significantly increasing the mounting cost.
This has the effect that a system that can operate at high speed at the rack level can be constructed at low cost.
【図１】 本発明実施例の光配線パッケージの概略構成
図FIG. 1 is a schematic configuration diagram of an optical wiring package according to an embodiment of the present invention.
【図２】 本発明実施例の光配線パッケージの光端子部
分を示す構成図FIG. 2 is a configuration diagram showing an optical terminal portion of the optical wiring package according to the embodiment of the present invention;
【図３】 本発明実施例の光配線装置の実装状態を示す
構成図FIG. 3 is a configuration diagram showing a mounting state of the optical wiring device according to the embodiment of the present invention;
【図４】 本発明実施例の光配線パッケージの光端子部
分を示す構成図FIG. 4 is a configuration diagram showing an optical terminal portion of the optical wiring package according to the embodiment of the present invention;
【図５】 本発明実施例の光配線パッケージに用いる光
電変換素子を示す構成図FIG. 5 is a configuration diagram showing a photoelectric conversion element used for an optical wiring package according to an embodiment of the present invention.
【図６】 本発明実施例の光配線パッケージに用いる光
電変換素子を示す構成図FIG. 6 is a configuration diagram showing a photoelectric conversion element used for an optical wiring package according to an embodiment of the present invention.
【図７】 本発明実施例の光配線パッケージに用いる光
電変換素子を示す構成図FIG. 7 is a configuration diagram showing a photoelectric conversion element used for an optical wiring package according to an embodiment of the present invention.
【図８】 本発明実施例の光配線パッケージの光端子部
分を示す構成図FIG. 8 is a configuration diagram showing an optical terminal portion of the optical wiring package according to the embodiment of the present invention.
【図９】 本発明実施例の光配線パッケージに用いる光
電変換素子を示す構成図FIG. 9 is a configuration diagram showing a photoelectric conversion element used for an optical wiring package according to an embodiment of the present invention.
１ ＬＳＩチップ ２ 光半導体素子（アレイ） ３ パッケージ基板 ４ 内部配線 ５ ボンディングワイヤ ６ 電気端子 ７ モールド樹脂 ８ 球レンズ（光端子） ９ 透明樹脂 １０ 半田ボール １１ 光配線基板 １２ 光導波路 １３ 光入出力部（凹部） １４ 透明樹脂 １５ 透明ロッド（光端子） ２００ 光電変換素子能動部 ２０１ 半導体基板 ２０２ 下部ミラー ２０３ 活性層 ２０４ 上部ミラー ２０５ モード制御領域（不要光吸収領域） ２０６ パッシベーション膜 ２０７ 配線電極 ２０８ 光吸収層 ２０９ ウィンドウ層 ２１０ 不純物拡散領域 ２１１ 接地電極 DESCRIPTION OF SYMBOLS 1 LSI chip 2 Optical semiconductor element (array) 3 Package board 4 Internal wiring 5 Bonding wire 6 Electric terminal 7 Mold resin 8 Ball lens (optical terminal) 9 Transparent resin 10 Solder ball 11 Optical wiring board 12 Optical waveguide 13 Optical input / output part (Concave part) 14 Transparent resin 15 Transparent rod (optical terminal) 200 Active part of photoelectric conversion element 201 Semiconductor substrate 202 Lower mirror 203 Active layer 204 Upper mirror 205 Mode control region (unnecessary light absorption region) 206 Passivation film 207 Wiring electrode 208 Light absorption Layer 209 Window layer 210 Impurity diffusion region 211 Ground electrode
フロントページの続き Ｆターム(参考） 2H037 AA01 BA03 BA12 CA14 DA03 DA05 DA06 5F049 MA03 MA04 MB02 MB07 NA20 NB10 QA02 RA02 SS04 TA12 WA01 5F073 AA65 AB02 AB15 AB17 AB21 AB25 AB27 CA05 FA08 FA22 FA23 FA29 FA30 Continued on the front page F-term (reference) 2H037 AA01 BA03 BA12 CA14 DA03 DA05 DA06 5F049 MA03 MA04 MB02 MB07 NA20 NB10 QA02 RA02 SS04 TA12 WA01 5F073 AA65 AB02 AB15 AB17 AB21 AB25 AB27 CA05 FA08 FA22 FA23 FA29 FA30
Claims (7)
と、前記基板上に設けられ、前記集積回路と電気信号の
やり取りをする光電変換素子と、前記基板の一部に設け
られた貫通孔と、この貫通孔に配置され、前記光電変換
素子と対向する曲面を有する光端子とを具備し、前記集
積回路への入力は、前記光端子を介して前記光電変換素
子へ光信号を入力し、前記光電変換素子が前記光信号を
電気信号に変換し、この電気信号を前記集積回路に入力
することによって行われることを特徴とする光配線装
置。A substrate, an integrated circuit disposed on the substrate, a photoelectric conversion element provided on the substrate for exchanging electric signals with the integrated circuit, and provided on a part of the substrate. A through-hole and an optical terminal disposed in the through-hole and having a curved surface facing the photoelectric conversion element, wherein an input to the integrated circuit transmits an optical signal to the photoelectric conversion element via the optical terminal. An optical wiring device, wherein the input is performed, the photoelectric conversion element converts the optical signal into an electric signal, and the electric signal is input to the integrated circuit.
と、前記基板上に設けられ、前記集積回路と電気信号の
やり取りをする光電変換素子と、前記基板の一部に設け
られた貫通孔と、この貫通孔に配置され、前記光電変換
素子と対向する曲面を有する光端子とを具備し、前記集
積回路からの出力は、前記集積回路から電気信号を前記
光電変換素子へ出力し、この電気信号により前記光電変
換素子が光信号に変換し、この光信号を前記光端子を介
して出力することによって行われることを特徴とする光
配線装置。2. A substrate, an integrated circuit disposed on the substrate, a photoelectric conversion element provided on the substrate for exchanging electric signals with the integrated circuit, and a part provided on the substrate. A through-hole, an optical terminal disposed in the through-hole and having a curved surface facing the photoelectric conversion element, wherein an output from the integrated circuit outputs an electric signal from the integrated circuit to the photoelectric conversion element. The optical wiring device is performed by converting the electric signal into an optical signal by the photoelectric conversion element and outputting the optical signal through the optical terminal.
有し、この傾斜側面によって前記光端子が位置決めされ
ることを特徴とする請求項１或いは請求項２記載の光配
線装置。3. The optical wiring device according to claim 1, wherein the through hole provided in the substrate has an inclined side surface, and the optical terminal is positioned by the inclined side surface.
に対向配置された集積回路と、前記基板上に設けられ、
前記集積回路と電気信号のやり取りをする光電変換素子
と、前記パッケージ基板の一部に設けられた貫通孔と、
この貫通孔に配置され、前記光電変換素子と対向する曲
面を有する光端子と、前記光端子を介し前記パッケージ
基板と対向配置された光配線基板とを具備し、前記集積
回路への入力は、前記光端子を介して前記光電変換素子
へ光信号を入力し、前記光電変換素子が前記光信号を電
気信号に変換し、この電気信号を前記集積回路に入力す
ることによって行われることを特徴とする光配線装置。4. A package substrate, an integrated circuit facing the package substrate, and an integrated circuit provided on the substrate,
A photoelectric conversion element that exchanges an electric signal with the integrated circuit, and a through hole provided in a part of the package substrate,
An optical terminal disposed in the through-hole and having a curved surface facing the photoelectric conversion element, and an optical wiring substrate disposed facing the package substrate via the optical terminal, wherein an input to the integrated circuit is: An optical signal is input to the photoelectric conversion element through the optical terminal, the photoelectric conversion element converts the optical signal into an electric signal, and the electric signal is input to the integrated circuit. Optical wiring equipment.
に対向配置された集積回路と、前記基板上に設けられ、
前記集積回路と電気信号のやり取りをする光電変換素子
と、前記パッケージ基板の一部に設けられた貫通孔と、
この貫通孔に配置され、前記光電変換素子と対向する曲
面を有する光端子と、前記光端子を介し前記パッケージ
基板と対向配置された光配線基板とを具備し、前記集積
回路からの出力は、前記集積回路から電気信号を前記光
電変換素子へ出力し、この電気信号により前記光電変換
素子が光信号に変換し、この光信号を前記光端子を介し
て出力することによって行われることを特徴とする光配
線装置。5. A package substrate, an integrated circuit facing the package substrate, and an integrated circuit provided on the substrate,
A photoelectric conversion element that exchanges an electric signal with the integrated circuit, and a through hole provided in a part of the package substrate,
An optical terminal having a curved surface facing the photoelectric conversion element, the optical terminal being disposed in the through-hole and facing the package substrate via the optical terminal, wherein an output from the integrated circuit is: Outputting an electric signal from the integrated circuit to the photoelectric conversion element, converting the electric signal into an optical signal by the electric signal, and outputting the optical signal through the optical terminal, is performed. Optical wiring equipment.
傾斜側面を有し、前記光配線基板の前記光結合された部
分は傾斜側面を持った凹部が設けられ、これらの傾斜側
面によって前記光端子、前記光導波路、前記光電変換素
子が光結合するように位置決めされることを特徴とする
請求項４或いは請求項５記載の光配線装置。6. A through hole provided in the package substrate has an inclined side surface, and the optically coupled portion of the optical wiring board is provided with a concave portion having an inclined side surface. 6. The optical wiring device according to claim 4, wherein the terminal, the optical waveguide, and the photoelectric conversion element are positioned so as to be optically coupled.
面より深い位置とし、この位置に前記光導波路を位置さ
せることによって、前記光導波路を前記光配線基板の表
面に露出させないことを特徴とする請求項４或いは請求
項５光配線装置。7. An optical imaging position by the optical terminal is set to a position deeper than the bottom surface of the concave portion, and the optical waveguide is located at this position, so that the optical waveguide is not exposed to the surface of the optical wiring board. The optical wiring device according to claim 4 or 5, wherein
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18274199A JP3612243B2 (en) | 1999-06-29 | 1999-06-29 | Optical wiring package and optical wiring device |
| US09/603,896 US6516104B1 (en) | 1999-06-25 | 2000-06-26 | Optical wiring device |
| US10/305,135 US6760500B2 (en) | 1999-06-25 | 2002-11-27 | Optical wiring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18274199A JP3612243B2 (en) | 1999-06-29 | 1999-06-29 | Optical wiring package and optical wiring device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001013377A true JP2001013377A (en) | 2001-01-19 |
| JP3612243B2 JP3612243B2 (en) | 2005-01-19 |
Family
ID=16123633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18274199A Expired - Fee Related JP3612243B2 (en) | 1999-06-25 | 1999-06-29 | Optical wiring package and optical wiring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3612243B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003298167A (en) * | 2002-03-29 | 2003-10-17 | Toshiba Corp | Optical semiconductor device |
| WO2004061506A1 (en) * | 2002-12-30 | 2004-07-22 | General Electric Company | Integrated micro optical bench with flexible dielectric subtrate |
| JP2006259730A (en) * | 2005-03-15 | 2006-09-28 | Fujitsu Ltd | Apparatus and method for coupling optical element |
| US7187702B2 (en) | 2002-09-25 | 2007-03-06 | Seiko Epson Corporation | Surface-emitting light emitting device, manufacturing method for the same, optical module, and optical transmission apparatus |
| JP2009163178A (en) * | 2008-01-10 | 2009-07-23 | Hitachi Cable Ltd | Junction structure between optical element and substrate, optical transmission and reception module, and method of manufacturing optical module |
| JP2011529205A (en) * | 2008-07-22 | 2011-12-01 | ナショナル セミコンダクタ コーポレイション | Mold optical package with fiber coupling |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008158440A (en) | 2006-12-26 | 2008-07-10 | Toshiba Corp | Photoelectric wiring board and method of manufacturing photoelectric wiring apparatus |
-
1999
- 1999-06-29 JP JP18274199A patent/JP3612243B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003298167A (en) * | 2002-03-29 | 2003-10-17 | Toshiba Corp | Optical semiconductor device |
| US7187702B2 (en) | 2002-09-25 | 2007-03-06 | Seiko Epson Corporation | Surface-emitting light emitting device, manufacturing method for the same, optical module, and optical transmission apparatus |
| WO2004061506A1 (en) * | 2002-12-30 | 2004-07-22 | General Electric Company | Integrated micro optical bench with flexible dielectric subtrate |
| US7327022B2 (en) | 2002-12-30 | 2008-02-05 | General Electric Company | Assembly, contact and coupling interconnection for optoelectronics |
| CN100409053C (en) * | 2002-12-30 | 2008-08-06 | 通用电气公司 | Assembly, contact and coupling interconnection for optoelectronics |
| JP2006259730A (en) * | 2005-03-15 | 2006-09-28 | Fujitsu Ltd | Apparatus and method for coupling optical element |
| JP2009163178A (en) * | 2008-01-10 | 2009-07-23 | Hitachi Cable Ltd | Junction structure between optical element and substrate, optical transmission and reception module, and method of manufacturing optical module |
| JP2011529205A (en) * | 2008-07-22 | 2011-12-01 | ナショナル セミコンダクタ コーポレイション | Mold optical package with fiber coupling |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3612243B2 (en) | 2005-01-19 |
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