JP2003249417A - Capacitor structure and manufacturing method of the same - Google Patents
Capacitor structure and manufacturing method of the sameInfo
- Publication number
- JP2003249417A JP2003249417A JP2002047958A JP2002047958A JP2003249417A JP 2003249417 A JP2003249417 A JP 2003249417A JP 2002047958 A JP2002047958 A JP 2002047958A JP 2002047958 A JP2002047958 A JP 2002047958A JP 2003249417 A JP2003249417 A JP 2003249417A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- thin film
- columnar
- several
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、コンデンサ構造体
およびその製造方法に係り、特に小型で大容量のコンデ
ンサ構造体およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor structure and a manufacturing method thereof, and more particularly to a small-sized and large-capacity capacitor structure and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来の薄膜コンデンサとしては、誘電体
薄膜として、ＢＳＴ（Ｂａ，Ｓｒ，Ｔｉ）系またはＰＭ
Ｎ（Ｐｂ，Ｍａ，Ｎｂ）系の単層の誘電体薄膜を用いた
薄膜コンデンサが知られている。この種の薄膜コンデン
サでは、誘電体の薄膜化により低誘電率化が進み、期待
されるほどには、大容量化が困難である。また、誘電体
薄膜の全体的な表面積が小さいことも、大容量化のネッ
クになっている。2. Description of the Related Art As a conventional thin film capacitor, a BST (Ba, Sr, Ti) system or PM is used as a dielectric thin film.
A thin film capacitor using an N (Pb, Ma, Nb) -based single-layer dielectric thin film is known. In this type of thin film capacitor, the dielectric constant has been reduced by thinning the dielectric material, and it has been difficult to increase the capacitance as expected. In addition, the fact that the overall surface area of the dielectric thin film is small is also a bottleneck for increasing the capacity.
【０００３】コンデンサの容量を大容量化させるための
手段として、特開平５−３３５１７２号公報に示すよう
に、導電体電極とＣＶＤ法により形成される誘電体層と
を交互に積層した薄膜積層コンデンサが提案されてい
る。As a means for increasing the capacity of a capacitor, as shown in Japanese Patent Laid-Open No. 335172/1993, a thin film multilayer capacitor in which conductor electrodes and dielectric layers formed by a CVD method are alternately laminated. Is proposed.
【０００４】しかしながら、この公報に示す薄膜積層コ
ンデンサでは、その製造に際して、マスクの位置合わせ
精度が要求され、生産効率が低いという課題を有する。
また、表面性の問題から、積層数にも限界があり、期待
されるほどには、大容量化が困難であるという課題も有
する。However, the thin film multilayer capacitor disclosed in this publication has a problem that the mask alignment accuracy is required in the manufacturing thereof and the production efficiency is low.
Further, due to the problem of surface properties, there is a limit to the number of layers that can be stacked, and it is difficult to increase the capacity as expected.
【０００５】また、特開平９−４５５７７号公報に示す
ように、基板の平面をエッチングすることにより、同一
平面内に櫛形電極を形成し、その櫛形電極の表面に誘電
体膜をＣＶＤなどの薄膜形成法により形成した垂直型薄
膜コンデンサも提案されている。Further, as disclosed in Japanese Patent Laid-Open No. 9-45577, by etching the plane of the substrate, a comb-shaped electrode is formed in the same plane, and a dielectric film is formed on the surface of the comb-shaped electrode by a thin film such as CVD. A vertical thin film capacitor formed by the forming method has also been proposed.
【０００６】しかしながら、この公報に示すコンデンサ
では、その製造に際して、通常のレジストマスクを用い
るフォトリソグラフィ法を利用して櫛形電極を形成する
ために、その微細化には限界があり、期待されるほどに
は、大容量化が困難であるという課題を有する。However, in the capacitor disclosed in this publication, the comb-shaped electrodes are formed by utilizing the photolithography method using a normal resist mask at the time of manufacturing, and therefore there is a limit to miniaturization, and as expected, Has a problem that it is difficult to increase the capacity.
【０００７】なお、特開平１１−２９７６２５号公報に
示すように、Ａｌ基板を陽極酸化して得られる多孔質ア
ルミナ基板をマスクとして用いて、半導体量子ドットを
形成する方法が提案されている。しかしながら、この方
法は、半導体量子ドットを形成するための方法であり、
薄膜コンデンサを製造するためのものではなかった。As disclosed in Japanese Patent Application Laid-Open No. 11-297625, a method of forming semiconductor quantum dots using a porous alumina substrate obtained by anodizing an Al substrate as a mask has been proposed. However, this method is a method for forming semiconductor quantum dots,
It was not for manufacturing thin film capacitors.
【０００８】[0008]
【発明が解決しようとする課題】本発明は、このような
実状に鑑みてなされ、その目的とするところは、特に小
型で大容量のコンデンサ構造体およびその製造方法を提
供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a particularly small-sized and large-capacity capacitor structure and a manufacturing method thereof. .
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明の第１の観点に係るコンデンサ構造体の製造
方法は、細孔形成用基板を陽極酸化して、それぞれの内
径が数ｎｍから数百ｎｍの多数の柱状細孔が規則的に配
列された多孔質基板を形成する工程と、前記多孔質基板
をマスクとして用いて薄膜成膜処理を行い、コンデンサ
用基板の表面に、それぞれの外径が数ｎｍから数百ｎｍ
の多数の柱状体が規則的に配列された第１電極を形成す
る工程と、前記柱状体の外側を覆うように、前記第１電
極の表面に、誘電体薄膜を形成する工程と、前記柱状体
の外側を覆うように、前記誘電体薄膜の表面に第２電極
を形成する工程とを有する。本発明の第１の観点に係る
コンデンサ構造体の製造方法において、前記第２電極の
表面にも、同様にして、それぞれの外径が数ｎｍから数
百ｎｍの多数の柱状体を規則的に形成し、コンデンサ構
造体を、二層以上の積層構造にしても良い。すなわち、
本発明の第１の観点に係る積層型コンデンサ構造体の製
造方法は、細孔形成用基板を陽極酸化して、それぞれの
内径が数ｎｍから数百ｎｍの多数の柱状細孔が規則的に
配列された多孔質基板を形成する工程と、前記多孔質基
板をマスクとして用いて薄膜成膜処理を行い、コンデン
サ用基板の表面に、それぞれの外径が数ｎｍから数百ｎ
ｍの多数の第１柱状体が規則的に配列された第１電極を
形成する工程と、前記第１柱状体の外側を覆うように、
前記第１電極の表面に、第１誘電体薄膜を形成する工程
と、前記第１柱状体の外側を覆うように、前記第１誘電
体薄膜の表面に第２電極を形成する工程と、前記多孔質
基板をマスクとして用いて薄膜成膜処理を行い、前記第
２電極の表面に、それぞれの外径が数ｎｍから数百ｎｍ
の多数の第２柱状体を規則的に形成する工程と、前記第
２柱状体の外側を覆うように、前記第２電極の表面に、
第２誘電体薄膜を形成する工程と、前記第２柱状体の外
側を覆うように、前記第２誘電体薄膜の表面に第３電極
を形成する工程と、を有する。In order to achieve the above object, in the method of manufacturing a capacitor structure according to the first aspect of the present invention, the pore forming substrate is anodized so that the inner diameter of each of them is several. a step of forming a porous substrate in which a large number of columnar pores of nm to several hundreds nm are regularly arranged, and a thin film forming process using the porous substrate as a mask, on the surface of the capacitor substrate, Each outer diameter is from a few nm to a few hundred nm
A step of forming a first electrode in which a large number of columnar bodies are regularly arranged, a step of forming a dielectric thin film on the surface of the first electrode so as to cover the outside of the columnar body, Forming a second electrode on the surface of the dielectric thin film so as to cover the outside of the body. In the method for manufacturing a capacitor structure according to the first aspect of the present invention, a large number of columnar bodies each having an outer diameter of several nm to several hundred nm are regularly formed on the surface of the second electrode in the same manner. The capacitor structure may be formed to have a laminated structure of two or more layers. That is,
A method of manufacturing a multilayer capacitor structure according to a first aspect of the present invention is characterized in that a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regularly formed by anodizing a pore-forming substrate. A step of forming an array of porous substrates and a thin film forming process using the porous substrate as a mask are performed, and the outer diameter of each film is several nm to several hundreds n on the surface of the capacitor substrate.
a step of forming a first electrode in which a large number of m first columnar bodies are regularly arranged, and so as to cover the outside of the first columnar bodies,
Forming a first dielectric thin film on the surface of the first electrode; forming a second electrode on the surface of the first dielectric thin film so as to cover the outside of the first columnar body; A thin film deposition process is performed using the porous substrate as a mask, and the outer diameter of each of the second electrodes is several nm to several hundreds nm.
Regularly forming a large number of the second columnar bodies, and on the surface of the second electrode so as to cover the outside of the second columnar bodies,
The method includes a step of forming a second dielectric thin film, and a step of forming a third electrode on the surface of the second dielectric thin film so as to cover the outside of the second columnar body.
【００１０】本発明の第１の観点に係るコンデンサ構造
体は、細孔形成用基板を陽極酸化して、それぞれの内径
が数ｎｍから数百ｎｍの多数の柱状細孔が規則的に配列
された多孔質基板をマスクとして用いて薄膜成膜処理を
行い、コンデンサ用基板の表面に、それぞれの外径が数
ｎｍから数百ｎｍの多数の柱状体が規則的に形成された
第１電極と、前記柱状体の外側を覆うように、前記第１
電極の表面に形成された誘電体薄膜と、前記柱状体の外
側を覆うように、前記誘電体薄膜の表面に形成された第
２電極と、を有する。本発明の第１の観点に係るコンデ
ンサ構造体において、前記第２電極の表面にも、同様に
して、それぞれの外径が数ｎｍから数百ｎｍの多数の柱
状体を規則的に形成し、コンデンサ構造体を、二層以上
の積層構造にしても良い。すなわち、本発明の第１の観
点に係る積層型コンデンサ構造体は、細孔形成用基板を
陽極酸化して、それぞれの内径が数ｎｍから数百ｎｍの
多数の柱状細孔が規則的に配列された多孔質基板をマス
クとして用いて薄膜成膜処理を行い、コンデンサ用基板
の表面に、それぞれの外径が数ｎｍから数百ｎｍの多数
の第１柱状体が規則的に形成された第１電極と、前記第
１柱状体の外側を覆うように、前記第１電極の表面に形
成された第１誘電体薄膜と、前記第１柱状体の外側を覆
うように、前記第１誘電体薄膜の表面に形成された第２
電極と、前記多孔質基板をマスクとして用いて薄膜成膜
処理を行い、前記第２電極の表面に規則的に形成され、
それぞれの外径が数ｎｍから数百ｎｍの多数の第２柱状
体と、前記第２柱状体の外側を覆うように、前記第２電
極の表面に形成された第２誘電体薄膜と、前記第２柱状
体の外側を覆うように、前記第２誘電体薄膜の表面に形
成された第３電極と、を有する。本発明の第１の観点に
係るコンデンサは、上記のコンデンサ構造体を有する。In the capacitor structure according to the first aspect of the present invention, the substrate for forming pores is anodized, and a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regularly arranged. A thin film forming process is performed using the porous substrate as a mask, and a large number of columnar bodies each having an outer diameter of several nm to several hundreds nm are regularly formed on the surface of the capacitor substrate and a first electrode. , The first so as to cover the outside of the columnar body.
A dielectric thin film formed on the surface of the electrode, and a second electrode formed on the surface of the dielectric thin film so as to cover the outside of the columnar body. In the capacitor structure according to the first aspect of the present invention, a large number of columnar bodies each having an outer diameter of several nm to several hundreds nm are regularly formed on the surface of the second electrode in the same manner. The capacitor structure may have a laminated structure of two or more layers. That is, in the multilayer capacitor structure according to the first aspect of the present invention, a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly arranged by anodizing the pore-forming substrate. A thin film deposition process is performed using the formed porous substrate as a mask, and a large number of first columnar bodies each having an outer diameter of several nm to several hundreds nm are regularly formed on the surface of the capacitor substrate. One electrode, a first dielectric thin film formed on the surface of the first electrode so as to cover the outer side of the first columnar body, and the first dielectric body so as to cover the outer side of the first columnar body. The second formed on the surface of the thin film
A thin film deposition process is performed using an electrode and the porous substrate as a mask to form a regular film on the surface of the second electrode,
A plurality of second columnar bodies each having an outer diameter of several nm to several hundred nm, a second dielectric thin film formed on the surface of the second electrode so as to cover the outside of the second columnar body, and A third electrode formed on the surface of the second dielectric thin film so as to cover the outside of the second columnar body. A capacitor according to a first aspect of the present invention has the above capacitor structure.
【００１１】本発明の第２の観点に係るコンデンサ構造
体の製造方法は、細孔形成用基板を陽極酸化して、それ
ぞれの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規
則的に配列された多孔質基板を形成する工程と、前記多
孔質基板をマスクとして用いてエッチング処理を行い、
コンデンサ用基板の表面に、それぞれの外径が数ｎｍか
ら数百ｎｍの多数の柱状細孔が規則的に配列された第１
電極を形成する工程と、前記柱状細孔の内部に入り込む
ように、前記第１電極の表面に、誘電体薄膜を形成する
工程と、前記柱状細孔の内部に入り込むように、前記誘
電体薄膜の表面に、第２電極を形成する工程とを有す
る。本発明の第２の観点に係るコンデンサ構造体の製造
方法において、前記第２電極の表面にも、同様にして、
それぞれの外径が数ｎｍから数百ｎｍの多数の柱状細孔
を規則的に形成し、コンデンサ構造体を、二層以上の積
層構造にしても良い。すなわち、本発明の第２の観点に
係る積層型コンデンサ構造体の製造方法は、細孔形成用
基板を陽極酸化して、それぞれの内径が数ｎｍから数百
ｎｍの多数の柱状細孔が規則的に配列された多孔質基板
を形成する工程と、前記多孔質基板をマスクとして用い
てエッチング処理を行い、コンデンサ用基板の表面に、
それぞれの外径が数ｎｍから数百ｎｍの多数の第１柱状
細孔が規則的に配列された第１電極を形成する工程と、
前記第１柱状細孔の内部に入り込むように、前記第１電
極の表面に、第１誘電体薄膜を形成する工程と、前記第
１柱状細孔の内部に入り込むように、前記第１誘電体薄
膜の表面に、第２電極を形成する工程と、前記多孔質基
板をマスクとして用いてエッチング処理を行い、前記第
２電極の表面に、それぞれの外径が数ｎｍから数百ｎｍ
の多数の第２柱状細孔を規則的に形成する工程と、前記
第２柱状細孔の内部に入り込むように、前記第２電極の
表面に、第２誘電体薄膜を形成する工程と、前記第２柱
状細孔の内部に入り込むように、前記第２誘電体薄膜の
表面に、第３電極を形成する工程と、を有する。In the method for manufacturing a capacitor structure according to the second aspect of the present invention, the pore-forming substrate is anodized so that a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regular. A step of forming a porous substrate arranged in, and performing an etching process using the porous substrate as a mask,
A large number of columnar pores each having an outer diameter of several nm to several hundred nm are regularly arranged on the surface of the capacitor substrate.
A step of forming an electrode, a step of forming a dielectric thin film on the surface of the first electrode so as to enter the inside of the columnar pore, and a step of forming the dielectric thin film so as to enter the inside of the columnar pore. Forming a second electrode on the surface of the. In the method of manufacturing a capacitor structure according to the second aspect of the present invention, the surface of the second electrode is also similarly treated as follows.
A large number of columnar pores each having an outer diameter of several nm to several hundreds nm may be regularly formed, and the capacitor structure may have a laminated structure of two or more layers. That is, in the method of manufacturing a multilayer capacitor structure according to the second aspect of the present invention, a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly formed by anodizing the pore-forming substrate. A step of forming a porous substrate arranged in a linear manner, an etching process using the porous substrate as a mask, on the surface of the capacitor substrate,
A step of forming a first electrode in which a large number of first columnar pores each having an outer diameter of several nm to several hundred nm are regularly arranged;
Forming a first dielectric thin film on the surface of the first electrode so as to enter the inside of the first columnar pore; and the first dielectric so as to enter the inside of the first columnar pore. A step of forming a second electrode on the surface of the thin film, and an etching process using the porous substrate as a mask, the outer diameter of each of which is several nm to several hundred nm on the surface of the second electrode.
Forming a large number of second columnar pores regularly, forming a second dielectric thin film on the surface of the second electrode so as to enter the inside of the second columnar pores, And a step of forming a third electrode on the surface of the second dielectric thin film so as to enter the inside of the second columnar pore.
【００１２】本発明の第２の観点に係るコンデンサ構造
体は、細孔形成用基板を陽極酸化して、それぞれの内径
が数ｎｍから数百ｎｍの多数の柱状細孔が規則的に配列
された多孔質基板をマスクとして用いてエッチング処理
を行い、コンデンサ用基板の表面に、それぞれの内径が
数ｎｍから数百ｎｍの多数の柱状細孔が規則的に形成さ
れた第１電極と、前記柱状細孔の内部に入り込むよう
に、前記第１電極の表面に形成された誘電体薄膜と、前
記柱状細孔の内部に入り込むように、前記誘電体薄膜の
表面に形成された第２電極と、を有する。本発明の第２
の観点に係るコンデンサ構造体の製造方法において、前
記第２電極の表面にも、同様にして、それぞれの外径が
数ｎｍから数百ｎｍの多数の柱状細孔を規則的に形成
し、コンデンサ構造体を、二層以上の積層構造にしても
良い。すなわち、本発明の第２の観点に係る積層型コン
デンサ構造体は、細孔形成用基板を陽極酸化して、それ
ぞれの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規
則的に配列された多孔質基板をマスクとして用いてエッ
チング処理を行い、コンデンサ用基板の表面に、それぞ
れの内径が数ｎｍから数百ｎｍの多数の第１柱状細孔が
規則的に形成された第１電極と、前記第１柱状細孔の内
部に入り込むように、前記第１電極の表面に形成された
第１誘電体薄膜と、前記第１柱状細孔の内部に入り込む
ように、前記第１誘電体薄膜の表面に形成された第２電
極と、前記多孔質基板をマスクとして用いてエッチング
処理を行い、前記第２電極の表面に規則的に形成され、
それぞれの内径が数ｎｍから数百ｎｍの多数の第２柱状
細孔と、前記第２柱状細孔の内部に入り込むように、前
記第２電極の表面に形成された第２誘電体薄膜と、前記
第２柱状細孔の内部に入り込むように、前記第２誘電体
薄膜の表面に形成された第３電極と、を有する。本発明
の第２の観点に係るコンデンサは、上記のコンデンサ構
造体を有する。なお、本発明では、本発明の第１の観点
に係るコンデンサ構造体と第２の観点に係るコンデンサ
構造体とを組み合わせて積層構造にしても良い。In the capacitor structure according to the second aspect of the present invention, the pore-forming substrate is anodized, and a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regularly arranged. The first electrode in which a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly formed on the surface of the capacitor substrate is etched using the porous substrate as a mask, A dielectric thin film formed on the surface of the first electrode so as to enter the columnar pores; and a second electrode formed on the surface of the dielectric thin film so as to enter the columnar pores. With. Second of the present invention
In the method for manufacturing a capacitor structure according to the above aspect, a large number of columnar pores each having an outer diameter of several nm to several hundreds nm are regularly formed on the surface of the second electrode in the same manner to form a capacitor. The structure may have a laminated structure of two or more layers. That is, in the multilayer capacitor structure according to the second aspect of the present invention, a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly arranged by anodizing the pore-forming substrate. Electrode is etched using the formed porous substrate as a mask, and a large number of first columnar pores each having an inner diameter of several nm to several hundred nm are regularly formed on the surface of the capacitor substrate. A first dielectric thin film formed on the surface of the first electrode so as to enter the inside of the first columnar pore, and the first dielectric thin film so as to enter the inside of the first columnar pore. The second electrode formed on the surface of the thin film and the porous substrate are used as a mask to perform an etching process, and are regularly formed on the surface of the second electrode,
A large number of second columnar pores each having an inner diameter of several nm to several hundred nm, and a second dielectric thin film formed on the surface of the second electrode so as to enter the inside of the second columnar pores, A third electrode formed on the surface of the second dielectric thin film so as to enter the inside of the second columnar pore. A capacitor according to a second aspect of the present invention has the above capacitor structure. In the present invention, the laminated structure may be formed by combining the capacitor structure according to the first aspect of the present invention and the capacitor structure according to the second aspect.
【００１３】本発明に係るコンデンサ構造体の製造方法
では、アルミニウム（Ａｌ）基板などの細孔形成用基板
をシュウ酸などの二塩基酸中で陽極酸化する際に基板の
表面に得られる規則的な数ｎｍから数百ｎｍの柱状孔を
持つ多孔質基板層を利用している。なお、多孔質基板層
における柱状孔の内径は、陽極酸化の際の電流および電
圧を制御することで制御される。In the method of manufacturing the capacitor structure according to the present invention, the regular surface obtained on the surface of the substrate when anodizing a substrate for forming pores such as an aluminum (Al) substrate in a dibasic acid such as oxalic acid. A porous substrate layer having columnar pores of several nm to several hundreds nm is used. The inner diameter of the columnar holes in the porous substrate layer is controlled by controlling the current and voltage during anodic oxidation.
【００１４】本発明では、このようにして得られる多孔
質基板をマスクとして、薄膜成膜処理（あるいはエッチ
ング処理）を行い、コンデンサ用基板の表面に、それぞ
れの外径（または内径）が数ｎｍから数百ｎｍの多数の
柱状体（または柱状孔）が規則的に配列された第１電極
を形成する。In the present invention, a thin film forming process (or etching process) is performed using the thus obtained porous substrate as a mask, and the outer diameter (or inner diameter) of each is several nm on the surface of the capacitor substrate. To form a first electrode in which a large number of columnar bodies (or columnar holes) of several hundred nm are regularly arranged.
【００１５】これらの柱状体の外側を覆う（または柱状
細孔の内部に入り込む）ように、第１電極の表面に、誘
電体薄膜を形成し、これらの柱状体の外側を覆う（また
は柱状細孔の内部に入り込む）ように、誘電体薄膜の表
面に第２電極を形成する。A dielectric thin film is formed on the surface of the first electrode so as to cover the outer side of these columnar bodies (or enter the inside of the columnar pores), and cover the outer side of these columnar bodies (or the columnar fine pores). A second electrode is formed on the surface of the dielectric thin film so as to enter the inside of the hole).
【００１６】その結果、第１電極と第２電極とが、誘電
体薄膜を介して対峙することになり、コンデンサ構造体
が得られる。このコンデンサ構造体は、チップ状コンデ
ンサとして用いることができると共に、たとえば集積回
路のキャパシタ素子などとしても利用することができ
る。As a result, the first electrode and the second electrode face each other via the dielectric thin film, and a capacitor structure is obtained. This capacitor structure can be used not only as a chip-shaped capacitor but also as, for example, a capacitor element of an integrated circuit.
【００１７】このようにして得られたコンデンサ構造体
では、第１電極の表面に、数ｎｍから数百ｎｍの多数の
柱状体（または柱状細孔）が規則的に形成してあること
から、その上に形成される誘電体薄膜の表面積が増大
し、静電容量が飛躍的に増大し、小型で大容量のコンデ
ンサ構造体を実現することができる。たとえば柱状体
（または柱状細孔）が何ら形成されていない従来のコン
デンサ構造体に比較して、本発明のコンデンサ構造体
は、静電容量が２桁以上増大する。In the thus obtained capacitor structure, a large number of columnar bodies (or columnar pores) of several nm to several hundred nm are regularly formed on the surface of the first electrode, The surface area of the dielectric thin film formed thereon is increased, the electrostatic capacitance is dramatically increased, and a compact and large-capacity capacitor structure can be realized. For example, the capacitance of the capacitor structure of the present invention is increased by two digits or more as compared with the conventional capacitor structure in which no columnar body (or columnar pore) is formed.
【００１８】なお、多数の柱状体（または柱状細孔）が
規則的に形成してあることが好ましいのは、不規則であ
ると、隣接する柱状体（または柱状細孔）が接触してし
まい、誘電体薄膜の表面積の増大効果が減少するからで
ある。It is preferable that a large number of columnar bodies (or columnar pores) are regularly formed. If the columnar bodies are irregular, adjacent columnar bodies (or columnar pores) come into contact with each other. This is because the effect of increasing the surface area of the dielectric thin film decreases.
【００１９】隣接する柱状体（または柱状細孔）の配置
ピッチは、特に限定されないが、数ｎｍ〜数百ｎｍであ
り、各柱状体（または柱状細孔）の高さ（または深さ）
は、特に限定されないが、好ましくは１ｎｍ〜数μｍ、
さらに好ましくは１０ｎｍ〜１μｍである。これらの高
さ（または深さ）は、高い（または深い）程、静電容量
の増大に効果があるが、製造が困難になる傾向にある。The arrangement pitch of adjacent columnar bodies (or columnar pores) is not particularly limited, but is several nm to several hundred nm, and the height (or depth) of each columnar body (or columnar pore).
Is not particularly limited, but is preferably 1 nm to several μm,
More preferably, it is 10 nm to 1 μm. The higher (or deeper) these heights (or depths) are, the more effective they are in increasing the capacitance, but they tend to be difficult to manufacture.
【００２０】本発明において、好ましくは、前記誘電体
薄膜を、化学気相析出（ＣＶＤ）法により形成する。Ｃ
ＶＤ法により形成される誘電体薄膜は、比誘電率が１０
０以上に高く、静電容量の増大に寄与し、しかも高周波
特性に優れている。本発明では、ＣＶＤ法の中でも、Ｍ
ＯＣＶＤが好ましい。また、本発明において、コンデン
サ構造体を積層構造にすることで、その積層数に応じ
て、コンデンサの静電容量を増大させることができる。In the present invention, preferably, the dielectric thin film is formed by a chemical vapor deposition (CVD) method. C
The dielectric thin film formed by the VD method has a relative dielectric constant of 10
It is higher than 0, contributes to increase in electrostatic capacity, and is excellent in high frequency characteristics. In the present invention, among the CVD methods, M
OCVD is preferred. Further, in the present invention, by forming the capacitor structure into a laminated structure, the capacitance of the capacitor can be increased according to the number of laminated layers.
【００２１】[0021]
【発明の実施の形態】以下、本発明を、図面に示す実施
形態に基づき説明する。図１は本発明の一実施形態に係
るコンデンサ構造体の製造方法に用いる細孔形成用基板
の要部斜視図、図２は細孔形成用基板に形成してある柱
状細孔の平面図、図３（Ａ）および図３（Ｂ）は本発明
の一実施形態に係るコンデンサ構造体の製造過程を示す
要部断面図、図４は図３（Ｂ）に示す柱状体の平面図、
図５（Ａ）および図５（Ｂ）は本発明の他の実施形態に
係るコンデンサ構造体の製造過程を示す要部断面図、図
６は本発明の他の実施形態に係るコンデンサ構造体の要
部断面図、図７は本発明のさらにその他の実施形態に係
るコンデンサ構造体の要部断面図である。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the embodiments shown in the drawings. FIG. 1 is a perspective view of a main part of a pore forming substrate used in a method for manufacturing a capacitor structure according to an embodiment of the present invention, and FIG. 2 is a plan view of columnar pores formed on the pore forming substrate. 3 (A) and 3 (B) are cross-sectional views of an essential part showing a manufacturing process of a capacitor structure according to an embodiment of the present invention, and FIG. 4 is a plan view of a columnar body shown in FIG. 3 (B).
5 (A) and 5 (B) are cross-sectional views of a main part showing a manufacturing process of a capacitor structure according to another embodiment of the present invention, and FIG. 6 shows a capacitor structure according to another embodiment of the present invention. FIG. 7 is a cross-sectional view of a main part, and FIG. 7 is a cross-sectional view of a main part of a capacitor structure according to still another embodiment of the present invention.
【００２２】第１実施形態
本実施形態では、図１に示すように、まず、細孔形成用
基板としてのＡｌ基板２を準備する。Ａｌ基板２は、た
とえばアルミニウム箔などで構成される。このＡｌ基板
２の表面を、たとえばシュウ酸などの二塩基酸中で陽極
酸化させる。 First Embodiment In this embodiment, as shown in FIG. 1, first, an Al substrate 2 as a pore forming substrate is prepared. The Al substrate 2 is made of, for example, aluminum foil. The surface of the Al substrate 2 is anodized in a dibasic acid such as oxalic acid.
【００２３】その結果、図１および図２に示すように、
Ａｌ基板２の表面に、それぞれの内径が数ｎｍから数百
ｎｍの多数の円柱状細孔６が規則的に配列された多孔質
基板層１０が形成される。多孔質基板層１０は、アルミ
ナ層で構成される。As a result, as shown in FIG. 1 and FIG.
On the surface of the Al substrate 2, a porous substrate layer 10 in which a large number of cylindrical pores 6 each having an inner diameter of several nm to several hundred nm are regularly arranged is formed. The porous substrate layer 10 is composed of an alumina layer.
【００２４】円柱状細孔６の内径および深さ、および配
置ピッチなどは、陽極酸化時の電圧および電流を調整す
ることにより制御することができる。Ａｌ基板２の表面
に、それぞれの内径が数ｎｍから数百ｎｍの多数の円柱
状細孔６が規則的に配列された多孔質基板層１０が形成
される条件などは、たとえばNATURE Vol.337, P.147(19
89)などに記載されている。The inner diameter and depth of the cylindrical pores 6, the arrangement pitch, and the like can be controlled by adjusting the voltage and current during anodic oxidation. Conditions for forming the porous substrate layer 10 in which a large number of cylindrical pores 6 each having an inner diameter of several nm to several hundred nm are regularly arranged on the surface of the Al substrate 2 are, for example, NATURE Vol.337. , P.147 (19
89) etc.
【００２５】本実施形態では、Ａｌ基板２の表面に多孔
質基板層１０が形成され、その背面側に、細孔６が形成
されない領域２ａが残ることになる。そこで、本実施形
態では、その残りの領域２ａをエッチング処理あるいは
機械的研磨処理などで除去し、図３（Ａ）に示すよう
に、細孔６が表裏面で貫通する多孔質基板１０ａを形成
する。多孔質基板１０ａの厚みは、好ましくは１〜５０
０μｍである。その厚みがあまりに薄いと、マスクとし
ての機械的強度が不足する傾向にあり、厚すぎる多孔質
基板１０ａの製造は困難である。In this embodiment, the porous substrate layer 10 is formed on the surface of the Al substrate 2, and the region 2a where the pores 6 are not formed remains on the back surface side thereof. Therefore, in the present embodiment, the remaining region 2a is removed by etching or mechanical polishing to form a porous substrate 10a having pores 6 penetrating through the front and back surfaces as shown in FIG. 3 (A). To do. The thickness of the porous substrate 10a is preferably 1 to 50.
It is 0 μm. If the thickness is too thin, the mechanical strength as a mask tends to be insufficient, and it is difficult to manufacture the porous substrate 10a that is too thick.
【００２６】なお、Ａｌ基板２の厚みや陽極酸化時の電
圧および電流を調整することにより、円柱状細孔６をＡ
ｌ基板２の表裏面に対して貫通させて形成することも可
能である。その場合には、陽極酸化の結果として得られ
る基板は、多孔質基板１０ａそのものとなる。By adjusting the thickness of the Al substrate 2 and the voltage and current at the time of anodic oxidation, the columnar pores 6 can be made
It is also possible to form it by penetrating the front and back surfaces of the substrate 2. In that case, the substrate obtained as a result of the anodic oxidation is the porous substrate 10a itself.
【００２７】次に、図３（Ａ）に示すように、コンデン
サ用基板１４の表面に、まず、第１電極１５の一部とな
る面状電極層１１を、蒸着法、スパッタリング法などの
薄膜成膜法により形成する。その時には、多孔質基板１
０ａをマスクとしては使用しない。その後に、好ましく
は引き続き、多孔質基板１０ａをマスクとして、好まし
くは面状電極層１１を成膜するための薄膜成膜法と同じ
薄膜成膜処理を行う。その結果、マスク１０ａに形成さ
れた細孔６のパターン形状に合わせて、面状電極層１１
の表面に、それぞれの外径が数ｎｍから数百ｎｍの多数
の円柱状体１２が規則的に形成される。面状電極層１１
と円柱状体１２とが、第１電極１５を形成する。なお、
コンデンサ用基板１４の材質としては、特に限定され
ず、たとえば石英基板などのガラス基板、単結晶基板、
あるいはその他の基板が用いられる。また、基板１４の
厚みは、特に限定されないが、好ましくは０．１〜１mm
である。コンデンサ用基板１４は、絶縁性物質で構成さ
れることが好ましい。Next, as shown in FIG. 3 (A), first, a planar electrode layer 11 which becomes a part of the first electrode 15 is formed on the surface of the capacitor substrate 14 by a thin film such as a vapor deposition method or a sputtering method. It is formed by a film forming method. At that time, the porous substrate 1
0a is not used as a mask. After that, preferably, subsequently, the same thin film forming process as the thin film forming method for forming the planar electrode layer 11 is preferably performed using the porous substrate 10a as a mask. As a result, the planar electrode layer 11 is formed in accordance with the pattern shape of the pores 6 formed in the mask 10a.
A large number of cylindrical bodies 12 each having an outer diameter of several nm to several hundred nm are regularly formed on the surface of the. Planar electrode layer 11
And the columnar body 12 form the first electrode 15. In addition,
The material of the capacitor substrate 14 is not particularly limited, and for example, a glass substrate such as a quartz substrate, a single crystal substrate,
Alternatively, another substrate is used. The thickness of the substrate 14 is not particularly limited, but is preferably 0.1 to 1 mm.
Is. The capacitor substrate 14 is preferably made of an insulating material.
【００２８】面状電極層１１と円柱状体１２とは、好ま
しくは同じ材質で構成され、たとえばニッケル、白金、
銅、あるいはこれらの一部を含む合金、あるいはルテニ
ウムオキサイド合金などの導電性金属で構成される。具
体的な材質は、その後に成膜される誘電体薄膜１６の材
質との相性などで決定される。The planar electrode layer 11 and the columnar body 12 are preferably made of the same material, for example, nickel, platinum,
It is composed of copper, an alloy containing a part thereof, or a conductive metal such as a ruthenium oxide alloy. The specific material is determined by compatibility with the material of the dielectric thin film 16 to be formed thereafter.
【００２９】面状電極層１１の厚みは、特に限定されな
いが、好ましくは５０〜５００ｎｍである。円柱状体１
２の外径φ１は、細孔６の内径にほぼ対応し、数ｎｍか
ら数百ｎｍである。また、円柱状体１２の高さは、薄膜
成膜時間などにより制御され、好ましくは１ｎｍ〜数μ
ｍ、さらに好ましくは１０ｎｍ〜１μｍである。これら
の高さは、高い程、静電容量の増大に効果があるが、製
造が困難になる傾向にある。The thickness of the planar electrode layer 11 is not particularly limited, but is preferably 50 to 500 nm. Cylindrical body 1
The outer diameter φ1 of 2 substantially corresponds to the inner diameter of the pores 6, and is several nm to several hundred nm. Further, the height of the cylindrical body 12 is controlled by the thin film deposition time and the like, and preferably 1 nm to several μm.
m, and more preferably 10 nm to 1 μm. The higher these heights are, the more effective they are in increasing the capacitance, but they tend to be difficult to manufacture.
【００３０】図４に示すように、円柱状体１２は、多孔
質基板１０ａにおける細孔６の配置ピッチに対応して、
規則正しく配置される。たとえば隣接する３つの円柱状
体１２は、ほぼ正三角形の位置に配置され、円柱状体１
２の配置ピッチ間隔Ｌは、柱状体１２の外径φ１との関
係で決定され、数ｎｍ〜数百ｎｍである。このピッチ間
隔Ｌは、柱状体１２の外周に厚さｔ１の誘電体薄膜１６
が後工程で成膜されたとしても、隣接する柱状体１２間
で、その外周に成膜される誘電体薄膜１６が接触しない
程度の間隔である。厚さｔ１については、後述する。As shown in FIG. 4, the columnar body 12 corresponds to the arrangement pitch of the pores 6 in the porous substrate 10a.
Arranged regularly. For example, three adjacent columnar bodies 12 are arranged at positions of substantially equilateral triangles, and the columnar body 1
The arrangement pitch interval L of 2 is determined in relation to the outer diameter φ1 of the columnar body 12 and is several nm to several hundred nm. The pitch interval L is such that the dielectric thin film 16 having a thickness t1 is formed on the outer circumference of the columnar body 12.
Even if the film is formed in the subsequent step, the distance is such that the dielectric thin film 16 formed on the outer periphery of the adjacent columnar bodies 12 does not come into contact with each other. The thickness t1 will be described later.
【００３１】次に、図３（Ｂ）に示すように、柱状体１
２の外側を覆うように、第１電極１５の表面に、誘電体
薄膜１６を成膜する。誘電体薄膜１６は、好ましくはＭ
ＯＣＶＤにより成膜される。誘電体薄膜１６の材質とし
ては、特に限定されないが、ＢＳＴ、ＰＭＮなどのペロ
ブスカイト化合物、ＢｉＴなどのビスマス層状化合物な
ど、比誘電率が１００以上のものが例示される。誘電体
薄膜１６の厚みｔ１は、好ましくは１０〜５００ｎｍ程
度である。この厚みｔ１は、図４において、（Ｌ−φ１
−２×ｔ１）が０よりも大きくなるように決定される。
すなわち、隣接する円柱状体１２の間で、それらの外周
に形成される誘電体薄膜１６の相互が接触しないよう
に、厚みｔ１が決定される。好ましくは、厚みｔ１は、
（Ｌ−φ１）／２の５０〜９０％が望ましい。Next, as shown in FIG. 3B, the columnar body 1
A dielectric thin film 16 is formed on the surface of the first electrode 15 so as to cover the outer side of the second electrode 15. The dielectric thin film 16 is preferably M
It is formed by OCVD. The material of the dielectric thin film 16 is not particularly limited, but examples thereof include those having a relative dielectric constant of 100 or more, such as perovskite compounds such as BST and PMN and bismuth layered compounds such as BiT. The thickness t1 of the dielectric thin film 16 is preferably about 10 to 500 nm. This thickness t1 is (L-φ1
−2 × t1) is determined to be larger than 0.
That is, the thickness t1 is determined so that the dielectric thin films 16 formed on the outer circumferences of the adjacent columnar bodies 12 do not come into contact with each other. Preferably, the thickness t1 is
50 to 90% of (L-φ1) / 2 is desirable.
【００３２】その後、図３（Ｂ）に示すように、各円柱
状体１２の外側を覆って埋め込むようように、第２電極
１８を、誘電体薄膜１６の表面に形成する。第２電極１
８は、第１電極１５と同様な材質で構成され、同様な成
膜法により成膜される。ただし、第２電極１８の成膜に
際しては、多孔質基板１０ａをマスクとしては用いな
い。また、第１電極１５と第２電極１８とは、材質を異
ならせても良い。第２電極１８の成膜後に、その表面を
平坦化処理しても良い。平坦化処理は、たとえば化学機
械研磨（ＣＭＰ）処理などで行うこともできる。最終的
に得られる第２電極１８の厚みは、第１電極１５の厚み
と同程度である。Thereafter, as shown in FIG. 3B, the second electrode 18 is formed on the surface of the dielectric thin film 16 so as to cover and embed the outer surface of each cylindrical body 12. Second electrode 1
8 is made of the same material as the first electrode 15, and is formed by the same film forming method. However, when forming the second electrode 18, the porous substrate 10a is not used as a mask. The first electrode 15 and the second electrode 18 may be made of different materials. After forming the second electrode 18, the surface thereof may be planarized. The planarization treatment can also be performed by, for example, chemical mechanical polishing (CMP) treatment. The thickness of the finally obtained second electrode 18 is approximately the same as the thickness of the first electrode 15.
【００３３】このようにして得られたコンデンサ構造体
３０では、第１電極１５の表面に、数ｎｍから数百ｎｍ
の多数の柱状体１２が規則的に形成してあることから、
その上に形成される誘電体薄膜１６の表面積が増大し、
静電容量が飛躍的に増大し、小型で大容量のコンデンサ
構造体３０を実現することができる。たとえば柱状体
（または柱状細孔）が何ら形成されていない従来のコン
デンサ構造体に比較して、本実施形態のコンデンサ構造
体３０は、静電容量が２桁以上増大する。In the capacitor structure 30 thus obtained, the surface of the first electrode 15 has a thickness of several nm to several hundred nm.
Since a large number of columnar bodies 12 are regularly formed,
The surface area of the dielectric thin film 16 formed thereon increases,
The capacitance is dramatically increased, and the small-sized and large-capacity capacitor structure 30 can be realized. For example, the capacitance of the capacitor structure 30 of the present embodiment is increased by two digits or more as compared with the conventional capacitor structure in which no columnar body (or columnar pore) is formed.
【００３４】また本実施形態では、多数の柱状体１２が
規則的に形成してあることから、隣接する柱状体１２が
接触することなく、誘電体薄膜１６における表面積の増
大効果が増大する。Further, in this embodiment, since a large number of columnar bodies 12 are regularly formed, the effect of increasing the surface area of the dielectric thin film 16 is increased without the adjacent columnar bodies 12 coming into contact with each other.
【００３５】本実施形態のコンデンサ構造体３０は、チ
ップ状コンデンサとして用いることができると共に、た
とえば集積回路のキャパシタ素子などとしても利用する
ことができる。The capacitor structure 30 of this embodiment can be used not only as a chip-shaped capacitor but also as, for example, a capacitor element of an integrated circuit.
【００３６】第２実施形態
図５（Ａ）および図５（Ｂ）に示すように、本実施形態
の方法は、前記の第１実施形態の方法の変形例であり、
以下の説明では、前記の第１実施形態の方法と異なる部
分についてのみ詳細に説明し、共通する部分の説明は省
略する。 Second Embodiment As shown in FIGS. 5A and 5B, the method of this embodiment is a modification of the method of the first embodiment, and
In the following description, only parts different from the method of the first embodiment will be described in detail, and description of common parts will be omitted.
【００３７】前記第１実施形態と同様にして多孔質基板
１０ａを形成した後、この多孔質基板１０ａを利用して
エッチング処理を行い、第１電極２０の表面に多数の規
則的な柱状細孔２２を形成する。円柱状細孔２２の内径
は、多孔質基板１０ａの細孔６の内径にほぼ対応し、数
ｎｍから数百ｎｍである。また、円柱状細孔２２の配置
パターンも、多孔質基板１０ａの細孔６の配置パターン
にほぼ対応する。円柱状細孔２２の深さは、図３（Ａ）
に示す柱状体１２の高さとほぼ同様である。円柱状細孔
２２は、第１電極２０を貫通せず、基板１４の表面で、
面状電極層２３が残るように形成される。第１電極２０
は、図３（Ａ）に示す面状電極１１と同様な成膜法によ
り成膜され、同様な材質で構成される。なお、この実施
形態では、円柱状細孔２２は、第１電極２０を貫通させ
ても良い。円柱状細孔２２が第１電極２０を貫通させた
としても、細孔２２以外の部分で、第１電極２０は、相
互に切断されることなく電気的に接続しているからであ
る。After the porous substrate 10a is formed in the same manner as in the first embodiment, the porous substrate 10a is used to perform an etching process to form a large number of regular columnar pores on the surface of the first electrode 20. 22 is formed. The inner diameter of the columnar pore 22 substantially corresponds to the inner diameter of the pore 6 of the porous substrate 10a, and is several nm to several hundred nm. Further, the arrangement pattern of the columnar pores 22 substantially corresponds to the arrangement pattern of the pores 6 of the porous substrate 10a. The depth of the cylindrical pores 22 is as shown in FIG.
The height is substantially the same as the height of the columnar body 12 shown in FIG. The cylindrical pores 22 do not penetrate the first electrode 20 and are formed on the surface of the substrate 14,
The planar electrode layer 23 is formed so as to remain. First electrode 20
Is formed by a film forming method similar to that of the planar electrode 11 shown in FIG. In addition, in this embodiment, the columnar pores 22 may penetrate the first electrode 20. This is because even if the columnar pores 22 penetrate the first electrode 20, the first electrodes 20 are electrically connected to each other at the portions other than the pores 22 without being cut off from each other.
【００３８】次に、図５（Ｂ）に示すように、円柱状細
孔２２の内部に入り込むように、第１電極２０の表面
に、誘電体薄膜２４を形成する。誘電体薄膜２４は、図
３（Ｂ）に示す誘電体薄膜１６と同様な薄膜成膜法によ
り成膜され、同様な材質で構成される。誘電体薄膜２４
の厚みは、誘電体薄膜１６と同程度である。ただし、誘
電体薄膜２４の厚みは、細孔２２を完全に埋め込まない
ように決定される。なお、細孔２２の内径は、柱状体１
２の外径よりも大きく設計されることが好ましく、１０
〜１０００ｎｍ程度が好ましい。また、誘電体薄膜１６
の厚みは、細孔２２の内径の１０〜４５％の厚みである
ことが好ましい。Next, as shown in FIG. 5B, a dielectric thin film 24 is formed on the surface of the first electrode 20 so as to enter the inside of the cylindrical pore 22. The dielectric thin film 24 is formed by the same thin film forming method as the dielectric thin film 16 shown in FIG. 3B, and is made of the same material. Dielectric thin film 24
Is approximately the same as the dielectric thin film 16. However, the thickness of the dielectric thin film 24 is determined so that the pores 22 are not completely filled. In addition, the inner diameter of the pore 22 is equal to that of the columnar body 1.
It is preferable that the diameter is designed to be larger than the outer diameter of 2.
It is preferably about 1000 nm. In addition, the dielectric thin film 16
Is preferably 10 to 45% of the inner diameter of the pore 22.
【００３９】次に、図５（Ｂ）に示すように、柱状細孔
２２の内部に入り込むように、誘電体薄膜２４の表面に
第２電極２６を成膜する。第２電極２６は、図３（Ｂ）
に示す第２電極１８と同様な方法により成膜され、同様
な最終厚みを有する。Next, as shown in FIG. 5B, a second electrode 26 is formed on the surface of the dielectric thin film 24 so as to enter the inside of the columnar pores 22. The second electrode 26 is shown in FIG.
The second electrode 18 is formed by a method similar to that of the second electrode 18 and has a similar final thickness.
【００４０】このようにして得られたコンデンサ構造体
４０では、第１電極２０の表面に、数ｎｍから数百ｎｍ
の多数の円柱状細孔２２が規則的に形成してあることか
ら、その上に形成される誘電体薄膜２４の表面積が増大
し、静電容量が飛躍的に増大し、小型で大容量のコンデ
ンサ構造体４０を実現することができる。たとえば柱状
体（または柱状細孔）が何ら形成されていない従来のコ
ンデンサ構造体に比較して、本実施形態のコンデンサ構
造体４０は、静電容量が２桁以上増大する。In the capacitor structure 40 thus obtained, the surface of the first electrode 20 has several nm to several hundred nm.
Since a large number of cylindrical pores 22 are regularly formed, the surface area of the dielectric thin film 24 formed thereon is increased, the electrostatic capacitance is dramatically increased, and the small-sized and large-capacity The capacitor structure 40 can be realized. For example, the capacitance of the capacitor structure 40 of the present embodiment is increased by two digits or more as compared with the conventional capacitor structure in which no columnar body (or columnar pore) is formed.
【００４１】また本実施形態では、多数の円柱状細孔２
２が規則的に形成してあることから、隣接する細孔２２
が接触することなく、誘電体薄膜２４における表面積の
増大効果が増大する。In the present embodiment, a large number of cylindrical pores 2
Since 2 are regularly formed, the adjacent pores 22
Without being in contact with each other, the effect of increasing the surface area of the dielectric thin film 24 increases.
【００４２】本実施形態のコンデンサ構造体４０は、チ
ップ状コンデンサとして用いることができると共に、た
とえば集積回路のキャパシタ素子などとしても利用する
ことができる。The capacitor structure 40 of this embodiment can be used not only as a chip-shaped capacitor but also as, for example, a capacitor element of an integrated circuit.
【００４３】なお、本発明は、上述した実施形態に限定
されるものではなく、本発明の範囲内で種々に改変する
ことができる。たとえば図６に示すように、前記第１実
施形態において、図３（Ｂ）に示す第２電極１８を形成
した後、その表面を平坦化して、その上に、同様な手法
により、図３（Ｂ）に示すコンデンサ構造体を積層させ
ても良い。すなわち、第２電極１８の表面に、前記と同
様な方法により、多数の円柱状体１２を形成し、その上
に、誘電体膜１６を形成し、その上に、第３電極１９を
形成するのである。第３電極１９は、第２電極１８と同
様にして形成され、同様な材質で構成される。これらの
工程を繰り返せば、図３（Ｂ）に示すコンデンサ構造体
が二層以上に積層された積層型のコンデンサ構造体３０
ａを得ることができる。あるいは、図７に示すように、
前記第２実施形態において、図５（Ｂ）に示す第２電極
２６を形成した後、その表面を平坦化して、その上に、
同様な手法により、図５（Ｂ）に示すコンデンサ構造体
を積層させても良い。すなわち、第２電極２６の表面
に、前記と同様な方法により、多数の円柱状細孔２２を
形成し、その上に、誘電体膜２４を形成し、その上に、
第３電極２７を形成するのである。第３電極２７は、第
２電極２６と同様にして形成され、同様な材質で構成さ
れる。これらの工程を繰り返せば、図５（Ｂ）に示すコ
ンデンサ構造体が二層以上に積層された積層型のコンデ
ンサ構造体４０ａを得ることができる。また、本発明で
は、図３（Ｂ）に示すコンデンサ構造体と、図５（Ｂ）
に示すコンデンサ構造体とを組み合わせて積層させても
良い。このような積層型のコンデンサ構造体によれば、
積層数に応じて、コンデンサの静電容量を増大させるこ
とができる。The present invention is not limited to the above-mentioned embodiment, but can be variously modified within the scope of the present invention. For example, as shown in FIG. 6, in the first embodiment, after the second electrode 18 shown in FIG. 3B is formed, the surface thereof is flattened, and then the second electrode 18 shown in FIG. The capacitor structure shown in B) may be laminated. That is, a large number of columnar bodies 12 are formed on the surface of the second electrode 18 by the same method as described above, the dielectric film 16 is formed thereon, and the third electrode 19 is formed thereon. Of. The third electrode 19 is formed similarly to the second electrode 18, and is made of the same material. By repeating these steps, a laminated capacitor structure 30 in which two or more capacitor structures shown in FIG.
a can be obtained. Alternatively, as shown in FIG.
In the second embodiment, after forming the second electrode 26 shown in FIG. 5B, the surface thereof is flattened, and
The capacitor structure shown in FIG. 5B may be laminated by a similar method. That is, a large number of columnar pores 22 are formed on the surface of the second electrode 26 by the same method as described above, the dielectric film 24 is formed thereon, and then the dielectric film 24 is formed thereon.
The third electrode 27 is formed. The third electrode 27 is formed similarly to the second electrode 26 and is made of the same material. By repeating these steps, it is possible to obtain a laminated capacitor structure 40a in which the capacitor structure shown in FIG. 5B is laminated in two or more layers. Further, according to the present invention, the capacitor structure shown in FIG.
You may laminate | stack by combining with the capacitor structure shown in. According to such a laminated capacitor structure,
The capacitance of the capacitor can be increased according to the number of stacked layers.
【００４４】[0044]
【実施例】以下、本発明を、さらに詳細な実施例に基づ
き説明するが、本発明は、これら実施例に限定されな
い。EXAMPLES The present invention will be described below based on more detailed examples, but the present invention is not limited to these examples.
【００４５】実施例１
まず、多孔質基板１０ａを形成した。多孔質基板１０ａ
を形成するための条件は、次の通りである。厚さ０．１
mmのアルミニウム箔を用い、陽極酸化処理を行った。陽
極酸化時の処理液としては、シュウ酸を用いた。陽極酸
化時の電圧は、４０Ｖであった。陽極酸化処理の結果、
アルミニウム箔に、内径が５０ｎｍで、ピッチＬが３０
０ｎｍの貫通した多数の規則正しく配置された円柱状細
孔が得られた。円柱状細孔の配置は、隣接する３つの細
孔の中心を結ぶ線がほぼ正三角形になる配置であった。 Example 1 First, the porous substrate 10a was formed. Porous substrate 10a
The conditions for forming the are as follows. Thickness 0.1
Anodizing treatment was performed using an aluminum foil of mm. Oxalic acid was used as a treatment liquid during anodization. The voltage during anodic oxidation was 40V. As a result of anodizing,
Aluminum foil with an inner diameter of 50 nm and a pitch L of 30
A large number of regularly arranged cylindrical pores with 0 nm penetration were obtained. The cylindrical pores were arranged such that the line connecting the centers of three adjacent pores was a substantially equilateral triangle.
【００４６】石英板からなる厚さ０．５mmの基板１４の
表面に、厚さ１００ｎｍの面状電極１１を、Ｐｔを用い
たスパッタ法により全面に成膜した後、引き続き、多孔
質基板を用いて、基板１４の表面に、Ｐｔを用いたスパ
ッタ法により高さ５００ｎｍの柱状体１２を規則正しく
形成し、第１電極１５を得た。On the surface of a substrate 14 made of a quartz plate and having a thickness of 0.5 mm, a planar electrode 11 having a thickness of 100 nm was formed on the entire surface by a sputtering method using Pt, and then a porous substrate was used. Then, the columnar bodies 12 having a height of 500 nm were regularly formed on the surface of the substrate 14 by the sputtering method using Pt to obtain the first electrodes 15.
【００４７】その後、ＢｉＴ（Ｂｉ（ＣＨ３）３トリメ
チルビスマス、Ｔｉ（Ｏ・ｉ−Ｃ３Ｈ７）４テトライソ
プロポキシチタニウム）を用いたＭＯＣＶＤ法により、
柱状体１２の外側を覆うように、第１電極１５の表面
に、誘電体薄膜１６を成膜した。誘電体薄膜１６の厚み
は、２５ｎｍであった。その後、各円柱状体１２の外側
を覆って埋め込むようように、第２電極１８を、誘電体
薄膜１６の表面に形成した。第２電極１８は、面状電極
１１と同様な方法により成膜し、その材質も同じであっ
た。第２電極１８の最終厚みは、２００ｎｍであり、そ
の面積は、０．１×０．１mmであった。Then, by the MOCVD method using BiT (Bi (CH 3 ) 3 trimethylbismuth, Ti (O.i-C 3 H 7 ) 4 tetraisopropoxytitanium).
A dielectric thin film 16 was formed on the surface of the first electrode 15 so as to cover the outside of the columnar body 12. The thickness of the dielectric thin film 16 was 25 nm. After that, the second electrode 18 was formed on the surface of the dielectric thin film 16 so as to cover and embed the outside of each cylindrical body 12. The second electrode 18 was formed by a method similar to that of the planar electrode 11, and the material thereof was also the same. The final thickness of the second electrode 18 was 200 nm, and its area was 0.1 × 0.1 mm.
【００４８】このようにして得られたコンデンサ構造体
について、静電容量を測定したところ、５３０ｐＦであ
った。また、誘電損失は４％であった（測定条件：１０
ｋＨｚ、０．０２Ｖ）。The capacitance of the capacitor structure thus obtained was measured and found to be 530 pF. The dielectric loss was 4% (measurement condition: 10
kHz, 0.02V).
【００４９】[0049]
【発明の効果】以上説明してきたように、本発明によれ
ば、特に小型で大容量のコンデンサ構造体およびその製
造方法を提供することができる。As described above, according to the present invention, it is possible to provide a particularly small-sized and large-capacity capacitor structure and a manufacturing method thereof.
【図１】 図１は本発明の一実施形態に係るコンデンサ
構造体の製造方法に用いる細孔形成用基板の要部斜視図
である。FIG. 1 is a perspective view of a main part of a pore forming substrate used in a method for manufacturing a capacitor structure according to an embodiment of the present invention.
【図２】 図２は細孔形成用基板に形成してある柱状細
孔の平面図である。FIG. 2 is a plan view of columnar pores formed on a pore-forming substrate.
【図３】 図３（Ａ）および図３（Ｂ）は本発明の一実
施形態に係るコンデンサ構造体の製造過程を示す要部断
面図である。FIG. 3A and FIG. 3B are cross-sectional views of a main part showing a manufacturing process of a capacitor structure according to an embodiment of the present invention.
【図４】 図４は図３（Ｂ）に示す柱状体の平面図であ
る。FIG. 4 is a plan view of the columnar body shown in FIG. 3 (B).
【図５】 図５（Ａ）および図５（Ｂ）は本発明の他の
実施形態に係るコンデンサ構造体の製造過程を示す要部
断面図である。5 (A) and 5 (B) are cross-sectional views of essential parts showing a manufacturing process of a capacitor structure according to another embodiment of the present invention.
【図６】 図６は本発明の他の実施形態に係るコンデン
サ構造体の要部断面図である。FIG. 6 is a sectional view of an essential part of a capacitor structure according to another embodiment of the present invention.
【図７】 図７は本発明のさらにその他の実施形態に係
るコンデンサ構造体の要部断面図である。FIG. 7 is a sectional view of an essential part of a capacitor structure according to still another embodiment of the present invention.
２… Ａｌ基板（細孔形成用基板） ６… 円柱状細孔 １０ａ… 多孔質基板 １１，２３… 面状電極 １２… 円柱状体 １４… コンデンサ用基板 １５，２０… 第１電極 １６，２４… 誘電体薄膜 １８，２６… 第２電極 １９，２７… 第３電極 ２２… 円柱状細孔 ３０，３０ａ，４０，４０ａ… コンデンサ構造体 2. Al substrate (pore forming substrate) 6 ... Cylindrical pores 10a ... Porous substrate 11, 23 ... Planar electrodes 12 ... Cylindrical body 14 ... Capacitor substrate 15, 20 ... First electrode 16, 24 ... Dielectric thin film 18, 26 ... Second electrode 19, 27 ... Third electrode 22 ... Cylindrical pores 30, 30a, 40, 40a ... Capacitor structure
Claims (14)
れの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規則
的に配列された多孔質基板を形成する工程と、 前記多孔質基板をマスクとして用いて薄膜成膜処理を行
い、コンデンサ用基板の表面に、それぞれの外径が数ｎ
ｍから数百ｎｍの多数の柱状体が規則的に配列された第
１電極を形成する工程と、 前記柱状体の外側を覆うように、前記第１電極の表面
に、誘電体薄膜を形成する工程と、 前記柱状体の外側を覆うように、前記誘電体薄膜の表面
に第２電極を形成する工程とを有するコンデンサ構造体
の製造方法。1. A step of forming a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly arranged by anodizing the pore-forming substrate, A thin film is formed by using a high quality substrate as a mask, and each outer diameter is several n on the surface of the capacitor substrate.
a step of forming a first electrode in which a large number of columnar bodies of m to several hundred nm are regularly arranged, and a dielectric thin film is formed on the surface of the first electrode so as to cover the outer side of the columnar bodies. A method of manufacturing a capacitor structure, comprising: a step; and a step of forming a second electrode on the surface of the dielectric thin film so as to cover the outside of the columnar body.
り形成することを特徴とする請求項１に記載のコンデン
サ構造体の製造方法。2. The method for manufacturing a capacitor structure according to claim 1, wherein the dielectric thin film is formed by a chemical vapor deposition method.
れの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規則
的に配列された多孔質基板をマスクとして用いて薄膜成
膜処理を行い、コンデンサ用基板の表面に、それぞれの
外径が数ｎｍから数百ｎｍの多数の柱状体が規則的に形
成された第１電極と、 前記柱状体の外側を覆うように、前記第１電極の表面に
形成された誘電体薄膜と、 前記柱状体の外側を覆うように、前記誘電体薄膜の表面
に形成された第２電極と、 を有するコンデンサ構造体。3. A thin film is formed by anodizing a pore-forming substrate and using as a mask a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regularly arranged. A first electrode on which a large number of columnar bodies each having an outer diameter of several nm to several hundred nm are regularly formed on the surface of the substrate for capacitors, and the outer surface of the columnar bodies is covered with the first electrode. A capacitor structure comprising: a dielectric thin film formed on the surface of the first electrode; and a second electrode formed on the surface of the dielectric thin film so as to cover the outside of the columnar body.
であることを特徴とする請求項１に記載のコンデンサ構
造体。4. The capacitor structure according to claim 1, wherein the dielectric thin film has a relative permittivity of 100 or more.
造体を具備するチップ状コンデンサ。5. A chip-shaped capacitor comprising the capacitor structure according to claim 3.
れの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規則
的に配列された多孔質基板を形成する工程と、 前記多孔質基板をマスクとして用いてエッチング処理を
行い、コンデンサ用基板の表面に、それぞれの外径が数
ｎｍから数百ｎｍの多数の柱状細孔が規則的に配列され
た第１電極を形成する工程と、 前記柱状細孔の内部に入り込むように、前記第１電極の
表面に、誘電体薄膜を形成する工程と、 前記柱状細孔の内部に入り込むように、前記誘電体薄膜
の表面に、第２電極を形成する工程とを有するコンデン
サ構造体の製造方法。6. A step of forming a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly arrayed by anodizing the pore-forming substrate; A first electrode in which a large number of columnar pores each having an outer diameter of several nm to several hundred nm are regularly arranged on the surface of the capacitor substrate by performing an etching process using the quality substrate as a mask A step of forming a dielectric thin film on the surface of the first electrode so as to enter the inside of the columnar pores; and a step of forming a dielectric thin film on the surface of the dielectric thin film so as to enter the inside of the columnar pores. A method of manufacturing a capacitor structure, the method including the step of forming two electrodes.
り形成することを特徴とする請求項６に記載のコンデン
サ構造体の製造方法。7. The method of manufacturing a capacitor structure according to claim 6, wherein the dielectric thin film is formed by a chemical vapor deposition method.
れの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規則
的に配列された多孔質基板をマスクとして用いてエッチ
ング処理を行い、コンデンサ用基板の表面に、それぞれ
の内径が数ｎｍから数百ｎｍの多数の柱状細孔が規則的
に形成された第１電極と、 前記柱状細孔の内部に入り込むように、前記第１電極の
表面に形成された誘電体薄膜と、 前記柱状細孔の内部に入り込むように、前記誘電体薄膜
の表面に形成された第２電極と、 を有するコンデンサ構造体。8. The etching treatment is performed by anodizing the pore-forming substrate and using as a mask a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regularly arranged as a mask. Then, the first electrode in which a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly formed on the surface of the capacitor substrate, and the first electrode is inserted so as to enter the columnar pores. A capacitor structure comprising: a dielectric thin film formed on the surface of one electrode; and a second electrode formed on the surface of the dielectric thin film so as to enter the inside of the columnar pores.
であることを特徴とする請求項８に記載のコンデンサ構
造体。9. The capacitor structure according to claim 8, wherein the dielectric thin film has a relative dielectric constant of 100 or more.
構造体を具備するチップ状コンデンサ。10. A chip-shaped capacitor comprising the capacitor structure according to claim 8.
ぞれの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規
則的に配列された多孔質基板を形成する工程と、 前記多孔質基板をマスクとして用いて薄膜成膜処理を行
い、コンデンサ用基板の表面に、それぞれの外径が数ｎ
ｍから数百ｎｍの多数の第１柱状体が規則的に配列され
た第１電極を形成する工程と、 前記第１柱状体の外側を覆うように、前記第１電極の表
面に、第１誘電体薄膜を形成する工程と、 前記第１柱状体の外側を覆うように、前記第１誘電体薄
膜の表面に第２電極を形成する工程と、 前記多孔質基板をマスクとして用いて薄膜成膜処理を行
い、前記第２電極の表面に、それぞれの外径が数ｎｍか
ら数百ｎｍの多数の第２柱状体を規則的に形成する工程
と、 前記第２柱状体の外側を覆うように、前記第２電極の表
面に、第２誘電体薄膜を形成する工程と、 前記第２柱状体の外側を覆うように、前記第２誘電体薄
膜の表面に第３電極を形成する工程と、 を有するコンデンサ構造体の製造方法。11. A step of forming a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly arranged, by anodizing the pore-forming substrate, A thin film is formed by using a high quality substrate as a mask, and each outer diameter is several n on the surface of the capacitor substrate.
a step of forming a first electrode in which a large number of first columnar bodies of m to several hundred nm are regularly arranged, and a first electrode is formed on the surface of the first electrode so as to cover the outside of the first columnar body. Forming a dielectric thin film, forming a second electrode on the surface of the first dielectric thin film so as to cover the outside of the first columnar body, and forming a thin film using the porous substrate as a mask. A step of performing a film treatment to regularly form a large number of second columnar bodies each having an outer diameter of several nm to several hundreds nm on the surface of the second electrode; and covering the outside of the second columnar bodies. A step of forming a second dielectric thin film on the surface of the second electrode, and a step of forming a third electrode on the surface of the second dielectric thin film so as to cover the outside of the second columnar body. A method for manufacturing a capacitor structure having:
ぞれの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規
則的に配列された多孔質基板をマスクとして用いて薄膜
成膜処理を行い、コンデンサ用基板の表面に、それぞれ
の外径が数ｎｍから数百ｎｍの多数の第１柱状体が規則
的に形成された第１電極と、 前記第１柱状体の外側を覆うように、前記第１電極の表
面に形成された第１誘電体薄膜と、 前記第１柱状体の外側を覆うように、前記第１誘電体薄
膜の表面に形成された第２電極と、 前記多孔質基板をマスクとして用いて薄膜成膜処理を行
い、前記第２電極の表面に規則的に形成され、それぞれ
の外径が数ｎｍから数百ｎｍの多数の第２柱状体と、 前記第２柱状体の外側を覆うように、前記第２電極の表
面に形成された第２誘電体薄膜と、 前記第２柱状体の外側を覆うように、前記第２誘電体薄
膜の表面に形成された第３電極と、 を有するコンデンサ構造体。12. A thin film is formed by anodizing a pore-forming substrate and using as a mask a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regularly arranged. A first electrode on which a large number of first columnar bodies each having an outer diameter of several nm to several hundred nm are regularly formed on the surface of the capacitor substrate, and the outside of the first columnar body is covered. A first dielectric thin film formed on the surface of the first electrode, a second electrode formed on the surface of the first dielectric thin film so as to cover the outside of the first columnar body, A thin film forming process is performed by using a porous substrate as a mask, and a large number of second columnar bodies each regularly formed on the surface of the second electrode and each having an outer diameter of several nm to several hundreds nm; The second dielectric thin film formed on the surface of the second electrode so as to cover the outside of the two columnar bodies. When the as second cover the outside of the columnar body, a capacitor structure having a third electrode formed on the second dielectric surface of the thin film.
ぞれの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規
則的に配列された多孔質基板を形成する工程と、 前記多孔質基板をマスクとして用いてエッチング処理を
行い、コンデンサ用基板の表面に、それぞれの外径が数
ｎｍから数百ｎｍの多数の第１柱状細孔が規則的に配列
された第１電極を形成する工程と、 前記第１柱状細孔の内部に入り込むように、前記第１電
極の表面に、第１誘電体薄膜を形成する工程と、 前記第１柱状細孔の内部に入り込むように、前記第１誘
電体薄膜の表面に、第２電極を形成する工程と、 前記多孔質基板をマスクとして用いてエッチング処理を
行い、前記第２電極の表面に、それぞれの外径が数ｎｍ
から数百ｎｍの多数の第２柱状細孔を規則的に形成する
工程と、 前記第２柱状細孔の内部に入り込むように、前記第２電
極の表面に、第２誘電体薄膜を形成する工程と、 前記第２柱状細孔の内部に入り込むように、前記第２誘
電体薄膜の表面に、第３電極を形成する工程と、 を有するコンデンサ構造体の製造方法。13. A step of forming a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundreds nm are regularly arranged by anodizing the pore-forming substrate; A first electrode in which a large number of first columnar pores each having an outer diameter of several nm to several hundred nm are regularly arranged is formed on the surface of the capacitor substrate by performing an etching process using the quality substrate as a mask. And a step of forming a first dielectric thin film on the surface of the first electrode so as to enter the inside of the first columnar pores, and a step of entering the inside of the first columnar pores, A step of forming a second electrode on the surface of the first dielectric thin film, and an etching process using the porous substrate as a mask so that the outer diameter of each of the electrodes is several nm.
To regularly form a large number of second columnar pores each having a thickness of 100 nm to several hundred nm, and forming a second dielectric thin film on the surface of the second electrode so as to enter the inside of the second columnar pores. And a step of forming a third electrode on the surface of the second dielectric thin film so as to enter the inside of the second columnar pores.
ぞれの内径が数ｎｍから数百ｎｍの多数の柱状細孔が規
則的に配列された多孔質基板をマスクとして用いてエッ
チング処理を行い、コンデンサ用基板の表面に、それぞ
れの内径が数ｎｍから数百ｎｍの多数の第１柱状細孔が
規則的に形成された第１電極と、 前記第１柱状細孔の内部に入り込むように、前記第１電
極の表面に形成された第１誘電体薄膜と、 前記第１柱状細孔の内部に入り込むように、前記第１誘
電体薄膜の表面に形成された第２電極と、 前記多孔質基板をマスクとして用いてエッチング処理を
行い、前記第２電極の表面に規則的に形成され、それぞ
れの内径が数ｎｍから数百ｎｍの多数の第２柱状細孔
と、 前記第２柱状細孔の内部に入り込むように、前記第２電
極の表面に形成された第２誘電体薄膜と、 前記第２柱状細孔の内部に入り込むように、前記第２誘
電体薄膜の表面に形成された第３電極と、 を有するコンデンサ構造体。14. An anodizing treatment is applied to a pore-forming substrate, and an etching treatment is carried out using as a mask a porous substrate in which a large number of columnar pores each having an inner diameter of several nm to several hundred nm are regularly arranged. Then, the first electrode in which a large number of first columnar pores each having an inner diameter of several nm to several hundreds nm are regularly formed on the surface of the capacitor substrate is inserted into the first electrode. A first dielectric thin film formed on the surface of the first electrode, a second electrode formed on the surface of the first dielectric thin film so as to enter the inside of the first columnar pores, Etching is performed using the porous substrate as a mask, and a large number of second columnar pores, which are regularly formed on the surface of the second electrode and each have an inner diameter of several nm to several hundred nm, and the second columnar The surface of the second electrode so that it enters the inside of the pores. A second dielectric thin film formed on the second so as to enter the interior of the columnar pore, capacitor structure having a third electrode formed on the second dielectric surface of the thin film.
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|---|---|---|---|
| JP2002047958A JP2003249417A (en) | 2002-02-25 | 2002-02-25 | Capacitor structure and manufacturing method of the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002047958A JP2003249417A (en) | 2002-02-25 | 2002-02-25 | Capacitor structure and manufacturing method of the same |
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| Publication Number | Publication Date |
|---|---|
| JP2003249417A true JP2003249417A (en) | 2003-09-05 |
Family
ID=28660882
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002047958A Withdrawn JP2003249417A (en) | 2002-02-25 | 2002-02-25 | Capacitor structure and manufacturing method of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003249417A (en) |
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