JP2003198347A - Driver for mos gate transistor and high-voltage mosfet - Google Patents
Driver for mos gate transistor and high-voltage mosfetInfo
- Publication number
- JP2003198347A JP2003198347A JP2002320420A JP2002320420A JP2003198347A JP 2003198347 A JP2003198347 A JP 2003198347A JP 2002320420 A JP2002320420 A JP 2002320420A JP 2002320420 A JP2002320420 A JP 2002320420A JP 2003198347 A JP2003198347 A JP 2003198347A
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- JP
- Japan
- Prior art keywords
- mosfet
- diode
- mos gate
- region
- driver
- Prior art date
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- 230000001939 inductive effect Effects 0.000 claims abstract description 12
- 230000002441 reversible effect Effects 0.000 claims abstract description 6
- 230000003071 parasitic effect Effects 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 239000000969 carrier Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 5
- 230000004044 response Effects 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 32
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
- H01L29/782—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0416—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/04163—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
Landscapes
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Amplifiers (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、MOSゲートトラン
ジスタ用ドライバおよび高電圧MOSFETに関し、より詳細
には、順方向バイアス下の寄生ダイオードの導通を妨げ
近傍の制御回路への少数キャリアの注入を妨げることを
可能とするMOSゲートトランジスタ用ドライバおよび高
電圧MOSFETに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver for a MOS gate transistor and a high voltage MOSFET, and more particularly, it prevents conduction of a parasitic diode under forward bias and prevents injection of minority carriers into a control circuit in the vicinity thereof. The present invention relates to a driver for a MOS gate transistor and a high voltage MOSFET that enable the above.
【0002】[0002]
【従来の技術】従来より、電力制御回路のローサイドか
つ/またはハイサイドのMOSゲートデバイス用の集積回路
MOSFETドライバが知られており、ハイサイドドライバは
パワーMOSFETのターンオンおよびターンオフを制御し、
パワーMOSFETの負荷への電力の結合を可能にする。2. Description of the Related Art Conventionally, an integrated circuit for a low-side and / or high-side MOS gate device of a power control circuit
MOSFET drivers are known, high-side drivers control the turn-on and turn-off of power MOSFETs,
Allows coupling of power to the load of the power MOSFET.
【0003】この種のハイサイドドライバのチップは、
通常、グラウンド(ground)電位にある本体内に集積化
された第1の複数の制御デバイスを有する単一シリコン
チップで構成される。こうしたチップはまた、グラウン
ドに対して高電位にあるハイサイドフローティングウェ
ル内に含まれる第2の複数の制御デバイスを有する。チ
ップは、VCC(制御電圧)、入力制御ピン、COMM(またはグ
ラウンド)ピンを含むいくつかの入力ピンを有し、これ
らのピンは全てチップの低電圧部内の素子に接続されか
つグラウンドを基準とされている。This kind of high side driver chip is
It usually consists of a single silicon chip with a first plurality of control devices integrated within the body at ground potential. Such a chip also has a second plurality of control devices contained within the high side floating well at a high potential with respect to ground. The chip has several input pins, including V CC (control voltage), input control pin, and COMM (or ground) pin, all of which are connected to elements in the low voltage part of the chip and referenced to ground. It is said that.
【0004】ハイサイドスイッチ(MOSFETまたはIGBT)の
ゲートへの出力は高電圧であるため、入力ピンへの入力
信号は上にレベルシフトされなければならない。これ
は、一般に、集積回路チップ内のハイサイドウェルの回
路によって行われる。ハイサイド回路は、VSピンの電位
に「フロート(floats)」し、VSピンは、普通、ハイサ
イドスイッチ(MOSFETまたはIGBT)のソースに接続され
る。出力ピンHOは、駆動されるハイサイドスイッチのゲ
ートに接続されて駆動信号を供給する。VbおよびVSピン
上の電圧差は、集積回路内のフローティングハイサイド
回路のために電源を供給する。複数のVbsフローティン
グ電源を生成することができる多くの方法が存在し、ブ
ートストラップ技法が最も単純で、費用がかからない。
この技法において、電源は、以下で詳細に説明される図
1に示す高電圧ダイオードとコンデンサによって形成さ
れる。Since the output to the gate of the high side switch (MOSFET or IGBT) is a high voltage, the input signal to the input pin must be level shifted up. This is typically done by high side well circuitry in the integrated circuit chip. High side circuit is to "float (floats) 'to the potential of V S pin, V S pin is usually connected to the high side source of the switch (MOSFET or IGBT). The output pin HO is connected to the gate of the high side switch to be driven and supplies a drive signal. The voltage difference on the V b and V S pins provides the power for the floating high side circuitry within the integrated circuit. There are many ways in which multiple V bs floating supplies can be generated, and the bootstrap technique is the simplest and least expensive.
In this technique, the power supply is described in detail below.
It is formed by the high voltage diode and capacitor shown in 1.
【0005】図1のVSがグラウンド電位の時、ブートス
トラップコンデンサ36は、15VのVCC電源からブートスト
ラップダイオード35を介して充電される。このブースト
ラップコンデンサ36が完全に充電されると、ブートスト
ラップダイオード35が逆バイアスされるために、たとえ
VSピンが高電圧にフロートしたとしてもその電荷が保持
される。ブートストラップコンデンサ36は、駆動される
外部MOSFETをターンオンするのに必要なゲート電荷のみ
ならず、ハイサイド回路用の電源電流も供給する。しか
し、ブートストラップコンデンサ36は、大幅に放電する
前に何らかの手段でリフレッシュされる必要がある。When V S in FIG. 1 is at ground potential, bootstrap capacitor 36 is charged through a bootstrap diode 35 from a 15 V V CC power supply. When this bootstrap capacitor 36 is fully charged, the bootstrap diode 35 is reverse biased,
V S pin also its charge as the float to a high voltage is maintained. The bootstrap capacitor 36 supplies not only the gate charge required to turn on the driven external MOSFET, but also the power supply current for the high side circuit. However, the bootstrap capacitor 36 needs to be refreshed by some means before it is significantly discharged.
【0006】ハイサイドスイッチが抵抗性または誘導性
負荷を駆動する場合には、単にこのスイッチを周期的に
ターンオフしてVS電位が負荷を通してグラウンド(COMM)
電位に降下するのを待つことによって、ブートストラッ
プコンデンサ36は容易にリフレッシュされる。VB電位が
0.7Vにまで降下してVCC未満になると、ブートストラッ
プダイオード35は導通し、ブートストラップコンデンサ
36を再充電する。When the high side switch drives a resistive or inductive load, it is simply turned off periodically so that the V S potential passes through the load to ground (COMM).
By waiting for the potential to drop, the bootstrap capacitor 36 is easily refreshed. V B potential is
When it drops to 0.7V below V CC , bootstrap diode 35 conducts and the bootstrap capacitor
Recharge 36.
【0007】さらに、ハーフブリッジ回路において、ハ
イサイドスイッチ(MOSFETまたはIGBT)をターンオフしロ
ーサイドスイッチ(MOSFETまたはIGBT)をターンオンする
ことでVSはグラウンドに接続されて、ブートストラップ
コンデンサ36が充電される。VB電位がVCCを大幅に下回
る場合、ブートストラップダイオード35が導通し、ブー
ストラップコンデンサ36をリフレッシュする。Further, in the half bridge circuit, V S is connected to the ground by turning off the high side switch (MOSFET or IGBT) and turning on the low side switch (MOSFET or IGBT), and the bootstrap capacitor 36 is charged. . When the V B potential is significantly below V CC , the bootstrap diode 35 conducts and refreshes the bootstrap capacitor 36.
【0008】抵抗性(または誘導性)負荷または同期した
ローサイドスイッチがない場合には、VS電位はハイサイ
ドスイッチがターンオフされるときにグラウンド電位に
自動的に降下できない。こうした状況では、ブートスト
ラップコンデンサ36をリフレッシュするためにVSをグラ
ウンドに接続する内部高電圧MOSFETをゲートドライバIC
に付加することが好ましい。しかし、こうした付加トラ
ンジスタは、多くの用途でしばしば経験されるVSがグラ
ウンド電位より数ボルト下がる(-)VS条件を満たさない
であろうことがわかった。このような(-)VS偏位の間
に、リフレッシュトランジスタの固有の本体ドレインダ
イオードが順導通方向に導通して少数キャリアを生成す
る。これらの少数キャリアは制御回路に注入され、いく
らかの少数キャリアは、ハイサイドフローティングウェ
ル内の近傍レベルシフトFETドレイン領域によって収集
される。これにより少量のドレイン電流が生じ、レベル
シフト回路(特許文献1参照)で使用されるR-Sラッチの誤
動作を生ずる。したがって、HOピンの出力状態は、入力
信号がない場合にもlowからhigh(またはその逆)に変化
することができることとなる。[0008] If there is no resistance (or inductive) loads or synchronized low side switch, V S potential can not automatically drop to ground potential when the high side switch is turned off. In these situations, an internal high voltage MOSFET that connects V S to ground to refresh the bootstrap capacitor 36 is added to the gate driver IC.
Is preferably added to. However, it has been found that such an additional transistor will not meet the (-) V S condition where V S is often experienced in many applications, where V S is a few volts below ground potential. During such a (−) V S excursion, the intrinsic body drain diode of the refresh transistor conducts in the forward conduction direction, generating minority carriers. These minority carriers are injected into the control circuit and some minority carriers are collected by the near level shift FET drain region in the high side floating well. This causes a small amount of drain current, which causes malfunction of the RS latch used in the level shift circuit (see Patent Document 1). Therefore, the output state of the HO pin can change from low to high (or vice versa) even when there is no input signal.
【0009】[0009]
【特許文献1】米国特許第5,545,955号明細書[Patent Document 1] US Pat. No. 5,545,955
【0010】[0010]
【特許文献2】米国特許第4,866,495号明細書[Patent Document 2] US Pat. No. 4,866,495
【0011】[0011]
【発明が解決しようとする課題】したがって、このよう
な集積回路MOSFETドライバにおいては、不正確な制御信
号を発生させる危険性なしで抵抗性/誘導性負荷のない
状態でブートストラップコンデンサをリフレッシュする
ための手段を提供することが望まれる。また、一般のMO
SFETの多くの用途においても、順方向バイアス下の寄生
ダイオードの導通を妨げ近傍の制御回路への少数キャリ
アの注入を妨げることが望まれる。Therefore, in such an integrated circuit MOSFET driver, in order to refresh the bootstrap capacitor in the absence of a resistive / inductive load without the risk of generating an inaccurate control signal. It is desired to provide the means. Also, general MO
In many applications of SFETs as well, it is desirable to prevent the conduction of parasitic diodes under forward bias to prevent minority carrier injection into nearby control circuits.
【0012】本発明の目的は、不正確な制御信号を発生
させる危険性なしで抵抗性/誘導性負荷のない状態でブ
ートストラップコンデンサをリフレッシュすること、お
よび、順方向バイアス下の寄生ダイオードの導通を妨げ
近傍の制御回路への少数キャリアの注入を妨げること、
を可能とするMOSゲートトランジスタ用ドライバおよび
高電圧MOSFETを提供することである。It is an object of the present invention to refresh the bootstrap capacitor in the absence of resistive / inductive loading without the risk of generating an inaccurate control signal and the conduction of parasitic diodes under forward bias. To prevent injection of minority carriers into the control circuit in the vicinity,
It is to provide a driver for a MOS gate transistor and a high-voltage MOSFET that enable the above.
【0013】[0013]
【課題を解決するための手段】本発明は、このような目
的を達成するために主にブートストラップ技法が使用さ
れる用途に向けられるもので、請求項1に記載の発明
は、MOSゲートトランジスタ用ドライバであって、前記
ドライバは、信号入力ピンと、グラウンドピンと、信号
出力ピンと、MOSゲートトランジスタと負荷との間のノ
ードに接続可能なV Sピンと、前記信号入力ピンへの入力
信号を前記信号出力ピンに対して変換する(translate)
レベルシフト回路と、前記VSピンと前記グラウンドピン
との間に接続され固有寄生ダイオードを有する垂直伝導
のリフレッシュMOSFETと、当該リフレッシュMOSFETと直
列に接続されたショットキダイオードとを備え、前記シ
ョットキーダイオードは、前記リフレッシュMOSFETの固
有寄生ダイオードに対して逆極性であることを特徴とす
る。SUMMARY OF THE INVENTION The present invention has the following object.
Bootstrap techniques are mainly used to achieve
The invention according to claim 1, which is directed to the intended use.
Is a driver for a MOS gate transistor,
The driver has a signal input pin, a ground pin, and a signal
The node between the output pin and the MOS gate transistor and load.
V that can be connected to SPin and input to the signal input pin
Translate the signal to the signal output pin
Level shift circuit and VSPin and the ground pin
Vertical conduction with intrinsic parasitic diode connected between and
Of the refresh MOSFET and
A Schottky diode connected to the column,
The hotkey diode is a fixed MOSFET of the refresh MOSFET.
Characterized by having a reverse polarity with respect to a parasitic diode
It
【0014】また、請求項2に記載の発明は、請求項1
に記載のMOSゲートトランジスタ用ドライバにおいて、
前記MOSゲートトランジスタ用ドライバはシリコンチッ
プ内の集積回路であり、前記シリコンチップは低電圧領
域とハイサイドフローティングウェルとを有し、前記レ
ベルシフト回路は前記フローティングウェル内に集積化
されており、前記リフレッシュMOSFETおよび前記ショト
キーダイオードは前記低電圧領域内に集積化されている
ことを特徴とする。The invention described in claim 2 is the same as claim 1
In the driver for the MOS gate transistor described in
The MOS gate transistor driver is an integrated circuit in a silicon chip, the silicon chip has a low voltage region and a high side floating well, and the level shift circuit is integrated in the floating well. The refresh MOSFET and the Schottky diode are integrated in the low voltage region.
【0015】また、請求項3に記載の発明は、請求項1
または2に記載のMOSゲートトランジスタ用ドライバにお
いて、前記MOSゲートトランジスタ用ドライバにより制
御されるMOSゲートトランジスタは非抵抗性かつ非誘導
性の負荷と直列に接続されており、前記リフレッシュMO
SFETは前記MOSゲートトランジスタがターンオフする時
にターンオンし、当該リフレッシュMOSFETのターンオン
により前記負荷の蓄積電荷が当該リフレッシュMOSFETを
通って放電されることを特徴とする。The invention described in claim 3 is the same as that of claim 1.
Alternatively, in the MOS gate transistor driver according to 2, the MOS gate transistor controlled by the MOS gate transistor driver is connected in series with a non-resistive and non-inductive load, and the refresh MO
The SFET is turned on when the MOS gate transistor is turned off, and the charge stored in the load is discharged through the refresh MOSFET when the refresh MOSFET is turned on.
【0016】また、請求項4に記載の発明は、請求項1
に記載のMOSゲートトランジスタ用ドライバにおいて、
前記リフレッシュMOSFETは、大電圧降下本体ドレインダ
イオード(large voltage drop body drain diode)を
有する高電圧MOSFETであり、前記リフレッシュMOSFET
は、横方向に離して配置されたソース領域およびドレイ
ン領域とその表面濃度が反転するときに前記ソース領域
と前記ドレイン領域との間のキャリアの伝導を可能にす
るように作動可能な反転可能な横方向のチャンネル領域
とを有するシリコン本体と、MOSゲート構造であって前
記チャンネル領域に接続され前記MOSゲート構造へのゲ
ート信号に応答して前記チャンネル領域を反転させるよ
うに作動可能なMOSゲート構造と、前記ソース領域およ
び前記ドレイン領域にそれぞれ接続された金属ソース接
点および金属ドレイン接点とを備え、前記ソース領域と
前記ドレイン領域の少なくとも一方は、前記金属ソース
接点と前記金属ドレイン接点との間でショットキーダイ
オードを規定するのに充分に低い不純物濃度を有してい
ることを特徴とする。The invention according to claim 4 is the same as claim 1
In the driver for the MOS gate transistor described in
The refresh MOSFET is a high voltage MOSFET having a large voltage drop body drain diode.
Are invertible operable to enable conduction of carriers between the source and drain regions and the laterally spaced source and drain regions when their surface concentration is inverted. A silicon body having a lateral channel region, a MOS gate structure connected to the channel region and operable to invert the channel region in response to a gate signal to the MOS gate structure. And a metal source contact and a metal drain contact respectively connected to the source region and the drain region, wherein at least one of the source region and the drain region is between the metal source contact and the metal drain contact. It is characterized by having an impurity concentration low enough to define a Schottky diode.
【0017】さらに、請求項5に記載の発明は、請求項
4に記載のMOSゲートトランジスタ用ドライバにおいて、
前記リフレッシュMOSFETは固有寄生ダイオードを有し、
前記ショットキーダイオードは前記固有寄生ダイオード
と逆極性であることを特徴とする。Further, the invention according to claim 5 is
In the driver for the MOS gate transistor described in 4,
The refresh MOSFET has an intrinsic parasitic diode,
The Schottky diode has a polarity opposite to that of the intrinsic parasitic diode.
【0018】請求項6に記載の発明は、大電圧降下本体
ドレインダイオード(large voltage drop body drain
diode)を有する高電圧MOSFETであって、当該高電圧MOS
FETは、横方向に離して配置されたソース領域およびド
レイン領域とその表面濃度が反転するときに前記ソース
領域と前記ドレイン領域との間のキャリアの伝導を可能
にするように作動可能な反転可能な横方向のチャンネル
領域とを有するシリコン本体と、MOSゲート構造であっ
て前記チャンネル領域に接続され前記MOSゲート構造へ
のゲート信号に応答して前記チャンネル領域を反転させ
るように作動可能なMOSゲート構造と、前記ソース領域
および前記ドレイン領域にそれぞれ接続された金属ソー
ス接点および金属ドレイン接点とを備え、前記ソース領
域と前記ドレイン領域の少なくとも一方は、前記金属ソ
ース接点と前記金属ドレイン接点との間でショットキー
ダイオードを規定するのに充分に低い不純物濃度を有し
ていることを特徴とする。The invention according to claim 6 is a large voltage drop body drain diode.
high voltage MOSFET having a diode)
The FET is invertible operable to enable conduction of carriers between the source and drain regions and their laterally spaced source and drain regions when their surface concentration is inverted. A silicon body having a lateral channel region and a MOS gate structure connected to the channel region and operable to invert the channel region in response to a gate signal to the MOS gate structure. A metal source contact and a metal drain contact respectively connected to the source region and the drain region, wherein at least one of the source region and the drain region is between the metal source contact and the metal drain contact. Is characterized by having a sufficiently low impurity concentration to define a Schottky diode.
【0019】また、請求項7に記載の発明は、請求項6
に記載の高電圧MOSFETにおいて、前記高電圧MOSFETは固
有寄生ダイオードを有し、前記ショットキーダイオード
は前記固有寄生ダイオードと逆極性であることを特徴と
する。The invention according to claim 7 is the same as claim 6
The high-voltage MOSFET as described in 1 above, wherein the high-voltage MOSFET has an intrinsic parasitic diode, and the Schottky diode has a polarity opposite to that of the intrinsic parasitic diode.
【0020】[0020]
【発明の実施の形態】以下に図面を参照して、本発明の
実施の形態について説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【0021】図1は、低電圧部21およびハイサイドフロ
ーティングウェル22を有するハイサイドドライバチップ
20の本発明の関連部分を示す図で、このチップは例えば
シリコンチップであって、低電圧部21は、それぞれ、V
CC(15ボルト)ピン23、入力信号ピン24およびCOMM(グラ
ウンド)ピン25を有する。ハイサイドフローティングウ
ェル22は、それぞれ、フローティング電源の(+)veであ
るVBピン30、HO出力ピン31、およびフローティング電源
の(-)veであるVSピン32を有し、たとえば、グラウンド
に対して0から200ボルトの間を振れる。VBピン30の電位
VBは、たとえば、VB=VS+15ボルトに設定される。COMMピ
ン25の電位は、通常、負荷に対する戻り端子と同じであ
る。FIG. 1 shows a high side driver chip having a low voltage section 21 and a high side floating well 22.
FIG. 20 is a view showing relevant portions of the present invention of 20, wherein the chip is, for example, a silicon chip, and the low voltage portion 21 is
It has a CC (15 volt) pin 23, an input signal pin 24 and a COMM (ground) pin 25. The high side floating well 22 has a V B pin 30 which is (+) v e of the floating power supply, a HO output pin 31, and a V S pin 32 which is the (-) v e of the floating power supply, respectively, for example, Can swing between 0 and 200 volts with respect to ground. V B Pin 30 potential
V B is set to, for example, V B = V S +15 volts. The potential on COMM pin 25 is usually the same as the return terminal to the load.
【0022】ブートストラップダイオード35は、VCCピ
ン23とVBピン30の間に接続され、ブートストラップコン
デンサ36は、VBピン30とVSピン32の間に接続される。バ
イパスコンデンサ37は、VCCピン23とCOMM25の間に接続
される。Bootstrap diode 35 is connected between V CC pin 23 and V B pin 30, and bootstrap capacitor 36 is connected between V B pin 30 and V S pin 32. Bypass capacitor 37 is connected between V CC pin 23 and COMM 25.
【0023】主MOSゲート制御デバイスは、高電圧電源4
1に接続され、また負荷42に接続された例えばパワーMOS
FETであるMOSFET40として示される。負荷42は任意のタ
イプの負荷で、ハイサイドドライバチップ20およびHO出
力ピン31の入力信号によって制御されるMOSFET40のパル
ス周波数変調によって制御される。The main MOS gate control device is a high voltage power supply 4
For example, a power MOS connected to 1 and to load 42
Shown as MOSFET 40, which is a FET. Load 42 is any type of load and is controlled by pulse frequency modulation of MOSFET 40, which is controlled by the input signals at high side driver chip 20 and HO output pin 31.
【0024】負荷42が抵抗性または誘導性でない場合
は、VSピン32をCOMMピン25に接続することによってブー
トストラップコンデンサ36を再充電するリフレッシュト
ランジスタを提供するのが望ましいであろう。しかし、
説明した回路において、VSは、一時的にCOMMより数ボル
ト下がる可能性がある。このことが起こると、リフレッ
シュトランジスタの本体ドレインダイオードは順方向バ
イアスされ、少数キャリアが制御回路内に注入されて誤
動作または破壊的なラッチアップ故障さえも引き起こ
す。If the load 42 is not resistive or inductive, it would be desirable to provide a refresh transistor that recharges the bootstrap capacitor 36 by connecting V S pin 32 to COMM pin 25. But,
In the circuit described, V S can be temporarily several volts below COM M. When this happens, the body drain diode of the refresh transistor is forward biased and minority carriers are injected into the control circuit, causing malfunction or even catastrophic latch-up failure.
【0025】ブートストラップコンデンサ36は、VCCか
らブーストラップダイオード35を通してリフレッシュさ
れなければならない。したがって、ブーストラップコン
デンサ36が充電されるために、VBはVCC未満でなければ
ならない。VBがVCCより高くなる場合には、ブーストラ
ップコンデンサ36はブーストラップダイオード35の阻止
動作によって放電しないであろう。しかし、ブーストラ
ップコンデンサ36は放電する傾向を有し、充電すなわち
リフレッシュされなければならない。ブーストラップコ
ンデンサ36を充電する回路は、バイパスコンデンサ37(1
5ボルト)、VCCピン23、ブーストラップダイオード35、
ブーストラップコンデンサ36、VSピン32そしてCOMMピン
25に戻る直列回路を含むことに注目されたい。Bootstrap capacitor 36 must be refreshed from V CC through bootstrap diode 35. Therefore, V B must be less than V CC for bootstrap capacitor 36 to be charged. If V B goes above V CC , bootstrap capacitor 36 will not discharge due to the blocking action of bootstrap diode 35. However, bootstrap capacitor 36 has a tendency to discharge and must be charged or refreshed. The circuit that charges the bootstrap capacitor 36 is
5 V), V CC pin 23, bootstrap diode 35,
Bootstrap capacitor 36, V S pin 32 and COMM pin
Note that it includes a series circuit back to 25.
【0026】負荷42が抵抗性または誘導性である場合
は、ブートストラップコンデンサ36が単にMOSFET40をタ
ーンオフすることによってリフレッシュされるため、リ
フレッシュトランジスタは必要とされない。次に、負荷
42自体は、VSピン32をグラウンド電位に接続し、それに
よって、VB電位がブートストラップダイオード35の導通
を通してほぼVCC電位に達する。しかし、負荷42がたと
えば容量性である、すなわち、そうでなければ抵抗性で
も誘導性でもない場合は、MOSFET40がターンオフすると
きにノードVSはすぐにはグラウンド電位に落ちないであ
ろう。したがって、ブートストラップコンデンサ36は、
必要とされているようにはリフレッシュされない。If the load 42 is resistive or inductive, the refresh transistor is not needed because the bootstrap capacitor 36 is refreshed by simply turning off MOSFET 40. Then load
42 itself connects V S pin 32 to ground potential, which causes the V B potential to reach approximately the V CC potential through the conduction of bootstrap diode 35. However, if the load 42 is, for example, capacitive, that is, otherwise neither resistive nor inductive, then node V S will not immediately fall to ground potential when MOSFET 40 turns off. Therefore, the bootstrap capacitor 36 is
Not refreshed as needed.
【0027】負荷42が抵抗性または誘導性である場合
は、MOSFET40がターンオフするときにVSピン32の電位は
負にならないため、ブートストラップコンデンサ36をリ
フレッシュするために本発明の新規構造は必要とされな
い。すなわち、VBがVCCより下がる場合はVSはゼロにな
るため、ブーストラップダイオード35は、ダイオード順
方向電圧降下を超えた後に導通するであろう。しかし、
負荷42がたとえば容量性である場合は、MOSFET40がター
ンオフするとき、VSのノードはすぐにゼロボルトに落ち
ないであろう。したがって、ブートストラップコンデン
サ36は必要とされているようにはリフレッシュされな
い。If the load 42 is resistive or inductive, the potential of the V S pin 32 will not be negative when the MOSFET 40 is turned off, so the novel structure of the present invention is needed to refresh the bootstrap capacitor 36. Not taken That is, since V S is zero when V B falls below V CC , bootstrap diode 35 will conduct after exceeding the diode forward voltage drop. But,
If load 42 is, for example, capacitive, the node at V S will not immediately drop to zero volts when MOSFET 40 turns off. Therefore, the bootstrap capacitor 36 is not refreshed as needed.
【0028】この問題を解決し、ブートストラップコン
デンサ36の継続したリフレッシュ動作を確実に行うため
に、垂直伝導のリフレッシュMOSFET60が、ディスクリー
ト部品としてまたはシリコンに集積化されて図1の回路
に付加され、VSからCOMMに接続される。リフレッシュMO
SFET60の目的は、VSをVCOMMに近づけることである。
今、主MOSゲート制御デバイスであるMOSFET40(パワーMO
SFETまたはIGBT)がターンオフするとき、リフレッシュM
OSFET60をターンオンすることによって、VSピン32の電
位を適当にグラウンドに接続することができる。しか
し、リフレッシュMOSFET60は、寄生ダイオード61を有し
ており、この寄生ダイオード61は、VSが約(-)0.5ボルト
未満に下がるとすぐにターンオンし、次に、少数キャリ
アが制御回路内に注入されるであろう。In order to solve this problem and ensure a continuous refresh operation of the bootstrap capacitor 36, a vertical conduction refresh MOSFET 60 is added to the circuit of FIG. 1 either as a discrete component or integrated in silicon, Connected from V S to COMM. Refresh MO
The purpose of SFET60 is to bring V S closer to V COMM .
Now, MOSFET 40 (Power MO
When the SFET or IGBT) turns off, refresh M
Turning on OSFET60 allows the potential on V S pin 32 to be properly connected to ground. However, the refresh MOSFET 60 does have a parasitic diode 61 that turns on as soon as V S drops below about (-) 0.5 volts, and then minority carriers are injected into the control circuit. Will be done.
【0029】本発明によれば、ショットキーダイオード
62は、リフレッシュMOSFET60の寄生ダイオード61の順方
向導通を阻止する方向に、リフレッシュMOSFET60と直列
に接続される。ショットキーダイオード62の付加によっ
て、リフレッシュMOSFET60回路のオン抵抗が少し増える
が、リフレッシュMOSFET60およびショットキーダイオー
ド62がハイサイドドライバチップ20に集積化されると、
VSノードの電位(VSピン32の電位)がCOMMの電位(COMMピ
ン25の電位)を数ボルト下まわるとき、少数キャリアは
制御回路内に注入されない。According to the present invention, a Schottky diode
The refresh MOSFET 60 is connected in series with the refresh MOSFET 60 so as to prevent the parasitic diode 61 of the refresh MOSFET 60 from conducting in the forward direction. Although the addition of the Schottky diode 62 slightly increases the on-resistance of the refresh MOSFET 60 circuit, when the refresh MOSFET 60 and the Schottky diode 62 are integrated in the high side driver chip 20,
Minority carriers are not injected into the control circuit when the potential on the V S node (the potential on V S pin 32) is below the potential on COMM (the potential on COMM pin 25) by a few volts.
【0030】図2は、リフレッシュMOSFET60およびショ
ットキーダイオード62の一実施形態を示すための図で、
この図に示したデバイスは、ショットキー接触をN-シリ
コンに対して行うようにドレイン接続用のN+接触が除去
されていることを除いて、公知のハイサイドスイッチ用
の横型MOSトランジスタと同じである(例えば、特許文献
2参照)。したがって、図2では、低電圧部21のチップエ
リアを、その上にN-エピタキシャル層100を有するP-領
域として示す。低電圧部21のチップエリアは、P +シンカ
ー(sinker)101および102によって、ハイサイドフローテ
ィングウェルおよび/または他の素子から分離されてい
る。P-リサーフ(resurf)拡散領域105、106、107および1
08は、チップ上部表面のフィールド酸化膜109の下部領
域に形成される。深いP+領域110および111を有する、離
れて配置されたP-チャンネル拡散領域は、それぞれのN+
ソース領域112および113を含み、ゲート酸化膜およびポ
リシリコンゲート114によって覆われる。伝導性のポリ
シリコンゲート114は、層間酸化物115によってソース接
点116から絶縁される。ドレイン接点120および121は、N
+接点領域よりむしろN-シリコン100に直接に接続される
(例えば、特許文献2参照)。ソース接点116のようなドレ
イン接点120および121は、アルミニウムで作られ、ショ
ットキーダイオード62を規定するようにN-エピタキシャ
ル層100へのショットキー接続を形成する。FIG. 2 shows the refresh MOSFET 60 and the short circuit.
FIG. 6 is a diagram for showing one embodiment of the Tokukey diode 62,
The device shown in this figure has N Schottky contacts.-Siri
N for drain connection as you do for con+Contact removed
For known high-side switches, except that
Same as the lateral MOS transistor of
2). Therefore, in FIG. 2, the chip voltage of the low voltage section 21 is
Rear, N on it-P with epitaxial layer 100-Territory
Shown as a zone. The chip area of the low voltage part 21 is P +Sinker
(Sinker) 101 and 102 enable high side float
Separated from the swingwell and / or other components
It P-Resurf diffusion areas 105, 106, 107 and 1
08 is the lower region of the field oxide film 109 on the upper surface of the chip.
Formed in the area. Deep P+With regions 110 and 111,
Placed P-The channel diffusion area is N+
Source regions 112 and 113, including gate oxide and porosity.
Covered by a silicon gate 114. Conductive poly
The silicon gate 114 is connected to the source by the interlayer oxide 115.
Isolated from point 116. The drain contacts 120 and 121 are N
+N rather than contact area-Connected directly to Silicon 100
(See, for example, Patent Document 2). Drain like source contact 116
The in-contacts 120 and 121 are made of aluminum and are
T-key diode 62 to specify N-Epitaxia
A Schottky connection to layer 100.
【0031】すなわちこのリフレッシュMOSFET60は、例
えば、大電圧降下本体ドレインダイオード(large volt
age drop body drain diode)を有する高電圧MOSFETで
あり、表面濃度が反転するときにソース領域とドレイン
領域との間のキャリアの伝導を可能にするように作動可
能な反転可能な横方向のチャンネル領域をシリコンエピ
層に有しており、ソース領域とドレイン領域の少なくと
も一方は、金属ソース接点と金属ドレイン接点との間で
ショットキーダイオードを規定するのに充分に低い不純
物濃度を有している。That is, the refresh MOSFET 60 is, for example, a large voltage drop body drain diode (large volt).
high voltage MOSFET with an age drop body drain diode), which is operable to enable conduction of carriers between the source region and the drain region when the surface concentration is reversed, and a reversible lateral channel region. In the silicon epilayer and at least one of the source and drain regions has an impurity concentration low enough to define a Schottky diode between the metal source contact and the metal drain contact.
【0032】リフレッシュMOSFET60が信号オンゲートで
あるポリシリコンゲート114によってターンオンすると
き、電流Iは図中に矢印で示したように、N-エピタキシ
ャル層100内のチャネルエリアの下を通って、ドレイン
接点120および121へと流れる。When the refresh MOSFET 60 is turned on by the polysilicon gate 114, which is the signal on gate, the current I passes under the channel area in the N - epitaxial layer 100, as indicated by the arrow in the figure, and the drain contact 120. And flows to 121.
【0033】本発明は、その特定の実施形態に関連して
説明されたが、当業者には多くの他の変形形態および変
更形態および他の用途が明らかになるであろう。したが
って、本発明は、本明細書の特定の開示によって限定さ
れるものではない。Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the present invention is not limited by the specific disclosure herein.
【0034】[0034]
【発明の効果】以上説明したように、本発明では、ブー
トストラップコンデンサをリフレッシュするために、VS
ピンをグラウンドに接続するために用いられるリフレッ
シュMOSFETとショットキーダイオードとが直列に配置さ
れる。そして、これらのリフレッシュMOSFETとショット
キーダイオードとはチップ内に集積化可能であり、ショ
ットキーダイオードはリフレッシュMOSFETのドレインと
直列に接続できる。このようなショットキーダイオード
は、そのオン状態中にリフレッシュMOSFETのVDS( ON)に
対しておよそ0.5ボルトの電圧降下を付加するように作
動するが、逆方向では、阻止電圧が(-)0.5ボルトから約
(-)8ボルトまで増加する。したがって、VSが(-)veに下
がるとき、すなわち、従来であれば本体ドレインダイオ
ードが導通し始め少数キャリアをハイサイドウェル内に
注入するときに、デバイス本体ダイオードは導通しない
こととなる。As described above, in the present invention, in order to refresh the bootstrap capacitor, V S
A refresh MOSFET and a Schottky diode used to connect the pin to ground are placed in series. The refresh MOSFET and the Schottky diode can be integrated in a chip, and the Schottky diode can be connected in series with the drain of the refresh MOSFET. Such a Schottky diode operates to add a voltage drop of approximately 0.5 V to the refresh MOSFET's V DS ( ON) during its on-state, but in the reverse direction, the blocking voltage is (-) 0.5. About from bolt
(-) Increase to 8 volts. Therefore, when V S drops to (−) v e , that is, when the body drain diode starts to conduct in the conventional case and minority carriers are injected into the high side well, the device body diode does not conduct.
【0035】このように本発明によれば、不正確な制御
信号を発生する危険性を伴うことなく抵抗性/誘導性負
荷のない状態でブートストラップコンデンサをリフレッ
シュする手段を提供することが可能となる。また、一般
のMOSFETの多くの用途においても、順方向バイアス下の
寄生ダイオードの導通を妨げ近傍の制御回路への少数キ
ャリアの注入を妨げることが可能となる。As described above, according to the present invention, it is possible to provide a means for refreshing the bootstrap capacitor without a resistive / inductive load without the risk of generating an inaccurate control signal. Become. Further, in many applications of general MOSFETs, it is possible to prevent conduction of a parasitic diode under forward bias and prevent injection of minority carriers into a control circuit in the vicinity.
【図1】低電圧部およびハイサイドフローティングウェ
ルを有するハイサイドドライバチップの本発明の関連部
分を説明するための図である。FIG. 1 is a diagram for explaining a relevant part of the present invention of a high side driver chip having a low voltage part and a high side floating well.
【図2】リフレッシュMOSFETおよびショットキーダイオ
ードの一実施形態を示すための図である。FIG. 2 is a diagram showing one embodiment of a refresh MOSFET and a Schottky diode.
20 ハイサイドドライバチップ 21 低電圧部 22 ハイサイドフローティングウェル 23 VCC(15ボルト)ピン 24 入力信号ピン 25 COMM(グラウンド)ピン 30 VBピン 31 HO出力ピン 32 VSピン 35 ブートストラップダイオード 36 ブートストラップコンデンサ 37 バイパスコンデンサ 40 MOSFET 41 高電圧電源 42 負荷 60 リフレッシュMOSFET 61 寄生ダイオード 62 ショットキーダイオード 100 N-エピタキシャル層 101,102 P+シンカー 105,106,107,108 P-リサーフ拡散領域 109 フィールド酸化膜 110,111 深いP+領域 112,113 N+ソース領域 114 ポリシリコンゲート 115 層間酸化物 116 ソース接点 120,121 ドレイン接点20 High Side Driver Chip 21 Low Voltage Section 22 High Side Floating Well 23 V CC (15 Volts) Pin 24 Input Signal Pin 25 COMM (Ground) Pin 30 V B Pin 31 HO Output Pin 32 V S Pin 35 Bootstrap Diode 36 Boot Strap capacitor 37 Bypass capacitor 40 MOSFET 41 High voltage power supply 42 Load 60 Refresh MOSFET 61 Parasitic diode 62 Schottky diode 100 N - Epitaxial layer 101,102 P + sinker 105,106,107,108 P - Resurf diffusion region 109 Field oxide film 110,111 Deep P + region 112,113 N + Source region 114 Polysilicon gate 115 Interlayer oxide 116 Source contact 120,121 Drain contact
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 29/872 H03K 17/687 (72)発明者 ニラジ ランジャン アメリカ合衆国 90246 カリフォルニア 州 エル セグンド ロマ ビスタ 124 ナンバービー Fターム(参考) 4M104 BB01 BB02 CC03 GG03 5F048 AA03 AA05 AC06 AC10 BA02 BA07 BC03 BC05 BC18 BF16 BH05 5F140 AA00 AB06 AC21 BA16 BF01 BF04 BH30 BJ01 BJ05 BJ30 DA01 DA08 5J055 AX47 BX16 CX07 DX09 DX22 EX07 EY10 EY12 EY13 EY21 EY29 EZ67 FX04 FX12 FX27 FX33 FX34 GX01 GX07 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 7 Identification code FI Theme Coat (reference) H01L 29/872 H03K 17/687 (72) Inventor Niraji Lanjan USA 90246 El Segundo Loma Vista 124 Number B F Terms (reference) 4M104 BB01 BB02 CC03 GG03 5F048 AA03 AA05 AC06 AC10 BA02 BA07 BC03 BC05 BC18 BF16 BH05 5F140 AA00 AB06 AC21 BA16 BF01 BF04 BH30 BJ01 BJ05 BJ30 FX21 EY27 EYE BX17 EX12 BX16 EX12 DX09 C07 DX07 C07 FX33 FX34 GX01 GX07
Claims (7)
って、 前記ドライバは、信号入力ピンと、グラウンドピンと、
信号出力ピンと、MOSゲートトランジスタと負荷との間
のノードに接続可能なVSピンと、前記信号入力ピンへの
入力信号を前記信号出力ピンに対して変換する(transla
te)レベルシフト回路と、前記VSピンと前記グラウンド
ピンとの間に接続され固有寄生ダイオードを有する垂直
伝導のリフレッシュMOSFETと、当該リフレッシュMOSFET
と直列に接続されたショットキダイオードとを備え、 前記ショットキーダイオードは、前記リフレッシュMOSF
ETの固有寄生ダイオードに対して逆極性であることを特
徴とするMOSゲートトランジスタ用ドライバ。1. A driver for a MOS gate transistor, the driver comprising a signal input pin, a ground pin, and
A signal output pin, a V S pin connectable to a node between a MOS gate transistor and a load, and an input signal to the signal input pin is converted to the signal output pin (transla).
te) the level shift circuit, and the refresh MOSFET vertical conduction with the connected specific parasitic diode between the ground pin and the V S pin, the refresh MOSFET
And a Schottky diode connected in series to the refresh MOSF.
A driver for a MOS gate transistor, which has a reverse polarity with respect to the intrinsic parasitic diode of ET.
はシリコンチップ内の集積回路であり、前記シリコンチ
ップは低電圧領域とハイサイドフローティングウェルと
を有し、前記レベルシフト回路は前記フローティングウ
ェル内に集積化されており、前記リフレッシュMOSFETお
よび前記ショトキーダイオードは前記低電圧領域内に集
積化されていることを特徴とする請求項1に記載のMOSゲ
ートトランジスタ用ドライバ。2. The driver for the MOS gate transistor is an integrated circuit in a silicon chip, the silicon chip has a low voltage region and a high side floating well, and the level shift circuit is integrated in the floating well. 2. The driver for a MOS gate transistor according to claim 1, wherein the refresh MOSFET and the Schottky diode are integrated in the low voltage region.
により制御されるMOSゲートトランジスタは非抵抗性か
つ非誘導性の負荷と直列に接続されており、前記リフレ
ッシュMOSFETは前記MOSゲートトランジスタがターンオ
フする時にターンオンし、当該リフレッシュMOSFETのタ
ーンオンにより前記負荷の蓄積電荷が当該リフレッシュ
MOSFETを通って放電されることを特徴とする請求項1ま
たは2に記載のMOSゲートトランジスタ用ドライバ。3. A MOS gate transistor controlled by the driver for the MOS gate transistor is connected in series with a non-resistive and non-inductive load, and the refresh MOSFET turns on when the MOS gate transistor turns off. , The charge accumulated in the load is refreshed by turning on the refresh MOSFET.
3. The driver for a MOS gate transistor according to claim 1, which is discharged through a MOSFET.
本体ドレインダイオード(large voltage drop body dr
ain diode)を有する高電圧MOSFETであり、 前記リフレッシュMOSFETは、横方向に離して配置された
ソース領域およびドレイン領域とその表面濃度が反転す
るときに前記ソース領域と前記ドレイン領域との間のキ
ャリアの伝導を可能にするように作動可能な反転可能な
横方向のチャンネル領域とを有するシリコン本体と、MO
Sゲート構造であって前記チャンネル領域に接続され前
記MOSゲート構造へのゲート信号に応答して前記チャン
ネル領域を反転させるように作動可能なMOSゲート構造
と、前記ソース領域および前記ドレイン領域にそれぞれ
接続された金属ソース接点および金属ドレイン接点とを
備え、 前記ソース領域と前記ドレイン領域の少なくとも一方
は、前記金属ソース接点と前記金属ドレイン接点との間
でショットキーダイオードを規定するのに充分に低い不
純物濃度を有していることを特徴とする請求項1に記載
のMOSゲートトランジスタ用ドライバ。4. The refresh MOSFET is a large voltage drop body drain diode.
a refreshing MOSFET having a source diode and a drain region laterally spaced apart from each other and carriers between the source region and the drain region when the surface concentration thereof is inverted. A silicon body having an invertible lateral channel region operable to allow conduction of the MO;
An S gate structure connected to the channel region and operable to invert the channel region in response to a gate signal to the MOS gate structure, and the MOS gate structure connected to the source region and the drain region, respectively. A metal source contact and a metal drain contact, wherein at least one of the source region and the drain region is sufficiently low in impurities to define a Schottky diode between the metal source contact and the metal drain contact. The driver for a MOS gate transistor according to claim 1, wherein the driver has a concentration.
オードを有し、前記ショットキーダイオードは前記固有
寄生ダイオードと逆極性であることを特徴とする請求項
4に記載のMOSゲートトランジスタ用ドライバ。5. The refresh MOSFET has an intrinsic parasitic diode, and the Schottky diode has a polarity opposite to that of the intrinsic parasitic diode.
Driver for MOS gate transistor described in 4.
rge voltage drop body drain diode)を有する高電圧M
OSFETであって、 当該高電圧MOSFETは、横方向に離して配置されたソース
領域およびドレイン領域とその表面濃度が反転するとき
に前記ソース領域と前記ドレイン領域との間のキャリア
の伝導を可能にするように作動可能な反転可能な横方向
のチャンネル領域とを有するシリコン本体と、MOSゲー
ト構造であって前記チャンネル領域に接続され前記MOS
ゲート構造へのゲート信号に応答して前記チャンネル領
域を反転させるように作動可能なMOSゲート構造と、前
記ソース領域および前記ドレイン領域にそれぞれ接続さ
れた金属ソース接点および金属ドレイン接点とを備え、 前記ソース領域と前記ドレイン領域の少なくとも一方
は、前記金属ソース接点と前記金属ドレイン接点との間
でショットキーダイオードを規定するのに充分に低い不
純物濃度を有していることを特徴とする高電圧MOSFET。6. A large voltage drop body drain diode (la
high voltage M with rge voltage drop body drain diode)
An OSFET, wherein the high-voltage MOSFET enables conduction of carriers between the source region and the drain region when the surface concentration of the source region and the drain region that are laterally separated is reversed. A silicon body having an invertible lateral channel region operable to operate, and a MOS gate structure connected to the channel region.
A MOS gate structure operable to invert the channel region in response to a gate signal to a gate structure; and a metal source contact and a metal drain contact connected to the source region and the drain region, respectively. At least one of the source region and the drain region has an impurity concentration low enough to define a Schottky diode between the metal source contact and the metal drain contact. .
を有し、前記ショットキーダイオードは前記固有寄生ダ
イオードと逆極性であることを特徴とする請求項6に記
載の高電圧MOSFET。7. The high voltage MOSFET according to claim 6, wherein the high voltage MOSFET has an intrinsic parasitic diode, and the Schottky diode has a polarity opposite to that of the intrinsic parasitic diode.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/045,451 US6529034B1 (en) | 2001-11-07 | 2001-11-07 | Integrated series schottky and FET to allow negative drain voltage |
US10/045,451 | 2001-11-07 |
Related Child Applications (1)
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JP2006162698A Division JP4485490B2 (en) | 2001-11-07 | 2006-06-12 | MOS gate transistor driver and high voltage MOSFET |
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JP2003198347A true JP2003198347A (en) | 2003-07-11 |
JP3857216B2 JP3857216B2 (en) | 2006-12-13 |
Family
ID=21937951
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JP2002320420A Expired - Fee Related JP3857216B2 (en) | 2001-11-07 | 2002-11-01 | MOS gate transistor driver and high voltage MOSFET |
JP2006162698A Expired - Lifetime JP4485490B2 (en) | 2001-11-07 | 2006-06-12 | MOS gate transistor driver and high voltage MOSFET |
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---|---|
US (2) | US6529034B1 (en) |
EP (1) | EP1311067B1 (en) |
JP (2) | JP3857216B2 (en) |
AT (1) | ATE322764T1 (en) |
DE (1) | DE60210393T2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8536847B2 (en) | 2011-09-14 | 2013-09-17 | Mitsubishi Electric Corporation | Semiconductor device |
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US6835619B2 (en) * | 2002-08-08 | 2004-12-28 | Micron Technology, Inc. | Method of forming a memory transistor comprising a Schottky contact |
US6987305B2 (en) * | 2003-08-04 | 2006-01-17 | International Rectifier Corporation | Integrated FET and schottky device |
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US7829928B2 (en) * | 2006-06-26 | 2010-11-09 | System General Corp. | Semiconductor structure of a high side driver and method for manufacturing the same |
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-
2002
- 2002-11-01 JP JP2002320420A patent/JP3857216B2/en not_active Expired - Fee Related
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2003
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US8536847B2 (en) | 2011-09-14 | 2013-09-17 | Mitsubishi Electric Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
ATE322764T1 (en) | 2006-04-15 |
DE60210393T2 (en) | 2007-01-11 |
EP1311067A1 (en) | 2003-05-14 |
EP1311067B1 (en) | 2006-04-05 |
JP2006311594A (en) | 2006-11-09 |
DE60210393D1 (en) | 2006-05-18 |
JP4485490B2 (en) | 2010-06-23 |
US20030102886A1 (en) | 2003-06-05 |
US6529034B1 (en) | 2003-03-04 |
US6707101B2 (en) | 2004-03-16 |
JP3857216B2 (en) | 2006-12-13 |
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