JP2003197741A - Method for manufacturing multilayer circuit board - Google Patents
Method for manufacturing multilayer circuit boardInfo
- Publication number
- JP2003197741A JP2003197741A JP2001394257A JP2001394257A JP2003197741A JP 2003197741 A JP2003197741 A JP 2003197741A JP 2001394257 A JP2001394257 A JP 2001394257A JP 2001394257 A JP2001394257 A JP 2001394257A JP 2003197741 A JP2003197741 A JP 2003197741A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating
- pad
- forming
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、金属配線と絶縁樹
脂層とを交互に積層して多層回路基板を製造する際、ダ
マシン法などで用いられている研磨プロセスを必要とす
ることなく、微細化及び平坦化した多層配線を実現する
為の多層回路基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microfabrication method which does not require a polishing process used in a damascene method when a metal wiring and an insulating resin layer are alternately laminated to manufacture a multilayer circuit board. The present invention relates to a method for manufacturing a multilayer circuit board for realizing a standardized and flattened multilayer wiring.
【０００２】[0002]
【従来の技術】多層回路基板を製造する場合、樹脂材料
の形態及び特性に依って多層化プロセスが相違し、例え
ばＭＣＭ−Ｄ（ｍｕｌｔｉ ｃｈｉｐ ｍｏｄｕｌｅ
ｄｅｐｏｓｉｔｅｄ ｔｈｉｎ ｆｉｌｍ ｓｕｂｓｔ
ｒａｔｅ）と呼ばれ、フォト・ビア開口の形成、スパッ
タリング法、電解めっき法を利用して配線を形成するこ
とが特徴になっているプロセスが知られている（例え
ば、特開平７−１４７４８３号公報、特開平６−３３４
３４１号公報、特開平６−１６４４０号公報、特開昭６
３−１８４３３号公報などを参照）。2. Description of the Related Art When manufacturing a multi-layer circuit board, the multi-layering process differs depending on the form and characteristics of the resin material, and for example, MCM-D (multi chip module).
deposited thin film subst
known as “rate”, and a process characterized by forming wirings by using photo via opening formation, sputtering method, and electroplating method is known (for example, JP-A-7-147483). JP-A-6-334
341, JP-A-6-16440, JP-A-6-6
3-18433 publication etc.).
【０００３】図４及び図５は従来の技術を説明する為の
工程要所に於ける多層回路基板を表す要部切断側面図で
あり、以下、これ等の図を参照しつつ説明する。FIG. 4 and FIG. 5 are side sectional views showing a main part of a multi-layer circuit board in a process step for explaining a conventional technique, which will be described below with reference to these figures.
【０００４】図４（Ａ）参照
（１）基板１に感光性ポリイミドを塗布してポリイミド
層２を形成し、次いで、露光、現像、最終硬化を行って
ビア３を形成する。Referring to FIG. 4 (A), (1) a substrate 1 is coated with a photosensitive polyimide to form a polyimide layer 2, and then exposure, development and final curing are performed to form a via 3.
【０００５】図４（Ｂ）参照
（２）スパッタリング法を適用することに依り、ビア３
内も含めた全面にＣｒ或いはＴｉなどからなる密着層及
びＣｕからなる導体層を積層形成してシード層４を形成
する。See FIG. 4B. (2) Via 3 is formed by applying the sputtering method.
A seed layer 4 is formed by laminating an adhesion layer made of Cr or Ti or the like and a conductor layer made of Cu on the entire surface including the inside.
【０００６】図４（Ｃ）参照
（３）レジスト・プロセスを適用することに依り、パッ
ドや配線などの導体パターンの開口をもつレジスト膜５
を形成する。See FIG. 4C. (3) By applying a resist process, a resist film 5 having openings for conductor patterns such as pads and wirings is formed.
To form.
【０００７】図５（Ａ）参照
（４）電解めっき法を適用することに依ってＣｕ層を形
成し、次いで、レジスト膜５を剥離して前記Ｃｕ層をパ
ッド６やその他の配線などを実現する。Referring to FIG. 5A, (4) a Cu layer is formed by applying an electrolytic plating method, and then the resist film 5 is peeled off to realize the pad 6 and other wiring by the Cu layer. To do.
【０００８】（５）パッド６の外側に露出されているシ
ード層４をパッド６と同じパターンにエッチングして除
去する。(5) The seed layer 4 exposed outside the pad 6 is removed by etching in the same pattern as the pad 6.
【０００９】図５（Ｂ）参照
（６）パッド６を含めて全面に感光性ポリイミドを塗布
して二層目のポリイミド層７を形成する。Referring to FIG. 5B, (6) photosensitive polyimide is applied to the entire surface including the pad 6 to form a second polyimide layer 7.
【００１０】図５（Ｃ）参照
（７）ポリイミド層７の露光、現像、最終硬化を行って
ビア８を形成する。以下、前記プロセスを繰り返して多
層化する。尚、記号９はポリイミドの残渣を示してい
る。Referring to FIG. 5C, (7) the polyimide layer 7 is exposed, developed, and finally cured to form a via 8. Hereinafter, the above process is repeated to form a multilayer. The symbol 9 indicates a polyimide residue.
【００１１】前記ＭＣＭ−Ｄプロセスで多層回路基板を
製造する場合、パッドなどの導体パターン用としてビア
３よりも大きい開口をもつレジスト膜５を形成してめっ
きを行うようにしている為、ポリイミド層２に於けるビ
ア３の周縁にはパッド６など導体パターンの一部が積層
された状態で存在することになる。When a multi-layer circuit board is manufactured by the MCM-D process, a resist film 5 having an opening larger than the via 3 for a conductor pattern such as a pad is formed and plated. A part of the conductor pattern such as the pad 6 exists in the state of being laminated on the peripheral edge of the via 3 in 2.
【００１２】その積層に依って盛り上った高さは、ビア
３を埋めたパッド６の厚さと同じであり、従って、その
上にポリイミド層７を成膜してビア８を形成した場合に
は、ビア３内を埋めたパッド６に於ける表面とビア８の
周縁に於けるポリイミド層７の盛り上がりとの段差を非
常に大きなものとなる。The height raised by the stacking is the same as the thickness of the pad 6 in which the via 3 is filled. Therefore, when the polyimide layer 7 is formed on the pad 6 to form the via 8. Makes a very large step between the surface of the pad 6 filling the inside of the via 3 and the swelling of the polyimide layer 7 at the periphery of the via 8.
【００１３】前記した段差は多層化の層数を増加させる
程大きくなって、リソグラフィに於ける解像度の低下を
招来し、従って、レジスト膜の露光及び現像を行った
際、ビア底に残渣が残り易くなる。The above-mentioned step becomes larger as the number of layers in the multilayer is increased, resulting in a decrease in resolution in lithography. Therefore, when the resist film is exposed and developed, a residue remains on the bottom of the via. It will be easier.
【００１４】このようなことから、スタック・ビアを用
いて多層回路基板の多層化を行うには限界あり、従っ
て、ビアをずらせて形成するなどの対策が必要となっ
て、実装面積が増大し、微細化を阻害する旨の問題が起
こる。For this reason, there is a limit to stacking the multilayer circuit board by using the stacked vias. Therefore, it is necessary to take measures such as forming the vias by shifting them, which increases the mounting area. However, there arises a problem of inhibiting miniaturization.
【００１５】例えば特開２０００−２９９２９３公報に
見られるような非感光性ワニス材料を用いた多層配線プ
ロセスでは、通常、ダマシン・プロセスを用いている。In a multilayer wiring process using a non-photosensitive varnish material as disclosed in, for example, Japanese Patent Laid-Open No. 2000-299293, a damascene process is usually used.
【００１６】これは、パッド及びビアを予めスパッタリ
ング法と電解めっき法に依って作製しておき、その上に
樹脂膜及び研磨停止槽を形成した後、ＣＭＰ（ｃｈｅｍ
ｉｃａｌ ｍｅｃｈａｎｉｃａｌ ｐｏｌｉｓｈｉｎ
ｇ）法を適用して研磨を行うことに依り、接続ビアの頭
出し及び平坦化を行う技術である。In this method, pads and vias are prepared in advance by a sputtering method and an electrolytic plating method, a resin film and a polishing stop tank are formed thereon, and then CMP (chem) is performed.
ical mechanical polishin
This is a technique for cueing and flattening the connection via by applying the method g) and polishing.
【００１７】このプロセスを用いると、面内の平坦化を
実現できると共にスタック・ビアの形成が容易である
為、実装面積の縮小及び微細化に有利なのであるが、樹
脂膜に対してＣＭＰに耐え得る高い強度が要求され、ま
た、ＣＭＰプロセスを実施する為には、研磨用スラリー
の作製プロセスや研磨停止槽形成プロセスが新たに必要
となるから、コスト上昇に結び付くことになる。When this process is used, in-plane flattening can be realized and stack vias can be easily formed, which is advantageous for reducing the mounting area and miniaturization, but it is resistant to CMP with respect to the resin film. A high strength to be obtained is required, and in order to carry out the CMP process, a polishing slurry preparation process and a polishing stop tank formation process are newly required, resulting in an increase in cost.
【００１８】[0018]
【発明が解決しようとする課題】本発明では、通常のＭ
ＣＭ−Ｄプロセスで多層回路基板を作製するに際し、第
２層以後の作製時に発生するパターン解像度の低下や各
層に於ける平坦性低下の問題を解消し、ダマシン法に於
ける研磨プロセスなどを必要とすることなく、低コスト
で目的を達成しようとする。In the present invention, a normal M
When manufacturing a multi-layer circuit board by the CM-D process, the problems of pattern resolution deterioration and flatness deterioration of each layer that occur during the manufacture of the second and subsequent layers are solved, and a polishing process in the damascene method is required. Without trying to achieve the goal at low cost.
【００１９】[0019]
【課題を解決するための手段】本発明に依る多層回路基
板の製造方法に於いては、ビアをもつ樹脂絶縁層を形成
し、ビア内を含めてシード層を形成し、シード層上にＣ
ｕめっき層を形成し、Ｃｕめっき層に生成されている凹
所にＣｕをめっきして埋めることに依って平坦化し、平
坦化されたＣｕめっき層の外方に表出されたシード層を
除去してＣｕめっき層を主体とする導体パターンを形成
することが基本になっている。In the method of manufacturing a multilayer circuit board according to the present invention, a resin insulating layer having a via is formed, a seed layer is formed including the inside of the via, and C is formed on the seed layer.
The u plating layer is formed, and the recesses formed in the Cu plating layer are flattened by filling and filling with Cu, and the seed layer exposed outside the flattened Cu plating layer is removed. Then, a conductor pattern mainly composed of a Cu plating layer is formed.
【００２０】前記手段を採ることに依り、第２層以後の
作製時に発生するパターン解像度の低下や各層に於ける
平坦性低下の問題を解消し、ダマシン法に於ける研磨プ
ロセスなどを必要とすることなく、低コストで目的を達
成することができる。By adopting the above-mentioned means, the problems of pattern resolution reduction and flatness reduction in each layer which occur during the production of the second and subsequent layers are solved, and a polishing process in the damascene method is required. It is possible to achieve the purpose at low cost.
【００２１】[0021]
【発明の実施の形態】図１乃至図３は本発明に於ける実
施の形態を説明する為の工程要所に於ける多層回路基板
を表す要部切断側面図であり、以下、これ等の図を参照
しつつ説明する。尚、図４及び図５に於いて用いた記号
と同記号は同部分を表すか或いは同じ意味を持つものと
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 are side sectional views showing essential parts of a multi-layer circuit board in process steps for explaining an embodiment of the present invention. Description will be made with reference to the drawings. The same symbols as those used in FIGS. 4 and 5 represent the same parts or have the same meanings.
【００２２】図１（Ａ）参照
（１）１５〔ｃｍ〕（６〔インチ〕）Ｓｉウエハからな
る基板１に感光性ネガ型ポリイミドＰ１２７３１（ＨＤ
マイクロシステムズ社製）をスピン・コートしてから、
ホット・プレートに依って、８５〔℃〕で２〔分〕、１
０５〔℃〕で２〔分〕のプリキュアを行ってポリイミド
層２を形成する。Referring to FIG. 1A, (1) a photosensitive negative polyimide P12731 (HD) on a substrate 1 made of a 15 [cm] (6 [inch]) Si wafer.
Micro Systems Co., Ltd.) after spin coating,
Depending on the hot plate, 2 minutes at 85 degrees Celsius, 1
Precure is performed for 2 minutes at 05 [° C.] to form the polyimide layer 2.
【００２３】（２）５０〔μｍ〕φのビア開口用マスク
を用い、ポリイミド層２に対してｇ線に依る３５０〔ｍ
Ｊ／ｃｍ2 〕の露光を行い、次いで、現像液ＰＡ４００
Ｄ（ＨＤマイクロシステムズ社製）を用いて超音波ディ
ップ現像を５〔分〕間行った後、リンス液ＲＩ９１８０
（ＨＤマイクロシステムズ社製）を用いて２〔分〕間の
超音波ディップリンスを行って５０〔μｍ〕径のビア３
を形成する。(2) 350 [m] depending on the g-line with respect to the polyimide layer 2 by using a via opening mask of 50 [μm] φ.
J / cm 2 ], and then the developer PA400
After performing ultrasonic dip development for 5 [minutes] using D (manufactured by HD Micro Systems), rinse solution RI9180
(HD Micro Systems Co., Ltd.) is used to perform ultrasonic dip rinsing for 2 [minutes], and a via 3 having a diameter of 50 [μm] is used.
To form.
【００２４】（３）窒素雰囲気中で温度３５０〔℃〕、
時間６０〔分〕としてポリイミド層２を硬化させた。硬
化後の膜厚は約１０〔μｍ〕（厳密には９．８〔μ
ｍ〕）であった。(3) In a nitrogen atmosphere, the temperature is 350 [° C.],
The polyimide layer 2 was cured at time 60 [minutes]. The film thickness after curing is about 10 [μm] (strictly 9.8 [μm]
m]).
【００２５】図１（Ｂ）参照
（４）スパッタリング法を適用することに依り、ビア３
内も含めた全面に厚さ８００〔Å〕のＣｒからなる密着
層及び厚さ５０００〔Å〕のＣｕからなる導体層を積層
形成してシード層４を形成する。尚、密着層の材料はＣ
ｒに限られず、例えばＴｉを用いても良い。See FIG. 1B. (4) Via 3 is formed by applying the sputtering method.
The seed layer 4 is formed by laminating an adhesion layer made of Cr having a thickness of 800 [Å] and a conductor layer made of Cu having a thickness of 5000 [Å] on the entire surface including the inside. The material of the adhesion layer is C
For example, Ti may be used instead of r.
【００２６】図１（Ｃ）参照
（５）スピン・コート法を適用することに依り、回転数
を２０００〔ｒｐｍ〕としてポジ型レジストＡＺＰ４６
２０（クリアラントジャパン社製）をシード層４上に塗
布し、クリーン・オーブン中で温度８０〔℃〕、時間３
０〔分〕のプリキュアを行ってレジスト膜５を形成す
る。See FIG. 1C. (5) By applying the spin coating method, the positive resist AZP46 is set at a rotation speed of 2000 [rpm].
20 (manufactured by Clearant Japan Co., Ltd.) is coated on the seed layer 4, and the temperature is 80 [° C.] in a clean oven for 3 hours.
Precuring is performed for 0 [minutes] to form a resist film 5.
【００２７】（６）８０〔μｍ〕φのパッド開口用マス
クを介して、レジスト膜５にｇ及びｉ線混合（ブロード
・バンド）光に依る４００〔ｍＪ／ｃｍ2 〕の露光を行
い、次いで、現像液ＡＺ４００Ｋデベロッパ（クラリア
ントジャパン社製）を水で５倍に希釈して用い、４
〔分〕間のディップ現像を行い、８０〔μｍ〕φのパッ
ド形成用開口５Ａを形成する。尚、ここでは、パッドの
形成について説明するが、配線などの形成に応用しても
同様である。(6) The resist film 5 is exposed to 400 [mJ / cm 2 ] by g and i ray mixed (broad band) light through a pad opening mask of 80 μm! , Developer AZ400K developer (Clariant Japan) diluted 5 times with water
Dip development is performed for [minutes] to form a pad forming opening 5A of 80 [μm] φ. Although the pad formation will be described here, the same applies to the formation of wiring and the like.
【００２８】図２（Ａ）参照
（４）硫酸銅を用いた電解めっき法を適用することに依
って厚さが約５〔μｍ〕のＣｕ層を形成し、次いで、Ａ
Ｚリムーバ（クラリアントジャパン社製）中に浸漬し、
レジスト膜５を剥離することに依って前記Ｃｕ層からな
るパッド６が実現される。尚、パッド６とシード層４と
は同じＣｕを用いているので、図では一体のものとして
表してある。See FIG. 2A. (4) A Cu layer having a thickness of about 5 [μm] is formed by applying an electrolytic plating method using copper sulfate, and then A
Immerse in Z remover (Clariant Japan),
By removing the resist film 5, the pad 6 made of the Cu layer is realized. Since the pad 6 and the seed layer 4 are made of the same Cu, they are shown as one in the figure.
【００２９】図２（Ｂ）参照
（５）スピン・コート法を適用することに依り、回転数
を２０００〔ｒｐｍ〕としてポジ型レジストＡＺＰ４６
２０をパッド６上を含む全面に塗布し、クリーン・オー
ブン中で温度８０〔℃〕、時間３０〔分〕のプリキュア
を行ってレジスト膜１１を形成する。See FIG. 2B. (5) By applying the spin coating method, the rotational speed is set to 2000 [rpm] and the positive type resist AZP46.
20 is applied to the entire surface including the pad 6 and pre-cured at a temperature of 80 ° C. for a time of 30 minutes in a clean oven to form a resist film 11.
【００３０】（６）５０〔μｍ〕φのビア開口用マスク
を介して、レジスト膜１１にｇ線及びｉ線混合（ブロー
ド・バンド）光に依る４００〔ｍＪ／ｃｍ2 〕の露光を
行い、次に、現像液ＡＺ４００Ｋデベロッパを水で５倍
に希釈して用い、４〔分〕間のディップ現像を行い、５
０〔μｍ〕φのビア形成用開口１１Ａを形成する。(6) The resist film 11 is exposed to 400 [mJ / cm 2 ] by g-line and i-line mixed (broad band) light through a 50 [μm] φ via opening mask. Next, the developer AZ400K developer was diluted 5 times with water, and dip development was performed for 4 [minutes].
A via forming opening 11A of 0 [μm] φ is formed.
【００３１】この工程に依って、ビア形成用開口１１Ａ
内にはパッド６に於ける凹所６Ａが表出される。尚、こ
こで、ビア形成用開口１１Ａをもつレジスト膜１１を形
成するに際しては、シード層４を残したままで実施する
ことが好ましい。これは工程増加を可能な限り抑止する
為である。Through this step, the via forming opening 11A is formed.
A recess 6A in the pad 6 is exposed inside. Here, when forming the resist film 11 having the via forming opening 11A, it is preferable to perform it with the seed layer 4 left. This is to suppress the number of processes as much as possible.
【００３２】図２（Ｃ）参照
（７）硫酸銅を用いた電解めっき法を適用することに依
り、パッド６に於ける凹所６Ａを埋める約５〔μｍ〕の
Ｃｕ層を形成して表面を平坦化する。尚、ここで形成し
たＣｕ層もパッド６の一部と見做して同じ記号で指示し
てあり、また、パッド６の埋め込み程度は、場所に依っ
てばらつきはあるが、５±０．５〔μｍ〕程度である。See FIG. 2C. (7) By applying an electrolytic plating method using copper sulfate, a Cu layer of about 5 [μm] filling the recess 6A in the pad 6 is formed and the surface is formed. Flatten. The Cu layer formed here is also regarded as a part of the pad 6 and designated by the same symbol, and the degree of embedding of the pad 6 is 5 ± 0.5 although it varies depending on the location. It is about [μm].
【００３３】図３（Ａ）参照
（７）ＡＺリムーバ中に浸漬し、レジスト膜１１を剥離
してから、エッチャントを過硫酸アンモニウム水溶液
（Ｃｕ用）及びフェリシアンカカリウム（ＩＩＩ）＋Ｎ
ａＯＨ水溶液（Ｃｒ用）とするウエット・エッチング法
を適用することに依り、パッド６の外側に露出されたシ
ード層４をエッチングして除去する。See FIG. 3A (7) After immersing in AZ remover to remove the resist film 11, the etchant is an ammonium persulfate aqueous solution (for Cu) and potassium ferricyanide (III) + N.
The seed layer 4 exposed on the outside of the pad 6 is removed by etching by applying a wet etching method using an aOH aqueous solution (for Cr).
【００３４】（８）スピン・コート法を適用することに
依り、回転数を４５００〔ｒｐｍ〕、時間を３０〔ｓｅ
ｃ〕として感光性ネガ型ポリイミドＰ１２７３１をパッ
ド６上を含む全面に塗布し、ホット・プレートに依っ
て、８５〔℃〕で２〔分〕間、１０５〔℃〕で２〔分〕
間のプリキュアを行って第２層目ポリイミド層７の一部
を形成する。尚、ここで形成したポリイミド層７は、必
要厚さ全体の１／２である。(8) By applying the spin coating method, the rotation speed is 4500 [rpm] and the time is 30 [se].
As c], a photosensitive negative polyimide P12731 is applied to the entire surface including the pad 6, and depending on the hot plate, 85 [° C.] for 2 [min] and 105 [° C.] for 2 [min].
Precure is performed between them to form a part of the second polyimide layer 7. The polyimide layer 7 formed here is ½ of the total required thickness.
【００３５】図３（Ｂ）参照
（７）工程（８）と同じ工程を繰り返し、第２層目のポ
リイミド層７の厚さを増加させる。このとき、増加させ
たポリイミド層７は、必要厚さ全体の１／２であり、こ
れで第２層目のポリイミド層７が完成される。尚、その
硬化後の厚さは約１０〔μｍ〕である。The same process as the process (8) (7) (see FIG. 3B) is repeated to increase the thickness of the second polyimide layer 7. At this time, the increased thickness of the polyimide layer 7 is 1/2 of the total required thickness, and thus the second polyimide layer 7 is completed. The thickness after curing is about 10 [μm].
【００３６】図３（Ｃ）参照
（８）前記工程（２）と同様にして、ポリイミド層７の
露光、現像、熱硬化を行ってビア８を形成する。Referring to FIG. 3C, (8) In the same manner as in the step (2), the polyimide layer 7 is exposed, developed, and thermally cured to form the via 8.
【００３７】前記説明したプロセスに依れば、従来の技
術に於けるような大きな段差は生じないから、ポリイミ
ド層７の露光及び現像は良好に行われ、従って、ビア８
内にポリイミドの残渣は発生せず、また、平坦性も良好
であった。According to the process described above, a large step difference as in the prior art does not occur, so that the exposure and development of the polyimide layer 7 are performed well, and thus the via 8 is formed.
No polyimide residue was generated inside, and the flatness was good.
【００３８】更に多層化するには、前記説明したプロセ
スを繰り返せば良く、実験に依れば、積層数６まで良好
な結果が得られることを確認している。In order to further increase the number of layers, it is sufficient to repeat the above-mentioned process, and it has been confirmed through experiments that good results can be obtained up to 6 layers.
【００３９】[0039]
【発明の効果】本発明に依る多層回路基板の製造方法に
於いては、導体パターンをもつ基板上にビアをもつ樹脂
絶縁層を形成し、ビア内を含めてシード層を形成し、シ
ード層上にめっきマスクのレジスト層を形成し、めっき
マスクのレジスト層に於ける開口内にＣｕめっき層を形
成し、めっきマスクのレジスト層を除去した後、Ｃｕめ
っき層に生成されている凹所を表出する開口をもつめっ
きマスクのレジスト層を形成し、凹所を表出する開口を
もつめっきマスクのレジスト層に於ける開口内にＣｕを
めっきしてＣｕめっき層の凹所を埋めて平坦化し、凹所
を表出する開口をもつめっきマスクのレジスト層を除去
してから平坦化されたＣｕめっき層の外方に表出された
シード層を除去してＣｕめっき層を主体とする導体パタ
ーンを形成することが基本になっている。In the method for manufacturing a multilayer circuit board according to the present invention, a resin insulating layer having a via is formed on a board having a conductor pattern, and a seed layer is formed including the inside of the via to form a seed layer. A resist layer of the plating mask is formed on the Cu mask, a Cu plating layer is formed in the opening of the resist layer of the plating mask, the resist layer of the plating mask is removed, and then the recess formed in the Cu plating layer is removed. A resist layer of a plating mask having an exposed opening is formed, and Cu is plated in the opening in the resist layer of the plating mask having an exposed opening to fill the recess of the Cu plating layer and flatten it. And a conductor mainly composed of the Cu plating layer by removing the resist layer of the plating mask having an opening exposing the recess and then removing the seed layer exposed outside the flattened Cu plating layer. Forming a pattern There has been made to the basic.
【００４０】前記構成を採ることに依り、第２層以後の
作製時に発生するパターン解像度の低下や各層に於ける
平坦性低下の問題を解消し、ダマシン法に於ける研磨プ
ロセスなどを必要とすることなく、低コストで目的を達
成することができる。By adopting the above-mentioned structure, the problems of pattern resolution deterioration and flatness deterioration of each layer that occur during the fabrication of the second and subsequent layers are solved, and a polishing process in the damascene method is required. It is possible to achieve the purpose at low cost.
【図１】本発明に於ける実施の形態を説明する為の工程
要所に於ける多層回路基板を表す要部切断側面図であ
る。FIG. 1 is a side sectional view showing a main part of a multilayer circuit board at a process step for explaining an embodiment of the present invention.
【図２】本発明に於ける実施の形態を説明する為の工程
要所に於ける多層回路基板を表す要部切断側面図であ
る。FIG. 2 is a side sectional view showing an essential part of a multi-layer circuit board at a process step for explaining an embodiment of the present invention.
【図３】本発明に於ける実施の形態を説明する為の工程
要所に於ける多層回路基板を表す要部切断側面図であ
る。FIG. 3 is a side sectional view showing an essential part of a multilayer circuit board at a process step for explaining an embodiment of the present invention.
【図４】従来の技術を説明する為の工程要所に於ける多
層回路基板を表す要部切断側面図である。FIG. 4 is a cutaway side view of an essential part showing a multilayer circuit board in a process key part for explaining a conventional technique.
【図５】従来の技術を説明する為の工程要所に於ける多
層回路基板を表す要部切断側面図である。FIG. 5 is a cutaway side view of an essential part showing a multilayer circuit board at a process key part for explaining a conventional technique.
１ 基板 ２ 第１層目ポリイミド層 ３ ビア ４ シード層 ５ レジスト膜 ６ パッド ６Ａ 凹所 ７ 第２層目ポリイミド層 ８ ビア ９ 残渣 １１ レジスト膜 １１Ａ ビア形成用開口 1 substrate 2 First layer polyimide layer 3 vias 4 Seed layer 5 Resist film 6 pads 6A recess 7 Second layer polyimide layer 8 vias 9 residue 11 Resist film 11A Via forming opening
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/46 Ｈ０５Ｋ 3/46 Ｎ Ｈ０１Ｌ 21/90 Ａ Ｆターム(参考） 4M104 BB04 DD37 DD52 FF13 HH12 5E317 AA24 BB03 BB04 BB12 CC33 CC44 CC51 CD15 CD18 CD25 GG01 GG16 5E343 AA02 AA22 AA39 BB15 BB24 BB61 BB71 CC62 DD43 DD76 ER18 ER21 ER25 GG06 GG08 GG11 5E346 AA02 AA12 AA15 AA35 AA43 BB01 BB16 CC10 CC32 CC54 DD03 DD24 DD33 DD47 EE33 FF14 GG17 GG22 GG23 HH11 HH32 5F033 HH11 HH17 HH18 MM05 PP15 PP27 PP33 QQ09 QQ19 RR22 RR27 VV07 XX01 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 3/46 H05K 3/46 N H01L 21/90 A F term (reference) 4M104 BB04 DD37 DD52 FF13 HH12 5E317 AA24 BB03 BB04 BB12 CC33 CC44 CC51 CD15 CD18 CD25 GG01 GG16 5E343 AA02 AA22 AA39 BB15 BB24 BB61 BB71 CC62 DD43 DD76 ER18 ER21 ER25 GG06 GG08 GG11 DD32 DD23 CC32 CC14 CC23 CC14 CC33 CC44 CC15 5F033 HH11 HH17 HH18 MM05 PP15 PP27 PP33 QQ09 QQ19 RR22 RR27 VV07 XX01
Claims (2)
脂絶縁層を形成する工程と、 前記ビア内を含めてシード層を形成する工程と、 前記シード層上にめっきマスクのレジスト層を形成する
工程と、 前記めっきマスクのレジスト層に於ける開口内にＣｕめ
っき層を形成する工程と、 前記めっきマスクのレジスト層を除去した後、前記Ｃｕ
めっき層に生成されている凹所を表出する開口をもつめ
っきマスクのレジスト層を形成する工程と、 前記凹所を表出する開口をもつめっきマスクのレジスト
層に於ける該開口内にＣｕをめっきして該Ｃｕめっき層
の凹所を埋めて平坦化する工程と、 前記凹所を表出する開口をもつめっきマスクのレジスト
層を除去してから前記平坦化されたＣｕめっき層の外方
に表出された前記シード層を除去して前記Ｃｕめっき層
を主体とする導体パターンを形成する工程とを含んでな
ることを特徴とする多層回路基板の製造方法。1. A step of forming a resin insulating layer having a via on a substrate having a conductor pattern, a step of forming a seed layer including the inside of the via, and a resist layer of a plating mask on the seed layer. And a step of forming a Cu plating layer in the opening in the resist layer of the plating mask, the Cu layer after removing the resist layer of the plating mask,
Forming a resist layer of a plating mask having an opening that exposes a recess formed in the plating layer; and Cu in the opening of the resist layer of the plating mask having an opening that exposes the recess. And then flattening by filling the recess of the Cu plating layer, and removing the resist layer of the plating mask having an opening that exposes the recess, and then removing the flattened Cu plating layer from the outside. And a step of removing the exposed seed layer to form a conductor pattern mainly composed of the Cu plating layer.
は２回に分けて半硬化状態で形成してから開口形成と完
全硬化とを実施することを特徴とする請求項１記載の多
層回路基板の製造方法。2. The resin insulating layer in the formation of the second or higher layer is formed in a semi-cured state in two steps, and then the opening formation and the complete curing are carried out. A method for manufacturing the multilayer circuit board described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001394257A JP3800405B2 (en) | 2001-12-26 | 2001-12-26 | Multilayer circuit board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001394257A JP3800405B2 (en) | 2001-12-26 | 2001-12-26 | Multilayer circuit board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003197741A true JP2003197741A (en) | 2003-07-11 |
| JP3800405B2 JP3800405B2 (en) | 2006-07-26 |
Family
ID=27601045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001394257A Expired - Fee Related JP3800405B2 (en) | 2001-12-26 | 2001-12-26 | Multilayer circuit board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3800405B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006005351A (en) * | 2004-06-17 | 2006-01-05 | Sharp Corp | Method for forming metal pattern by plating method |
| JP2010130003A (en) * | 2008-11-26 | 2010-06-10 | Samsung Electro-Mechanics Co Ltd | Multi-layer printed circuit board, and manufacturing method thereof |
| CN105990353A (en) * | 2015-01-28 | 2016-10-05 | 旺宏电子股份有限公司 | Memory structure and manufacturing method thereof |
| WO2021010754A1 (en) * | 2019-07-15 | 2021-01-21 | 엘지이노텍 주식회사 | Printed circuit board |
-
2001
- 2001-12-26 JP JP2001394257A patent/JP3800405B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006005351A (en) * | 2004-06-17 | 2006-01-05 | Sharp Corp | Method for forming metal pattern by plating method |
| JP2010130003A (en) * | 2008-11-26 | 2010-06-10 | Samsung Electro-Mechanics Co Ltd | Multi-layer printed circuit board, and manufacturing method thereof |
| CN105990353A (en) * | 2015-01-28 | 2016-10-05 | 旺宏电子股份有限公司 | Memory structure and manufacturing method thereof |
| CN105990353B (en) * | 2015-01-28 | 2019-01-11 | 旺宏电子股份有限公司 | Memory construction and its manufacturing method |
| WO2021010754A1 (en) * | 2019-07-15 | 2021-01-21 | 엘지이노텍 주식회사 | Printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3800405B2 (en) | 2006-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102084731B (en) | Printed wiring board and method for manufacturing same | |
| US5266446A (en) | Method of making a multilayer thin film structure | |
| EP0457501B1 (en) | Method of manufacturing a multilayer wiring board | |
| EP0450381B1 (en) | Multilayer interconnection structure | |
| JPH0432295A (en) | Manufacture of multilayer wiring board | |
| US6426011B1 (en) | Method of making a printed circuit board | |
| CN103314649A (en) | Method of transferring and electrically joining high density multilevel thin film to circuitized and flexible organic substrate and associated devices | |
| US20130062106A1 (en) | Printed Circuit Board and Method of Manufacturing the Same | |
| US7168936B2 (en) | Light transparent substrate imprint tool with light blocking distal end | |
| US5200300A (en) | Methods for forming high density multi-chip carriers | |
| JPH04277696A (en) | Multilayer interconnection board and manufacture thereof | |
| JP2006041029A (en) | Wiring substrate, manufacturing method thereof, and electronic device | |
| JP2003197741A (en) | Method for manufacturing multilayer circuit board | |
| JPH11238970A (en) | Multilayered printed board and manufacture thereof | |
| JP5640667B2 (en) | Circuit board manufacturing method | |
| JP4401527B2 (en) | Manufacturing method of semiconductor chip | |
| JPH07235768A (en) | Production process for thin film multilayer wiring board | |
| WO1992009102A1 (en) | A method of making a multilayer thin film structure | |
| JP2005244104A (en) | Manufacturing method of wiring board | |
| JPH08250857A (en) | Manufacture of multilayer interconnection board | |
| JP2002076633A (en) | Manufacturing method of multilayer interconnection board and plating method | |
| KR101136389B1 (en) | Printed circuit board and method for manufacturing same | |
| JP2002290048A (en) | Via forming method in multilayer circuit board | |
| JP3272945B2 (en) | Manufacturing method of wiring board | |
| JPH0745948A (en) | Multilayer wiring board and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20041124 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060315 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060322 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060419 |
|
| R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090512 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100512 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100512 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110512 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120512 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130512 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140512 Year of fee payment: 8 |
|
| LAPS | Cancellation because of no payment of annual fees |