JP2003115497A - Thin film semiconductor device and its manufacturing method, and electronic device having the same device - Google Patents
Thin film semiconductor device and its manufacturing method, and electronic device having the same deviceInfo
- Publication number
- JP2003115497A JP2003115497A JP2001307807A JP2001307807A JP2003115497A JP 2003115497 A JP2003115497 A JP 2003115497A JP 2001307807 A JP2001307807 A JP 2001307807A JP 2001307807 A JP2001307807 A JP 2001307807A JP 2003115497 A JP2003115497 A JP 2003115497A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- active
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 252
- 239000010409 thin film Substances 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 239000010408 film Substances 0.000 claims abstract description 221
- 239000013078 crystal Substances 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000010438 heat treatment Methods 0.000 claims description 43
- 238000002425 crystallisation Methods 0.000 claims description 11
- 230000008025 crystallization Effects 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 23
- 239000010453 quartz Substances 0.000 abstract description 6
- 230000001678 irradiating effect Effects 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 18
- 239000004973 liquid crystal related substance Substances 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 description 12
- 229910019901 yttrium aluminum garnet Inorganic materials 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- 101100321669 Fagopyrum esculentum FA02 gene Proteins 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- JGRGMDZIEXDEQT-UHFFFAOYSA-N [Cl].[Xe] Chemical compound [Cl].[Xe] JGRGMDZIEXDEQT-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 101100116283 Arabidopsis thaliana DD11 gene Proteins 0.000 description 1
- 101000592773 Halobacterium salinarum (strain ATCC 700922 / JCM 11081 / NRC-1) 50S ribosomal protein L22 Proteins 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Recrystallisation Techniques (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、薄膜半導体装置及
びその製造方法並びに当該装置を備える電子デバイスに
関する。特に、ガラス等の絶縁表面を有する基板上に形
成される薄膜半導体装置（以下、ＴＦＴという）等の薄
膜半導体装置及びその製造方法並びに当該装置を備える
液晶表示装置及び有機ＥＬ表示装置等の電子デバイスに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device, a method for manufacturing the same, and an electronic device equipped with the device. In particular, a thin film semiconductor device such as a thin film semiconductor device (hereinafter referred to as a TFT) formed on a substrate having an insulating surface such as glass, a method of manufacturing the same, and an electronic device such as a liquid crystal display device and an organic EL display device. Regarding
【０００２】[0002]
【従来の技術】複数の画素を有するアクティブ型液晶表
示装置、有機ＥＬ表示装置、及びイメージセンサ等の各
種電子デバイスにおいては、各画素を個別に駆動するた
めに、ガラス等の絶縁表面を有する基板上に形成される
ＴＦＴが用いられることが多い。また、近年の表示素子
は、画素を駆動するためのＴＦＴが形成された基板上
に、このＴＦＴのスイッチング動作を制御するための駆
動回路が設けられることが多い。この駆動回路内には多
数のトランジスタが設けられるが、このトランジスタも
ＴＦＴで形成されている。ＴＦＴは、ガラス等の絶縁性
表面上に薄膜状の珪素半導体（Ｓｉ）又はその酸化物
（酸化珪素（ＳｉＯ2））を堆積し、エッチング処理、
熱処理、電極形成処理、その他の処理を行いつつ、これ
らの処理を繰り返し行うことにより製造される。薄膜状
の珪素半導体は、結晶性を有するものと非晶質珪素半導
体（ａ−Ｓｉ）とに大別される。2. Description of the Related Art In various electronic devices such as an active liquid crystal display device having a plurality of pixels, an organic EL display device, and an image sensor, a substrate having an insulating surface such as glass in order to drive each pixel individually. The TFT formed above is often used. Further, in recent display elements, a drive circuit for controlling the switching operation of the TFT is often provided on a substrate on which a TFT for driving a pixel is formed. Although a large number of transistors are provided in this drive circuit, these transistors are also formed by TFTs. The TFT is formed by depositing a thin film silicon semiconductor (Si) or its oxide (silicon oxide (SiO 2 )) on an insulating surface such as glass, and performing an etching treatment,
It is manufactured by repeating these treatments while performing heat treatment, electrode formation treatment, and other treatments. Thin film silicon semiconductors are roughly classified into those having crystallinity and amorphous silicon semiconductors (a-Si).
【０００３】非晶質珪素半導体は作成温度が低く、気相
法で比較的容易に作成することが可能であり、更に量産
性にも富むため、ＴＦＴに用いる薄膜状の珪素半導体と
して最も一般的に用いられている。しかしながら、非晶
質珪素半導体は、導電率等の物性が結晶性を有する珪素
半導体に比べて劣るという欠点がある。従って、今後Ｔ
ＦＴの動作速度を高速化するためには、結晶性を有する
珪素半導体を用いたＴＦＴ及びその製造方法を確立する
ことが極めて重要となる。Amorphous silicon semiconductors have a low production temperature, can be produced relatively easily by a vapor phase method, and have high mass productivity. Is used for. However, the amorphous silicon semiconductor has a drawback that physical properties such as conductivity are inferior to those of a crystalline silicon semiconductor. Therefore, in the future T
In order to increase the operation speed of FT, it is extremely important to establish a TFT using a crystalline silicon semiconductor and a manufacturing method thereof.
【０００４】現状においては、結晶性を有する珪素半導
体として製造上の容易さから多結晶珪素半導体（ｐ−Ｓ
ｉ）が多く用いられている。汎用ガラス基板を使用し得
る６００℃程度以下の低温にて薄膜状の多結晶珪素半導
体を作成する方法としては、非晶質珪素半導体膜を厚さ
５０ｎｍ程度成膜した後、この非晶質珪素半導体膜にキ
セノン塩素（ＸｅＣｌ）エキシマレーザ光（波長３０８
ｎｍ）を照射し、非晶質珪素半導体膜を溶融結晶化させ
て多結晶珪素半導体膜を得るという方法が一般的であ
る。At present, a polycrystalline silicon semiconductor (p-S) is used as a crystalline silicon semiconductor because of its ease of manufacture.
i) is often used. As a method of forming a thin-film polycrystalline silicon semiconductor at a low temperature of about 600 ° C. or lower, which can use a general-purpose glass substrate, an amorphous silicon semiconductor film is formed to a thickness of about 50 nm, and then this amorphous silicon semiconductor is formed. Xenon chlorine (XeCl) excimer laser light (wavelength 308
(nm) to melt and crystallize the amorphous silicon semiconductor film to obtain a polycrystalline silicon semiconductor film.
【０００５】しかしながら、上述の多結晶珪素半導体膜
を用いたＴＦＴのチャネル形成領域には、多結晶珪素半
導体膜の結晶粒界が存在する為、その電気特性が単結晶
珪素半導体を用いたＴＦＴに比べて著しく劣ることが分
かっている。このため、大粒径の多結晶珪素半導体を用
いることにより、結晶粒界の電気特性への影響を小さく
する方法等の方策が採られている。However, since the crystal grain boundaries of the polycrystalline silicon semiconductor film exist in the channel formation region of the TFT using the above-mentioned polycrystalline silicon semiconductor film, the electrical characteristics of the TFT use the single crystal silicon semiconductor. It is known to be significantly inferior to the comparison. For this reason, measures such as a method of reducing the influence of the crystal grain boundaries on the electrical characteristics by using a polycrystalline silicon semiconductor having a large grain size have been adopted.
【０００６】[0006]
【発明が解決しようとする課題】ところで、上述した従
来のエキシマレーザ光を照射して多結晶珪素半導体膜を
得る方法では、最大１μｍ程度の結晶粒が得られるが、
結晶粒及び結晶粒界の位置を制御することができない。
このため、チャネル形成領域に結晶粒界が含まれるかど
うかは確率的事象であって、全く制御不可能であった。
チャネル形成領域に結晶粒界が含まれるか否かによりＴ
ＦＴの特性は大きくばらつくことになる。例えば、チャ
ネル形成領域に存在する結晶粒界の数が多ければＴＦＴ
の電気特性は悪くなり、チャネル形成領域に存在する結
晶粒界の数が少なければＴＦＴの電気特性は比較的良く
なる。しかしながら、例えチャネル形成領域に存在する
結晶粒界の数を少なくすることができたとしても、その
ＴＦＴの電気特性は単結晶珪素半導体を用いたＴＦＴに
比べれば遙かに劣る。By the way, according to the above-mentioned method of obtaining a polycrystalline silicon semiconductor film by irradiating the excimer laser beam, a crystal grain of about 1 μm at maximum can be obtained.
It is not possible to control the positions of the crystal grains and the grain boundaries.
Therefore, whether or not the channel forming region contains a grain boundary is a stochastic event and cannot be controlled at all.
Depending on whether the grain boundary is included in the channel formation region, T
The characteristics of FT will vary greatly. For example, if the number of crystal grain boundaries existing in the channel formation region is large, the TFT
The electrical characteristics of the TFT are deteriorated, and if the number of crystal grain boundaries existing in the channel formation region is small, the electrical characteristics of the TFT are relatively good. However, even if the number of crystal grain boundaries existing in the channel formation region can be reduced, the electric characteristics of the TFT are far inferior to those of a TFT using a single crystal silicon semiconductor.
【０００７】近年の電子デバイスは高速動作が求められ
ており、特に電子デバイス内に設けられるＴＦＴには各
素子毎の電気的特性のばらつきが少なく、且つ、高速で
スイッチング可能な優れた電気的特性が求められてい
る。例えば、液晶表示装置を例に挙げると、高精細化に
より画素の数が増加すると、増加した分だけ１画素がオ
ン状態となっている時間が短くなる。これは、画素を駆
動するＴＦＴのみならず、このＴＦＴを駆動するための
駆動回路内に設けられているＴＦＴについても同様であ
る。従って、電子デバイスの特性を向上させるために
は、基本となるＴＦＴの電気的特性を改善することが極
めて重要である。Recent electronic devices are required to operate at high speed, and particularly, the TFT provided in the electronic device has excellent variation in electric characteristics among the respective elements and has excellent electric characteristics capable of switching at high speed. Is required. For example, taking a liquid crystal display device as an example, as the number of pixels increases due to higher definition, the time during which one pixel is in the ON state becomes shorter due to the increase. This applies not only to the TFT that drives the pixel, but also to the TFT that is provided in the drive circuit that drives this TFT. Therefore, in order to improve the characteristics of the electronic device, it is extremely important to improve the electrical characteristics of the basic TFT.
【０００８】本発明は上記事情に鑑みてなされたもので
あり、結晶粒界の位置が制御された結晶性の良い大粒径
の結晶粒からなる半導体膜を備え、電気特性が良く且つ
そのばらつきが少ない薄膜半導体装置及びその製造方法
並びに当該装置を備える電子デバイスを提供することを
目的とする。The present invention has been made in view of the above circumstances, and is provided with a semiconductor film composed of large-sized crystal grains with good crystallinity, in which the positions of crystal grain boundaries are controlled, and has good electric characteristics and variations thereof. It is an object of the present invention to provide a thin film semiconductor device having a small number of devices, a manufacturing method thereof, and an electronic device including the device.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
に、本発明の薄膜半導体装置の製造方法は、基板上に形
成された半導体膜の一部を活性領域として用いる薄膜半
導体装置の製造方法において、前記半導体膜の一部を局
所的に加熱する局所加熱機構を前記基板上に形成する加
熱機構形成工程と、前記加熱機構形成工程後に行われ、
前記半導体膜としての活性半導体膜を形成する活性半導
体膜形成工程と、前記局所加熱機構により前記活性半導
体膜が局所的に加熱された状態にて前記活性半導体膜を
溶融結晶化させる結晶化工程と、前記活性半導体膜を島
状に加工して前記活性領域を２つ形成する素子分離工程
とを含み、前記素子分離工程では、前記活性領域が配列
された第１方向に関して、前記活性領域が前記局所加熱
機構に完全に含まれ、且つ、前記局所加熱機構の中心近
傍の両側に所定の距離だけ離間した位置に配置されるよ
うに前記活性半導体膜を加工することを特徴としてい
る。かかる構成の発明は、まず基板上に局所加熱機構を
形成する（加熱機構形成工程）。局所加熱機構は、一例
として基板上に形成された島状の第一半導体膜とこれを
覆う下側絶縁膜とからなる。従って局所加熱機構形成工
程の具体例としては、基板上に第一半導体膜を堆積する
第一半導体膜堆積工程と、この第一半導体膜を所定の形
状に加工する第一半導体膜加工工程と、第一半導体膜上
に下側絶縁膜を形成する下側絶縁膜形成工程とを含んだ
工程が挙げられる。次に前記局所加熱機構上に活性半導
体膜を形成する（活性半導体膜形成工程）。活性半導体
膜は、非晶質半導体膜又は結晶性を有する半導体膜から
なる。従って活性半導体膜形成工程の具体例としては、
前記局所加熱機構上に非晶質半導体膜を堆積する工程が
挙げられ、更にこの非晶質半導体膜の結晶性を高める工
程として非晶質半導体膜を固相にて結晶化させる固相成
長工程又は非晶質半導体膜を溶融状態を経て結晶性を改
善する溶融結晶化改善工程が挙げられる。次に前記局所
加熱機構により前記活性半導体膜が局所的に加熱された
状態にて前記活性半導体膜を溶融結晶化させる（結晶化
工程）。この結晶化工程では、一例として前記活性半導
体膜側から光を照射することにより前記活性半導体膜を
溶融結晶化させる。光を照射すると、一部の光は前記活
性半導体膜に吸収され、一部の光は前記活性半導体膜を
透過する。ある程度の光を吸収した活性半導体膜は溶融
結晶化する。一方、活性半導体膜を透過した光は前記局
所加熱機構の第一半導体膜に吸収される。第一半導体膜
の温度は光を吸収したことにより上昇し、第一半導体膜
上の活性半導体膜は局所的に加熱される。ここで、活性
半導体膜は溶融結晶化過程にあるが、溶融結晶化過程で
は結晶粒は低温部から高温部に向かって成長する。活性
半導体膜の内でその下に局所加熱機構が配置されている
部位のみがその周辺に比べて高温になるため、冷却固化
時における結晶粒は局所加熱機構の辺の僅かに外側上の
活性半導体膜部位から局所加熱機構の中心上の活性半導
体膜部位に向かって成長する。局所加熱機構によって形
成された温度差が溶融半導体膜の冷却固化時に結晶の横
成長を生じさせるのである。ここで、結晶化工程の具体
例としては、活性半導体膜側から活性半導体膜を２０％
程度以上透過するレーザ光を照射するという工程が挙げ
られる。そのレーザ光の具体例としては光の波長が約５
３２ｎｍの固体レーザの高調波が挙げられ、更に具体的
にいえばＱスイッチ発振するネオジウム（Ｎｄ）添加の
イットリウムアルミニウムガーネット（ＹＡＧ）レーザ
光の第二高調波（Ｎｄ：ＹＡＧ２ωレーザ光）等が挙げ
られる。結晶化工程が終了したら、前記活性半導体膜を
島状に加工して２つの活性領域を形成する（素子分離工
程）。この素子分離工程では、前記活性領域が配列され
た第１方向に関して、前記活性領域の各々が前記局所加
熱機構に完全に含まれるように前記活性半導体膜を加工
する。活性半導体膜内での結晶横成長は必ず局所加熱機
構の外側１μｍ程度の位置から始まる。従って、上述の
位置関係に局所加熱機構と活性領域とを設定しておけ
ば、活性領域内で第１方向（薄膜半導体装置が動作する
際の電流方向）を横切る第２方向に延びる結晶粒界（電
流を横切る結晶粒界）の数を常に局所加熱機構の中心上
付近に一個とすることができる。更に、本発明では、前
記活性領域が配列された第１方向に関して、前記活性領
域が前記局所加熱機構に完全に含まれ、且つ、前記局所
加熱機構の中心近傍の両側に所定の距離だけ離間した位
置に配置されるように前記活性半導体膜を加工する。か
かる位置関係に局所加熱機構と活性領域とを設定してお
けば、活性領域内において第１方向（半導体装置が動作
する際の電流方向）を横切る結晶粒界（電流を横切る結
晶粒界）を全く無くすことができる。即ち、活性領域内
に結晶粒界を横切らない電流経路を必ず複数個形成する
ことができるので、本発明の薄膜半導体装置は単結晶珪
素薄膜を用いた小さなシリコン−オン−インシュレータ
ー（ＳＯＩ）装置を複数個並列接続したものと同等と化
し、その性能は一般的な薄膜半導体装置に比べて飛躍的
に向上する。また、活性領域内で第１方向を横切る結晶
粒界が全く無いので、結晶粒界の存在に起因する薄膜半
導体装置の特性ばらつきが無くなる。即ち、基板上に形
成される全ての薄膜半導体装置がほとんど同じ特性を示
す様になる。更に、上述の位置関係に局所加熱機構と活
性領域とを設定しておけば、薄膜半導体装置のオフ電流
が低減されるという効果がある。上述の位置関係に局所
加熱機構と活性領域とを設定しておくということは、活
性領域を第１方向に分割するということである。すると
薄膜半導体装置のソース・ドレイン電圧は各活性領域に
割り振られ、その結果ドレイン領域端空乏領域の電場が
弱くなる。よってプール・フレンケル効果を伴うフォノ
ン・アシスト・トンネリング現象は抑制され、薄膜半導
体装置のオフ電流は低減されるのである。以上のよう
に、本発明の薄膜半導体装置の製造方法によれば、活性
領域内において、当該活性領域が配列された第１方向を
横切る結晶粒界が全く無く、活性領域は第１方向に分割
されているので、電気特性が良く、ばらつきの少ない薄
膜半導体装置を製造できる。また、本発明の薄膜半導体
装置の製造方法は、前記第１方向における前記活性領域
それぞれの長さが、２μｍ以下であることを特徴として
いる。この発明によれば、活性領域内において、前記第
１方向を横切る結晶粒界を確実に無くすことができると
いう効果を有する。結晶の横成長の大きさは典型的には
２μｍから２．５μｍ程度であり、最大でも３．５μｍ
程度である。よって、活性領域の第１方向の長さを２μ
ｍ以下にすることによって、活性領域内において前記第
１方向を横切る結晶粒界を確実に無くすことができるの
である。また、本発明の薄膜半導体装置の製造方法は、
前記活性領域各々の位置が、前記局所加熱機構の中心近
傍から前記第１方向にそれぞれ０．５μｍ以上離間した
位置に設定されることを特徴としている。この発明によ
れば、活性領域内において第１方向を横切る第２方向に
延びる結晶粒界を確実に含まないようにすることができ
るという効果を有する。第２方向に延びる結晶粒界付近
は、結晶粒界部を頂上として山状に***している。この
発明によれば、結晶粒界部を頂上とする山状の領域を避
けて活性領域を形成することができる。即ち、活性領域
は半導体膜厚の薄い領域のみに形成されるため、半導体
装置の電気特性が向上する。また、活性領域が平坦な領
域に形成されるので、活性領域とゲート絶縁膜との界面
状態が良好になり、半導体装置の信頼性が向上する。上
記課題を解決するために、本発明の薄膜半導体装置は、
基板上に形成された半導体膜の一部を活性領域として用
いる薄膜半導体装置において、前記半導体膜には、異な
る２箇所に活性領域が形成されており、前記活性領域に
は、前記活性領域が配列された第１方向に延びる結晶粒
界のみが存在し、前記活性領域の間には、前記第１方向
を横切る第２方向に延びる１つの結晶粒界が存在するこ
とを特徴としている。この発明によれば、活性領域内に
おいて第２方向に延びる結晶粒界が全く無く、しかも活
性領域が第２方向に分割されているので、電気特性が良
く、ばらつきの少ない薄膜半導体装置となる。また、本
発明の薄膜半導体装置は、前記第１方向における前記活
性領域それぞれの長さが、２μｍ以下であることを特徴
としている。この発明によれば、活性領域内において、
第２方向に延びる結晶粒界を確実に無くすことができる
という効果を有する。半導体膜を溶融結晶化によって横
成長させた場合、結晶の横成長の大きさは典型的には２
μｍから２．５μｍ程度であり、最大で３．５μｍ程度
である。よって、活性領域の第１方向の長さを２μｍ以
下にすることによって、活性領域内において第２方向に
延びる結晶粒界を確実に無くすことができるのである。
また、本発明の薄膜半導体装置は、前記活性領域各々の
位置が、前記結晶粒界から前記第１方向にそれぞれ０．
５μｍ以上離間した位置に設定されることを特徴として
いる。この発明によれば、活性領域内において第１方向
を横切る第２方向に延びる結晶粒界を確実に含まないよ
うにすることができるという効果を有する。第２方向に
延びる結晶粒界付近は、結晶粒界部を頂上として山状に
***している。この発明によれば、結晶粒界部を頂上と
する山状の領域を避けて活性領域を形成することができ
る。即ち、活性領域は半導体膜厚の薄い領域のみに形成
されるため、半導体装置の電気特性が向上する。また、
活性領域が平坦な領域に形成されるので、活性領域とゲ
ート絶縁膜との界面状態が良好になり、半導体装置の信
頼性が向上する。上記課題を解決するために、本発明の
電子デバイスは、上記の何れかに記載された薄膜半導体
装置の製造方法を用いて製造された薄膜半導体装置、又
は、上記の何れかに記載された薄膜半導体装置を、画素
のスイッチング手段として備えることを特徴としてい
る。ここで、画素とは、走査線と、データ線と、走査線
とデータ線とに接続されたスイッチング手段と、当該ス
イッチング手段に接続された画素電極からなるものであ
る。この発明によれば、電気特性が良く且つそのばらつ
きが少ない薄膜半導体装置を電気的なスイッチング手段
及び電気光学的なスイッチング手段の少なくとも一方の
スイッチング手段として備えており、動作速度を高速化
することができるため、多数の画素を有するアクティブ
型液晶表示装置、有機ＥＬ表示装置、及びイメージセン
サ等の各種電子デバイスに用いて極めて好適である。In order to solve the above problems, a method of manufacturing a thin film semiconductor device according to the present invention is a method of manufacturing a thin film semiconductor device using a part of a semiconductor film formed on a substrate as an active region. In, a heating mechanism forming step of forming a local heating mechanism for locally heating a part of the semiconductor film on the substrate, and after the heating mechanism forming step,
An active semiconductor film forming step of forming an active semiconductor film as the semiconductor film, and a crystallization step of melting and crystallizing the active semiconductor film in a state where the active semiconductor film is locally heated by the local heating mechanism. And an element isolation step of forming the two active regions by processing the active semiconductor film into an island shape, wherein the active area is formed in the first direction in the element isolation step. It is characterized in that the active semiconductor film is processed so as to be completely included in the local heating mechanism and to be arranged at positions separated by a predetermined distance on both sides near the center of the local heating mechanism. In the invention having such a configuration, first, the local heating mechanism is formed on the substrate (heating mechanism forming step). The local heating mechanism includes, for example, an island-shaped first semiconductor film formed on a substrate and a lower insulating film covering the island-shaped first semiconductor film. Therefore, as a specific example of the local heating mechanism forming step, a first semiconductor film deposition step of depositing a first semiconductor film on a substrate, and a first semiconductor film processing step of processing the first semiconductor film into a predetermined shape, A step including a lower insulating film forming step of forming a lower insulating film on the first semiconductor film can be mentioned. Next, an active semiconductor film is formed on the local heating mechanism (active semiconductor film forming step). The active semiconductor film is made of an amorphous semiconductor film or a crystalline semiconductor film. Therefore, as a specific example of the active semiconductor film forming step,
There is a step of depositing an amorphous semiconductor film on the local heating mechanism, and as a step of further enhancing the crystallinity of the amorphous semiconductor film, a solid phase growth step of crystallizing the amorphous semiconductor film in a solid phase. Alternatively, a melt crystallization improving step of improving the crystallinity of the amorphous semiconductor film through a molten state can be mentioned. Next, the active semiconductor film is melted and crystallized while the active semiconductor film is locally heated by the local heating mechanism (crystallization process). In this crystallization step, as an example, the active semiconductor film is melt-crystallized by irradiating with light from the active semiconductor film side. When irradiated with light, part of the light is absorbed by the active semiconductor film and part of the light passes through the active semiconductor film. The active semiconductor film which has absorbed a certain amount of light is melted and crystallized. On the other hand, the light transmitted through the active semiconductor film is absorbed by the first semiconductor film of the local heating mechanism. The temperature of the first semiconductor film rises due to the absorption of light, and the active semiconductor film on the first semiconductor film is locally heated. Here, the active semiconductor film is in the melt crystallization process, but in the melt crystallization process, crystal grains grow from the low temperature portion toward the high temperature portion. Since only the portion of the active semiconductor film in which the local heating mechanism is arranged below the active semiconductor film has a higher temperature than the surrounding area, crystal grains during cooling and solidification are active semiconductors slightly outside the side of the local heating mechanism. It grows from the film site toward the active semiconductor film site on the center of the local heating mechanism. The temperature difference formed by the local heating mechanism causes lateral growth of crystals when the molten semiconductor film is cooled and solidified. Here, as a specific example of the crystallization process, 20% of the active semiconductor film is provided from the active semiconductor film side.
A step of irradiating a laser beam that transmits a certain degree or more can be mentioned. As a specific example of the laser light, the wavelength of the light is about 5
32 nm solid-state laser harmonics are mentioned, and more specifically, the second harmonic (Nd: YAG2ω laser light) of yttrium aluminum garnet (YAG) laser light with Q-switch oscillation is added. To be After the crystallization process is completed, the active semiconductor film is processed into an island shape to form two active regions (element isolation process). In this element isolation step, the active semiconductor film is processed such that each of the active regions is completely included in the local heating mechanism in the first direction in which the active regions are arranged. The lateral crystal growth in the active semiconductor film always starts at a position of about 1 μm outside the local heating mechanism. Therefore, if the local heating mechanism and the active region are set in the above-mentioned positional relationship, the crystal grain boundaries extending in the second direction across the first direction (current direction when the thin film semiconductor device operates) in the active region. The number of (grain boundaries crossing the current) can always be one near the center of the local heating mechanism. Furthermore, in the present invention, in the first direction in which the active regions are arranged, the active regions are completely included in the local heating mechanism, and are separated by a predetermined distance on both sides near the center of the local heating mechanism. The active semiconductor film is processed so as to be arranged at the position. If the local heating mechanism and the active region are set in such a positional relationship, the crystal grain boundary (the crystal grain boundary that crosses the current) that crosses the first direction (the current direction when the semiconductor device operates) in the active region is set. It can be completely eliminated. That is, since a plurality of current paths that do not cross the crystal grain boundaries can be formed in the active region without fail, the thin film semiconductor device of the present invention is a small silicon-on-insulator (SOI) device using a single crystal silicon thin film. It is equivalent to a device in which a plurality of devices are connected in parallel, and its performance is dramatically improved compared to a general thin film semiconductor device. Further, since there is no crystal grain boundary crossing the first direction in the active region, variations in characteristics of the thin film semiconductor device due to the presence of the crystal grain boundary are eliminated. That is, all the thin film semiconductor devices formed on the substrate have almost the same characteristics. Furthermore, setting the local heating mechanism and the active region in the above-mentioned positional relationship has the effect of reducing the off current of the thin film semiconductor device. Setting the local heating mechanism and the active region in the above-mentioned positional relationship means dividing the active region in the first direction. Then, the source / drain voltage of the thin film semiconductor device is allocated to each active region, and as a result, the electric field in the drain region end depletion region becomes weak. Therefore, the phonon-assisted tunneling phenomenon accompanied by the Pool-Frenkel effect is suppressed, and the off current of the thin film semiconductor device is reduced. As described above, according to the method of manufacturing a thin film semiconductor device of the present invention, there is no crystal grain boundary that crosses the first direction in which the active regions are arranged, and the active region is divided in the first direction. Therefore, it is possible to manufacture a thin film semiconductor device having good electric characteristics and less variation. Further, the method of manufacturing a thin film semiconductor device of the present invention is characterized in that the length of each of the active regions in the first direction is 2 μm or less. According to the present invention, there is an effect that the crystal grain boundaries that cross the first direction can be surely eliminated in the active region. The size of lateral growth of crystal is typically about 2 μm to 2.5 μm, and the maximum is 3.5 μm.
It is a degree. Therefore, the length of the active region in the first direction is 2μ.
By setting m or less, it is possible to surely eliminate the crystal grain boundaries that cross the first direction in the active region. In addition, the method of manufacturing the thin film semiconductor device of the present invention,
The position of each of the active regions is set to a position separated by 0.5 μm or more from the vicinity of the center of the local heating mechanism in the first direction. According to the present invention, there is an effect that it is possible to surely exclude a crystal grain boundary that extends in the second direction crossing the first direction in the active region. In the vicinity of the crystal grain boundary extending in the second direction, the crystal grain boundary portion is a peak and bulges in a mountain shape. According to the present invention, the active region can be formed while avoiding the mountain-shaped region having the crystal grain boundary portion as the apex. That is, since the active region is formed only in the region where the semiconductor film thickness is thin, the electrical characteristics of the semiconductor device are improved. In addition, since the active region is formed in a flat region, the interface between the active region and the gate insulating film becomes good, and the reliability of the semiconductor device is improved. In order to solve the above problems, the thin film semiconductor device of the present invention,
In a thin film semiconductor device using a part of a semiconductor film formed on a substrate as an active region, the semiconductor film has active regions formed at two different locations, and the active regions are arranged in the active region. The present invention is characterized in that only the defined grain boundaries extending in the first direction exist, and one grain boundary extending in the second direction crossing the first direction exists between the active regions. According to the present invention, since there are no crystal grain boundaries extending in the second direction in the active region and the active region is divided in the second direction, the thin film semiconductor device has good electric characteristics and little variation. Further, the thin film semiconductor device of the present invention is characterized in that the length of each of the active regions in the first direction is 2 μm or less. According to this invention, in the active region,
There is an effect that the crystal grain boundary extending in the second direction can be surely eliminated. When a semiconductor film is laterally grown by melt crystallization, the size of lateral crystal growth is typically 2
It is about 2.5 to 2.5 μm, and the maximum is about 3.5 μm. Therefore, by setting the length of the active region in the first direction to be 2 μm or less, it is possible to reliably eliminate the crystal grain boundaries extending in the second direction in the active region.
Further, in the thin film semiconductor device of the present invention, the position of each of the active regions is 0.
The feature is that they are set at positions separated by 5 μm or more. According to the present invention, there is an effect that it is possible to surely exclude a crystal grain boundary that extends in the second direction crossing the first direction in the active region. In the vicinity of the crystal grain boundary extending in the second direction, the crystal grain boundary portion is a peak and bulges in a mountain shape. According to the present invention, the active region can be formed while avoiding the mountain-shaped region having the crystal grain boundary portion as the apex. That is, since the active region is formed only in the region where the semiconductor film thickness is thin, the electrical characteristics of the semiconductor device are improved. Also,
Since the active region is formed in the flat region, the state of the interface between the active region and the gate insulating film becomes good, and the reliability of the semiconductor device is improved. In order to solve the above problems, the electronic device of the present invention is a thin film semiconductor device manufactured by using the method for manufacturing a thin film semiconductor device described in any of the above, or a thin film described in any of the above. A semiconductor device is provided as a pixel switching unit. Here, the pixel includes a scanning line, a data line, a switching means connected to the scanning line and the data line, and a pixel electrode connected to the switching means. According to the present invention, the thin film semiconductor device having good electric characteristics and little variation is provided as at least one of the electrical switching means and the electro-optical switching means, and the operating speed can be increased. Therefore, it is very suitable for use in various electronic devices such as an active liquid crystal display device having a large number of pixels, an organic EL display device, and an image sensor.
【００１０】[0010]
【発明の実施の形態】以下、図面を参照して本発明の一
実施形態による薄膜半導体装置及びその製造方法並びに
当該装置を備える電子デバイスについて詳細に説明す
る。図１は、本発明の一実施形態による電子デバイスの
全体構成の一例を示す斜視図である。図１に示した電子
デバイスは、薄膜トランジスタ（Thin Film Transisto
r, 以下、ＴＦＴと略記する）をスイッチング手段とし
て用いたアクティブマトリクス方式の透過型液晶装置の
例であり、図１（ａ）は液晶装置の全体構成を示す斜視
図であって、図１（ｂ）は図１（ａ）における一画素の
拡大図である。尚、図１においては、理解を容易にする
ため、画素及び画素に設けられたＴＦＴを拡大して図示
している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film semiconductor device, a method of manufacturing the same, and an electronic device equipped with the device according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a perspective view showing an example of the overall configuration of an electronic device according to an embodiment of the present invention. The electronic device shown in FIG. 1 is a thin film transistor (Thin Film Transistor).
r, hereinafter abbreviated as TFT) is an example of an active matrix type transmissive liquid crystal device using switching means, and FIG. 1A is a perspective view showing the entire configuration of the liquid crystal device. 1B is an enlarged view of one pixel in FIG. Note that, in FIG. 1, in order to facilitate understanding, a pixel and a TFT provided in the pixel are enlarged and illustrated.
【００１１】本実施形態による電子デバイスとしての液
晶装置１は、図１（ａ）に示すように、ＴＦＴが形成さ
れた側の素子基板２と対向基板３とが対向配置され、こ
れらの素子基板２と対向基板３との間に誘電率異方性が
正の液晶からなる液晶層（図示省略）が封入されてい
る。素子基板２の内面側には、多数のソース線４及び多
数のゲート線５が互いに交差するように格子状に設けら
れている。各ソース線４と各ゲート線５の交差点の近傍
にはＴＦＴ６が形成されており、各ＴＦＴ６を介して画
素電極７がそれぞれ接続されている。即ち、マトリクス
状に配置された各画素毎に１つのＴＦＴ６と１つの画素
電極７とが設けられている。一方、対向基板３の内面側
全面には、多数の画素がマトリクス状に配列されてなる
表示領域の全体にわたって一つの共通電極８が形成され
ている。In a liquid crystal device 1 as an electronic device according to the present embodiment, as shown in FIG. 1A, an element substrate 2 on the side where a TFT is formed and an opposite substrate 3 are arranged so as to face each other. A liquid crystal layer (not shown) made of liquid crystal having a positive dielectric anisotropy is enclosed between 2 and the counter substrate 3. On the inner surface side of the element substrate 2, a large number of source lines 4 and a large number of gate lines 5 are provided in a grid pattern so as to intersect with each other. TFTs 6 are formed near the intersections of the source lines 4 and the gate lines 5, and the pixel electrodes 7 are connected via the TFTs 6, respectively. That is, one TFT 6 and one pixel electrode 7 are provided for each pixel arranged in a matrix. On the other hand, one common electrode 8 is formed on the entire inner surface of the counter substrate 3 over the entire display area in which a large number of pixels are arranged in a matrix.
【００１２】図１（ｂ）に示すように、ＴＦＴ６は、ゲ
ート線５から延びるゲート電極１０と、ゲート電極１０
を覆う絶縁膜（図示略）と、この絶縁膜上に形成された
多結晶シリコンからなる半導体層１１と、半導体層１１
中のソース領域に電気的に接続されたソース線４から延
びるソース電極１２と、半導体層１１中のドレイン領域
に電気的に接続されたドレイン電極１３とを有してい
る。そして、ＴＦＴ６のドレイン電極１３が画素電極７
に電気的に接続されている。本実施形態においては、画
素電極７がＩＴＯ等の透明導電膜で形成され、対向基板
３側の共通電極８もＩＴＯ等の透明導電膜で形成されて
いる。As shown in FIG. 1B, the TFT 6 includes a gate electrode 10 extending from the gate line 5 and a gate electrode 10.
An insulating film (not shown) that covers the semiconductor layer 11, a semiconductor layer 11 made of polycrystalline silicon formed on the insulating film, and a semiconductor layer 11
It has a source electrode 12 extending from the source line 4 electrically connected to the source region therein and a drain electrode 13 electrically connected to the drain region in the semiconductor layer 11. Then, the drain electrode 13 of the TFT 6 becomes the pixel electrode 7
Electrically connected to. In the present embodiment, the pixel electrode 7 is formed of a transparent conductive film such as ITO, and the common electrode 8 on the counter substrate 3 side is also formed of a transparent conductive film such as ITO.
【００１３】また、図１において、２０，２１はＴＦＴ
６を駆動するための駆動回路（ソースドライバ）を示し
ている。この駆動回路２０，２１は、ＴＦＴ６と同様に
素子基板２の内面側に形成されており、図示せぬ多数の
ＴＦＴを含んで構成されている。この駆動回路２０，２
１には、図示せぬ制御回路から制御信号が供給されてお
り、この制御信号に基づいて各ＴＦＴ６を駆動するため
の駆動信号（走査信号）を生成する。また、図１中の２
２，２３は、ＴＦＴ６を駆動するためのもう一つの駆動
回路（ゲートドライバ）を示している。この駆動回路２
２，２３も多数のＴＦＴを含んで構成され、供給される
制御信号から各ＴＦＴ６を駆動するための駆動信号（デ
ータ信号）を生成する。In FIG. 1, 20 and 21 are TFTs.
6 shows a driving circuit (source driver) for driving the driving circuit 6. The drive circuits 20 and 21 are formed on the inner surface side of the element substrate 2 similarly to the TFT 6, and include a large number of TFTs (not shown). This drive circuit 20, 2
A control signal is supplied to 1 from a control circuit (not shown), and a drive signal (scanning signal) for driving each TFT 6 is generated based on this control signal. In addition, 2 in FIG.
Reference numerals 2 and 23 denote another drive circuit (gate driver) for driving the TFT 6. This drive circuit 2
2 and 23 also include a large number of TFTs, and generate a drive signal (data signal) for driving each TFT 6 from the supplied control signal.
【００１４】以上、本発明の一実施形態による電子デバ
イスの一例としての液晶装置について説明したが、次
に、本発明の実施形態による薄膜半導体装置としてのＴ
ＦＴ６及び駆動回路２０〜２３内に設けられる図示しな
いＴＦＴの製造方法及びその構成の詳細について説明す
る。The liquid crystal device as an example of the electronic device according to the embodiment of the present invention has been described above. Next, T as the thin film semiconductor device according to the embodiment of the present invention will be described.
A method of manufacturing a TFT (not shown) provided in the FT 6 and the drive circuits 20 to 23 and its configuration will be described in detail.
【００１５】〔第１実施形態による薄膜半導体装置及び
その製造方法〕図２〜図６は、本発明の第１実施形態に
よる薄膜半導体装置の製造方法の一例を示す工程図であ
る。図２〜図６において、（ａ）は薄膜半導体装置の断
面図であり、（ｂ）は平面透視図である。尚、以下の説
明においては、図２〜図６中に示したＸＹＺ直交座標系
を設定し、このＸＹＺ直交座標系を参照しつつ各部材の
位置関係について説明する。図２〜図６に示したＸＹＺ
直交座標系は、積層構造を有する薄膜半導体装置の界面
内にＸＹ平面を設定し、界面に直交する方向をＺ軸方向
に設定してある。[Thin Film Semiconductor Device According to First Embodiment and Manufacturing Method Thereof] FIGS. 2 to 6 are process diagrams showing an example of a manufacturing method of the thin film semiconductor device according to the first embodiment of the present invention. 2 to 6, (a) is a cross-sectional view of the thin film semiconductor device, and (b) is a plan perspective view. In the following description, the XYZ rectangular coordinate system shown in FIGS. 2 to 6 is set, and the positional relationship of each member will be described with reference to the XYZ rectangular coordinate system. XYZ shown in FIGS.
In the Cartesian coordinate system, the XY plane is set within the interface of the thin film semiconductor device having the laminated structure, and the direction orthogonal to the interface is set as the Z-axis direction.
【００１６】本実施形態の薄膜半導体装置は、図２に示
すように、まず、基板として厚さ１．１ｍｍの石英基板
１１１を用い、この石英基板１１１上に下地保護膜１１
２として電子サイクロトロン共鳴プラズマ化学気相堆積
法（ＥＣＲ−ＰＥＣＶＤ法）により酸化珪素膜（ＳｉＯ
2膜）を膜厚２００ｎｍ程度堆積する。次に、下地保護
膜１１２としての酸化珪素膜上に低圧化学気相堆積法
（ＬＰＣＶＤ法）により非晶質珪素膜（ａ−Ｓｉ膜）を
膜厚５０ｎｍ程度堆積し、その後フォト・リソグラフィ
ー法により上記非晶質珪素膜をパターニングして第一半
導体膜１１３とする。In the thin film semiconductor device of this embodiment, as shown in FIG. 2, a quartz substrate 111 having a thickness of 1.1 mm is first used as a substrate, and a base protective film 11 is formed on the quartz substrate 111.
2 is a silicon oxide film (SiO 2) formed by electron cyclotron resonance plasma chemical vapor deposition (ECR-PECVD method).
2 film) is deposited to a film thickness of about 200 nm. Next, an amorphous silicon film (a-Si film) having a thickness of about 50 nm is deposited on the silicon oxide film serving as the base protection film 112 by a low pressure chemical vapor deposition method (LPCVD method), and then by a photolithography method. The amorphous silicon film is patterned to form the first semiconductor film 113.
【００１７】第一半導体膜１１３の長さ（Ｙ方向の長
さ）は後述する活性領域の長さ（Ｘ方向の長さ）よりも
約１μｍ長くなるように形成される。尚、詳細は後述す
るが、活性領域のＹ方向の位置は第一半導体膜１１３の
中央付近に設定される。また、第一半導体膜の幅（Ｘ方
向の長さ）は５０μｍ程度に設定され、活性領域は幅方
向（Ｘ方向）に関して完全に第一半導体膜１１３に包含
されるように設定される。The length of the first semiconductor film 113 (the length in the Y direction) is formed to be about 1 μm longer than the length of the active region (the length in the X direction) described later. As will be described in detail later, the position of the active region in the Y direction is set near the center of the first semiconductor film 113. The width (length in the X direction) of the first semiconductor film is set to about 50 μm, and the active region is set to be completely included in the first semiconductor film 113 in the width direction (X direction).
【００１８】第一半導体膜１１３を形成すると、次に、
第一半導体膜１１３上に下側絶縁膜１１４としてＥＣＲ
−ＰＥＣＶＤ法により酸化珪素膜を膜厚１６０ｎｍ程度
堆積する。上述した第一半導体膜１１３と下側絶縁膜１
１４とは、後に活性領域と化す半導体膜（活性半導体
膜）部位を局所的に加熱する発熱部材であり、本発明に
いう局所加熱機構に相当するものである。尚、第一半導
体膜１１３及び下側絶縁膜１１４を形成する工程は、本
発明にいう加熱機構形成工程に相当する。After the first semiconductor film 113 is formed, next,
ECR as the lower insulating film 114 on the first semiconductor film 113
A silicon oxide film is deposited to a thickness of about 160 nm by PECVD. The first semiconductor film 113 and the lower insulating film 1 described above
Reference numeral 14 denotes a heat generating member that locally heats a semiconductor film (active semiconductor film) portion that will later become an active region, and corresponds to the local heating mechanism according to the present invention. The step of forming the first semiconductor film 113 and the lower insulating film 114 corresponds to the heating mechanism forming step of the present invention.
【００１９】以上の工程が終了すると、下側絶縁膜１１
４としての酸化珪素膜上に活性半導体膜１１５としてＬ
ＰＣＶＤ法により非晶質珪素膜を膜厚５０ｎｍ程度堆積
し、その後固相成長法により窒素雰囲気下６００℃にて
４８時間の熱処理を施して活性半導体膜１１５の結晶性
を改善し、更に活性半導体膜１１５としての大粒径多結
晶珪素膜にキセノン塩素（ＸｅＣｌ）エキシマレーザ
（波長３０８ｎｍ）を照射して活性珪素膜中の結晶内部
欠陥を低減する。この工程は本発明にいう活性半導体膜
形成工程に相当する。When the above steps are completed, the lower insulating film 11
L as the active semiconductor film 115 on the silicon oxide film as 4.
An amorphous silicon film is deposited to a thickness of about 50 nm by the PCVD method, and then heat treatment is performed at 600 ° C. for 48 hours in a nitrogen atmosphere by the solid phase growth method to improve the crystallinity of the active semiconductor film 115. The large grain polycrystalline silicon film as the film 115 is irradiated with a xenon chlorine (XeCl) excimer laser (wavelength 308 nm) to reduce crystal internal defects in the active silicon film. This step corresponds to the active semiconductor film forming step according to the present invention.
【００２０】以上の工程が終了すると、第一半導体膜１
１３と下側絶縁膜１１４とからなる発熱部材によって活
性半導体膜１１５を局所的に加熱した状態で活性半導体
膜１１５を溶融結晶化させる工程が行われる。具体的に
は、図３（ａ）に示すように、活性半導体膜１１５とし
ての多結晶珪素膜側からイットリウムアルミニウムガー
ネットにＮｄ3+イオンをドープしたものを母体結晶とし
たレーザ（ＹＡＧレーザ：波長１０６４ｎｍ）の第二高
調波を用いたレーザ（ＹＡＧ２ωレーザ：波長５３２ｎ
ｍ）から射出されるＹＡＧ２ωレーザ光１１６を照射す
る。When the above steps are completed, the first semiconductor film 1
A step of melting and crystallizing the active semiconductor film 115 in a state where the active semiconductor film 115 is locally heated by a heat generating member composed of 13 and the lower insulating film 114 is performed. Specifically, as shown in FIG. 3A, a laser (YAG laser: wavelength) obtained by doping yttrium aluminum garnet with Nd 3+ ions from the polycrystalline silicon film side as the active semiconductor film 115 is used as a host crystal. Laser (YAG2ω laser: wavelength 532n) using the second harmonic of 1064 nm)
The YAG 2ω laser beam 116 emitted from the m) is irradiated.
【００２１】ＹＡＧ２ωレーザ光１１６の照射領域は長
さ１５ｍｍで幅６５μｍの長方形状であり、その照射領
域内における光強度分布は、長さ方向に略台形状に分布
しており、幅方向については、略台形状又は略ガウス関
数的な光強度分布を有しているのが好ましい。ＹＡＧ２
ωレーザ光１１６の照射領域は、その長さ方向が第一半
導体膜１１３の幅方向（Ｘ方向）とほぼ一致するように
設定される。従って、ＹＡＧ２ωレーザ光１１６は、照
射領域の幅の分だけ移動（進行）させて順次照射される
が、この照射領域の進行方向と薄膜半導体装置のソース
・ドレイン方向とがほぼ平行になる。The irradiation area of the YAG 2ω laser light 116 is a rectangular shape having a length of 15 mm and a width of 65 μm, and the light intensity distribution in the irradiation area is distributed in a substantially trapezoidal shape in the length direction and in the width direction. It is preferable that the light intensity distribution has a substantially trapezoidal shape or a Gaussian function. YAG2
The irradiation area of the ω laser light 116 is set so that its length direction is substantially aligned with the width direction (X direction) of the first semiconductor film 113. Therefore, the YAG 2ω laser light 116 is moved (advanced) by the width of the irradiation region and is sequentially irradiated, but the traveling direction of this irradiation region and the source / drain direction of the thin film semiconductor device are substantially parallel.
【００２２】ここで、ＹＡＧ２ωレーザ光１１６の照射
エネルギー密度は４５０ｍＪ・ｃｍ -2で、活性半導体膜
１１５上の任意の一点は２０回のパルスレーザ光が照射
される。ＹＡＧ２ωレーザ光１１６を照射すると、ＹＡ
Ｇ２ωレーザ光１１６の一部は活性半導体膜１１５とし
ての多結晶珪素膜に吸収されるが、残りのＹＡＧ２ωレ
ーザ光１１６は活性半導体膜１１５としての多結晶珪素
膜に吸収されずに透過する。活性半導体膜１１５として
の多結晶珪素膜を透過したＹＡＧ２ωレーザ光１１７は
下側絶縁膜１１４としての酸化珪素膜を透過して第一半
導体膜１１３に吸収される。尚、下側絶縁膜１１４に入
射したＹＡＧ２ωレーザ光１１７の一部は、酸化珪素膜
１１内において多重反射又は干渉した後で第一半導体膜
１１３に吸収される。Irradiation of YAG 2ω laser light 116
Energy density is 450 mJ · cm -2And the active semiconductor film
Irradiation of any one point on 115 with pulsed laser light 20 times
To be done. When the YAG 2ω laser light 116 is irradiated, YA
A part of the G2ω laser light 116 is used as the active semiconductor film 115.
Is absorbed by all polycrystalline silicon films, but the remaining YAG2ω
Laser light 116 is polycrystalline silicon as the active semiconductor film 115.
Permeates without being absorbed by the membrane. As the active semiconductor film 115
YAG2ω laser beam 117 transmitted through the polycrystalline silicon film of
The first half is transmitted through the silicon oxide film as the lower insulating film 114.
It is absorbed by the conductor film 113. In addition, the lower insulating film 114
A part of the emitted YAG 2ω laser light 117 is a silicon oxide film.
First semiconductor film after multiple reflection or interference in 11
Absorbed by 113.
【００２３】第一半導体膜１１３はＹＡＧ２ωレーザ光
１１７を吸収したことにより温度が上昇し、熱を持つよ
うになる。この第一半導体膜１１３から放出される熱１
１８が活性半導体膜１１５に影響して、第一半導体膜１
１３直上の活性半導体膜１１５の温度が、第一半導体膜
１１３直上以外の活性半導体膜１１５の温度よりも高く
なる。こうして生じた活性半導体膜１１５内の温度差に
より活性半導体膜１１５の結晶成長が温度が低い領域
（第一半導体膜１１３直上以外の活性半導体膜から温度
が高い領域（第一半導体膜１１３直上の活性半導体膜）
へ（図３中Ｙ方向）と生じる。The first semiconductor film 113 rises in temperature and absorbs the YAG 2ω laser light 117, and becomes heat. Heat 1 radiated from the first semiconductor film 113
18 affects the active semiconductor film 115, and the first semiconductor film 1
The temperature of the active semiconductor film 115 immediately above 13 is higher than the temperature of the active semiconductor film 115 other than immediately above the first semiconductor film 113. Due to the temperature difference in the active semiconductor film 115 thus generated, a region where the crystal growth of the active semiconductor film 115 is low (a region where the temperature is higher than that of the active semiconductor film other than immediately above the first semiconductor film 113 (activity above the first semiconductor film 113). Semiconductor film)
To (Y direction in FIG. 3).
【００２４】Ｙ軸方向に関しては、第一半導体膜１１３
の直上が最も温度が高く、この位置からＹ方向及び−Ｙ
方向へ進むに従って、温度が低くなる。従って、結晶成
長はＹ方向及び−Ｙ方向へ進行する訳であるが、最終的
に第一半導体膜１１３の中央直上で二つの成長した結晶
が衝突し、そこに結晶の成長方向（Ｙ方向：第１方向）
に垂直な方向（Ｘ方向：第２方向）に延びる結晶粒界１
１９が生ずる。図３（ｂ）に示すように、Ｘ軸方向に延
びる結晶粒界１１９は１つのみであり、他の結晶粒界は
Ｙ軸方向へ延びていることに注意されたい。尚、結晶の
横成長（Ｘ方向及びＹ方向）の大きさは典型的には２μ
ｍ〜２．５μｍ程度であり、最大で３．５μｍ程度とな
る。尚、以上の工程は、本発明にいう結晶化工程に相当
する。Regarding the Y-axis direction, the first semiconductor film 113
The temperature is the highest just above, from this position in the Y direction and -Y
The temperature decreases in the direction. Therefore, although the crystal growth proceeds in the Y direction and the −Y direction, finally, the two grown crystals collide with each other right above the center of the first semiconductor film 113, and the crystal growth direction (Y direction: (First direction)
Grain boundaries 1 extending in a direction perpendicular to the direction (X direction: second direction)
19 occurs. Note that, as shown in FIG. 3B, only one grain boundary 119 extends in the X-axis direction, and the other grain boundaries 119 extend in the Y-axis direction. The size of the lateral growth of the crystal (X direction and Y direction) is typically 2 μm.
m to about 2.5 μm, and the maximum is about 3.5 μm. The above process corresponds to the crystallization process in the present invention.
【００２５】ＹＡＧ２ωレーザー光１１６を照射して活
性半導体膜１１５の結晶化を行なった後は、活性半導体
膜１１５を島状に加工して活性領域を形成する素子分離
工程として、フォト・リソグラフィー法により活性半導
体膜１１５のパターニングを行う。ここで、図４（ｂ）
に示すように、パターニング後の活性半導体膜１１５の
幅（Ｘ方向の長さ）が第一半導体膜１１３の幅（Ｘ方向
の長さ）よりも短くなり、且つ活性半導体膜１１５の長
さ（Ｙ方向の長さ）が第一半導体膜１１３の長さ（Ｙ方
向の長さ）よりも長くなるようにパターニングする。こ
のようにパターニングすることで、活性領域が長さ方向
（Ｙ方向）に関して局所加熱機構としての第一半導体膜
１１３に完全に含まれることになる。After the active semiconductor film 115 is crystallized by irradiating the YAG 2ω laser beam 116, the active semiconductor film 115 is processed into an island shape to form an active region by a photolithography method as an element isolation process. The active semiconductor film 115 is patterned. Here, FIG. 4 (b)
As shown in, the width (length in the X direction) of the active semiconductor film 115 after patterning becomes shorter than the width (length in the X direction) of the first semiconductor film 113, and the length of the active semiconductor film 115 ( Patterning is performed so that the length in the Y direction) is longer than the length (length in the Y direction) of the first semiconductor film 113. By patterning in this manner, the active region is completely included in the first semiconductor film 113 as the local heating mechanism in the length direction (Y direction).
【００２６】以上の工程が終了すると、活性半導体膜１
１５上にゲート絶縁膜としてＥＣＲ−ＰＥＣＶＤ法によ
り酸化珪素膜を膜厚６０ｎｍ程度堆積する。この酸化珪
素膜は、ゲート絶縁膜１２０として用いられる。そし
て、ゲート絶縁膜１２０としての酸化珪素膜上にスパッ
タリング法により窒化タンタル（ＴａＮ）膜を５０ｎｍ
程度堆積し、タンタル（Ｔａ）膜を４５０ｎｍ程度堆積
する。その後、フォト・リソグラフィー法により上記Ｔ
ａＮ膜、Ｔａ膜をパターニングしてゲート電極１２１
ａ，１２１ｂとする。When the above steps are completed, the active semiconductor film 1
A silicon oxide film having a thickness of about 60 nm is deposited on 15 as a gate insulating film by the ECR-PECVD method. This silicon oxide film is used as the gate insulating film 120. Then, a 50 nm thick tantalum nitride (TaN) film is formed on the silicon oxide film as the gate insulating film 120 by a sputtering method.
And a tantalum (Ta) film is deposited to about 450 nm. After that, the T
The gate electrode 121 is formed by patterning the aN film and the Ta film.
a, 121b.
【００２７】このパターニングを行なう際に、薄膜半導
体装置のチャネル形成領域となるゲート電極１２１ａ，
１２１ｂ直下の活性半導体膜１１５が、長さ方向（Ｙ方
向）に関して第一半導体膜１１３に完全に含まれ、且つ
第一半導体膜１１３の長さ方向に関する中心近傍、即ち
結晶の横成長方向（Ｙ方向：第１方向）に垂直な方向
（Ｘ方向：第２方向）の結晶粒界１１９を含まず、且つ
Ｙ方向に関して第一半導体膜１１３の中心近傍の両側に
位置するようにゲート電極１２１ａ，１２１ｂを形成す
る。ゲート電極１２１ａ，１２１ｂのＹ方向の長さは２
μｍとし、ゲート電極１２１ａ，１２１ｂのＹ方向の位
置はＹ方向における第一半導体膜１１３の中心直上位置
からＹ方向及びーＹ方向へそれぞれ０．５μｍ離間した
位置に設定する。尚、図４（ｂ）に示すようにゲート電
極１２１ａ，１２１ｂは、共通の電極１２１に接続され
ている。When this patterning is performed, the gate electrode 121a which becomes the channel forming region of the thin film semiconductor device,
The active semiconductor film 115 immediately below 121b is completely included in the first semiconductor film 113 in the length direction (Y direction), and is close to the center in the length direction of the first semiconductor film 113, that is, the crystal lateral growth direction (Y Direction: the gate electrodes 121a, which do not include the crystal grain boundaries 119 in the direction perpendicular to the first direction (X direction: the second direction) and are located on both sides near the center of the first semiconductor film 113 in the Y direction. 121b is formed. The length of the gate electrodes 121a and 121b in the Y direction is 2
The positions of the gate electrodes 121a and 121b in the Y direction are set at positions separated by 0.5 μm in the Y direction from the position just above the center of the first semiconductor film 113 in the Y direction. As shown in FIG. 4B, the gate electrodes 121a and 121b are connected to the common electrode 121.
【００２８】以上の工程を経て、ゲート電極１２１ａ，
１２１ｂを形成すると、次にゲート電極１２１ａ，１２
１ｂをマスクとしてドナー又はアクセプターとなる不純
物イオンをイオンドーピング法により打ち込み、図５
（ａ）、図５（ｂ）に示すように、ソース領域１１５
ａ、ドレイン領域１１５ｃ、及びチャネル形成領域１１
５ｂを自己整合的に形成する。この時、活性半導体膜１
１５の結晶の横成長方向（Ｙ方向）に沿ってキャリアが
移動するようにソース領域１１５ａ及びドレイン領域１
１５ｃを形成する。そして、ソース領域１１５ａ及びド
レイン領域１１５ｃに添加された不純物元素の活性化を
行なうために、窒素雰囲気下において、３００℃にて４
時間の熱処理を施す。ここで、チャネル形成領域１１５
ｂは、ゲート電極１２１ａ，１２１ｂをマスクとして形
成されるため、Ｘ方向に延びた結晶粒界１１９の両側に
形成される。つまり、２つのチャネル形成領域１１５ｂ
の間に結晶流界１１９が位置するように形成される。Through the above steps, the gate electrodes 121a,
After forming 121b, the gate electrodes 121a, 12
Impurity ions serving as a donor or an acceptor are implanted by the ion doping method using 1b as a mask.
As shown in FIGS. 5A and 5B, the source region 115
a, the drain region 115c, and the channel formation region 11
5b is formed in a self-aligned manner. At this time, the active semiconductor film 1
Source region 115a and drain region 1 so that carriers move along the lateral growth direction (Y direction) of the crystal of No. 15.
15c is formed. Then, in order to activate the impurity element added to the source region 115a and the drain region 115c, in a nitrogen atmosphere, at 300 ° C. for 4 hours.
Heat treatment for an hour. Here, the channel formation region 115
Since b is formed using the gate electrodes 121a and 121b as a mask, it is formed on both sides of the crystal grain boundary 119 extending in the X direction. That is, the two channel formation regions 115b
Is formed so that the crystal flow field 119 is located between the two.
【００２９】その後、層間絶縁膜１２２としてプラズマ
ＣＶＤ法（ＰＥＣＶＤ法）によりＴＥＯＳ（Ｓｉ（ＯＣ
Ｈ2ＣＨ3）4）と酸素とを原料気体とした酸化珪素膜を
膜厚５００ｎｍ程度堆積する。最後に、フォト・リソグ
ラフィー法によりコンタクト・ホールを形成した後で、
スパッタリング法によりアルミニウム（Ａｌ）を堆積
し、フォト・リソグラフィー法によりＡｌをパターニン
グしてソース電極１２３及びドレイン電極１２４を形成
して薄膜半導体装置が製造される。After that, as the interlayer insulating film 122, TEOS (Si (OC) is formed by the plasma CVD method (PECVD method).
A silicon oxide film using H 2 CH 3 ) 4 ) and oxygen as source gases is deposited to a film thickness of about 500 nm. Finally, after forming contact holes by photolithography,
A thin film semiconductor device is manufactured by depositing aluminum (Al) by a sputtering method and patterning Al by a photolithography method to form a source electrode 123 and a drain electrode 124.
【００３０】以上説明したように、本発明の第１実施形
態による薄膜半導体装置によれば、ゲート電極１２１
ａ，１２１ｂの直下に形成されるチャネル形成領域１１
５ｂには、キャリアが移動する方向（Ｙ方向）に垂直な
方向（Ｘ方向）に延びる結晶粒界が存在しないため、単
結晶半導体装置並みの高性能のスイッチング特性を有
し、しかも薄膜半導体装置毎の特性のばらつきがない薄
膜半導体装置を製造することができる。As described above, according to the thin film semiconductor device of the first embodiment of the present invention, the gate electrode 121
Channel formation region 11 formed directly under a and 121b
Since 5b does not have a crystal grain boundary extending in a direction (X direction) perpendicular to the direction in which carriers move (Y direction), it has a high-performance switching characteristic comparable to that of a single crystal semiconductor device, and a thin film semiconductor device. It is possible to manufacture a thin film semiconductor device in which there is no variation in characteristics for each.
【００３１】〔第２実施形態による薄膜半導体装置〕次
に、本発明の第２実施形態による薄膜半導体装置及びそ
の製造方法について説明する。尚、以下の説明において
は、以上説明した第１実施形態による薄膜半導体装置及
びその製造方法と共通する部分については、説明を簡略
化し又は説明を割愛する。図７は、本発明の第２実施形
態による薄膜半導体装置を説明するための図であり、
（ａ）は薄膜半導体装置の断面図であり、（ｂ）は平面
透視図である。尚、第１実施形態と同様に、ＸＹＺ直交
座標系を設定し、このＸＹＺ直交座標系を参照しつつ各
部材の位置関係について説明する。図２〜図６に示した
ＸＹＺ直交座標系は、積層構造を有する薄膜半導体装置
の界面内にＸＹ平面を設定し、界面に直交する方向をＺ
軸方向に設定してある。[Thin Film Semiconductor Device According to Second Embodiment] Next, a thin film semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same will be described. In the following description, the parts common to those of the thin-film semiconductor device and the method of manufacturing the same according to the first embodiment described above will be simplified or omitted. FIG. 7 is a view for explaining the thin film semiconductor device according to the second embodiment of the present invention,
(A) is sectional drawing of a thin film semiconductor device, (b) is a plane perspective view. Similar to the first embodiment, an XYZ rectangular coordinate system is set, and the positional relationship of each member will be described with reference to this XYZ rectangular coordinate system. The XYZ orthogonal coordinate system shown in FIGS. 2 to 6 sets the XY plane in the interface of the thin film semiconductor device having the laminated structure, and the direction orthogonal to the interface is Z.
It is set in the axial direction.
【００３２】本実施形態の薄膜半導体装置は、基板とし
て厚さ１．１ｍｍの石英基板２１１があり、この石英基
板２１１上に下地保護膜２１２として酸化珪素膜が膜厚
２００ｎｍ程度に形成されている。更に、下地保護膜２
１２としての酸化珪素膜上に活性半導体膜として多結晶
珪素膜２１３が膜厚５０ｎｍ程度形成されている。ここ
で、本発明の第１実施形態と同様に、下地保護膜２１２
としての酸化珪素膜と活性半導体膜としての多結晶珪素
膜２１３との間に発熱部材として第一半導体膜と下側絶
縁膜とが存在していても良い。In the thin film semiconductor device of this embodiment, a 1.1 mm-thick quartz substrate 211 is used as a substrate, and a silicon oxide film is formed as a base protective film 212 on the quartz substrate 211 to a film thickness of about 200 nm. . Further, the base protective film 2
A polycrystalline silicon film 213 as an active semiconductor film is formed on the silicon oxide film 12 as a film thickness of about 50 nm. Here, similarly to the first embodiment of the present invention, the base protective film 212.
The first semiconductor film and the lower insulating film may be present as a heat generating member between the silicon oxide film as the above and the polycrystalline silicon film 213 as the active semiconductor film.
【００３３】また、上述した活性半導体膜としての多結
晶珪素膜２１３の上にゲート絶縁膜２１５としての酸化
珪素膜が形成されており、このゲート絶縁膜２１５とし
ての酸化珪素膜上にゲート電極２１６ａ，２１６ｂとし
て膜厚５０ｎｍ程度の窒化タンタル（ＴａＮ）膜と膜厚
４５０ｎｍ程度のタンタル（Ｔａ）膜が形成されてい
る。更に、ゲート電極２１６ａ，２１６ｂ及びゲート絶
縁膜２１５上には、層間絶縁膜２１７としての酸化珪素
膜とアルミニウム（Ａｌ）からなるソース電極２１８及
びドレイン電極２１９が形成されている。本実施形態の
薄膜半導体装置は以上の構成を有している。A silicon oxide film as a gate insulating film 215 is formed on the above-described polycrystalline silicon film 213 as an active semiconductor film, and a gate electrode 216a is formed on the silicon oxide film as the gate insulating film 215. , 216b, a tantalum nitride (TaN) film having a film thickness of about 50 nm and a tantalum (Ta) film having a film thickness of about 450 nm are formed. Further, on the gate electrodes 216a and 216b and the gate insulating film 215, a source electrode 218 and a drain electrode 219 made of a silicon oxide film as an interlayer insulating film 217 and aluminum (Al) are formed. The thin film semiconductor device of this embodiment has the above-described configuration.
【００３４】第１実施形態と同様に、本実施形態におい
てもチャネル形成領域２１３ｂは長さ方向（Ｙ方向）に
２つ形成され、この２つのチャネル形成領域２１３ｂの
間に長さ方向（Ｙ方向）を横切る方向（Ｘ方向）に延び
る結晶粒界２１４が一つ存在する。そして、２つチャネ
ル形成領域２１３ｂ内には、Ｘ方向に延びる結晶粒界が
存在しない。２つのチャネル形成領域２１３ｂの間、チ
ャネル形成領域２１３ｂを挟む２つの領域（図７中斜線
を付した領域）は不純物イオンが打ち込まれた低抵抗領
域であり、チャネル形成領域２１３ｂを挟む２つの領域
は、それぞれソース領域２１３ａ及びドレイン領域２１
３ｃである。また、チャネル形成領域２１３ｂのＹ方向
の長さはそれぞれ２μｍであり、２つのチャネル形成領
域２１３ｂ各々は、Ｘ方向に延びる結晶粒界２１４から
ぞれぞれＹ方向、−Ｙ方向に０．５μｍ離間した位置に
形成されている。Similar to the first embodiment, also in this embodiment, two channel forming regions 213b are formed in the length direction (Y direction), and the two channel forming regions 213b are formed between the two channel forming regions 213b in the length direction (Y direction). ), There is one grain boundary 214 extending in the direction (X direction). Further, there is no crystal grain boundary extending in the X direction in the two channel formation regions 213b. Between the two channel formation regions 213b, two regions sandwiching the channel formation region 213b (hatched regions in FIG. 7) are low resistance regions into which impurity ions are implanted, and two regions sandwiching the channel formation region 213b. Are the source region 213a and the drain region 21 respectively.
3c. In addition, the length of the channel formation region 213b in the Y direction is 2 μm, and the two channel formation regions 213b each have 0.5 μm in the Y direction and −Y direction from the crystal grain boundaries 214 extending in the X direction. It is formed at a separated position.
【００３５】以上説明したように、本発明の第２実施形
態による薄膜半導体装置によれば、薄膜半導体装置のチ
ャネル形成領域となるゲート電極直下の活性領域に、キ
ャリアが移動する方向に垂直な方向に延びる結晶粒界が
存在しないので、単結晶半導体装置並みの高性能な薄膜
半導体装置が得られる。As described above, according to the thin film semiconductor device of the second embodiment of the present invention, the direction perpendicular to the direction in which carriers move in the active region immediately below the gate electrode, which is the channel forming region of the thin film semiconductor device. Since there is no crystal grain boundary extending to, a high-performance thin film semiconductor device equivalent to a single crystal semiconductor device can be obtained.
【００３６】以上、本発明の第１、第２実施形態による
薄膜半導体装置、及びその製造方法、並びに薄膜半導体
装置を備える電子デバイスについて説明したが、本発明
は上記実施形態に制限されず、本発明の範囲内で自由に
変更が可能である。例えば、上記実施形態では、薄膜半
導体装置として液晶表示装置の画素を駆動するために設
けられるＴＦＴ及びこのＴＦＴを駆動するための駆動装
置内に設けられるＴＦＴを例に挙げて説明したが。しか
しながら、本発明は液晶表示装置に設けられるＴＦＴの
みならず、有機ＥＬ表示装置に設けられるＴＦＴにも適
用することができる。勿論、有機ＥＬ表示装置の場合
も、画素を駆動するために設けられるＴＦＴ及びこのＴ
ＦＴを駆動するための駆動装置内に設けられるＴＦＴに
適用することができる。つまるところ、本発明は、トラ
ンジスタを製造する過程で活性領域内に結晶粒界が生
じ、電気特性が悪化する場合の全般について適用可能で
ある。Although the thin film semiconductor device and the method of manufacturing the same according to the first and second embodiments of the present invention and the electronic device including the thin film semiconductor device have been described above, the present invention is not limited to the above embodiments. Modifications can be freely made within the scope of the invention. For example, in the above embodiment, the thin film semiconductor device has been described by taking the TFT provided for driving the pixel of the liquid crystal display device and the TFT provided in the driving device for driving the TFT as an example. However, the present invention can be applied not only to the TFT provided in the liquid crystal display device but also to the TFT provided in the organic EL display device. Of course, also in the case of the organic EL display device, the TFT provided for driving the pixel and the T
It can be applied to the TFT provided in the driving device for driving the FT. After all, the present invention can be generally applied to the case where crystal grain boundaries are generated in the active region during the process of manufacturing a transistor and electrical characteristics are deteriorated.
【００３７】また、上記実施形態では、電子デバイスと
して液晶表示装置を例に挙げたが、有機ＥＬ表示装置及
びイメージセンサのみならず、液晶プロジェクタ、マル
チメディア対応のパーソナルコンピュータ（ＰＣ）及び
エンジニアリング・ワークステーション（ＥＷＳ）、ペ
ージャ、携帯電話、ワードプロセッサ、テレビ、ビュー
ファインダ型又はモニタ直視型のビデオテープレコー
ダ、電子手帳、電子卓上計算機、カーナビゲーション装
置、ＰＯＳ端末、タッチパネルを備えた装置等の電子デ
バイスに適用することが可能である。In the above embodiment, the liquid crystal display device is taken as an example of the electronic device, but not only the organic EL display device and the image sensor, but also a liquid crystal projector, a multimedia compatible personal computer (PC) and an engineering work. Stations (EWS), pagers, mobile phones, word processors, televisions, viewfinder type or monitor direct-view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation devices, POS terminals, electronic devices such as devices with a touch panel It is possible to apply.
【００３８】[0038]
【発明の効果】以上説明したように、本発明によれば、
結晶性の良い大粒径の結晶粒から成る半導体膜から成
り、チャネル形成領域の結晶粒界の位置が制御された、
電気特性が良く、ばらつきの少ない薄膜半導体装置を提
供することができるという効果がある。また、本発明の
薄膜半導体装置の製造方法によると、安価なガラス基板
の使用が可能となる低温プロセスを用いて高性能な薄膜
半導体装置を容易に且つ安定的に製造することができる
という効果がある。従って、本発明の薄膜半導体装置、
及びその製造方法をアクティブ・マトリックス液晶表示
装置に適用した場合には、大型で高品質な液晶表示装置
を容易に且つ安定的に製造することができる。この発明
によれば、電気特性が良く且つそのばらつきが少ない薄
膜半導体装置を電気的なスイッチング手段及び電気光学
的なスイッチング手段の少なくとも一方のスイッチング
手段として備えており、動作速度を高速化することがで
きるため、多数の画素を有するアクティブ型液晶表示装
置、有機ＥＬ表示装置、及びイメージセンサ等の各種電
子デバイスに用いて極めて好適である。更に、他の電子
デバイスの製造に適用した場合にも高品質な電子デバイ
スを容易に且つ安定的に製造することができる。As described above, according to the present invention,
It is composed of a semiconductor film composed of large crystal grains with good crystallinity, and the position of the crystal grain boundary of the channel formation region is controlled.
There is an effect that it is possible to provide a thin film semiconductor device having good electric characteristics and little variation. Further, according to the method of manufacturing a thin film semiconductor device of the present invention, it is possible to easily and stably manufacture a high performance thin film semiconductor device by using a low temperature process that enables the use of an inexpensive glass substrate. is there. Therefore, the thin film semiconductor device of the present invention,
And when the manufacturing method thereof is applied to an active matrix liquid crystal display device, a large-sized and high-quality liquid crystal display device can be manufactured easily and stably. According to the present invention, the thin film semiconductor device having good electric characteristics and little variation is provided as at least one of the electrical switching means and the electro-optical switching means, and the operating speed can be increased. Therefore, it is very suitable for use in various electronic devices such as an active liquid crystal display device having a large number of pixels, an organic EL display device, and an image sensor. Further, when applied to the production of other electronic devices, high quality electronic devices can be easily and stably produced.
【図１】 本発明の一実施形態による電子デバイスの全
体構成の一例を示す斜視図である。FIG. 1 is a perspective view showing an example of the overall configuration of an electronic device according to an embodiment of the present invention.
【図２】 本発明の第１実施形態による薄膜半導体装置
の製造方法の一例を示す工程図であり、（ａ）は薄膜半
導体装置の断面図であり、（ｂ）は平面透視図である。FIG. 2 is a process diagram showing an example of the method of manufacturing the thin film semiconductor device according to the first embodiment of the present invention, (a) is a cross-sectional view of the thin film semiconductor device, and (b) is a plan perspective view.
【図３】 本発明の第１実施形態による薄膜半導体装置
の製造方法の一例を示す工程図であり、（ａ）は薄膜半
導体装置の断面図であり、（ｂ）は平面透視図である。FIG. 3 is a process diagram showing an example of the method of manufacturing the thin film semiconductor device according to the first embodiment of the present invention, (a) is a cross-sectional view of the thin film semiconductor device, and (b) is a plan perspective view.
【図４】 本発明の第１実施形態による薄膜半導体装置
の製造方法の一例を示す工程図であり、（ａ）は薄膜半
導体装置の断面図であり、（ｂ）は平面透視図である。FIG. 4 is a process diagram showing an example of the method of manufacturing the thin film semiconductor device according to the first embodiment of the present invention, (a) is a cross-sectional view of the thin film semiconductor device, and (b) is a plan perspective view.
【図５】 本発明の第１実施形態による薄膜半導体装置
の製造方法の一例を示す工程図であり、（ａ）は薄膜半
導体装置の断面図であり、（ｂ）は平面透視図である。FIG. 5 is a process diagram showing an example of the method of manufacturing the thin film semiconductor device according to the first embodiment of the present invention, (a) is a cross-sectional view of the thin film semiconductor device, and (b) is a plan perspective view.
【図６】 本発明の第１実施形態による薄膜半導体装置
の製造方法の一例を示す工程図であり、（ａ）は薄膜半
導体装置の断面図であり、（ｂ）は平面透視図である。6A and 6B are process diagrams showing an example of a method of manufacturing the thin film semiconductor device according to the first embodiment of the present invention, FIG. 6A is a sectional view of the thin film semiconductor device, and FIG.
【図７】 本発明の第２実施形態による薄膜半導体装置
を説明するための図であり、（ａ）は薄膜半導体装置の
断面図であり、（ｂ）は平面透視図である。7A and 7B are views for explaining a thin film semiconductor device according to a second embodiment of the present invention, FIG. 7A is a sectional view of the thin film semiconductor device, and FIG. 7B is a plan perspective view.
２０〜２３……駆動回路
１１１，２１１……石英基板
１１２，２１２……下地保護膜
１１３……第一半導体膜
１１４……下側絶縁膜
１１５，２１３……活性半導体膜
１１５ａ，２１３ａ……ソース領域
１１５ｃ，２１３ｃ……ドレイン領域
１１５ｂ，２１３ｂ……チャネル形成領域
１１６……ＹＡＧ２ωレーザ光
１１７……活性半導体膜を透過したＹＡＧ２ωレーザ光
１１８……第一半導体膜の熱
１１９，２１４……結晶粒界
１２０，２１５……ゲート絶縁膜
１２１ａ，１２１ｂ，２１６ａ，２１６ｂ……ゲート電
極
１２２，２１７……層間絶縁膜
１２３，２１８……ソース電極
１２４，２１９……ドレイン電極20 to 23 ... Driving circuits 111 and 211 ... Quartz substrates 112 and 212 ... Base protection film 113 ... First semiconductor film 114 ... Lower insulating films 115 and 213 ... Active semiconductor films 115a and 213a ... Source Regions 115c, 213c ... Drain regions 115b, 213b ... Channel formation region 116 ... YAG2.omega. Laser light 117 ... YAG2.omega. Laser light 118 transmitted through the active semiconductor film ... Heat of the first semiconductor film 119, 214 ... Crystal grains Fields 120, 215 ... Gate insulating films 121a, 121b, 216a, 216b ... Gate electrodes 122, 217 ... Interlayer insulating films 123, 218 ... Source electrodes 124, 219 ... Drain electrodes
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/78 ６１８Ｚ (72)発明者 宮坂 光敏 長野県諏訪市大和３丁目３番５号 セイコ ーエプソン株式会社内 (72)発明者 小川 哲也 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 (72)発明者 時岡 秀忠 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 Ｆターム(参考） 2H092 JA25 JA29 JA31 JA33 JA35 JA43 JB13 KA04 KA07 KA12 KA17 KA22 MA08 MA13 MA17 MA29 MA35 MA37 NA22 NA27 5C094 AA13 AA25 AA42 AA43 AA48 AA53 BA03 BA27 BA43 CA19 DA09 DA13 DB01 DB04 EA04 EB02 FA01 FA02 FB12 FB14 FB15 GB10 JA08 5F052 AA02 AA17 BA01 BA04 BA07 BB02 BB07 DA02 DB02 DB03 EA11 FA04 FA19 HA01 JA01 5F110 AA30 BB01 BB02 CC02 DD03 DD11 DD12 DD13 DD17 EE01 EE04 EE14 EE28 EE44 FF02 FF31 GG02 GG13 GG25 GG26 GG28 GG47 HJ12 HL03 HL23 NN02 NN04 NN23 NN35 NN72 PP01 PP03 PP04 PP06 PP10 PP13 PP24 PP29 QQ11 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/78 618Z (72) Inventor Mitsutoshi Miyasaka 3-3-5 Yamato, Suwa-shi, Nagano Seiko Epson Corporation (72) Inventor Tetsuya Ogawa 2-3-3, Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. (72) Hidetada Tokioka 2-3-2, Marunouchi, Chiyoda-ku, Tokyo F, Sanryo Electric Co., Ltd. Terms (Reference) 2H092 JA25 JA29 JA31 JA33 JA35 JA43 JB13 KA04 KA07 KA12 KA17 KA22 MA08 MA13 MA17 MA29 MA35 MA37 NA22 NA27 5C094 AA13 AA25 AA42 AA43 AA48 AA53 BA03 BA27 BA27 BA27 BA02 FA01 FB02 FA01 EA02 FA02 FA01 EA02 FA02 FA01 EA02 FA02 FA01 FB02 FA01 EA02 AA02 AA17 BA01 BA04 BA07 BB02 BB07 DA02 DB02 DB03 EA11 FA04 FA19 HA01 JA01 5F110 AA30 BB01 BB02 CC02 DD03 DD11 DD12 DD13 DD17 EE01 EE04 EE14 EE28 EE44 FF02 FF31 GG02 GG13 GG25 GG26 GG28 GG47 HJ12 HL03 HL23 NN02 NN04 NN23 NN35 NN72 PP01 PP03 PP04 PP06 PP10 PP13 PP24 PP29 QQ11
Claims (7)
性領域として用いる薄膜半導体装置の製造方法におい
て、 前記半導体膜の一部を局所的に加熱する局所加熱機構を
前記基板上に形成する加熱機構形成工程と、 前記加熱機構形成工程後に行われ、前記半導体膜として
の活性半導体膜を形成する活性半導体膜形成工程と、 前記局所加熱機構により前記活性半導体膜が局所的に加
熱された状態にて前記活性半導体膜を溶融結晶化させる
結晶化工程と、 前記活性半導体膜を島状に加工して前記活性領域を２つ
形成する素子分離工程とを含み、 前記素子分離工程では、前記活性領域が配列された第１
方向に関して、前記活性領域が前記局所加熱機構に完全
に含まれ、且つ、前記局所加熱機構の中心近傍の両側に
所定の距離だけ離間した位置に配置されるように前記活
性半導体膜を加工することを特徴とする薄膜半導体装置
の製造方法。1. A method of manufacturing a thin film semiconductor device using a part of a semiconductor film formed on a substrate as an active region, wherein a local heating mechanism for locally heating a part of the semiconductor film is formed on the substrate. A heating mechanism forming step, and an active semiconductor film forming step that is performed after the heating mechanism forming step and forms an active semiconductor film as the semiconductor film; and the active semiconductor film is locally heated by the local heating mechanism. A crystallization step of melting and crystallizing the active semiconductor film in a state, and an element isolation step of processing the active semiconductor film into an island shape to form two active regions. First array of active regions
Processing the active semiconductor film so that the active region is completely included in the local heating mechanism with respect to the direction, and is disposed at positions separated by a predetermined distance on both sides near the center of the local heating mechanism. A method for manufacturing a thin film semiconductor device, comprising:
ぞれの長さは、２μｍ以下であることを特徴とする請求
項１記載の薄膜半導体装置の製造方法。2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the length of each of the active regions in the first direction is 2 μm or less.
熱機構の中心近傍から前記第１方向にそれぞれ０．５μ
ｍ以上離間した位置に設定されることを特徴とする請求
項１又は請求項２記載の薄膜半導体装置の製造方法。3. The position of each of the active regions is 0.5 μm from the vicinity of the center of the local heating mechanism in the first direction.
3. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the thin film semiconductor devices are set at positions separated by m or more.
性領域として用いる薄膜半導体装置において、 前記半導体膜には、異なる２箇所に活性領域が形成され
ており、 前記活性領域には、前記活性領域が配列された第１方向
に延びる結晶粒界のみが存在し、前記活性領域の間に
は、前記第１方向を横切る第２方向に延びる１つの結晶
粒界が存在することを特徴とする薄膜半導体装置。4. A thin film semiconductor device using a part of a semiconductor film formed on a substrate as an active region, wherein the semiconductor film has active regions formed at two different positions, and the active region has: Only the grain boundaries extending in the first direction in which the active regions are arranged are present, and one grain boundary extending in the second direction crossing the first direction is present between the active regions. Thin film semiconductor device.
ぞれの長さは、２μｍ以下であることを特徴とする請求
項４記載の薄膜半導体装置。5. The thin film semiconductor device according to claim 4, wherein the length of each of the active regions in the first direction is 2 μm or less.
界から前記第１方向にそれぞれ０．５μｍ以上離間した
位置に設定されることを特徴とする請求項４又は請求項
５記載の薄膜半導体装置。6. The thin film according to claim 4, wherein the position of each of the active regions is set at a position spaced apart from the crystal grain boundary by 0.5 μm or more in the first direction. Semiconductor device.
載の薄膜半導体装置の製造方法を用いて製造された薄膜
半導体装置、又は、請求項４から請求項６の何れか一項
に記載の薄膜半導体装置を、電気的なスイッチング手段
及び電気光学的なスイッチング手段の少なくとも一方の
スイッチング手段として備えることを特徴とする電子デ
バイス。7. A thin film semiconductor device manufactured by using the method for manufacturing a thin film semiconductor device according to claim 1, or any one of claims 4 to 6. An electronic device comprising the thin film semiconductor device according to claim 1 as at least one of an electrical switching means and an electro-optical switching means.
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| JP2001307807A JP3845566B2 (en) | 2001-10-03 | 2001-10-03 | Thin film semiconductor device, method for manufacturing the same, and electronic device including the device |
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|---|---|---|---|
| JP2001307807A JP3845566B2 (en) | 2001-10-03 | 2001-10-03 | Thin film semiconductor device, method for manufacturing the same, and electronic device including the device |
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| JP3845566B2 JP3845566B2 (en) | 2006-11-15 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005001921A1 (en) * | 2003-06-27 | 2005-01-06 | Nec Corporation | Thin film transistor, thin film transistor substrate, electronic apparatus and process for producing polycrystalline semiconductor thin film |
| JP2005340775A (en) * | 2004-05-28 | 2005-12-08 | Samsung Sdi Co Ltd | Thin film transistor and its manufacturing method, and plate indicator including thin film transistor and its manufacturing method |
| JP2016133702A (en) * | 2015-01-21 | 2016-07-25 | 株式会社ジャパンディスプレイ | Display device |
-
2001
- 2001-10-03 JP JP2001307807A patent/JP3845566B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005001921A1 (en) * | 2003-06-27 | 2005-01-06 | Nec Corporation | Thin film transistor, thin film transistor substrate, electronic apparatus and process for producing polycrystalline semiconductor thin film |
| US7745822B2 (en) | 2003-06-27 | 2010-06-29 | Nec Corporation | Thin film transistor and thin film transistor substrate including a polycrystalline semiconductor thin film having a large heat capacity part and a small heat capacity part |
| US8017507B2 (en) | 2003-06-27 | 2011-09-13 | Nec Corporation | Method of manufacturing a polycrystalline semiconductor thin film |
| JP2005340775A (en) * | 2004-05-28 | 2005-12-08 | Samsung Sdi Co Ltd | Thin film transistor and its manufacturing method, and plate indicator including thin film transistor and its manufacturing method |
| US7554118B2 (en) | 2004-05-28 | 2009-06-30 | Samsung Mobile Display Co., Ltd. | Thin film transistor, flat panel display having the same and a method of fabricating each |
| JP2016133702A (en) * | 2015-01-21 | 2016-07-25 | 株式会社ジャパンディスプレイ | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3845566B2 (en) | 2006-11-15 |
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