JP2003068758A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2003068758A
JP2003068758A JP2001253188A JP2001253188A JP2003068758A JP 2003068758 A JP2003068758 A JP 2003068758A JP 2001253188 A JP2001253188 A JP 2001253188A JP 2001253188 A JP2001253188 A JP 2001253188A JP 2003068758 A JP2003068758 A JP 2003068758A
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JP
Japan
Prior art keywords
region
gate
concentration
semiconductor device
present
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Granted
Application number
JP2001253188A
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Japanese (ja)
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JP4127987B2 (en
Inventor
Hidekatsu Onose
秀勝 小野瀬
Takasumi Oyanagi
孝純 大柳
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a J-FET which can sufficiently turn off by a negative gate bias of a few volts and reduce the capacitance between the gate and drain. SOLUTION: In this semiconductor device, the minimum of a channel width Wch is set to be 1.5 μm or less. At least one part of the n-type channel region has a lower concentration than the concentration of the drift region 11, or has a thinner layer than the thickness of the drift region. Moreover, the sum of the channel width Wch and the p-gate width is made four times or less the channel width Wch. Furthermore, in this semiconductor device, a depletion layer between the gate and drain is made to extend more easily by reducing the concentration in the drift region just below the p-gate 13.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特にトランジスタの構造、好ましくはＪＦＥＴの構
造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a transistor structure, preferably a JFET structure.

【０００２】[0002]

【従来の技術】シリコンカーバイド（SiC）は絶縁破壊
電界がSiに比べ約10倍大きいため、耐圧を維持するドリ
フト層を薄く、かつ高濃度にすることができ、損失を低
減できる材料である。SiCを用いたパワー半導体素子の
一つに接合FET（JFET）あるいは静電誘導トランジスタ
（SIT）がある。SiCの特長を利用したJFETの例として、
図２に示す特開平１０−２９４４７１号公報記載の構造
がある。図２において10はドレイン領域であるn+基板、
11はnドリフト層、12はn+ソース領域、13はpゲート領域
である。また21はドレイン電極、22はソース電極、23は
ゲート電極である。SiCは絶縁破壊電界が高いため、Si
素子では困難であった高濃度のpn接合が可能であるた
め、図のようなソースとゲートが重なり合った構造で高
いゲート耐圧が実現できる。2. Description of the Related Art Silicon carbide (SiC) has a dielectric breakdown electric field that is about 10 times larger than that of Si. Therefore, the drift layer that maintains the breakdown voltage can be made thin and the concentration can be high, and the loss can be reduced. Junction FET (JFET) or static induction transistor (SIT) is one of the power semiconductor devices using SiC. As an example of JFET utilizing the characteristics of SiC,
There is a structure described in JP-A-10-294471 shown in FIG. In FIG. 2, 10 is a drain region, n + substrate,
Reference numeral 11 is an n drift layer, 12 is an n + source region, and 13 is a p gate region. Further, 21 is a drain electrode, 22 is a source electrode, and 23 is a gate electrode. Since SiC has a high dielectric breakdown electric field,
Since high-concentration pn junction, which was difficult for the device, is possible, high gate breakdown voltage can be realized with the structure in which the source and the gate overlap as shown in the figure.

【０００３】[0003]

【発明が解決しようとする課題】JFETはゲートからチャ
ネルに拡がる空乏層により電流をオンオフするトランジ
スタである。n+ドレインとn+ソースはnドリフト層を介
してつながっているため、オフ状態を実現するためには
通常負のゲート電圧が必要となる。このようなデバイス
をノーマリオンと称す。特開平１０−２９４４７１号公
報等では、オン抵抗とゲート逆バイアスを共に低減させ
る具体的数値が明らかになっておらず、プロセスマージ
ン等を考慮に入れた構造最適化によるには安定な特性実
現不充分であった。A JFET is a transistor that turns on / off a current by a depletion layer extending from a gate to a channel. Since the n + drain and n + source are connected through the n drift layer, a negative gate voltage is usually required to realize the off state. Such a device is called normally-on. In Japanese Patent Laid-Open No. 10-294471, etc., specific numerical values for reducing both the on-resistance and the gate reverse bias have not been clarified, and stable characteristics cannot be realized by structural optimization in consideration of process margins and the like. It was enough.

【０００４】これに対しMOSFETの場合はp型領域がドレ
イン/ソース間に存在するため、負のゲート電圧がない
場合でもオフ状態が実現できている。このようなデバイ
スをノーマリオフと称す。しかしながらMOSFETであって
も電圧の変動に対応するため、-10V程度の負のゲート電
圧を印加しているのが通常である。さらにJFETの場合は
pn接合面積が多いためゲート/ドレイン間の容量が大き
く、高速スイッチングの妨げとなっている。On the other hand, in the case of the MOSFET, since the p-type region exists between the drain and the source, the off state can be realized even when there is no negative gate voltage. Such a device is called normally-off. However, even with a MOSFET, a negative gate voltage of about -10V is usually applied in order to cope with voltage fluctuations. In the case of JFET
Since the pn junction area is large, the gate-drain capacitance is large, which hinders high-speed switching.

【０００５】本発明の目的は低いオン抵抗を保ちながら
数Vの負のゲートバイアスで十分オフ状態を実現できる
構造を提供することであり、さらにはゲート/ドレイン
間の容量を低減できる構造を提供することである。An object of the present invention is to provide a structure capable of realizing a sufficiently off state with a negative gate bias of several V while maintaining a low on-resistance, and further to provide a structure capable of reducing the gate-drain capacitance. It is to be.

【０００６】[0006]

【課題を解決するための手段】低いゲート電圧を実現す
るために、本発明の半導体装置はpゲートとn+ソースが
接する構造のJFETにおいて、チャネル幅の最小値を1.5
μmより狭くしたものである。さらにチャネル領域の少
なくとも一部の濃度がドリフト領域の濃度より低くし
た、あるいは薄いp型層を形成したものである。微細チ
ャネル幅を実現するために本発明は、ゲート電極にアル
ミニウムを用い、熱処理によりアルミニウムを半導体中
に拡散することにより、ゲート電極とpゲート領域をセ
ルフアラインで形成したものである。さらにチャネル幅
とpゲート幅の和がチャネル幅の４倍と等しいかもしく
は小さくした。In order to achieve a low gate voltage, the semiconductor device of the present invention has a minimum channel width of 1.5 in a JFET having a structure in which a p gate and an n + source are in contact with each other.
It is narrower than μm. Further, the concentration of at least part of the channel region is lower than that of the drift region, or a thin p-type layer is formed. In order to realize a fine channel width, the present invention uses aluminum for the gate electrode, and aluminum is diffused into the semiconductor by heat treatment to form the gate electrode and the p gate region by self-alignment. Further, the sum of the channel width and the p gate width is equal to or smaller than four times the channel width.

【０００７】上記目的の異なる実現方法として本発明の
半導体装置はn+ソース下部に埋め込みpゲートを設け、
かつ表面pゲートと埋め込みpゲートの間で横方向チャネ
ルを形成し、上下のpゲート間隔の最小値を1.5μmより
狭くした。As a method of realizing the above-mentioned different purpose, the semiconductor device of the present invention is provided with an embedded p gate under the n + source,
In addition, a lateral channel was formed between the surface p gate and the buried p gate, and the minimum value of the upper and lower p gate intervals was narrower than 1.5 μm.

【０００８】ゲート/ドレイン間の容量を低減する方法
として、本発明の半導体装置はpゲート下側のドリフト
領域の濃度を、チャネル領域下側のドリフト領域の濃度
より低くした。As a method of reducing the capacitance between the gate and the drain, in the semiconductor device of the present invention, the concentration of the drift region below the p gate is set lower than the concentration of the drift region below the channel region.

【０００９】図１は負のゲートバイアス（ゲート逆電
圧）とチャネル幅Wchとの関係を示し、耐圧600Vを実現
できる逆バイアスを示している。図１から明らかなよう
に、チャネル幅を1.5μm以下とすることによりゲート逆
バイアスを数Vに抑えることができる。従ってゲート逆
バイアスの設定を10Vとすることにより、電源電圧の変
動が40％程度生じても十分オフ状態を実現できる。FIG. 1 shows the relationship between the negative gate bias (gate reverse voltage) and the channel width Wch, showing the reverse bias capable of realizing a withstand voltage of 600V. As is apparent from FIG. 1, the gate reverse bias can be suppressed to several V by setting the channel width to 1.5 μm or less. Therefore, by setting the gate reverse bias to 10 V, it is possible to realize a sufficiently off state even when the power supply voltage fluctuates by about 40%.

【００１０】一方、チャネル幅狭くなるとオン抵抗の増
大が懸念される。図３にチャネル幅とオン抵抗の関係の
計算結果を示す。これから明らかなように、チャネル幅
が0.3μmより狭くなるとオン抵抗が急激に増大する。従
って低いオン抵抗を実現するにはチャネル幅を0.4μm以
上とすることが好ましい。ユニット幅（チャネル幅とp
ゲート幅の和）との関係で見ると、チャネル幅がチャネ
ル幅の５倍の場合、チャネル幅が1.5μmから1.2μmに変
動(±10％)するとオン抵抗は9.0mΩ・cm2から7.9mΩ・c
m2と10％以上変動する。これに対し４倍以下であれば、
オン抵抗の変動は約9％と10％以下に抑えることができ
る。加えて絶対値も低減することがわかる。On the other hand, when the channel width becomes narrow, there is a concern that the on-resistance will increase. FIG. 3 shows the calculation result of the relationship between the channel width and the on-resistance. As is clear from this, when the channel width becomes narrower than 0.3 μm, the on-resistance rapidly increases. Therefore, the channel width is preferably 0.4 μm or more in order to realize a low on-resistance. Unit width (channel width and p
In terms of the relationship with the sum of gate widths), when the channel width is 5 times the channel width, when the channel width fluctuates from 1.5 μm to 1.2 μm (± 10%), the on resistance is 9.0 mΩ ・ cm 2 to 7.9 mΩ.・ C
It fluctuates more than 10% with m 2 . On the other hand, if it is 4 times or less,
The fluctuation of on-resistance can be suppressed to about 9% and 10% or less. In addition, it can be seen that the absolute value also decreases.

【００１１】従ってチャネル幅を1.5μm以下とし、ユニ
ット幅をチャネル幅の４倍以内にすることでプロセスマ
ージンが拡大し、かつオン抵抗とゲート逆バイアスを低
減することができる。なおチャネル幅の最適値は図から
明らかなように0.5μmから1.0μmであり、これに設定す
ることが望ましい。Therefore, by setting the channel width to 1.5 μm or less and setting the unit width to within 4 times the channel width, the process margin can be expanded and the ON resistance and the gate reverse bias can be reduced. The optimum value of the channel width is 0.5 μm to 1.0 μm as is clear from the figure, and it is desirable to set this value.

【００１２】チャネル領域における空乏層はチャネル部
の濃度が低い方が大きく拡がる。従ってチャネル領域の
濃度を低濃度化することで低いゲート逆バイアスでオフ
状態を実現できる。しかしながらオン抵抗は濃度に比例
するため、ドリフト領域の濃度も下げると電流経路全体
の抵抗が増大する。The depletion layer in the channel region spreads greatly when the concentration of the channel portion is low. Therefore, by reducing the concentration of the channel region, an off state can be realized with a low gate reverse bias. However, since the on-resistance is proportional to the concentration, reducing the concentration in the drift region also increases the resistance of the entire current path.

【００１３】そのため本発明のように空乏層拡がりが関
係する部分のみの濃度を低下させることにより、ゲート
逆バイアスの低減を図りながらオン抵抗への影響を少な
くすることができる。ただしチャネル部をドリフト領域
に対し10倍低濃度化させるとその分チャネル領域での抵
抗が増大する。その結果デバイス全体のオン抵抗が増加
する。Therefore, as in the present invention, by reducing the concentration only in the portion related to the depletion layer expansion, it is possible to reduce the reverse bias of the gate and reduce the effect on the on-resistance. However, if the concentration of the channel portion is made 10 times lower than that of the drift region, the resistance in the channel region increases correspondingly. As a result, the on-resistance of the entire device increases.

【００１４】例えば抵抗のチャネル成分とドリフト成分
が50：50の場合を考えてみる。10倍低濃度化するとチャ
ネル領域における空乏層拡がりは３倍となり従ってゲー
ト逆バイアスも約1/3に低減できる。しかしながら抵抗
配分は500：50となり、抵抗のほとんどがチャネル領域
で支配され、かつ抵抗自体も約５倍に増大する。そのた
め低濃度化は３倍以下に抑えることが望ましい。この場
合ゲート逆バイアス低減効果は約1/1.7（空乏層拡がり
は約1.7倍）であるため、チャネル幅1.5μmであっても
ゲート逆バイアスを5V以下に抑えることが可能である。
抵抗配分は150：50となり、抵抗増加分は約２倍に抑え
ることができる。Consider, for example, a case where the channel component and the drift component of the resistance are 50:50. When the concentration is reduced 10 times, the depletion layer spread in the channel region is tripled, and therefore the gate reverse bias can be reduced to about 1/3. However, the distribution of resistance is 500: 50, most of the resistance is dominated by the channel region, and the resistance itself increases about 5 times. Therefore, it is desirable to reduce the concentration to 3 times or less. In this case, since the gate reverse bias reduction effect is about 1 / 1.7 (the depletion layer spread is about 1.7 times), the gate reverse bias can be suppressed to 5 V or less even if the channel width is 1.5 μm.
The distribution of resistance is 150: 50, and the amount of resistance increase can be doubled.

【００１５】ノーマリオフを実現にはn+ソースとドリフ
ト領域の間にp層を設ければよい。しかしながらp層を設
けるとオン状態を実現するにはゲート電流の注入が必要
となり、バイポーラ動作させる必要がある。これを防ぐ
ため本発明ではp層を電子がトンネル透過可能なプロフ
ァイルとする。これにより、ゲートに順バイアスを加え
ることで電子が透過しやすくなり、低いオン抵抗とノー
マリオフを実現することが可能になる。To realize normally-off, a p layer may be provided between the n + source and the drift region. However, when the p-layer is provided, the gate current must be injected to realize the on-state, and the bipolar operation must be performed. In order to prevent this, in the present invention, the p layer has a profile that allows electrons to tunnel through. As a result, electrons can easily pass through by applying a forward bias to the gate, and low on-resistance and normally-off can be realized.

【００１６】次にゲート/ドレイン間容量について説明
する。ゲート/ドレイン間の空乏層幅で容量は決まる。
空乏層幅は濃度の平方根に反比例する。従って低容量化
を達成するにはドリフト領域の濃度を低濃度化すればよ
い。しかしながら低濃度化するとオン抵抗が増大する。
JFETの場合、pゲート下部は電流経路に対しデッドスペ
ースとなっている。従って本発明のように、この部分の
濃度を下げることでオン抵抗に影響を及ぼすことなくゲ
ート/ドレイン間の容量を下げることができ、スイッチ
ングの高速化を図ることができる。Next, the gate-drain capacitance will be described. The capacitance is determined by the width of the depletion layer between the gate and drain.
The depletion layer width is inversely proportional to the square root of the concentration. Therefore, the concentration in the drift region may be reduced to achieve a low capacitance. However, when the concentration is lowered, the on-resistance increases.
In the case of JFET, the bottom of the p gate is a dead space for the current path. Therefore, like the present invention, by reducing the concentration of this portion, the capacitance between the gate and the drain can be reduced without affecting the on-resistance, and the switching speed can be increased.

【００１７】[0017]

【発明の実施の形態】以下、本発明を実施例により詳細
に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to Examples.

【００１８】図2は本発明の第２の実施例であり、JFET
の断面構造である。図２において10はドレイン領域であ
るn+基板、11はnドリフト層、12はn+ソース領域、13はp
ゲート領域である。また21はドレイン電極、22はソース
電極、23はゲート電極である。FIG. 2 shows a second embodiment of the present invention, which is a JFET.
Is a sectional structure of. In FIG. 2, 10 is a drain region, n + substrate, 11 is an n drift layer, 12 is an n + source region, and 13 is p.
It is a gate region. Further, 21 is a drain electrode, 22 is a source electrode, and 23 is a gate electrode.

【００１９】本実施例では基板10としてn型4H-SiCを用
いた。ドリフト領域には厚み6.5μm、濃度3.0×1016cm
-3のnエピ層11を用いた。pゲート13にはAlをドーパント
に用い、そのイオン注入条件は最大加速エネルギー1.25
MeV、ドーズ量5×1013cm-2である。チャネル幅は0.5μ
m、ユニット幅は1.0μmである。pゲート用イオン注入
後、窒素のイオン注入によりn+ソース12を形成した。注
入条件は最大200keVの多重注入であり、ドーズ量の総計
は1.8×1015cm-2である。イオン注入後、アルゴン雰囲
気中で1700℃の欠陥回復・活性化熱処理をした。各電極
にはNiを用いた。作製したデバイスの電気特性を測定し
た結果、600V以上の耐圧を得ることができ、そのときの
ゲート逆バイアスは2Vであった。またオン抵抗は0.5mΩ
・cm2と、オン、オフともに良好な特性を得ることができ
た。In this embodiment, n-type 4H—SiC is used as the substrate 10. The drift area has a thickness of 6.5 μm and a concentration of 3.0 × 10 16 cm.
-3 n-epi layer 11 was used. Al is used as a dopant for the p-gate 13, and the ion implantation condition is a maximum acceleration energy of 1.25.
MeV, dose amount 5 × 10 13 cm -2 . Channel width is 0.5μ
m, unit width is 1.0 μm. After the p-gate ion implantation, nitrogen ion implantation was performed to form an n + source 12. The implantation conditions were multiple implantation up to 200 keV, and the total dose was 1.8 × 10 15 cm -2 . After the ion implantation, a defect recovery / activation heat treatment was performed at 1700 ° C. in an argon atmosphere. Ni was used for each electrode. As a result of measuring the electric characteristics of the fabricated device, it was possible to obtain a breakdown voltage of 600 V or more, and the gate reverse bias at that time was 2 V. On-resistance is 0.5mΩ
・ Satisfactory properties of cm 2 and on / off could be obtained.

【００２０】図４は本発明の第２の実施例であり、JFET
の断面構造である。本実施例では実施例１のドリフト層
１１を5.0μmとし、その上に厚み1.5μｍ、濃度1.0×10
16cm -3のn-層をエピ成長により追加した。これにより加
工精度を和らげることができ、チャネル幅は0.8μm、ユ
ニット幅は2.4μmとした。これにより、4Vのゲート逆バ
イアスで600V以上の耐圧を得ることができた。またオン
抵抗は1.5mΩ・cm2と良好な特性をであった。FIG. 4 shows a second embodiment of the present invention, which is a JFET.
Is a sectional structure of. In this example, the drift layer of Example 1 was used.
11 is 5.0 μm, on which thickness 1.5 μm, density 1.0 × 10
16cm -3N-Layers were added by epi growth. This adds
The processing accuracy can be softened and the channel width is 0.8 μm.
The knit width was 2.4 μm. This allows 4V gate reverse
I was able to obtain a breakdown voltage of 600V or higher. Also on
Resistance is 1.5mΩ ・ cm2And had good properties.

【００２１】図５は本発明の第３の実施例を示すJFETの
断面構造である。本実施例においては、ドリフト層１１
を5.3μmmとしn-層14の厚みを1.2μmとし、pゲート領域
13の深さと同じにした。これにより、4.5Vのゲート逆バ
イアスで600V以上の耐圧を得ることができ、またオン抵
抗は1.4mΩ・cm2と、良好な特性であった。FIG. 5 is a sectional structure of a JFET showing a third embodiment of the present invention. In this embodiment, the drift layer 11
Is 5.3 μmm, the thickness of the n − layer 14 is 1.2 μm, and the p gate region is
Same as 13 depths. As a result, it was possible to obtain a breakdown voltage of 600 V or higher with a gate reverse bias of 4.5 V, and an on-resistance of 1.4 mΩ · cm 2 , which was a good characteristic.

【００２２】図６は本発明の第４の実施例を示すJFETの
断面構造である。本実施例においては、ドリフト層１１
を5.5μmとしn-層14の厚みを1.0μmとし、pゲート領域1
3より浅い構造とした。これにより、6Vとやや高いゲー
ト逆バイアスであったが600V以上の耐圧を得ることがで
き、またオン抵抗は1.2mΩ・cm2と、良好な特性であっ
た。FIG. 6 is a sectional structure of a JFET showing a fourth embodiment of the present invention. In this embodiment, the drift layer 11
Is 5.5 μm and the thickness of the n − layer 14 is 1.0 μm.
The structure is shallower than 3. As a result, although the gate reverse bias was 6 V, which was rather high, a breakdown voltage of 600 V or higher could be obtained, and the on-resistance was 1.2 mΩ · cm 2 , which was a good characteristic.

【００２３】図７は本発明の第５の実施例を示すJFETの
断面構造である。本実施例においては、実施例１におけ
るドリフト層11を6.0μmとし、その上に厚み0.5μm、濃
度3.0×1017cm-3のn層15をエピ成長により追加した形成
した。チャネル幅は0.5μm、ユニット幅は1.0μmであ
る。これにより、3Vのゲート逆バイアスで600V以上の耐
圧を得ることができ、またオン抵抗は0.4mΩ・cm2と、良
好な特性であった。FIG. 7 is a sectional structure of a JFET showing a fifth embodiment of the present invention. In this example, the drift layer 11 in Example 1 was set to 6.0 μm, and an n layer 15 having a thickness of 0.5 μm and a concentration of 3.0 × 10 17 cm −3 was additionally formed thereon by epi growth. The channel width is 0.5 μm and the unit width is 1.0 μm. As a result, it was possible to obtain a breakdown voltage of 600 V or more with a gate reverse bias of 3 V, and an on-resistance of 0.4 mΩ · cm 2 , which was a good characteristic.

【００２４】図８は本発明の第６の実施例を示すJFETの
断面構造である。本実施例においては、ドリフト層11を
5.0μmとし、その上に厚み0.8μm、濃度3.0×1015cm-3
のn-層14をエピ成長により形成した。さらに厚み0.7μ
m、濃度3.0×1017cm-3のn層15をエピ成長により追加し
て形成した。チャネル幅は0.5μm、ユニット幅は1.0μm
である。これにより、2Vのゲート逆バイアスで600V以上
の耐圧を得ることができ、またオン抵抗は0.5mΩ・cm
2と、良好な特性であった。FIG. 8 is a sectional structure of a JFET showing a sixth embodiment of the present invention. In this embodiment, the drift layer 11 is
5.0μm, thickness 0.8μm on it, concentration 3.0 × 10 15 cm -3
N − layer 14 was formed by epi growth. Furthermore thickness 0.7μ
An n layer 15 with m and a concentration of 3.0 × 10 17 cm −3 was additionally formed by epi growth. Channel width 0.5 μm, unit width 1.0 μm
Is. As a result, it is possible to obtain a breakdown voltage of 600 V or more with a gate reverse bias of 2 V, and an on-resistance of 0.5 mΩ · cm.
2 was a good characteristic.

【００２５】図９は本発明の第７の実施例を示すJFETの
断面構造である。本実施例においては、ドリフト層11を
5.3μmとし、その上に厚み0.5μm、濃度3.0×1015cm-3
のn-層14をエピ成長により形成した。さらに厚み0.7μ
m、濃度3.0×1017cm-3のn層15をエピ成長により追加し
て形成し、pゲート領域13の深さと同じにした。チャネ
ル幅は0.5μm、ユニット幅は1.0μmである。これによ
り、3Vのゲート逆バイアスで600V以上の耐圧を得ること
ができ、またオン抵抗は0.4mΩ・cm2と、良好な特性であ
った。FIG. 9 is a sectional structure of a JFET showing a seventh embodiment of the present invention. In this embodiment, the drift layer 11 is
5.3μm, thickness 0.5μm on it, concentration 3.0 × 10 15 cm -3
N − layer 14 was formed by epi growth. Furthermore thickness 0.7μ
An n layer 15 of m and a concentration of 3.0 × 10 17 cm −3 was additionally formed by epi growth to have the same depth as the p gate region 13. The channel width is 0.5 μm and the unit width is 1.0 μm. As a result, it was possible to obtain a breakdown voltage of 600 V or more with a gate reverse bias of 3 V, and an on-resistance of 0.4 mΩ · cm 2 , which was a good characteristic.

【００２６】図10は本発明の第８の実施例を示すJFETの
断面構造である。本実施例においては、ドリフト層11を
5.5μmとし、その上に厚み0.3μm、濃度3.0×1015cm-3
のn-層14をエピ成長により形成した。さらに厚み0.7μ
m、濃度3.0×1017cm-3のn層15をエピ成長により追加し
て形成し、pゲート領域13より浅い構造とした。チャネ
ル幅は0.5μm、ユニット幅は1.0μmである。これによ
り、5Vのゲート逆バイアスで600V以上の耐圧を得ること
ができ、またオン抵抗は0.3mΩ・cm2と、良好な特性であ
った。FIG. 10 is a sectional structure of a JFET showing an eighth embodiment of the present invention. In this embodiment, the drift layer 11 is
5.5 μm, thickness 0.3 μm on it, concentration 3.0 × 10 15 cm -3
N − layer 14 was formed by epi growth. Furthermore thickness 0.7μ
An n layer 15 with m and a concentration of 3.0 × 10 17 cm −3 was additionally formed by epi growth to form a structure shallower than the p gate region 13. The channel width is 0.5 μm and the unit width is 1.0 μm. As a result, it was possible to obtain a breakdown voltage of 600 V or more with a gate reverse bias of 5 V, and an on-resistance of 0.3 mΩ · cm 2 , which was a good characteristic.

【００２７】図11は本発明の第９の実施例を示すJFETの
断面構造である。微細チャネルJFETを実現するには必然
的に高精度のアライメントが要求される。しかしながら
本発明のJFETの場合、pゲートとn+ソースが接している
構造であるため、本実施例のように一つのn+ソースに複
数個の副次的pゲートを接して設けても問題はない。こ
れにより異なる領域間に関する高精度のアライメントは
必要ではなくなる。FIG. 11 is a sectional structure of a JFET showing a ninth embodiment of the present invention. High-precision alignment is inevitably required to realize a fine channel JFET. However, in the case of the JFET of the present invention, since the p gate and the n + source are in contact with each other, there is a problem even if one n + source is provided with a plurality of secondary p gates as in this embodiment. There is no. This eliminates the need for high precision alignment between different regions.

【００２８】本実施例では実施例２に示した構造を用
い、n+ソース下部に２本の副次的pゲートを設けた。こ
の場合のチャネル幅は0.8μm、副次的pゲートの幅は1.6
μmである。なお副次的pゲートは図示していない場所で
ゲート電極22に接する構造となっている。この場合のユ
ニット幅は10μmであるが、チャネル幅の４倍のユニッ
ト幅を実現した場合と同様の効果を得ることができた。
本構造を採用することにより、実施例２と同様の特性を
得ることができた。In this example, the structure shown in Example 2 was used, and two subsidiary p gates were provided below the n + source. In this case, the channel width is 0.8 μm and the width of the secondary p-gate is 1.6 μm.
μm. The secondary p-gate has a structure in contact with the gate electrode 22 at a location not shown. The unit width in this case is 10 μm, but the same effect as when the unit width four times the channel width was realized could be obtained.
By adopting this structure, the same characteristics as in Example 2 could be obtained.

【００２９】図12は本発明の第10の実施例を示すJFETの
断面構造である。本実施例は実施例３に副次的pゲート
を加えた例であり、実施例９と同様の理由により、異な
る領域間に関する高精度のアライメントを必要とせず
に、実施例３と同様の特性を得ることができた。FIG. 12 is a sectional structure of a JFET showing a tenth embodiment of the present invention. This embodiment is an example in which a secondary p-gate is added to the third embodiment, and for the same reason as that of the ninth embodiment, the characteristics similar to those of the third embodiment can be obtained without the need for highly accurate alignment between different regions. I was able to get

【００３０】図13は本発明の第11の実施例を示すJFETの
断面構造である。本実施例は実施例４に副次的pゲート
を加えた例であり、実施例９と同様の理由により、異な
る領域間に関する高精度のアライメントを必要とせず
に、実施例４と同様の特性を得ることができた。FIG. 13 is a sectional structure of a JFET showing an eleventh embodiment of the present invention. This embodiment is an example in which a secondary p-gate is added to the fourth embodiment, and for the same reason as in the ninth embodiment, the characteristics similar to those in the fourth embodiment can be obtained without requiring highly accurate alignment between different regions. I was able to get

【００３１】図14は本発明の第12の実施例を示すJFETの
断面構造である。本実施例は実施例５に副次的pゲート
を加えた例であり、実施例９と同様の理由により、異な
る領域間に関する高精度のアライメントを必要とせず
に、実施例５と同様の特性を得ることができた。FIG. 14 is a sectional structure of a JFET showing a twelfth embodiment of the present invention. This embodiment is an example in which a secondary p-gate is added to the fifth embodiment, and for the same reason as in the ninth embodiment, the characteristics similar to those in the fifth embodiment can be obtained without requiring highly accurate alignment between different regions. I was able to get

【００３２】図15は本発明の第13の実施例を示すJFETの
断面構造である。本実施例は実施例６に副次的pゲート
を加えた例であり、実施例９と同様の理由により、異な
る領域間に関する高精度のアライメントを必要とせず
に、実施例６と同様の特性を得ることができた。FIG. 15 is a sectional structure of a JFET showing a 13th embodiment of the present invention. This embodiment is an example in which a secondary p-gate is added to the sixth embodiment, and for the same reason as that of the ninth embodiment, the characteristics similar to those of the sixth embodiment can be obtained without the need for highly accurate alignment between different regions. I was able to get

【００３３】図16は本発明の第14の実施例を示すJFETの
断面構造である。本実施例は実施例７に副次的pゲート
を加えた例であり、実施例９と同様の理由により、異な
る領域間に関する高精度のアライメントを必要とせず
に、実施例７と同様の特性を得ることができた。FIG. 16 is a sectional structure of a JFET showing a 14th embodiment of the present invention. This embodiment is an example in which a secondary p-gate is added to the seventh embodiment, and for the same reason as that of the ninth embodiment, the characteristics similar to those of the seventh embodiment can be obtained without requiring high-precision alignment between different regions. I was able to get

【００３４】図17は本発明の第15の実施例を示すJFETの
断面構造である。本実施例は実施例８に副次的pゲート
を加えた例であり、実施例９と同様の理由により、異な
る領域間に関する高精度のアライメントを必要とせず
に、実施例８と同様の特性を得ることができた。FIG. 17 is a sectional structure of a JFET showing a fifteenth embodiment of the present invention. This embodiment is an example in which a secondary p gate is added to the eighth embodiment, and for the same reason as that of the ninth embodiment, the characteristics similar to those of the eighth embodiment can be obtained without requiring highly accurate alignment between different regions. I was able to get

【００３５】図18は本発明の第16の実施例を示すJFETの
断面構造である。本実施例はチャネル中央部下に、pゲ
ート13と同一断面では接することなく埋め込みpゲート1
6を設けた構造である。nドリフト層11は濃度3×1016cm
-3、厚さ8μmであり、埋め込みpゲート16の厚さは0.5μ
mである。pゲート13と埋め込みpゲート16の間がチャネ
ルとなる横型チャネル方式のデバイスであり、間隔がチ
ャネル幅となる。本実施例では1.0μmとした。pゲート1
3と埋め込みpゲート16が接することなく重なっている距
離がチャネル長であり、本実施例では3.0μmとした。こ
れによりゲート電圧０Vで耐圧600Vを実現することがで
きた。しかしながらユニット幅が大きいためオン抵抗は
2mΩ・cm2であった。FIG. 18 is a sectional structure of a JFET showing a 16th embodiment of the present invention. In this embodiment, a buried p-gate 1 is formed below the center of the channel without contacting with the p-gate 13 in the same cross section.
It is a structure with 6. n Drift layer 11 has a concentration of 3 × 10 16 cm
-3 , the thickness is 8μm, and the thickness of the buried p-gate 16 is 0.5μ
m. This is a lateral channel device in which the channel is between the p-gate 13 and the buried p-gate 16, and the spacing is the channel width. In this embodiment, the thickness is 1.0 μm. p gate 1
The distance that 3 and the buried p gate 16 overlap without contacting each other is the channel length, and in this embodiment, it is 3.0 μm. As a result, a breakdown voltage of 600V could be realized with a gate voltage of 0V. However, since the unit width is large, the on-resistance is
It was 2 mΩ · cm 2 .

【００３６】図19は本発明の第17の実施例を示すJFETの
断面構造である。本実施例は実施例16のチャネルの濃度
を低くした構造としたものである。ドリフト層11の厚さ
を6.5μmとし、埋め込みpゲート16を形成後、濃度1.5×
1016cm-3、厚さ1.5μmのn-層14をエピ成長により追加し
た。これによりチャネル幅を2μmとすることができ、ユ
ニット全体も微細化でき、ゲート電圧０Vで耐圧600Vを
実現できたとともに、オン抵抗を1.5mΩ・cm2に低減で
きた。FIG. 19 is a sectional structure of a JFET showing a seventeenth embodiment of the present invention. The present example has a structure in which the channel concentration of Example 16 is lowered. The drift layer 11 has a thickness of 6.5 μm, the buried p-gate 16 is formed, and then the concentration of 1.5 ×
An n − layer 14 of 10 16 cm −3 and a thickness of 1.5 μm was added by epi growth. As a result, the channel width can be set to 2 μm, the entire unit can be miniaturized, the breakdown voltage of 600 V can be realized at the gate voltage of 0 V, and the on-resistance can be reduced to 1.5 mΩ · cm 2 .

【００３７】図20は本発明の第18の実施例を示すJFETの
断面構造である。実施例16においてn+ソース下部のn型
領域はオン抵抗を大きくする一因となっている。そのた
め、本実施例ではn+ソース12を埋め込みpゲート16と接
する構造とした。これによりゲート電圧０Vで耐圧600V
を実現できたとともに、オン抵抗を1.5mΩ・cm2に低減
できた。FIG. 20 is a sectional structure of a JFET showing the 18th embodiment of the present invention. In the sixteenth embodiment, the n-type region under the n + source contributes to increase the on-resistance. Therefore, in this embodiment, the n + source 12 is in contact with the embedded p gate 16. With this, the gate voltage is 0V and the breakdown voltage is 600V.
And the on-resistance was reduced to 1.5 mΩ · cm 2 .

【００３８】図21は本発明の第19の実施例を示すJFETの
断面構造である。実施例17においてn+ソース下部のn-領
域はオン抵抗を大きくする一因となっている。そのた
め、本実施例ではn+ソース12を埋め込みpゲート16と接
する構造とした。これによりゲート電圧０Vで耐圧600V
を実現できたとともに、オン抵抗を1.0mΩ・cm2に低減
できた。FIG. 21 is a sectional structure of a JFET showing a 19th embodiment of the present invention. In the seventeenth embodiment, the n − region under the n + source contributes to increase the on-resistance. Therefore, in this embodiment, the n + source 12 is in contact with the embedded p gate 16. With this, the gate voltage is 0V and the breakdown voltage is 600V.
And the on-resistance could be reduced to 1.0 mΩ · cm 2 .

【００３９】図22は本発明の第20の実施例を示すJFETの
断面構造である。ノーマリオフを実現するため、本実施
例ではn+ソース12とnドリフト11の間に低濃度かつ極薄
のp-層17を設けた。厚さ6.2μm、濃度3×1016cm-3のnド
リフト11をエピ成長後、厚さ0.3μm、濃度1×1015cm-3
のp層17を成長させた。その後イオン注入によりpゲート
13とn+ソース12を形成した。n+ソース形成時の注入エネ
ルギーの最大値を160keVとしp-層17の厚さをトンネル可
能10nmとした。チャネル幅は0.8μm、ユニット幅は2.4
μmである。これによりゲートバイアス０Vの状態であっ
てもpゲート13ならびにp-層17からの空乏層拡がりによ
り耐圧600Vを実現できた。一方ゲートに順バイアスを印
加することにより空乏層拡がりが減少し、かつp-層17は
トンネル可能であるためオン状態が実現でき，1mΩ・cm
2のオン抵抗が得られた。FIG. 22 is a sectional structure of a JFET showing a twentieth embodiment of the present invention. In order to realize normally-off, in this embodiment, the p − layer 17 having a low concentration and an extremely thin thickness is provided between the n + source 12 and the n drift 11. After epitaxial growth of n drift 11 with a thickness of 6.2 μm and a concentration of 3 × 10 16 cm −3 , a thickness of 0.3 μm and a concentration of 1 × 10 15 cm −3
P layer 17 was grown. Then p-gate by ion implantation
13 and n + source 12 were formed. The maximum implantation energy at the time of n + source formation was set to 160 keV, and the thickness of p − layer 17 was set to 10 nm for tunneling. Channel width 0.8 μm, unit width 2.4
μm. As a result, even when the gate bias was 0 V, a breakdown voltage of 600 V could be realized due to the depletion layer spreading from the p gate 13 and the p − layer 17. On the other hand, by applying a forward bias to the gate, the depletion layer spread is reduced, and the p - layer 17 is tunnelable, so an on-state can be realized.
An on-resistance of 2 was obtained.

【００４０】図23は本発明の第21の実施例を示すJFETの
断面構造である。実施例20ではn+ソースのイオン注入条
件を制御することによりp-層の厚さを制御していたが、
再現性の点からは容易ではない。そのため本実施例では
5nmのp-層17をエピ成長後厚さ0.3μm、濃度3×1016cm-3
のn層15を追加成長させた。その後イオン注入によりpゲ
ート13とn+ソース12を形成した。これによりp-層の厚さ
制御性が向上し、ノーマリオフが実現できたとともに、
1mΩ・cm2のオン抵抗が得られた。FIG. 23 is a sectional structure of a JFET showing a 21st embodiment of the present invention. In Example 20, the thickness of the p - layer was controlled by controlling the ion implantation conditions of the n + source.
It is not easy in terms of reproducibility. Therefore, in this embodiment,
After epitaxial growth of a 5 nm p - layer 17, the thickness is 0.3 μm and the concentration is 3 × 10 16 cm -3.
N layer 15 was additionally grown. After that, a p-gate 13 and an n + source 12 were formed by ion implantation. As a result, the controllability of the p - layer thickness was improved, and normally-off was realized.
An on-resistance of 1 mΩ · cm 2 was obtained.

【００４１】図24は本発明の第22の実施例を示すJFETの
断面構造である。ゲート逆バイアスを低減するには、チ
ャネル幅のみならず深いpゲートが必要である。そのた
めには高エネルギーイオン注入が不可欠である。しかし
ながらMeV級のイオン注入装置は一般的でなく、さらに
厚いマスキング材料が必要であり、微細加工時の寸法シ
フトを考慮するなど、プロセス的には容易ではない。そ
のため本実施例ではゲート形成領域をドライエッチング
等によりする構造とした。さらにはpゲート13の形成方
法として、ゲート電極にAlを用い、これからレーザー照
射によりAlを拡散させる方式を採用した。この方式はゲ
ート電極とpゲートがセルフアラインで形成できるた
め、ユニット幅の大幅短縮が容易になり、チャネル幅0.
5μm、ユニット幅1.0μmという微細デバイスを形成でき
た。これによりゲート逆バイアス2Vで耐圧600Vを実現で
き、さらに0.5mΩ・cm2という低オン抵抗を実現でき
た。FIG. 24 is a sectional structure of a JFET showing a 22nd embodiment of the present invention. To reduce the gate reverse bias, not only the channel width but also a deep p gate is required. For that purpose, high energy ion implantation is indispensable. However, the MeV class ion implanter is not general, requires a thicker masking material, and is not easy in terms of process, such as taking into account the dimensional shift during microfabrication. Therefore, in this embodiment, the gate formation region is formed by dry etching or the like. Furthermore, as a method of forming the p gate 13, a method of using Al for the gate electrode and diffusing Al by laser irradiation from this is adopted. In this method, the gate electrode and p-gate can be formed by self-alignment, so it is easy to significantly reduce the unit width and the channel width is zero.
A micro device with a size of 5 μm and unit width of 1.0 μm could be formed. As a result, a breakdown voltage of 600V can be achieved with a gate reverse bias of 2V, and a low on-resistance of 0.5mΩ · cm 2 has been achieved.

【００４２】図25は本発明の第23の実施例を示すJFETの
断面構造である。本実施例ではpゲート13下側の領域全
てを低濃度のn-領域18とした。厚さ6.5μm、濃度3×10
16cm- 3のドリフト層11を用い、イオン注入によりpゲー
ト13、n+ソース12を形成し、さらにボロンなどのp型不
純物をイオン注入により選択的に低濃度でpゲートの下
部に注入し、補償効果で1×1015cm-3のn-領域とした。
これによりゲート/ドレイン間の容量は約25％低減し、
スイッチングの高速化を図ることができた。FIG. 25 is a sectional structure of a JFET showing a 23rd embodiment of the present invention. In this embodiment, the entire region below the p gate 13 is a low concentration n − region 18. Thickness 6.5 μm, concentration 3 × 10
Using a 16 cm - 3 drift layer 11, a p-gate 13 and an n + source 12 are formed by ion implantation, and a p-type impurity such as boron is selectively ion-implanted into the lower part of the p-gate. , 1 × 10 15 cm -3 in n - region due to compensation effect.
This reduces the gate-drain capacitance by about 25%,
We were able to speed up switching.

【００４３】図26は本発明の第24の実施例を示すJFETの
断面構造である。本実施例ではpゲート13下側の領域の
うち、pゲート側の部分を低濃度のn-領域18とした。こ
の場合でも実施例23と同様ゲート/ドレイン間の容量を
低減できた。FIG. 26 is a sectional structure of a JFET showing a 24th embodiment of the present invention. In this embodiment, of the region under the p gate 13, the portion on the p gate side is the low concentration n − region 18. Even in this case, the gate-drain capacitance could be reduced as in the case of Example 23.

【００４４】図27は本発明の第25の実施例を示すJFETの
断面構造である。本実施例は横チャネル型JFETにおいて
ゲート/ドレイン間容量の低減を図った例である。厚さ5
μm、濃度3×1016cm-3のドリフト層11に埋め込みゲート
16を形成後、さらにボロンなどのp型不純物をイオン注
入により選択的に低濃度でpゲートの下部に注入し、補
償効果で1×1015cm-3のn-領域とした。引続き濃度1.5×
1016cm-3、厚さ1.5μmのn-層14をエピ成長により追加
し、表面側のpゲート13とn+ソース12を形成した。これ
により実施例23と同様ゲート/ドレイン間の容量を低減
できた。FIG. 27 is a sectional structure of a JFET showing a 25th embodiment of the present invention. The present embodiment is an example of reducing the gate-drain capacitance in a lateral channel JFET. Thickness 5
Embedded gate in drift layer 11 with μm concentration 3 × 10 16 cm -3
After 16 was formed, a p-type impurity such as boron was further ion-implanted at a low concentration to the lower part of the p-gate to form a 1 × 10 15 cm -3 n − region with a compensation effect. Continuation 1.5 ×
An n − layer 14 of 10 16 cm −3 and a thickness of 1.5 μm was added by epi growth to form a p gate 13 and an n + source 12 on the surface side. As a result, the gate / drain capacitance can be reduced as in the case of Example 23.

【００４５】図28は本発明の第26の実施例を示すJFETの
断面構造である。本実施例では横チャネルJFETにおける
埋め込みpゲート16下側の領域のうち、pゲート側の部分
を低濃度のn-領域18とした。この場合でも実施例23と同
様ゲート/ドレイン間の容量を低減できた。FIG. 28 is a sectional structure of a JFET showing a 26th embodiment of the present invention. In the present embodiment, of the region under the buried p gate 16 in the lateral channel JFET, the portion on the p gate side is the low concentration n − region 18. Even in this case, the gate-drain capacitance could be reduced as in the case of Example 23.

【００４６】上記実施例では横チャネルJFETのうち実施
例19に適用した場合で説明したが、本発明はこれに限ら
ず、実施例16から実施例18に適用しても同様である。In the above-described embodiment, the case where the lateral channel JFET is applied to the nineteenth embodiment has been described, but the present invention is not limited to this and the same applies to the sixteenth to eighteenth embodiments.

【００４７】[0047]

【発明の効果】本発明によれば、低ゲート逆バイアスか
つ低オン抵抗が実現できるため、インバーター用のスイ
ッチングデバイスに用いるとゲート駆動が容易になると
共に損失を低減できる。According to the present invention, a low gate reverse bias and a low on-resistance can be realized. Therefore, when it is used in a switching device for an inverter, gate driving becomes easy and loss can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明を説明するためのチャネル幅とゲート逆
バイアスの関係を示す計算結果。FIG. 1 is a calculation result showing a relationship between a channel width and a gate reverse bias for explaining the present invention.

【図２】JFETの構造並びに本発明の第１の実施例を示す
略式断面図。FIG. 2 is a schematic sectional view showing a structure of a JFET and a first embodiment of the present invention.

【図３】本発明を説明するためのチャネル幅とオン抵抗
の関係を示す計算結果。FIG. 3 is a calculation result showing a relation between a channel width and an on resistance for explaining the present invention.

【図４】本発明の第２の実施例を説明する略式断面図。FIG. 4 is a schematic sectional view explaining a second embodiment of the present invention.

【図５】本発明の第３の実施例を説明する略式断面図。FIG. 5 is a schematic cross-sectional view illustrating a third embodiment of the present invention.

【図６】本発明の第４の実施例を説明する略式断面図。FIG. 6 is a schematic cross-sectional view explaining a fourth embodiment of the present invention.

【図７】本発明の第５の実施例を説明する略式断面図。FIG. 7 is a schematic sectional view explaining a fifth embodiment of the present invention.

【図８】本発明の第６の実施例を説明する略式断面図。FIG. 8 is a schematic sectional view illustrating a sixth embodiment of the present invention.

【図９】本発明の第７の実施例を説明する略式断面図。FIG. 9 is a schematic sectional view illustrating a seventh embodiment of the present invention.

【図10】本発明の第８の実施例を説明する略式断面図。FIG. 10 is a schematic sectional view illustrating an eighth embodiment of the present invention.

【図11】本発明の第９の実施例を説明する略式断面図。FIG. 11 is a schematic sectional view illustrating a ninth embodiment of the present invention.

【図12】本発明の第10の実施例を説明する略式断面図。FIG. 12 is a schematic sectional view illustrating a tenth embodiment of the present invention.

【図13】本発明の第11の実施例を説明する略式断面図。FIG. 13 is a schematic sectional view illustrating an eleventh embodiment of the present invention.

【図14】本発明の第12の実施例を説明する略式断面図。FIG. 14 is a schematic sectional view illustrating a twelfth embodiment of the present invention.

【図15】本発明の第13の実施例を説明する略式断面図。FIG. 15 is a schematic sectional view illustrating a thirteenth embodiment of the present invention.

【図16】本発明の第14の実施例を説明する略式断面図。FIG. 16 is a schematic sectional view illustrating a fourteenth embodiment of the present invention.

【図17】本発明の第15の実施例を説明する略式断面図。FIG. 17 is a schematic sectional view illustrating a fifteenth embodiment of the present invention.

【図18】本発明の第16の実施例を説明する略式断面図。FIG. 18 is a schematic sectional view illustrating a sixteenth embodiment of the present invention.

【図19】本発明の第11の実施例を説明する略式断面図。FIG. 19 is a schematic sectional view illustrating an eleventh embodiment of the present invention.

【図20】本発明の第12の実施例を説明する略式断面図。FIG. 20 is a schematic sectional view illustrating a twelfth embodiment of the present invention.

【図21】本発明の第13の実施例を説明する略式断面図。FIG. 21 is a schematic sectional view illustrating a thirteenth embodiment of the present invention.

【図22】本発明の第14の実施例を説明する略式断面図。FIG. 22 is a schematic sectional view explaining a fourteenth embodiment of the present invention.

【図23】本発明の第15の実施例を説明する略式断面図。FIG. 23 is a schematic sectional view illustrating a fifteenth embodiment of the present invention.

【図24】本発明の第16の実施例を説明する略式断面図。FIG. 24 is a schematic sectional view illustrating a sixteenth embodiment of the present invention.

【図25】本発明の第11の実施例を説明する略式断面図。FIG. 25 is a schematic sectional view illustrating an eleventh embodiment of the present invention.

【図26】本発明の第12の実施例を説明する略式断面図。FIG. 26 is a schematic sectional view illustrating a twelfth embodiment of the present invention.

【図27】本発明の第13の実施例を説明する略式断面図。FIG. 27 is a schematic sectional view illustrating a thirteenth embodiment of the present invention.

【図28】本発明の第16の実施例を説明する略式断面図。FIG. 28 is a schematic sectional view illustrating a sixteenth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10…n+基板、11…nドリフト層、12…n+ソース領域、13
…pゲート領域、14…n-層、15…n層、16…埋め込みp
層、17…p-層、18…n-領域、21…ドレイン電極、22…ソ
ース電極、23…ゲート電極。10… n + substrate, 11… n drift layer, 12… n + source region, 13
… P gate region, 14… n - layer, 15… n layer, 16… embedded p
Layer, 17 ... p - layer, 18 ... n - region, 21 ... drain electrode, 22 ... source electrode, 23 ... gate electrode.

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】 バンドギャップが2.0eV以上の半導体で
あり、かつ一対の主表面を有し、低不純物濃度の第一導
電型の基体と、前記基体の第一主表面に形成された第一
導電型を有し基体より低抵抗の第一層と、前記第一層の
表面に形成された第一電極と、前記基体の第二主表面に
形成され基体と同じ導電型の第二領域と、前記第二領域
に形成された第二電極と、前記基体の第二主表面に前記
第二領域より深く形成され基体と異なる導電型の制御領
域と、前記制御領域に形成された制御電極とから構成さ
れており、かつ前記第二領域と制御領域は互いに接する
ように配置された半導体装置において、 前記第二領域の下部にあって、前記制御領域に挟まれた
チャネル領域の幅の最小値が1.5μmより狭いことを特徴
とする半導体装置。1. A substrate of a semiconductor having a bandgap of 2.0 eV or more, having a pair of main surfaces, having a low impurity concentration and having a first conductivity type, and a first main surface formed on the first main surface of the base. A first layer having a conductivity type and having a resistance lower than that of the substrate; a first electrode formed on the surface of the first layer; and a second region having the same conductivity type as the substrate formed on the second main surface of the substrate. A second electrode formed in the second region, a control region formed on the second main surface of the base body deeper than the second region and having a conductivity type different from that of the base body, and a control electrode formed in the control region In the semiconductor device, wherein the second region and the control region are arranged so as to be in contact with each other, in the lower portion of the second region, the minimum value of the width of the channel region sandwiched between the control regions. Is a semiconductor device characterized by a narrower than 1.5 μm. 【請求項２】 請求項１において、前記チャネル領域の
少なくとも一部の濃度が前記基体の濃度より低いことを
特長とする半導体装置。2. The semiconductor device according to claim 1, wherein the concentration of at least a part of the channel region is lower than the concentration of the substrate. 【請求項３】 請求項１において、前記チャネル領域の
少なくとも一部に第二導電型を有する薄い層が形成され
ていることを特長とする半導体装置。3. The semiconductor device according to claim 1, wherein a thin layer having a second conductivity type is formed in at least a part of the channel region. 【請求項４】 請求項１及び請求項３のいずれかにおい
て、前記チャネル領域ならびにその下側の第一層側にお
ける領域の濃度が、前記制御領域下側の第一層側におけ
る領域の濃度より高いことを特長とする半導体装置。4. The density of the channel region and the region on the first layer side below the channel region is higher than the concentration of the region on the first layer side below the control region. A semiconductor device characterized by high price. 【請求項５】 請求項１において、前記制御電極にアル
ミニウムを用い、該アルミニウム電極から熱処理により
アルミニウムを半導体中に拡散することにより、前記電
極と前記制御領域を自己整合的に形成することを特長と
する半導体装置。5. The method according to claim 1, wherein aluminum is used for the control electrode, and the aluminum and the control region are formed in a self-aligned manner by diffusing aluminum into the semiconductor by heat treatment from the aluminum electrode. Semiconductor device. 【請求項６】 請求項１において、前記第二領域の下側
に前記制御領域と同じ導電型の第二制御領域を設けるこ
とにより、前記チャネル領域における電流の主たる流れ
が前記第二領域に対し横方向になっていることを特長と
する半導体装置。6. The second control region according to claim 1, wherein a second control region having the same conductivity type as that of the control region is provided below the second region, so that a main current flow in the channel region is different from that in the second region. A semiconductor device characterized by the lateral orientation. 【請求項７】 請求項６において、前記第二領域と前記
第二制御領域が接していることを特長とする半導体装
置。7. The semiconductor device according to claim 6, wherein the second region and the second control region are in contact with each other. 【請求項８】 請求項６または請求項７の何れかにおい
て、前記チャネル領域の少なくとも一部の濃度が前記前
記基体の濃度より低いことを特長とする半導体装置。8. The semiconductor device according to claim 6, wherein the concentration of at least a part of the channel region is lower than the concentration of the base body. 【請求項９】 請求項７において、前記第二領域に近い
部分の前記チャネル領域の濃度が前記基体より高いこと
を特長とする半導体装置。9. The semiconductor device according to claim 7, wherein a concentration of the channel region in a portion near the second region is higher than that of the substrate. 【請求項１０】 請求項６から請求項９の何れかにおい
て、前記第二制御領域下側の第一層側における領域の濃
度が前記基体より高いことを特長とする半導体装置。10. The semiconductor device according to claim 6, wherein the concentration of the region on the first layer side below the second control region is higher than that of the substrate. 【請求項１１】 請求項１から請求項５の何れかにおい
て、前記チャネル領域の幅と前記制御領域の幅の和が、
前記チャネル領域の幅の４倍と等しいかもしくは小さい
を特長とする半導体装置。11. The sum of the width of the channel region and the width of the control region according to claim 1,
A semiconductor device characterized by being equal to or smaller than four times the width of the channel region.
JP2001253188A 2001-08-23 2001-08-23 Semiconductor device Expired - Fee Related JP4127987B2 (en)

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