JP2003037366A - Laminated wiring board and its manufacturing method - Google Patents
Laminated wiring board and its manufacturing methodInfo
- Publication number
- JP2003037366A JP2003037366A JP2001225394A JP2001225394A JP2003037366A JP 2003037366 A JP2003037366 A JP 2003037366A JP 2001225394 A JP2001225394 A JP 2001225394A JP 2001225394 A JP2001225394 A JP 2001225394A JP 2003037366 A JP2003037366 A JP 2003037366A
- Authority
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- Japan
- Prior art keywords
- conductor
- wiring board
- interlayer
- laminated wiring
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は，導体層と層間絶縁
層とを積層してなる積層配線板およびその製造方法に関
する。さらに詳細には，３層以上の導体層を一箇所で導
通させる層間導通構造を有する積層配線板およびその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated wiring board formed by laminating a conductor layer and an interlayer insulating layer, and a method for manufacturing the same. More specifically, the present invention relates to a laminated wiring board having an interlayer conduction structure for conducting three or more conductor layers at one place, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来から，導体層と層間絶縁層とを交互
に積層する積層配線板においては，多様な回路の実現の
ため，多層間の層間導通構造を随所に配置している。こ
の多層間の導通構造を有する積層配線板の製造方法とし
ては，次の方法が一般的である。まず，複数の導体層と
層間絶縁層とを交互に重ね合わせて１枚の積層配線板を
作成する。その積層配線板に対して，ドリル等により貫
通孔を形成し，めっきすることによって層間の導通をと
る。そして，貫通孔の内部の充填，ふためっき等をする
のである。2. Description of the Related Art Conventionally, in a laminated wiring board in which conductor layers and interlayer insulating layers are alternately laminated, interlayer conductive structures between layers are arranged everywhere in order to realize various circuits. The following method is generally used as a method for manufacturing the laminated wiring board having the conduction structure between the multiple layers. First, a plurality of conductor layers and interlayer insulating layers are alternately laminated to form one laminated wiring board. Through holes are formed in the laminated wiring board with a drill or the like, and plating is performed to establish conduction between layers. Then, the inside of the through hole is filled, the lid is plated, and the like.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら，従来の
積層配線板には，次のような問題点があった。すなわ
ち，この積層配線板の層間導通構造にあっては，貫通孔
の内壁をめっきにより析出した金属が覆うことにより層
間導通を実現している。このめっきによる導通は，接続
面積が狭いため導通の信頼性が低い。また，貫通孔のめ
っき，充填，ふためっき等の多数の工程を踏まなければ
ならず，製造に多くの手間がかかる。However, the conventional laminated wiring board has the following problems. That is, in the interlayer conduction structure of this laminated wiring board, the interlayer conduction is realized by covering the inner wall of the through hole with the metal deposited by plating. Since the connection area of the plating is small, the reliability of the conduction is low. In addition, many steps such as through-hole plating, filling, and lid plating have to be performed, which requires a lot of labor for manufacturing.
【０００４】本発明は，前記した従来の積層配線板にお
ける層間導通構造が有する問題点を解決するためになさ
れたものである。すなわちその課題とするところは，層
間導通構造において，接続面積を拡大するとともに製造
の工程数を減らした積層配線板およびその製造方法を提
供することにある。The present invention has been made in order to solve the problems of the above-mentioned conventional interlayer conductive structure in a laminated wiring board. That is, it is an object of the invention to provide a laminated wiring board and a manufacturing method thereof in which the connection area is enlarged and the number of manufacturing steps is reduced in the interlayer conduction structure.
【０００５】[0005]
【課題を解決するための手段】この課題の解決を目的と
してなされた本発明の積層配線板は，導体層と層間絶縁
層とを交互に積層してなる積層配線板であって，「ある
層間絶縁層」の層間導通構造（Ａ）と，「ある層間絶縁
層」に隣接する層間絶縁層の層間導通構造（Ｂ）とが同
じ位置に配置され，層間導通構造（Ａ）を構成する導体
（Ａ）と，層間導通構造（Ｂ）を構成する導体（Ｂ）と
が異なる硬度を有するものである。The laminated wiring board of the present invention made for the purpose of solving this problem is a laminated wiring board in which conductor layers and interlayer insulating layers are alternately laminated. The inter-layer conductive structure (A) of the "insulating layer" and the inter-layer conductive structure (B) of the inter-layer insulating layer adjacent to the "certain inter-layer insulating layer" are arranged at the same position, and a conductor ( A) and the conductor (B) forming the interlayer conduction structure (B) have different hardnesses.
【０００６】また，本発明の積層配線板は，導体（Ａ）
は，導体（Ｂ）より高い硬度を有し，層間導通構造
（Ａ）と前記層間導通構造（Ｂ）とが接続する箇所で
は，導体（Ａ）が導体（Ｂ）にくい込んでいるものであ
る。Further, the laminated wiring board of the present invention comprises a conductor (A)
Has a hardness higher than that of the conductor (B), and the conductor (A) is hard to be embedded in the conductor (B) at a place where the interlayer conduction structure (A) and the interlayer conduction structure (B) are connected to each other. .
【０００７】すなわち，本発明の層間導通構造は，「あ
る層間絶縁層の層間導通構造」と，それに「隣接する層
間絶縁層の層間導通構造」とを，同じ位置に配置するこ
とで接続させ，３つの導体層の導通をとる多層間の層間
接続構造である。ここでいう同じ位置とは，積層配線板
の板面内における同じ位置であることをいう。この構造
は，実質的には両層間導通構造間の貫通孔を充填したも
のとほぼ同等の機能を有する。さらに，「ある層間絶縁
層の層間導通構造」を構成する導体と，「隣接する層間
絶縁層の層間導通構造」を構成する導体とが異なる硬度
を有している。このため，両層間導通構造が接続する箇
所では，導体が金属の可塑性により変形しており，導体
同士が密着している。さらに，硬度の高い導体（Ａ）が
導体（Ｂ）にくい込むことにより両層間導通構造の接続
面積が拡大しており，確実に導通がとられ信頼性が向上
している。That is, in the interlayer conductive structure of the present invention, the "interlayer conductive structure of a certain interlayer insulating layer" and the "interlayer conductive structure of an adjacent interlayer insulating layer" are arranged at the same position to connect them. This is an inter-layer connection structure between multiple layers that conducts three conductor layers. The same position here means the same position on the plate surface of the laminated wiring board. This structure has substantially the same function as that of filling the through hole between the two interlayer conductive structures. Further, the conductor forming the “interlayer conductive structure of a certain interlayer insulating layer” and the conductor forming the “interlayer conductive structure of the adjacent interlayer insulating layer” have different hardnesses. For this reason, the conductor is deformed by the plasticity of the metal at the location where the two-layer conductive structure is connected, and the conductors are in close contact with each other. Further, since the conductor (A) having high hardness is hard to be embedded in the conductor (B), the connection area of the both-layer conductive structure is expanded, and the conductive is surely conducted to improve the reliability.
【０００８】また，本発明の積層配線板の製造方法で
は，導体（Ａ）による層間導通構造（Ａ）を有する基板
（Ａ）と，導体（Ａ）と異なる硬度の導体（Ｂ）による
層間導通構造（Ｂ）を有する基板（Ｂ）とを，層間接続
構造（Ａ）と層間接続構造（Ｂ）とが同じ位置になるよ
うに組み合わせ，組み合わせた基板をプレスして一体化
することにより導体層と層間絶縁層とを交互に積層して
なる積層配線板を製造する。In the method for manufacturing a laminated wiring board according to the present invention, the substrate (A) having the interlayer conduction structure (A) of the conductor (A) and the interlayer conduction of the conductor (B) having a hardness different from that of the conductor (A) are used. The substrate (B) having the structure (B) is combined so that the interlayer connection structure (A) and the interlayer connection structure (B) are at the same position, and the combined substrate is pressed and integrated to form a conductor layer. A laminated wiring board is manufactured by alternately laminating the insulating layer and the interlayer insulating layer.
【０００９】この製造方法では，層間導通構造が形成さ
れた２枚の基板を出発材とする。この層間導通構造を構
成する導体の硬度は，それぞれ異なっている。この出発
材に対して，まず，層間導通構造同士が同じ位置になる
ように基板を組み合わせる。その後，その両基板をプレ
スし一体化することにより積層配線板とする。すなわ
ち，プレス後にふためっき等の作業はしない。これによ
り，製造工程が簡易である。In this manufacturing method, two substrates having an interlayer conductive structure are used as starting materials. The hardness of the conductors forming the interlayer conduction structure is different. First, a substrate is assembled with this starting material so that the interlayer conductive structures are at the same position. After that, both substrates are pressed and integrated to form a laminated wiring board. That is, no work such as lid plating is performed after pressing. This simplifies the manufacturing process.
【００１０】また，この製造方法では，導体（Ａ）の硬
度が導体（Ｂ）の硬度より高く，プレス前の導体（Ａ）
は，基板（Ａ）の基板（Ｂ）に接する面から突出してい
るとよい。この基板（Ａ）と基板（Ｂ）とをプレスする
ことにより，プレス後に突出している導体（Ａ）が，導
体（Ｂ）にくい込んだ状態が得られる。これにより，層
間導通構造同士の接続面積が拡大し，導通の信頼性が向
上する。Further, in this manufacturing method, the hardness of the conductor (A) is higher than that of the conductor (B), and the conductor (A) before pressing is pressed.
Is preferably projected from the surface of the substrate (A) in contact with the substrate (B). By pressing the substrate (A) and the substrate (B), it is possible to obtain a state in which the conductor (A) protruding after pressing is hard to be embedded in the conductor (B). As a result, the connection area between the interlayer conduction structures is increased, and the reliability of conduction is improved.
【００１１】[0011]
【発明の実施の形態】以下，本発明を具体化した実施の
形態について，添付図面を参照しつつ詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments embodying the present invention will be described in detail below with reference to the accompanying drawings.
【００１２】本実施の形態に係る積層配線板１００は，
図１に示す断面構造を有している。積層配線板１００
は，導体層１１，１２，２１と，層間絶縁層１０，２０
とを有する３層配線板である。勿論，各導体層には，適
宜パターニングが施されている。各層間絶縁層は板厚
０．０５〜０．１５ｍｍ程度であり，各導体層である銅
箔の厚さは５〜２０μｍ程度である。The laminated wiring board 100 according to the present embodiment is
It has the sectional structure shown in FIG. Laminated wiring board 100
Are the conductor layers 11, 12, 21 and the interlayer insulating layers 10, 20.
And a three-layer wiring board having Of course, each conductor layer is appropriately patterned. Each interlayer insulating layer has a plate thickness of about 0.05 to 0.15 mm, and the copper foil as each conductor layer has a thickness of about 5 to 20 μm.
【００１３】積層配線板１００は，導体層１１と導体層
１２との導通をとるためのビア１３を有している。ま
た，導体層１２と導体層２１との導通をとるためのビア
２３を有している。このビア１３とビア２３とは，同じ
位置に重ね合わせられている。さらに，ビア１３とビア
２３との接続部分は，ビア２３の材質がビア１３の材質
にくい込んだ形状をしている。The laminated wiring board 100 has a via 13 for electrically connecting the conductor layer 11 and the conductor layer 12. Further, it has a via 23 for electrically connecting the conductor layer 12 and the conductor layer 21. The via 13 and the via 23 are superposed at the same position. Further, the connection portion between the via 13 and the via 23 has a shape in which the material of the via 23 is difficult to be embedded in the material of the via 13.
【００１４】ビア１３は，絶縁層１０に設けられた０．
０６〜０．３０ｍｍ程度の径の穴にＡｇ製のピンを挿入
したものである。また，ビア２３は，絶縁層２０を貫通
した０．０６〜０．３０ｍｍ程度の径のＣｕ製のピンで
ある。このため，積層配線板１００は，導体層１１と導
体層１２と導体層２１とが，ビア１３およびビア２３に
より導通した層間導通構造を有している。The vias 13 are formed on the insulating layer 10.
A pin made of Ag is inserted into a hole having a diameter of about 06 to 0.30 mm. The via 23 is a Cu pin that penetrates the insulating layer 20 and has a diameter of about 0.06 to 0.30 mm. Therefore, the laminated wiring board 100 has an interlayer conduction structure in which the conductor layers 11, 12, and 21 are electrically connected by the vias 13 and 23.
【００１５】次に，積層配線板１００の製造プロセスを
説明する。積層配線板１００は，両面銅付き樹脂板１と
片面銅付き樹脂板２とを出発材として製造される。図２
は，両面銅つき樹脂板１を示す図である。両面銅付き樹
脂板１は，両面に銅箔（導体層）１１，１２を有してい
る。次に，図３に示すように，両面銅付き樹脂板１に対
して，ドリルにより貫通穴１４を開ける。貫通穴１４
は，層間導通構造を形成するためのものである。なお，
貫通穴１４の形成は，レーザ加工によるものでもよい。Next, the manufacturing process of the laminated wiring board 100 will be described. The laminated wiring board 100 is manufactured using the resin plate 1 with copper on both sides and the resin plate 2 with copper on one side as starting materials. Figure 2
FIG. 3 is a diagram showing a resin plate 1 with double-sided copper. The resin plate 1 with double-sided copper has copper foils (conductor layers) 11 and 12 on both sides. Next, as shown in FIG. 3, through holes 14 are drilled in the resin plate 1 with double-sided copper by a drill. Through hole 14
Is for forming an interlayer conduction structure. In addition,
The through hole 14 may be formed by laser processing.
【００１６】次に，貫通穴１４にＡｇ製のピンを挿入す
る。図４は，挿入後の樹脂板１を示す図である。樹脂板
１は，ビア（Ａｇ製のピン）１３によって導体層１１と
導体層１２との導通がとられている。ビア１３の長さ
は，樹脂板１の厚さと同じである。そして，この状態の
樹脂板１の銅箔１１，１２をパターニングする。Next, a pin made of Ag is inserted into the through hole 14. FIG. 4 is a diagram showing the resin plate 1 after insertion. In the resin plate 1, the conductor layers 11 and 12 are electrically connected by the vias (pins made of Ag) 13. The length of the via 13 is the same as the thickness of the resin plate 1. Then, the copper foils 11 and 12 of the resin plate 1 in this state are patterned.
【００１７】一方，片面銅付き樹脂板２は，片面に銅箔
（導体層）２１を有している。この片面銅付き樹脂板２
に対して，樹脂板２を貫通するようにＣｕ製のピン２３
を打ち込む。図５は，打ち込み後の樹脂板２を示す図で
ある。樹脂板２は，ビア（Ｃｕ製のピン）２３が導体層
２１の反対面まで突き出ているため，導体層２１と反対
面との導通をとることが可能である。そして，この状態
の樹脂板２の銅箔２１をパターニングする。On the other hand, the resin plate 2 with copper on one side has a copper foil (conductor layer) 21 on one side. This resin plate with copper on one side 2
On the other hand, a pin 23 made of Cu so as to penetrate the resin plate
Type in. FIG. 5 is a diagram showing the resin plate 2 after the driving. Since the resin plate 2 has the vias (Cu pins) 23 protruding to the opposite surface of the conductor layer 21, it is possible to establish conduction with the opposite surface of the conductor layer 21. Then, the copper foil 21 of the resin plate 2 in this state is patterned.
【００１８】次に，Ａｇ製のピンが挿入された両面銅箔
付き樹脂板１と，Ｃｕ製のピンが打ち込まれた片面銅箔
付き樹脂板２とを，ビア１３とビア２３とが上下に重な
るように組み合わせる。片面銅箔付き樹脂板２は，銅箔
２１のない面と樹脂板１とが接するように配置する。そ
して，組合せた樹脂板１と樹脂板２とをプレスして一体
化する。このとき，Ｃｕの方がＡｇより硬いため，ビア
２３のＣｕがビア１３のＡｇにくい込み，図１に示す積
層配線板１００が製造される。この積層配線板１００
は，銅箔１１，絶縁層１０，銅箔１２，絶縁層２０，銅
箔２１の順に積層された構造である。なお，この状態の
積層配線板１００の表面にソルダレジストを形成しても
よい。Next, the resin plate with double-sided copper foil 1 into which the pin made of Ag is inserted, and the resin plate 2 with single-sided copper foil into which the pin made of Cu is stamped, the via 13 and the via 23 are vertically arranged. Combine so that they overlap. The resin plate 2 with one-sided copper foil is arranged so that the surface without the copper foil 21 and the resin plate 1 are in contact with each other. Then, the combined resin plate 1 and resin plate 2 are pressed to be integrated. At this time, since Cu is harder than Ag, Cu in the via 23 is less likely to be contained in Ag in the via 13, and the laminated wiring board 100 shown in FIG. 1 is manufactured. This laminated wiring board 100
Is a structure in which a copper foil 11, an insulating layer 10, a copper foil 12, an insulating layer 20, and a copper foil 21 are laminated in this order. A solder resist may be formed on the surface of the laminated wiring board 100 in this state.
【００１９】次に，異種金属による層間導通構造となっ
ているビア１３とビア２３との接続部に着目して説明す
る。図７は，図４，図５のそれぞれ一部を示す（ただ
し，導体層は省略してある。）図である。まず，Ａｇ製
であるピン１３と，Ｃｕ製であるピン２３とが同じ位置
になるように配置する。また，ピン２３は樹脂板２から
突出している。Next, a description will be given focusing on the connection portion between the via 13 and the via 23, which have an interlayer conduction structure of different metals. FIG. 7 is a diagram showing a part of each of FIGS. 4 and 5 (however, the conductor layer is omitted). First, the pin 13 made of Ag and the pin 23 made of Cu are arranged at the same position. Further, the pin 23 projects from the resin plate 2.
【００２０】上記状態の樹脂板１と樹脂板２とをプレス
し，図８の状態とする。図８は，図１の一部を示す（た
だし，導体層は省略してある。）図である。ピン１３と
ピン２３との接続部分では，プレス加工の際にピン２３
のＣｕがピン１３のＡｇにくい込んでいる。これは金属
の可塑性による現象であり，ＣｕがＡｇより硬い材質の
金属だからである。これにより，ピン１３とピン２３と
の接続面積が拡大し，十分な接続面積を確保することが
できる。The resin plate 1 and the resin plate 2 in the above state are pressed to obtain the state shown in FIG. FIG. 8 is a view showing a part of FIG. 1 (however, the conductor layer is omitted). At the connecting part between the pin 13 and the pin 23, the pin 23
Cu of Ag is hard to be embedded in Ag of the pin 13. This is a phenomenon due to the plasticity of the metal, because Cu is a metal of a material harder than Ag. As a result, the connection area between the pins 13 and 23 is expanded, and a sufficient connection area can be secured.
【００２１】本実施例の積層配線板１００では，硬い金
属としてＣｕ，軟らかい金属としてＡｇを用いている。
この組合せ以外にも図９に示すような組合せが考えられ
る。図９中，金属Ａとして示したものは金属Ｂとして示
したものより硬度が高い。勿論，これ以外にも硬度が異
なる金属同士ならば実現可能である。なお，金属の硬さ
としては，ロックウェル法やビッカース法等の試験方法
により測定した値を用いればよい。In the laminated wiring board 100 of this embodiment, Cu is used as a hard metal and Ag is used as a soft metal.
In addition to this combination, a combination as shown in FIG. 9 can be considered. In FIG. 9, the metal A has a higher hardness than the metal B. Of course, other than this, it is possible to realize metals having different hardness. As the hardness of the metal, a value measured by a test method such as Rockwell method or Vickers method may be used.
【００２２】以上詳細に説明したように本実施の形態で
は，まず，ビア（Ａｇ製のピン）１３により層間導通構
造を有する樹脂板１と，ビア（Ｃｕ製のピン）２３によ
り層間導通構造を有する樹脂板２とを組み合わせること
としている。このとき，ビア１３とビア２３とが同じ位
置になるように配置することとしている。また，ビア２
３は，樹脂板２から突出している。この状態で樹脂板１
および樹脂板２をプレスし一体化することとしている。
これにより，導体層１１と導体層２１とが，ビア１３お
よびビア２３により導通した層間導通構造を有する積層
配線板１００が製造される。この積層配線板１００のビ
ア１３とビア２３とが接続している箇所では，突出して
いるビア２３のＣｕがビア１３のＡｇにくい込んだ形状
となっている。このため，ビア１３とビア２３と接続面
積が拡大し，接続信頼性が向上している。As described in detail above, in the present embodiment, first, the resin plate 1 having the interlayer conduction structure by the vias (pins made of Ag) 13 and the interlayer conduction structure by the vias (pins made of Cu) 23 are formed. It will be combined with the resin plate 2 that it has. At this time, the vias 13 and the vias 23 are arranged at the same position. Also, via 2
3 projects from the resin plate 2. Resin plate 1 in this state
The resin plate 2 is pressed and integrated.
As a result, the laminated wiring board 100 having the interlayer conductive structure in which the conductor layers 11 and 21 are electrically connected by the vias 13 and 23 is manufactured. At the location where the via 13 and the via 23 of the laminated wiring board 100 are connected to each other, the protruding Cu of the via 23 has a shape in which Ag of the via 13 is hard to be incorporated. Therefore, the connection area between the via 13 and the via 23 is expanded, and the connection reliability is improved.
【００２３】また，本実施の形態では，プレス後にめっ
き等の作業をしない。よって，製造の工程数が少なくて
すむ。これにより，接続面積を拡大するとともに製造の
工程数を減らした積層配線板およびその製造方法を実現
している。Further, in the present embodiment, no work such as plating is performed after pressing. Therefore, the number of manufacturing steps can be reduced. As a result, a laminated wiring board and a method of manufacturing the same have been realized in which the connection area is expanded and the number of manufacturing steps is reduced.
【００２４】なお，本実施の形態は単なる例示にすぎ
ず，本発明を何ら限定するものではない。したがって本
発明は当然に，その要旨を逸脱しない範囲内で種々の改
良，変形が可能である。例えば，ＡｇとＡｇペーストと
は，本発明にいう異なる硬度の導体に該当する。The present embodiment is merely an example and does not limit the present invention. Therefore, naturally, the present invention can be variously improved and modified without departing from the gist thereof. For example, Ag and Ag paste correspond to conductors having different hardness according to the present invention.
【００２５】また，同一金属を使用しても治金学的製法
によるものとめっきにより析出したものとでは硬さが異
なる場合がある。例えばＰｔは，治金学的製法によるも
のより，めっきにより析出したものの方が硬い。よっ
て，治金学的製法によるＰｔとめっきにより析出したＰ
ｔとは，本発明にいう異なる硬度の導体に該当する。Even if the same metal is used, the hardness of the metallurgical method and that of the metal deposited by plating may be different. For example, Pt is harder when deposited by plating than when it is manufactured by a metallurgical method. Therefore, Pt by metallurgical method and P deposited by plating
The t corresponds to conductors having different hardness according to the present invention.
【００２６】また，本実施例では，硬度の異なる材質の
ビアを有する２枚の基板を組み合わせているが，２枚以
上であれば幾つでもよい。例えば３枚の基板を組み合わ
せる場合は，ビアの材質をＣｕ，Ａｇ，Ｃｕの順に組合
せればよい。勿論，隣り合うビアの材質の硬度が異なっ
ていれば実現できる。また，組み合わせる基板も，両面
銅箔付き基板，銅箔なし基板，両面銅箔付き基板の順に
組み合わせる場合や，片面銅箔付き基板，両面銅箔付き
基板，片面銅箔付き基板の順に組み合わせる等のさまざ
まなバリエーションで実現できる。In this embodiment, two substrates having vias of different hardness are combined, but any number may be used as long as it is two or more. For example, when three substrates are combined, the via materials may be combined in the order of Cu, Ag, and Cu. Of course, this can be achieved if the materials of adjacent vias have different hardness. Also, the boards to be combined can be combined in the order of a board with double-sided copper foil, a board without copper foil, a board with double-sided copper foil, or a board with single-sided copper foil, a board with double-sided copper foil, a board with single-sided copper foil, and so on. It can be realized in various variations.
【００２７】[0027]
【発明の効果】以上の説明から明らかなように本発明に
よれば，層間導通構造において，接続面積を拡大すると
ともに製造の工程数を減らした積層配線板およびその製
造方法が提供されている。As is apparent from the above description, according to the present invention, there is provided a laminated wiring board in which the connection area is enlarged and the number of manufacturing steps is reduced in the interlayer conduction structure, and a manufacturing method thereof.
【図１】実施の形態に係る積層配線板の断面図である。FIG. 1 is a cross-sectional view of a laminated wiring board according to an embodiment.
【図２】図１の積層配線板の製造途上の段階の断面図
（工程１）である。FIG. 2 is a cross-sectional view (process 1) at a stage during manufacturing of the laminated wiring board of FIG.
【図３】図１の積層配線板の製造途上の段階の断面図
（工程２）である。FIG. 3 is a cross-sectional view (process 2) at a stage in the process of manufacturing the laminated wiring board of FIG.
【図４】図１の積層配線板の製造途上の段階の断面図
（工程３）である。FIG. 4 is a cross-sectional view (process 3) at a stage in the process of manufacturing the laminated wiring board of FIG.
【図５】図１の積層配線板の製造途上の段階の断面図
（工程４）である。5 is a cross-sectional view (process 4) at a stage during manufacturing of the laminated wiring board in FIG. 1. FIG.
【図６】図１の積層配線板の製造途上の段階の断面図
（工程５）である。FIG. 6 is a cross-sectional view (process 5) at a stage in the process of manufacturing the laminated wiring board of FIG.
【図７】異種金属による層間導通を示す図（プレス前）
である。FIG. 7 is a diagram showing inter-layer conduction by dissimilar metals (before pressing).
Is.
【図８】異種金属による層間導通を示す図（プレス後）
である。FIG. 8 is a diagram showing interlayer conduction by dissimilar metals (after pressing).
Is.
【図９】金属の組合せを示す図である。FIG. 9 is a diagram showing a combination of metals.
１０，２０ 層間絶縁層 １１，１２，２１ 導体層（銅箔） １３ ビア（Ａｇ製のピン） ２３ ビア（Ｃｕ製のピン） １００ 積層配線板 10, 20 Interlayer insulation layer 11, 12, 21 Conductor layer (copper foil) 13 vias (Ag pin) 23 Vias (Cu pins) 100 laminated wiring board
Claims (4)
なる積層配線板において，ある層間絶縁層の層間導通構
造（Ａ）と，前記ある層間絶縁層に隣接する層間絶縁層
の層間導通構造（Ｂ）とが同じ位置に配置され，前記層
間導通構造（Ａ）を構成する導体（Ａ）と，前記層間導
通構造（Ｂ）を構成する導体（Ｂ）とが異なる硬度を有
することを特徴とする積層配線板。1. In a laminated wiring board in which conductor layers and interlayer insulating layers are alternately laminated, an interlayer conduction structure (A) of a certain interlayer insulating layer and an interlayer of an interlayer insulating layer adjacent to the certain interlayer insulating layer. The conductive structure (B) is arranged at the same position, and the conductor (A) forming the interlayer conductive structure (A) and the conductor (B) forming the interlayer conductive structure (B) have different hardnesses. Laminated wiring board characterized by.
て，前記導体（Ａ）は，前記導体（Ｂ）より高い硬度を
有し，前記層間導通構造（Ａ）と前記層間導通構造
（Ｂ）とが接続する箇所では，前記導体（Ａ）が前記導
体（Ｂ）にくい込んでいることを特徴とする積層配線
板。2. The laminated wiring board according to claim 1, wherein the conductor (A) has a hardness higher than that of the conductor (B), and the interlayer conductive structure (A) and the interlayer conductive structure (B). A laminated wiring board, wherein the conductor (A) is embedded in the conductor (B) at a location where is connected to.
なる積層配線板の製造方法において，導体（Ａ）による
層間導通構造（Ａ）を有する基板（Ａ）と，前記導体
（Ａ）と異なる硬度の導体（Ｂ）による層間導通構造
（Ｂ）を有する基板（Ｂ）とを，層間接続構造（Ａ）と
層間接続構造（Ｂ）とが同じ位置になるように組み合わ
せ，組み合わせた基板をプレスして一体化することを特
徴とする積層配線板の製造方法。3. A method of manufacturing a laminated wiring board in which conductor layers and interlayer insulating layers are alternately laminated, wherein a substrate (A) having an interlayer conduction structure (A) of the conductor (A) and the conductor (A) are used. ) And a substrate (B) having an interlayer conduction structure (B) made of a conductor (B) having a different hardness are combined and combined so that the interlayer connection structure (A) and the interlayer connection structure (B) are at the same position. A method for manufacturing a laminated wiring board, which comprises pressing and integrating the substrates.
法において，前記導体（Ａ）の硬度が前記導体（Ｂ）の
硬度より高く，プレス前の前記導体（Ａ）は，前記基板
（Ａ）の前記基板（Ｂ）に接する面から突出しているこ
とを特徴とする積層配線板の製造方法。4. The method for manufacturing a laminated wiring board according to claim 3, wherein the hardness of the conductor (A) is higher than that of the conductor (B), and the conductor (A) before pressing is the substrate ( A method for manufacturing a laminated wiring board, characterized in that it protrudes from a surface of (A) in contact with the substrate (B).
Priority Applications (1)
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|---|---|---|---|
| JP2001225394A JP4795575B2 (en) | 2001-07-26 | 2001-07-26 | Laminated wiring board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001225394A JP4795575B2 (en) | 2001-07-26 | 2001-07-26 | Laminated wiring board and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003037366A true JP2003037366A (en) | 2003-02-07 |
| JP4795575B2 JP4795575B2 (en) | 2011-10-19 |
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ID=19058392
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001225394A Expired - Fee Related JP4795575B2 (en) | 2001-07-26 | 2001-07-26 | Laminated wiring board and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018182281A (en) * | 2017-04-12 | 2018-11-15 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Inductor and method for manufacturing the same |
| US11121123B2 (en) | 2017-12-27 | 2021-09-14 | Murata Manufacturing Co., Ltd. | Semiconductor composite device and package board used therein |
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| JP2000294931A (en) * | 1999-04-07 | 2000-10-20 | Shinko Electric Ind Co Ltd | Multilayer wiring board and manufacture thereof |
| JP2001068856A (en) * | 1999-06-22 | 2001-03-16 | Asahi Chem Ind Co Ltd | Insulation resin sheet and its manufacture |
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|---|---|---|---|---|
| JPH03257893A (en) * | 1990-03-07 | 1991-11-18 | Fujitsu Ltd | Multilayer wiring board |
| JPH1027824A (en) * | 1996-02-23 | 1998-01-27 | Matsushita Electric Ind Co Ltd | Semiconductor device having bump electrode and manufacture thereof |
| JP2000216198A (en) * | 1999-01-26 | 2000-08-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JP2000286553A (en) * | 1999-02-26 | 2000-10-13 | Fujitsu Ltd | Structure for manufacturing z connection-type stacked substrate for high-density electronic component packaging and method therefor |
| JP2000294931A (en) * | 1999-04-07 | 2000-10-20 | Shinko Electric Ind Co Ltd | Multilayer wiring board and manufacture thereof |
| JP2001068856A (en) * | 1999-06-22 | 2001-03-16 | Asahi Chem Ind Co Ltd | Insulation resin sheet and its manufacture |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018182281A (en) * | 2017-04-12 | 2018-11-15 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Inductor and method for manufacturing the same |
| US10629364B2 (en) | 2017-04-12 | 2020-04-21 | Samsung Electro-Mechanics Co., Ltd. | Inductor and method for manufacturing the same |
| US11121123B2 (en) | 2017-12-27 | 2021-09-14 | Murata Manufacturing Co., Ltd. | Semiconductor composite device and package board used therein |
| US11552020B2 (en) | 2017-12-27 | 2023-01-10 | Murata Manufacturing Co., Ltd. | Semiconductor composite device and package board used therein |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4795575B2 (en) | 2011-10-19 |
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