JP2003037125A - Method for manufacturing circuit device - Google Patents

Method for manufacturing circuit device

Info

Publication number
JP2003037125A
JP2003037125A JP2001225464A JP2001225464A JP2003037125A JP 2003037125 A JP2003037125 A JP 2003037125A JP 2001225464 A JP2001225464 A JP 2001225464A JP 2001225464 A JP2001225464 A JP 2001225464A JP 2003037125 A JP2003037125 A JP 2003037125A
Authority
JP
Japan
Prior art keywords
insulating resin
manufacturing
conductive foil
circuit device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001225464A
Other languages
Japanese (ja)
Inventor
Toshihiko Tono
俊彦 東野
Norihiro Sakai
紀泰 酒井
Koji Seki
幸治 関
Hideo Takada
秀夫 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2001225464A priority Critical patent/JP2003037125A/en
Publication of JP2003037125A publication Critical patent/JP2003037125A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To overcome a problem that a base plate is warped due to the differ ence in a thermal expansion coefficient or a forming shrinkage factor between a base plate and an insulation resin and hereby the resin is also warped, when a block formed by integrating a plurality of assembling parts is commonly molded and the insulation resin having a large area is formed. SOLUTION: In a method for manufacturing a circuit device, to keep flatness on the surface of the insulation resin 20, a reinforcing part 40 for preventing warpage is formed on the back face of the conductive foil 30 in each assembling block corresponding to the insulation resin 20 on the surface of the conductive foil 30. Flatness can be kept more steadily on the surface of the insulation resin 20. Hereby, it is possible to improve workability in the subsequent processes such as a resist printing process or a solder printing process for forming back face electrodes which need flatness.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は回路装置の製造方法
では、複数の搭載部を一括してモールドする絶縁性樹脂
裏面に反り防止のための補強部を形成することで、絶縁
性樹脂表面に平坦性を保持させるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit device, in which a reinforcing portion for preventing warpage is formed on a back surface of an insulating resin that molds a plurality of mounting portions at a time, so that The flatness is maintained.

【０００２】[0002]

【従来の技術】従来における半導体装置の製造方法で
は、例えば、特開２０００−２３２１８３号公報に開示
されているように、基板上に多数の搭載部が集約して形
成し、それら複数の搭載部を１ブロックとして一括して
共通に樹脂モールドしていた。2. Description of the Related Art In a conventional method of manufacturing a semiconductor device, a large number of mounting portions are collectively formed on a substrate, as disclosed in, for example, Japanese Patent Laid-Open No. 2000-232183, and the plurality of mounting portions are formed. Were collectively resin-molded as one block.

【０００３】以下に、その半導体装置の製造方法につい
て簡単に説明する。A method of manufacturing the semiconductor device will be briefly described below.

【０００４】第１工程：図１１に示す如く、１個の半導
体装置に対応する搭載部２を複数個分、例えば１００個
分を縦横に配置した、大判の基板１を準備する。基板１
は、セラミックやガラスエポキシ等からなる絶縁基板で
あり、それらが１枚あるいは数枚重ね合わされて、合計
の板厚が２００〜３５０μｍと製造工程における機械的
強度を維持し得る板厚を有している。First step: As shown in FIG. 11, a large-sized substrate 1 is prepared in which a plurality of mounting portions 2 corresponding to one semiconductor device, for example, 100 mounting portions 2 are arranged vertically and horizontally. Board 1
Is an insulating substrate made of ceramics, glass epoxy, or the like, and has a total thickness of 200 to 350 μm and a thickness capable of maintaining the mechanical strength in the manufacturing process by laminating one or several of them. There is.

【０００５】図１２（Ａ）は基板１の表面に形成した導
電パターンを示す平面図、図１２（Ｂ）は基板１の断面
図である。FIG. 12A is a plan view showing a conductive pattern formed on the surface of the substrate 1, and FIG. 12B is a sectional view of the substrate 1.

【０００６】点線で囲んだ各搭載部２は、例えば長辺×
短辺が１．０ｍｍ×０．８ｍｍの矩形形状を有してお
り、これらは互いに２０〜５０μｍの間隔を隔てて縦横
に配置されている。前記間隔は後の工程でのダイシング
ライン３となる。導電パターンは、各搭載部２内におい
てアイランド部５とリード部６を形成し、これらのパタ
ーンは各搭載部２内において同一形状である。そして、
アイランド部５およびリード部６からはそれぞれ第１の
連結部７および第２の連結部８が連続したパターンで延
長される。Each mounting portion 2 surrounded by a dotted line has, for example, a long side ×
It has a rectangular shape with a short side of 1.0 mm × 0.8 mm, and these are arranged vertically and horizontally at intervals of 20 to 50 μm. The interval becomes the dicing line 3 in a later step. The conductive pattern forms the island portion 5 and the lead portion 6 in each mounting portion 2, and these patterns have the same shape in each mounting portion 2. And
A first connecting portion 7 and a second connecting portion 8 extend from the island portion 5 and the lead portion 6, respectively, in a continuous pattern.

【０００７】図１２（Ｂ）に示す如く、基板１には、各
搭載部２毎にスルーホール４が設けられている。スルー
ホール４の内部はタングステンなどの導電材料によって
埋設されている。そして、各スルーホール４に対応し
て、裏面側に外部電極９を形成する。As shown in FIG. 12B, the board 1 is provided with through holes 4 for each mounting portion 2. The inside of the through hole 4 is filled with a conductive material such as tungsten. Then, an external electrode 9 is formed on the back surface side so as to correspond to each through hole 4.

【０００８】第２工程：図１３（Ａ）に示す如く、金メ
ッキ層を形成した基板１の各搭載部２毎に、半導体チッ
プ１０およびワイヤ１１をダイボンド、ワイヤボンドす
る。半導体チップ１０はアイランド部５表面にＡｇペー
ストなどの接着剤によって固定し、半導体チップ１０の
電極パッドとリード部６とを各々ワイヤ１１で接続す
る。半導体チップ１０としては、バイポーラトランジス
タ、パワーＭＯＳＦＥＴ等の３端子の能動素子を形成し
ている。Second step: As shown in FIG. 13A, the semiconductor chip 10 and the wire 11 are die-bonded and wire-bonded to each mounting portion 2 of the substrate 1 on which the gold plating layer is formed. The semiconductor chip 10 is fixed to the surface of the island portion 5 with an adhesive such as Ag paste, and the electrode pads of the semiconductor chip 10 and the lead portions 6 are connected by wires 11. As the semiconductor chip 10, a three-terminal active element such as a bipolar transistor or a power MOSFET is formed.

【０００９】第３工程：図１３（Ｂ）に示す如く、基板
１の上方に移送したディスペンサ（図示せず）から所定
量のエポキシ系液体樹脂を滴下（ポッティング）し、す
べての半導体チップ１０を共通の樹脂層１２で被覆す
る。例えば一枚の基板１に１００個の半導体チップ１０
を搭載した場合は、１００個全ての半導体チップ１０を
一括して被覆する。Third step: As shown in FIG. 13B, a predetermined amount of epoxy liquid resin is dropped (potted) from a dispenser (not shown) transferred above the substrate 1 to remove all the semiconductor chips 10. It is covered with a common resin layer 12. For example, one substrate 1 has 100 semiconductor chips 10
When 100 is mounted, all 100 semiconductor chips 10 are collectively covered.

【００１０】第４工程：図１３（Ｃ）に示す如く、滴下
した樹脂層１２を１００〜２００度、数時間の熱処理
（キュア）にて硬化させた後に、湾曲面を研削すること
によって樹脂層１２の表面を平坦面に加工する。研削に
は研削装置を用い、研削ブレード１３によって樹脂層１
２の表面が基板１から一定の高さに揃うように、樹脂層
１２表面を削る。この工程では、樹脂層１２の膜厚を
０．３〜１．０ｍｍに成形する。前記ブレードには様々
な板厚のものが準備されており、比較的厚めのブレード
を用いて、切削を複数回繰り返すことで全体を平坦面に
形成する。Fourth step: As shown in FIG. 13 (C), after the dropped resin layer 12 is cured by heat treatment (curing) at 100 to 200 ° C. for several hours, the resin layer is obtained by grinding the curved surface. The surface of 12 is processed into a flat surface. A grinding device is used for grinding, and the resin layer 1 is ground by the grinding blade 13.
The surface of the resin layer 12 is ground so that the surface of 2 is aligned with the substrate 1 at a constant height. In this step, the resin layer 12 is formed to have a film thickness of 0.3 to 1.0 mm. Various blade thicknesses are prepared for the blade, and a relatively thick blade is used to form the entire flat surface by repeating cutting a plurality of times.

【００１１】第５工程：図１４（Ａ）に示す如く、基板
１を反転し、樹脂層１２の表面にダイシングシート１４
（たとえば、商品名：ＵＶシート、リンテック株式会社
製）を貼り付ける。先の工程で樹脂層１２表面を平坦且
つ基板１表面に対して水平の面に加工したことによっ
て、樹脂層１２側に貼り付けても基板１が傾くことな
く、その水平垂直の精度を維持することができる。Fifth step: As shown in FIG. 14A, the substrate 1 is turned over and the dicing sheet 14 is formed on the surface of the resin layer 12.
(For example, a product name: UV sheet, manufactured by Lintec Co., Ltd.) is attached. By processing the surface of the resin layer 12 to be flat and horizontal to the surface of the substrate 1 in the previous step, the substrate 1 does not tilt even when it is attached to the resin layer 12 side, and the horizontal and vertical accuracy is maintained. be able to.

【００１２】第６工程：図１４（Ｂ）に示す如く、搭載
部２毎に樹脂層１２を切断して各々の半導体装置に分離
する。切断にはダイシング装置のダイシングブレード１
３を用い、ダイシングライン３に沿って樹脂層１２と基
板１とを同時にダイシングすることにより、搭載部２毎
に分割した半導体装置を形成する。Sixth step: As shown in FIG. 14B, the resin layer 12 is cut for each mounting portion 2 and separated into respective semiconductor devices. For cutting, dicing blade 1 of dicing machine
3, the resin layer 12 and the substrate 1 are simultaneously diced along the dicing line 3 to form a semiconductor device divided for each mounting portion 2.

【００１３】そして、図１５は、上述の工程によって形
成された各半導体装置を示す斜視図である。パッケージ
の周囲４側面は、樹脂層１２と基板１の切断面で形成さ
れ、パッケージの上面は平坦化した樹脂層１２の表面で
形成され、パッケージの下面は基板２１の裏面側で形成
される。FIG. 15 is a perspective view showing each semiconductor device formed by the above steps. The peripheral four side surfaces of the package are formed by the cut surface of the resin layer 12 and the substrate 1, the upper surface of the package is formed by the surface of the flattened resin layer 12, and the lower surface of the package is formed by the rear surface side of the substrate 21.

【００１４】尚、上述では半導体装置の製造方法につい
て説明したが、例えば、１００個全ての回路装置を一括
して被覆する回路装置の製造方法においても同様であ
る。また、半田ペーストを印刷法で塗布した後リフロー
炉で溶融し裏面半田電極を形成する製造方法に付いても
同様である。Although the method of manufacturing a semiconductor device has been described above, the same applies to a method of manufacturing a circuit device in which all 100 circuit devices are collectively covered. The same applies to a manufacturing method in which a solder paste is applied by a printing method and then melted in a reflow furnace to form a back surface solder electrode.

【００１５】[0015]

【発明が解決しようとする課題】上述したように、従来
における半導体装置の製造方法では、１個の半導体装置
に対応する搭載部２を複数個分、例えば１００個分を縦
横に配置した、大判の基板１を準備する。そして、１０
０個分の搭載部２を縦横に配置した１ブロックを一括し
て絶縁性樹脂で共通の樹脂層１２を形成する。そして、
この共通の樹脂層１２を形成する工程の間中、基板１お
よび樹脂層１２は、例えば１００〜２００度の高温下に
配置され樹脂層１２は硬化する。As described above, according to the conventional method of manufacturing a semiconductor device, a plurality of mounting portions 2 corresponding to one semiconductor device, for example, 100 mounting portions 2 are arranged vertically and horizontally. Substrate 1 is prepared. And 10
A common resin layer 12 made of an insulating resin is formed in one block in which 0 mounting portions 2 are arranged vertically and horizontally. And
During the process of forming the common resin layer 12, the substrate 1 and the resin layer 12 are arranged at a high temperature of 100 to 200 degrees, and the resin layer 12 is cured.

【００１６】しかし、この工程の際、基板１として用い
られるセラミックと樹脂層１２を形成するモールド樹脂
との熱膨張係数やリフロー後の温度低下時における成型
収縮率の違いにより基板１に反りが発生してしまう。そ
の結果、樹脂層１２表面にも反りが発生してしまい、樹
脂層１２を形成する工程後の裏面電極形成工程等の樹脂
層１２表面に平坦性を有する工程の作業及び素子ごとに
分割する工程であるダイシング作業が困難であるという
課題があった。However, during this step, the substrate 1 is warped due to the difference in the coefficient of thermal expansion between the ceramic used as the substrate 1 and the molding resin forming the resin layer 12 and the molding shrinkage ratio at the time of temperature decrease after reflow. Resulting in. As a result, the surface of the resin layer 12 is also warped, and the work of the step of forming the resin layer 12 after the step of forming the resin layer 12 has flatness on the surface of the resin layer 12 and the step of dividing each element. However, there is a problem that the dicing work is difficult.

【００１７】更に、上述した半導体装置の製造方法のよ
うに、所定量のエポキシ系液体樹脂を滴下（ポッティン
グ）し、すべての半導体チップ１０を共通の樹脂層１２
で被覆する場合には、滴下した液体樹脂は比較的粘性が
高く、表面張力を有しているので、その表面が湾曲す
る。そのため、樹脂層１２の表面に平坦性を保持させな
ければならず、例えば、ダイシングにより湾曲面を研削
することによって樹脂層１２の表面を平坦面に加工する
工程を追加しなければならないという課題があった。Further, as in the above-described method for manufacturing a semiconductor device, a predetermined amount of epoxy liquid resin is dropped (potting) to make all the semiconductor chips 10 common to the common resin layer 12.
In the case of coating with, the dripped liquid resin has a relatively high viscosity and has a surface tension, so that the surface is curved. Therefore, the flatness of the surface of the resin layer 12 must be maintained, and for example, a step of processing the surface of the resin layer 12 into a flat surface by grinding a curved surface by dicing has a problem. there were.

【００１８】また、上述した半導体装置の製造方法と同
様な方法により、半導体装置裏面に半田ペーストを印刷
法で塗布した後リフロー炉で溶融し裏面半田電極を形成
する製造方法については樹脂層１２の反りは大きな問題
となる。そして、リフロー炉を通した際に作業温度はモ
ールド樹脂のガラス転移点を超えた温度となり、収縮し
た際により大きく変形してしまうため、樹脂層１２の反
りの低減を図るプロセスの導入が不可欠であるという課
題があった。Further, according to the manufacturing method similar to the above-described method for manufacturing a semiconductor device, a solder paste is applied to the back surface of the semiconductor device by a printing method and then melted in a reflow furnace to form a back surface solder electrode. Warpage is a big problem. Then, the working temperature when passing through the reflow furnace exceeds the glass transition point of the mold resin and is greatly deformed when contracted, so it is essential to introduce a process for reducing the warpage of the resin layer 12. There was a problem of being there.

【００１９】[0019]

【課題を解決するための手段】本発明は、上記した従来
の課題に鑑みてなされたもので、本発明である回路装置
の製造方法は、導電箔を用意し、少なくとも回路素子の
搭載部を多数個形成する導電パターンを形成する工程
と、所望の前記導電パターンの前記各搭載部に回路素子
を固着する工程と、各搭載部の前記回路素子を一括して
被覆し、分離溝に充填されるように絶縁性樹脂で共通モ
ールドすると同時に前記導電箔裏面に反り防止のための
補強部を形成する工程とを具備することを特徴とする。The present invention has been made in view of the above-mentioned conventional problems, and a method of manufacturing a circuit device according to the present invention provides a conductive foil and at least a mounting portion for a circuit element. A step of forming a large number of conductive patterns, a step of fixing circuit elements to each of the mounting portions of the desired conductive pattern, and a method of collectively covering the circuit elements of each mounting portion and filling the separation groove. As described above, a step of forming a common portion with an insulating resin and simultaneously forming a reinforcing portion for preventing warpage on the back surface of the conductive foil is provided.

【００２０】更に、本発明の回路装置の製造方法は、好
適には、前記補強部は、共通モールドされた前記絶縁性
樹脂部の周端に形成されることを特徴とする。Furthermore, the method of manufacturing a circuit device according to the present invention is preferably characterized in that the reinforcing portion is formed at a peripheral end of the commonly molded insulating resin portion.

【００２１】更に、本発明の回路装置の製造方法は、好
適には、前記補強部は、共通モールドされた前記絶縁性
樹脂部の両端に少なくとも１組形成されることを特徴と
する。Further, the method of manufacturing a circuit device according to the present invention is preferably characterized in that at least one set of the reinforcing portions is formed at both ends of the commonly molded insulating resin portion.

【００２２】更に、本発明の回路装置の製造方法は、好
適には、前記補強部は、前記導電箔表面に形成される前
記絶縁性樹脂よりも厚く形成されることを特徴とする。Furthermore, the method of manufacturing a circuit device according to the present invention is preferably characterized in that the reinforcing portion is formed thicker than the insulating resin formed on the surface of the conductive foil.

【００２３】更に、本発明の回路装置の製造方法は、好
適には、前記補強部は、前記絶縁性樹脂と同じ樹脂によ
り形成されることを特徴とする。Furthermore, the method of manufacturing a circuit device according to the present invention is preferably characterized in that the reinforcing portion is formed of the same resin as the insulating resin.

【００２４】また、本発明である回路装置の製造方法
は、導電箔を用意し、少なくとも回路素子の搭載部を多
数個形成する導電パターンを形成し、複数の前記搭載部
を１つの領域に集約して形成する集合ブロックを前記導
電箔上に複数形成する工程と、所望の前記導電パターン
の前記各搭載部に回路素子を固着する工程と、前記複数
の集合ブロック毎に各搭載部の前記回路素子を一括して
被覆し、分離溝に充填されるように絶縁性樹脂で共通モ
ールドすると同時に前記導電箔裏面に前記複数の集合ブ
ロック毎に反り防止のための補強部を形成する工程と、
前記複数の集合ブロック毎に前記補強部より内に位置す
る前記導電箔の裏面全域を前記絶縁性樹脂が露出するま
で除去する工程と、前記絶縁性樹脂を各搭載部毎にダイ
シングにより分離する際に前記補強部を除去する工程と
を具備することを特徴とする。In the method for manufacturing a circuit device according to the present invention, a conductive foil is prepared, a conductive pattern for forming a large number of mounting portions for at least circuit elements is formed, and the plurality of mounting portions are integrated into one area. Forming a plurality of aggregate blocks on the conductive foil, fixing a circuit element to each mounting portion of the desired conductive pattern, and the circuit of each mounting portion for each of the plurality of aggregate blocks. A step of covering the elements all together, forming a reinforcing part for preventing warpage on the back surface of the conductive foil at the same time as common molding with an insulating resin so as to fill the separation groove,
A step of removing the entire back surface of the conductive foil located inside the reinforcing portion for each of the plurality of aggregate blocks until the insulating resin is exposed; and a step of separating the insulating resin by dicing for each mounting portion. And a step of removing the reinforcing portion.

【００２５】[0025]

【発明の実施の形態】本発明の回路装置の製造方法につ
いて図１〜図１０を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a circuit device according to the present invention will be described with reference to FIGS.

【００２６】先ず、本発明の第１の工程は、図１から図
３に示す如く、導電箔３０を用意し、少なくとも回路素
子２２の搭載部を多数個形成する導電パターン２１を除
く領域の導電箔３０に導電箔３０の厚みよりも浅い分離
溝３１をエッチングにより形成して導電パターン２１を
形成することにある。First, in the first step of the present invention, as shown in FIGS. 1 to 3, the conductive foil 30 is prepared and at least the conductive pattern 21 for forming a large number of mounting portions of the circuit elements 22 is formed in the conductive area. This is to form the conductive pattern 21 by forming the separation groove 31 in the foil 30 that is shallower than the thickness of the conductive foil 30 by etching.

【００２７】本工程では、先ず図１（Ａ）に示す如く、
シート状の導電箔３０を用意する。この導電箔３０は、
ロウ材の付着性、ボンディング性、メッキ性が考慮され
てその材料が選択され、材料としては、Ｃｕを主材料と
した導電箔、Ａｌを主材料とした導電箔またはＦｅ−Ｎ
ｉ等の合金から成る導電箔等が採用される。In this step, first, as shown in FIG.
A sheet-shaped conductive foil 30 is prepared. This conductive foil 30 is
The material is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material, and the material is a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al or Fe-N.
A conductive foil made of an alloy such as i is adopted.

【００２８】導電箔３０の厚さは、後のエッチングを考
慮すると１０μｍ〜３００μｍ程度が好ましく、ここで
は７０μｍ（２オンス）の銅箔を採用した。しかし３０
０μｍ以上でも１０μｍ以下でも基本的には良い。後述
するように、導電箔３０の厚みよりも浅い分離溝３１が
形成できればよい。The thickness of the conductive foil 30 is preferably about 10 μm to 300 μm in consideration of the later etching, and here, 70 μm (2 ounces) of copper foil was used. But 30
Basically, it is 0 μm or more and 10 μm or less. As will be described later, it suffices if the separation groove 31 that is shallower than the thickness of the conductive foil 30 can be formed.

【００２９】尚、シート状の導電箔３０は、所定の幅、
例えば４５ｍｍでロール状に巻かれて用意され、これが
後述する各工程に搬送されても良いし、所定の大きさに
カットされた短冊状の導電箔３０が用意され、後述する
各工程に搬送されても良い。The sheet-shaped conductive foil 30 has a predetermined width,
For example, it may be prepared by being rolled into a roll of 45 mm and conveyed to each step described later, or a strip-shaped conductive foil 30 cut into a predetermined size may be prepared and conveyed to each step described below. May be.

【００３０】具体的には、図１（Ｂ）に示す如く、短冊
状の導電箔３０に多数の搭載部が形成されるブロック３
２が複数個（ここでは４〜５個）離間して並べられる。
各ブロック３２間にはスリット３３が設けられ、モール
ド工程等での加熱処理で発生する導電箔３０の応力を吸
収する。また導電箔３０の両側にはインデックス孔３４
が一定の間隔で設けられ、各工程での位置決めに用いら
れる。Specifically, as shown in FIG. 1B, a block 3 in which a large number of mounting portions are formed on a strip-shaped conductive foil 30.
A plurality of 2s (here, 4 to 5) are spaced apart and arranged.
Slits 33 are provided between the blocks 32 to absorb the stress of the conductive foil 30 generated by the heat treatment in the molding process or the like. In addition, index holes 34 are provided on both sides of the conductive foil 30.
Are provided at regular intervals and are used for positioning in each process.

【００３１】続いて、導電パターンを形成する。Subsequently, a conductive pattern is formed.

【００３２】先ず、図２に示す如く、Ｃｕ箔３０の上
に、ホトレジスト（耐エッチングマスク）ＰＲを形成
し、導電パターン２１となる領域を除いた導電箔３０が
露出するようにホトレジストＰＲをパターニングする。
そして、図３（Ａ）に示す如く、ホトレジストＰＲを介
して導電箔３０を選択的にエッチングする。First, as shown in FIG. 2, a photoresist (etching resistant mask) PR is formed on the Cu foil 30, and the photoresist PR is patterned so as to expose the conductive foil 30 excluding the region to be the conductive pattern 21. To do.
Then, as shown in FIG. 3A, the conductive foil 30 is selectively etched through the photoresist PR.

【００３３】本工程では、エッチングで形成される分離
溝３１の深さを均一に且つ高精度にするために、図３
（Ａ）に示す如く、分離溝３１の開口部を下に向けて、
導電箔３０の下方に設けたエッチング液の供給管５０か
ら上方に向けてエッチング液をシャワーリングする。こ
の結果、エッチング液の当たる分離溝３１の部分がエッ
チングされ、エッチング液は分離溝３１内に液溜まりを
作らず直ぐに排出されるので、分離溝３１の深さはエッ
チング処理時間で制御でき、均一で高精度の分離溝３１
を形成できる。なお、エッチング液は塩化第二鉄または
塩化第二銅が主に採用される。In this step, in order to make the depth of the separation groove 31 formed by etching uniform and highly accurate, FIG.
As shown in (A), with the opening of the separation groove 31 facing downward,
The etchant is showered upward from the etchant supply pipe 50 provided below the conductive foil 30. As a result, the portion of the separation groove 31 that is in contact with the etching liquid is etched, and the etching liquid is immediately discharged without forming a liquid pool in the separation groove 31. Highly accurate separation groove 31
Can be formed. Ferric chloride or cupric chloride is mainly used as the etching solution.

【００３４】図３（Ｂ）に具体的な導電パターン２１を
示す。本図は図１（Ｂ）で示したブロック３２の１個を
拡大したものである。点線で示す部分が１つの搭載部３
５であり、導電パターン２１を構成し、１つのブロック
３２には５行１０列のマトリックス状に多数の搭載部３
５が配列され、各搭載部３５毎に同一の導電パターン２
１が設けられている。各ブロック３２の周辺には、詳細
な説明は後述するが、２点鎖線で示した絶縁性樹脂２０
の反り防止のための補給部４０形成領域が設けられ、そ
の領域と少し離間しその内側にダイシング時の位置合わ
せマーク３７が設けられている。FIG. 3B shows a concrete conductive pattern 21. This figure is an enlargement of one of the blocks 32 shown in FIG. The mounting part 3 with one part indicated by the dotted line
5, a conductive pattern 21 is formed, and one block 32 has a large number of mounting portions 3 in a matrix of 5 rows and 10 columns.
5 are arranged, and the same conductive pattern 2 is provided for each mounting portion 35.
1 is provided. Although detailed description will be given later on the periphery of each block 32, the insulating resin 20 indicated by a two-dot chain line is shown.
An area for forming the replenishment portion 40 for preventing the warp of the wafer is provided, and an alignment mark 37 at the time of dicing is provided inside the area for a little distance from the area.

【００３５】次に、本発明の第２の工程は、図４および
図５に示す如く、所望の導電パターン２１の各搭載部３
５に回路素子２２を固着し、その後回路素子２２の電極
と所望の導電パターン２１とをワイヤボンディングする
ことにある。Next, in the second step of the present invention, as shown in FIGS. 4 and 5, each mounting portion 3 of the desired conductive pattern 21 is formed.
5, the circuit element 22 is fixed, and then the electrode of the circuit element 22 and the desired conductive pattern 21 are wire-bonded.

【００３６】図４に示す如く、回路素子２２としては、
トランジスタ、ダイオード、ＩＣチップ等の半導体素
子、チップコンデンサ、チップ抵抗等の受動素子であ
る。また厚みが厚くはなるが、ＣＳＰ、ＢＧＡ等のフェ
イスダウンの半導体素子も実装できる。As shown in FIG. 4, as the circuit element 22,
It is a semiconductor element such as a transistor, a diode or an IC chip, or a passive element such as a chip capacitor or a chip resistor. Although the thickness is increased, face-down semiconductor elements such as CSP and BGA can also be mounted.

【００３７】ここでは、ベアのトランジスタチップ２２
Ａが導電パターン２１Ａにダイボンディングされ、チッ
プコンデンサまたは受動素子２２Ｂは半田等のロウ材ま
たは導電ペースト２５Ｂで固着される。Here, the bare transistor chip 22 is used.
A is die-bonded to the conductive pattern 21A, and the chip capacitor or the passive element 22B is fixed with a brazing material such as solder or a conductive paste 25B.

【００３８】次に、クランパ（図示せず）によって導電
箔３０のブロック３２の周端を押さえ、導電箔３０をヒ
ートブロック（図示せず）に密着させる。その後、図５
に示す如く、エミッタ電極と導電パターン２１Ｂ、ベー
ス電極と導電パターン２１Ｂを、熱圧着によるボールボ
ンディング及び超音波によるウェッヂボンディングによ
り一括してワイヤボンディングを行う。このことによ
り、各搭載部毎にクランパを使用してワイヤボンディン
グを行っていた従来の回路装置の製造方法と比較して、
極めて効率的にワイヤボンディングを行うことができ
る。Next, the peripheral edge of the block 32 of the conductive foil 30 is pressed by a clamper (not shown) to bring the conductive foil 30 into close contact with a heat block (not shown). After that, FIG.
As shown in FIG. 3, wire bonding is performed on the emitter electrode and the conductive pattern 21B and the base electrode and the conductive pattern 21B all together by ball bonding by thermocompression bonding and wedge bonding by ultrasonic waves. As a result, in comparison with the conventional circuit device manufacturing method in which the clamper is used for each mounting portion to perform wire bonding,
Wire bonding can be performed very efficiently.

【００３９】次に、本発明の第３の工程は、図６および
図７に示す如く、各搭載部３５の回路素子２２を一括し
て被覆し、分離溝３１に充填されるように絶縁性樹脂２
０で共通モールドすることにある。そして、更に、この
工程の同時に、導電箔３０裏面に反り防止のための補強
部４０を形成することにある。Next, in the third step of the present invention, as shown in FIGS. 6 and 7, the circuit elements 22 of each mounting portion 35 are collectively covered, and the isolation groove 31 is filled with an insulating material. Resin 2
0 is for common molding. Further, at the same time of this step, the reinforcing portion 40 for preventing warpage is formed on the back surface of the conductive foil 30.

【００４０】本工程では、図６（Ａ）に示す如く、絶縁
性樹脂２０は回路素子２２Ａ、２２Ｂおよび複数の導電
パターン２１Ａ、２１Ｂ、２１Ｃを完全に被覆し、導電
パターン２１間の分離溝３１には絶縁性樹脂２０が充填
された導電パターン２１Ａ、２１Ｂ、２１Ｃの側面の湾
曲構造と嵌合して強固に結合する。そして絶縁性樹脂２
０により導電パターン２１が支持されている。In this step, as shown in FIG. 6A, the insulating resin 20 completely covers the circuit elements 22A and 22B and the plurality of conductive patterns 21A, 21B and 21C, and the isolation groove 31 between the conductive patterns 21 is formed. The conductive patterns 21A, 21B, and 21C filled with the insulating resin 20 are fitted to the curved structures on the side surfaces of the conductive patterns 21A, 21B, and 21C to be firmly bonded. And insulating resin 2
The conductive pattern 21 is supported by 0.

【００４１】また本工程では、トランスファーモールド
またはインジェクションモールドにより実現できる。樹
脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトラ
ンスファーモールドで実現でき、ポリイミド樹脂、ポリ
フェニレンサルファイド等の熱可塑性樹脂はインジェク
ションモールドで実現できる。Further, this step can be realized by transfer molding or injection molding. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be realized by injection molding.

【００４２】導電箔３０表面に被覆された絶縁性樹脂２
０の厚さは、回路素子２２のボンディングワイヤー２５
Ａの最頂部から約１００μｍ程度が被覆されるように調
整されている。この厚みは、強度を考慮して厚くするこ
とも、薄くすることも可能である。Insulating resin 2 coated on the surface of the conductive foil 30
The thickness of 0 is the bonding wire 25 of the circuit element 22.
It is adjusted so that about 100 μm from the top of A is covered. This thickness can be increased or decreased in consideration of strength.

【００４３】そして、本工程では、図６（Ｂ）に示す如
く、導電箔３０表面に集合ブロック３２毎に絶縁性樹脂
２０を形成する。その結果、導電箔３０表面には複数個
の絶縁性樹脂２０が形成される。一方、本発明の回路装
置の製造方法には、図６（Ｃ）に示す如く、導電箔３０
の裏面には導電箔３０表面の集合ブロック３２に対応し
て反り防止のための補強部４０を形成することである。
この反り防止のための補強部４０は、反り防止のための
補強部４０形成用の金型を用いてトランスファーモール
ドまたはインジェクションモールドにより絶縁性樹脂２
０を形成するときに同時に形成されるので、絶縁性樹脂
２０と同じ樹脂から成る。Then, in this step, as shown in FIG. 6B, the insulating resin 20 is formed on the surface of the conductive foil 30 for each assembly block 32. As a result, a plurality of insulating resins 20 are formed on the surface of the conductive foil 30. On the other hand, according to the method for manufacturing a circuit device of the present invention, as shown in FIG.
That is, the reinforcing portion 40 for preventing the warp is formed on the back surface of the corresponding to the assembly block 32 on the surface of the conductive foil 30.
The reinforcing portion 40 for preventing the warp is formed of the insulating resin 2 by transfer molding or injection molding using a mold for forming the reinforcing portion 40 for preventing the warp.
Since it is formed at the same time when 0 is formed, it is made of the same resin as the insulating resin 20.

【００４４】具体的には、図７（Ａ）の断面図である図
７（Ｂ）、（Ｃ）に示す如く、反り防止のための補強部
４０は、導電箔３０表面に形成される絶縁性樹脂２０の
外周部の裏面または外周部より外側の裏面に形成され
る。このとき、後工程でのアニーリング工程、回路素子
２２の特性の測定工程等における作業性を考慮して、反
り防止のための補強部４０は複数の搭載部３５が形成さ
れている集合ブロック３２から外周部または外周部より
外側に形成される。本実施の形態では、反り防止のため
の補強部４０は紙面に対して左右両端部に絶縁性樹脂２
０の１側辺よりも長く形成する。そして、反り防止のた
めの補強部４０の厚みは絶縁性樹脂２０の厚みよりも厚
く形成するが、例えば、１．５〜２．０倍程度の厚みに
形成する。Specifically, as shown in FIGS. 7 (B) and 7 (C) which are sectional views of FIG. 7 (A), the reinforcing portion 40 for preventing warpage is an insulating layer formed on the surface of the conductive foil 30. It is formed on the back surface of the outer peripheral portion of the functional resin 20 or on the back surface outside the outer peripheral portion. At this time, in consideration of workability in a subsequent annealing process, a process of measuring the characteristics of the circuit element 22, and the like, the reinforcing portion 40 for preventing warpage is formed from the assembly block 32 in which the plurality of mounting portions 35 are formed. It is formed on the outer peripheral portion or outside the outer peripheral portion. In the present embodiment, the reinforcing portion 40 for preventing the warp has the insulating resin 2 at both left and right ends with respect to the paper surface.
It is formed longer than the 1 side of 0. The reinforcing portion 40 for preventing warpage is formed thicker than the insulating resin 20. For example, the reinforcing portion 40 is formed to have a thickness of about 1.5 to 2.0 times.

【００４５】そして、反り防止のための補強部４０の作
用としては、導電箔３０と絶縁性樹脂２０との熱膨張係
数の違いや絶縁性樹脂２０硬化時の成型収縮率の違いに
より導電箔３０の反り上がりを防止することである。そ
のため、導電箔３０表面の集合ブロック３２の外周部ま
たは外周部より少し外側の裏面に反り防止のための補強
部４０を設けて導電箔３０の反り上がりに対抗する。よ
って、本実施の形態のように、導電箔３０裏面に導電箔
３０表面の集合ブロック３２に対して両端部に反り防止
のための補強部４０を設ける場合の他、導電箔３０表面
の集合ブロック３２に対して外周部全てに反り防止のた
めの補強部４０を設けると、更に、導電箔３０の反り上
がりに対抗することができる。その他、反り防止のため
の補強部４０の形成位置としては、導電箔３０の反り上
がりを防止できる位置であれば、作業性を考慮して種々
の変更が可能である。また、反り防止のための補強部４
０の長さに関しても、作業性を考慮して種々の変更が可
能である。The function of the reinforcing portion 40 for preventing the warpage is that the conductive foil 30 and the insulating resin 20 have different thermal expansion coefficients or the molding shrinkage rate when the insulating resin 20 is cured. Is to prevent the warp of. Therefore, the reinforcing portion 40 for preventing the warp is provided on the outer peripheral portion of the collective block 32 on the surface of the conductive foil 30 or on the back surface slightly outside the outer peripheral portion to counter the warp of the conductive foil 30. Therefore, as in the present embodiment, in addition to the case where the reinforcing portions 40 for preventing warpage are provided on both ends of the collective block 32 on the surface of the conductive foil 30 as in the present embodiment, the collective block on the surface of the conductive foil 30 is provided. When the reinforcing portion 40 for preventing the warp is provided on the entire outer peripheral portion with respect to 32, the warp of the conductive foil 30 can be further countered. In addition, as the position where the reinforcing portion 40 is formed for preventing the warp, various changes can be made in consideration of workability as long as it is a position where the warp of the conductive foil 30 can be prevented. In addition, the reinforcing portion 4 for preventing warpage
Regarding the length of 0, various changes can be made in consideration of workability.

【００４６】その他に、本工程の特徴は、絶縁性樹脂２
０を被覆するまでは、導電パターン２１となる導電箔３
０が支持基板となることであり、支持基板となる導電箔
３０は電極材料として必要な材料である。そのため、構
成材料を極力省いて作業できるメリットを有し、コスト
の低下も実現できる。In addition, the characteristic of this step is that the insulating resin 2 is used.
The conductive foil 3 becomes the conductive pattern 21 until 0 is covered.
0 is to be the support substrate, and the conductive foil 30 to be the support substrate is a material necessary as an electrode material. Therefore, there is a merit that the constituent materials can be omitted as much as possible, and the cost can be reduced.

【００４７】また分離溝３１は、導電箔の厚みよりも浅
く形成されているため、導電箔３０が導電パターン２１
として個々に分離されていない。従って、シート状の導
電箔３０として一体で取り扱え、絶縁性樹脂２０をモー
ルドする際、金型への搬送、金型への実装の作業が非常
に楽になる特徴を有する。Since the separation groove 31 is formed shallower than the thickness of the conductive foil, the conductive foil 30 is formed in the conductive pattern 21.
As not individually separated. Therefore, the sheet-shaped conductive foil 30 can be handled integrally, and when the insulating resin 20 is molded, it is very easy to carry it to the mold and to mount it on the mold.

【００４８】次に、本発明の第４の工程は、図示はして
いないが、アニーリングにより絶縁性樹脂２０の表面を
平坦化させることにある。Next, although not shown, the fourth step of the present invention is to flatten the surface of the insulating resin 20 by annealing.

【００４９】本工程では、絶縁性樹脂２０および反り防
止のための補強部４０が形成された後、絶縁性樹脂２０
を再加熱し、アニーリングすることで絶縁性樹脂２０表
面の平坦性を保持する。本発明の回路装置のように、絶
縁性樹脂２０が広い面積を有して形成される場合は、特
に、導電箔３０と絶縁性樹脂２０を形成するモールド樹
脂との熱膨張係数やリフロー後の温度低下時における成
型収縮率の違いにより導電箔３０に反りが発生してしま
う。その結果、絶縁性樹脂２０表面にも反りが発生して
しまう。この時、上述したように、絶縁性樹脂２０を再
加熱し、アニーリングすることで絶縁性樹脂２０表面の
平坦性を形成することはできる。In this step, after the insulating resin 20 and the reinforcing portion 40 for preventing warpage are formed, the insulating resin 20 is formed.
Is reheated and annealed to maintain the flatness of the surface of the insulating resin 20. When the insulating resin 20 is formed to have a large area as in the circuit device of the present invention, the coefficient of thermal expansion between the conductive foil 30 and the mold resin forming the insulating resin 20 or the reflowed resin is particularly preferable. The conductive foil 30 is warped due to the difference in molding shrinkage ratio when the temperature decreases. As a result, the surface of the insulating resin 20 is also warped. At this time, as described above, it is possible to form the flatness of the surface of the insulating resin 20 by reheating the insulating resin 20 and annealing.

【００５０】尚、本実施の形態では導電箔３０の場合に
ついて説明したが、基板がシリコンウエハー、セラミッ
ク基板、銅フレーム等の材料から成る場合も同様なこと
がいえる。Although the case of the conductive foil 30 has been described in the present embodiment, the same can be said when the substrate is made of a material such as a silicon wafer, a ceramic substrate, or a copper frame.

【００５１】しかし、本工程のように、導電箔３０の裏
面に個々の絶縁性樹脂２０のそれぞれに対応して反り防
止のための補強部４０を形成することで、再加熱後の温
度低下時における絶縁性樹脂２０の再収縮を緩和し、絶
縁性樹脂２０表面の平坦性を保持することができる。更
に、通常のアニーリング工程では再加熱すると同時に平
坦性を有するプレートにより絶縁性樹脂２０の表裏面を
プレスするが、本工程では、反り防止のための補強部４
０により再加熱のみで平坦性を保持することができると
いうメリットがある。その結果、後工程であるレジスト
塗布工程において均一にレジストを塗布でき、その後の
エッチングを均一に行うことができる。また、裏面電極
２６形成時の半田印刷工程の際均一に印刷を行うことが
でき、半田ボールの高さが統一され実装効率や信頼性が
向上した回路装置を実現することができる。更に、絶縁
性樹脂２０表面へのレーザ印刷工程等の絶縁性樹脂２０
表面の平坦性を必要とする工程の作業性も向上させるこ
とができる。However, as in the present step, by forming the reinforcing portion 40 for preventing warpage on the back surface of the conductive foil 30 corresponding to each insulating resin 20, when the temperature decreases after reheating. It is possible to alleviate the re-shrinkage of the insulating resin 20 and maintain the flatness of the surface of the insulating resin 20. Further, in the normal annealing process, the front and back surfaces of the insulating resin 20 are pressed by a plate having flatness while being reheated, but in this process, the reinforcing portion 4 for preventing warpage is used.
When 0, there is an advantage that flatness can be maintained only by reheating. As a result, the resist can be uniformly applied in the resist applying step, which is a post-step, and the subsequent etching can be uniformly performed. Further, it is possible to perform printing uniformly during the solder printing process when forming the back electrode 26, and it is possible to realize a circuit device in which the height of the solder balls is unified and the mounting efficiency and reliability are improved. Furthermore, the insulating resin 20 for the laser printing process or the like on the surface of the insulating resin 20
Workability of the process that requires surface flatness can also be improved.

【００５２】次に、本発明の第５の工程は、図８に示す
如く、分離溝３１を設けていない厚み部分の導電箔３０
を除去することにある。Next, in the fifth step of the present invention, as shown in FIG. 8, the conductive foil 30 in the thickness portion where the separation groove 31 is not provided.
To remove.

【００５３】本工程は、導電箔３０の裏面を化学的およ
び／または物理的に除き、導電パターン２１として分離
するものである。この工程は、研磨、研削、エッチン
グ、レーザの金属蒸発等により施される。In this step, the back surface of the conductive foil 30 is chemically and / or physically removed to form the conductive pattern 21. This step is performed by polishing, grinding, etching, laser metal evaporation, or the like.

【００５４】実験では研磨装置または研削装置により全
面を３０μｍ程度削り、分離溝３１から絶縁性樹脂２０
を露出させている。この露出される面を図６（Ａ）では
点線で示している。その結果、約４０μｍの厚さの導電
パターン２１となって分離される。また、絶縁性樹脂２
０が露出する手前まで、導電箔３０を全面ウェトエッチ
ングし、その後、研磨または研削装置により全面を削
り、絶縁性樹脂２０を露出させても良い。更に、導電箔
３０を点線で示す位置まで全面ウェトエッチングし、絶
縁性樹脂２０を露出させても良い。In the experiment, the entire surface was ground to about 30 μm by a polishing device or a grinding device, and the insulating resin 20 was removed from the separation groove 31.
Is exposed. This exposed surface is shown by a dotted line in FIG. As a result, the conductive patterns 21 having a thickness of about 40 μm are separated. Insulating resin 2
The entire surface of the conductive foil 30 may be wet-etched before 0 is exposed, and then the entire surface may be ground by a polishing or grinding device to expose the insulating resin 20. Further, the conductive foil 30 may be entirely wet-etched to the position shown by the dotted line to expose the insulating resin 20.

【００５５】この結果、絶縁性樹脂２０に導電パターン
２１の裏面が露出する構造となる。すなわち、分離溝３
１に充填された絶縁性樹脂２０の表面と導電パターン２
１の表面は、実質的に一致している構造となっている。
従って、本発明の回路装置２３は、マウント時に半田等
の表面張力でそのまま水平に移動してセルフアラインで
きる特徴を有する。As a result, the back surface of the conductive pattern 21 is exposed on the insulating resin 20. That is, the separation groove 3
1. Surface of insulating resin 20 filled in 1 and conductive pattern 2
The surface of No. 1 has a structure that is substantially matched.
Therefore, the circuit device 23 of the present invention has a feature that it can be horizontally moved as it is by the surface tension of solder or the like during mounting and self-aligned.

【００５６】更に、導電パターン２１の裏面処理を行
い、図８に示す最終構造を得る。すなわち、必要によっ
て露出した導電パターン２１に半田等の導電材を被着
し、回路装置として完成する。Further, the back surface of the conductive pattern 21 is processed to obtain the final structure shown in FIG. That is, a conductive material such as solder is attached to the exposed conductive pattern 21 as necessary, and the circuit device is completed.

【００５７】尚、本工程では、導電箔３０裏面側は反り
防止のための補強部４０により、個々の集合ブロック３
２毎に区切られているため、それぞれの領域において上
述した作業が行われる。In the present step, the back surface of the conductive foil 30 is provided with the reinforcing portion 40 for preventing warpage so that the individual collective blocks 3
Since it is divided into two, the above-mentioned work is performed in each area.

【００５８】次に、本発明の第６の工程は、図９に示す
如く、絶縁性樹脂２０で一括してモールドされた各搭載
部３５の回路素子２２の特性の測定を行うことにある。Next, as shown in FIG. 9, the sixth step of the present invention is to measure the characteristics of the circuit elements 22 of each mounting portion 35 which are collectively molded with the insulating resin 20.

【００５９】前工程で導電箔３０の裏面エッチングをし
た後に、導電箔３０から各ブロック３２が切り離され
る。このブロック３２は絶縁性樹脂２０で導電箔３０の
残余部と連結されているので、切断金型を用いず機械的
に導電箔３０の残余部から剥がすことで達成できる。After the back surface of the conductive foil 30 is etched in the previous step, the blocks 32 are separated from the conductive foil 30. Since the block 32 is connected to the remaining portion of the conductive foil 30 by the insulating resin 20, the block 32 can be mechanically peeled from the remaining portion of the conductive foil 30 without using a cutting die.

【００６０】各ブロック３２の裏面には図９に示す如
く、導電パターン２１の裏面が露出されており、各搭載
部３５が導電パターン２１形成時と全く同一にマトリッ
クス状に配列されている。この導電パターン２１の絶縁
性樹脂２０から露出した裏面電極２６にプローブ３８を
当てて、各搭載部３５の回路素子２２の特性パラメータ
等を個別に測定して良不良の判定を行い、不良品には磁
気インク等でマーキングを行う。As shown in FIG. 9, the back surface of each block 32 exposes the back surface of the conductive pattern 21, and the respective mounting portions 35 are arranged in a matrix exactly as when the conductive pattern 21 was formed. A probe 38 is applied to the back surface electrode 26 exposed from the insulating resin 20 of the conductive pattern 21, and the characteristic parameters and the like of the circuit element 22 of each mounting portion 35 are individually measured to determine whether they are good or bad, and to determine whether they are defective products. Mark with magnetic ink.

【００６１】本工程では、各搭載部３５の回路装置２３
は絶縁性樹脂２０でブロック３２毎に一体で支持されて
いるので、個別にバラバラに分離されていない。従っ
て、テスターの載置台に置かれたブロック３２は搭載部
３５のサイズ分だけ矢印のように縦方向および横方向に
ピッチ送りをすることで、極めて早く大量にブロック３
２の各搭載部３５の回路装置２３の測定を行える。すな
わち、従来必要であった回路装置の表裏の判別、電極の
位置の認識等が不要にできるので、測定時間の大幅な短
縮を図れる。In this step, the circuit device 23 of each mounting portion 35
Since the blocks are integrally supported by the insulating resin 20 for each block 32, they are not individually separated. Therefore, the blocks 32 placed on the mounting table of the tester are pitch-fed in the vertical and horizontal directions by the size of the mounting portion 35 as shown by the arrows, so that a large number of blocks 3 can be transferred quickly.
The circuit device 23 of each mounting part 35 of No. 2 can be measured. That is, since it is not necessary to distinguish between the front and the back of the circuit device and to recognize the position of the electrode, which are conventionally required, the measurement time can be significantly shortened.

【００６２】尚、本工程では、導電箔３０裏面側は反り
防止のための補強部４０により、個々の集合ブロック３
２毎に区切られているため、それぞれの領域において上
述した作業が行われる。そして、上述したように、反り
防止のための補強部４０は導電箔３０表面の集合ブロッ
ク３２の外周部または外周部より少し外側に形成される
ので、上述の測定工程の邪魔になることはない。In this step, the back surface of the conductive foil 30 is provided with the reinforcing portion 40 for preventing the warp, so that the individual collecting blocks 3
Since it is divided into two, the above-mentioned work is performed in each area. Further, as described above, since the reinforcing portion 40 for preventing warpage is formed on the outer peripheral portion of the assembly block 32 on the surface of the conductive foil 30 or slightly outside the outer peripheral portion, it does not interfere with the above-described measurement process. .

【００６３】次に、本発明の第７の工程は、図１０に示
す如く、絶縁性樹脂２０を各搭載部３５毎にダイシング
により分離することにある。Next, the seventh step of the present invention is to separate the insulating resin 20 for each mounting portion 35 by dicing, as shown in FIG.

【００６４】本工程では、ブロック３２をダイシング装
置の載置台に真空で吸着させ、ダイシングブレード４２
で各搭載部３５間のダイシングライン４１に沿って分離
溝３１の絶縁性樹脂２０をダイシングし、個別の回路装
置２３に分離する。In this step, the block 32 is vacuum-sucked to the mounting table of the dicing machine, and the dicing blade 42
Then, the insulating resin 20 in the separation groove 31 is diced along the dicing line 41 between the mounting portions 35 to separate the individual circuit devices 23.

【００６５】本工程で、ダイシングブレード４２はほぼ
絶縁性樹脂２０を切断する切削深さで行い、ダイシング
装置からブロック３２を取り出した後にローラでチョコ
レートブレークするとよい。ダイシング時は予め前述し
た第１の工程で設けた各ブロックの周辺の枠状のパター
ン３６の内側の相対向する位置合わせマーク３７を認識
して、これを基準としてダイシングを行う。周知ではあ
るが、ダイシングは縦方向にすべてのダイシングライン
４１をダイシングをした後、載置台を９０度回転させて
横方向のダイシングライン４１に従ってダイシングを行
う。In this step, the dicing blade 42 is preferably cut to a depth to cut the insulating resin 20, and after taking out the block 32 from the dicing device, chocolate breaking may be performed with a roller. At the time of dicing, the alignment marks 37 facing each other inside the frame-shaped pattern 36 around each block provided in the above-described first step are recognized in advance, and dicing is performed using this as a reference. As is well known, in dicing, after dicing all the dicing lines 41 in the vertical direction, the mounting table is rotated by 90 degrees to perform dicing in accordance with the horizontal dicing lines 41.

【００６６】そして、本工程において、反り防止のため
の補強部４０も同時に除去され、上記した製造工程によ
り、回路装置２３は完成する。Then, in this process, the reinforcing portion 40 for preventing the warp is also removed at the same time, and the circuit device 23 is completed by the above-described manufacturing process.

【００６７】尚、本発明の回路装置の製造方法では、導
電箔上に集合ブロックを形成した場合について説明した
が、特に、この場合に限定する必要はなく、リードフレ
ーム等のように導電部材から成る基板に対しも同様な効
果を得ることができる。また、上述では回路装置の製造
方法について説明したが、半導体装置の製造方法につい
ても同様なことをいうことができる。その他、本発明の
要旨を逸脱しない範囲で、種々の変更が可能である。In the method for manufacturing a circuit device according to the present invention, the case where the collective block is formed on the conductive foil has been described, but the invention is not particularly limited to this case, and a conductive member such as a lead frame is used. Similar effects can be obtained with the substrate. Further, although the method for manufacturing the circuit device has been described above, the same can be said for the method for manufacturing the semiconductor device. Besides, various modifications can be made without departing from the scope of the present invention.

【００６８】[0068]

【発明の効果】本発明の回路装置の製造方法では、導電
箔表面に集合ブロック毎に形成される絶縁性樹脂に対応
して、導電箔裏面に反り防止のための補強部を集合ブロ
ック毎に形成することに特徴がある。そのことにより、
絶縁性樹脂を形成する工程、絶縁性樹脂を再加熱しアニ
ーリングする工程時に絶縁性樹脂表面の平坦性をより保
持することができる。その結果、後工程である裏面電極
形成のためのレジスト印刷工程や半田印刷工程、または
絶縁性樹脂表面へのレーザ印刷工程、ダイシング工程等
の絶縁性樹脂表面の平坦性を必要とする工程の作業性を
向上させることができる。According to the method of manufacturing a circuit device of the present invention, a reinforcing portion for preventing warpage is provided on the back surface of the conductive foil for each assembly block in correspondence with the insulating resin formed on the surface of the conductive foil for each assembly block. It is characterized by forming. By that,
It is possible to further maintain the flatness of the surface of the insulating resin during the step of forming the insulating resin and the step of reheating and annealing the insulating resin. As a result, the work of the resist printing process or the solder printing process for forming the back surface electrode which is a post process, the laser printing process on the insulating resin surface, the process requiring the flatness of the insulating resin surface such as the dicing process. It is possible to improve the sex.

【００６９】更に、本発明の回路装置の製造方法では、
導電箔表面に集合ブロック毎に形成される絶縁性樹脂に
対応して、導電箔裏面に反り防止のための補強部を集合
ブロック毎に形成することに特徴がある。そのことによ
り、通常のアニーリング工程では再加熱すると同時に平
坦性を有するプレートにより絶縁性樹脂の表裏面をプレ
スするが、本工程では、反り防止のための補強部により
再加熱のみで平坦性を保持することができる。Furthermore, in the method of manufacturing the circuit device of the present invention,
It is characterized in that a reinforcing portion for preventing warpage is formed on each back face of the conductive foil in correspondence with the insulating resin formed on the front face of the conductive foil for each gathering block. As a result, the normal annealing process reheats and at the same time presses the front and back surfaces of the insulating resin with a plate having flatness, but in this process, the flatness is maintained only by reheating by the reinforcing portion for warpage prevention can do.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の回路装置の製造方法を説明する図であ
る。FIG. 1 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

【図２】本発明の回路装置の製造方法を説明する図であ
る。FIG. 2 is a diagram illustrating a method of manufacturing a circuit device according to the present invention.

【図３】本発明の回路装置の製造方法を説明する図であ
る。FIG. 3 is a diagram illustrating a method of manufacturing a circuit device according to the present invention.

【図４】本発明の回路装置の製造方法を説明する図であ
る。FIG. 4 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

【図５】本発明の回路装置の製造方法を説明する図であ
る。FIG. 5 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

【図６】本発明の回路装置の製造方法を説明する図であ
る。FIG. 6 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

【図７】本発明の回路装置の製造方法を説明する図であ
る。FIG. 7 is a diagram illustrating a method of manufacturing a circuit device according to the present invention.

【図８】本発明の回路装置の製造方法を説明する図であ
る。FIG. 8 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

【図９】本発明の回路装置の製造方法を説明する図であ
る。FIG. 9 is a diagram illustrating a method for manufacturing a circuit device according to the present invention.

【図１０】本発明の回路装置の製造方法を説明する図で
ある。FIG. 10 is a drawing for explaining the manufacturing method of the circuit device of the present invention.

【図１１】従来の半導体装置の製造方法を説明する図で
ある。FIG. 11 is a diagram illustrating a conventional method for manufacturing a semiconductor device.

【図１２】従来の半導体装置の製造方法を説明する図で
ある。FIG. 12 is a diagram illustrating a conventional method for manufacturing a semiconductor device.

【図１３】従来の半導体装置の製造方法を説明する図で
ある。FIG. 13 is a diagram illustrating a conventional method for manufacturing a semiconductor device.

【図１４】従来の半導体装置の製造方法を説明する図で
ある。FIG. 14 is a diagram illustrating a conventional method for manufacturing a semiconductor device.

【図１５】従来の半導体装置の製造方法を説明する図で
ある。FIG. 15 is a diagram illustrating a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

２０ 絶縁性樹脂 ２１ 導電パターン ２２ 回路素子 ３２ ブロック ４０ 反り防止のための補強部 ４１ ダイシングライン 20 Insulating resin 21 Conductive pattern 22 circuit elements 32 blocks 40 Reinforcement part to prevent warping 41 dicing line

フロントページの続き (72)発明者 関 幸治 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 (72)発明者 高田 秀夫 群馬県伊勢崎市喜多町29番地 関東三洋電 子株式会社内 Ｆターム(参考） 5F061 AA01 BA07 CA21 CB13 FA02Continued front page    (72) Inventor Koji Seki             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Hideo Takada             29 Kita-cho, Isesaki-shi, Gunma Kanto Sanyoden             Child Co., Ltd. F-term (reference) 5F061 AA01 BA07 CA21 CB13 FA02

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 導電箔を用意し、少なくとも回路素子の
搭載部を多数個形成する導電パターンを形成する工程
と、 所望の前記導電パターンの前記各搭載部に回路素子を固
着する工程と、 各搭載部の前記回路素子を一括して被覆し、分離溝に充
填されるように絶縁性樹脂で共通モールドすると同時に
前記導電箔裏面に反り防止のための補強部を形成する工
程とを具備することを特徴とする回路装置の製造方法。1. A step of preparing a conductive foil and forming a conductive pattern for forming at least a large number of circuit element mounting portions, and a step of fixing circuit elements to the mounting portions of the desired conductive pattern, A step of collectively covering the circuit elements of the mounting portion, performing common molding with an insulating resin so as to fill the separation groove, and at the same time forming a reinforcing portion for preventing warpage on the back surface of the conductive foil. And a method for manufacturing a circuit device. 【請求項２】 前記補強部は、共通モールドされた前記
絶縁性樹脂部の周端に形成されることを特徴とする請求
項１記載の回路装置の製造方法。2. The method for manufacturing a circuit device according to claim 1, wherein the reinforcing portion is formed at a peripheral end of the commonly molded insulating resin portion. 【請求項３】 前記補強部は、共通モールドされた前記
絶縁性樹脂部の両端に少なくとも１組形成されることを
特徴とする請求項１記載の回路装置の製造方法。3. The method for manufacturing a circuit device according to claim 1, wherein at least one set of the reinforcing portion is formed at both ends of the commonly molded insulating resin portion. 【請求項４】 前記補強部は、前記導電箔表面に形成さ
れる前記絶縁性樹脂よりも厚く形成されることを特徴と
する請求項１記載の回路装置の製造方法。4. The method for manufacturing a circuit device according to claim 1, wherein the reinforcing portion is formed thicker than the insulating resin formed on the surface of the conductive foil. 【請求項５】 前記補強部は、前記絶縁性樹脂と同じ樹
脂により形成されることを特徴とする請求項１から請求
項４のいずれかに記載の回路装置の製造方法。5. The method for manufacturing a circuit device according to claim 1, wherein the reinforcing portion is formed of the same resin as the insulating resin. 【請求項６】 導電箔を用意し、少なくとも回路素子の
搭載部を多数個形成する導電パターンを形成し、複数の
前記搭載部を１つの領域に集約して形成する集合ブロッ
クを前記導電箔上に複数形成する工程と、 所望の前記導電パターンの前記各搭載部に回路素子を固
着する工程と、 前記複数の集合ブロック毎に各搭載部の前記回路素子を
一括して被覆し、分離溝に充填されるように絶縁性樹脂
で共通モールドすると同時に前記導電箔裏面に前記複数
の集合ブロック毎に反り防止のための補強部を形成する
工程と、 前記複数の集合ブロック毎に前記補強部より内に位置す
る前記導電箔の裏面全域を前記絶縁性樹脂が露出するま
で除去する工程と、 前記絶縁性樹脂を各搭載部毎にダイシングにより分離す
る際に前記補強部を除去する工程とを具備することを特
徴とする回路装置の製造方法。6. A conductive foil is prepared, a conductive pattern for forming at least a large number of mounting portions for circuit elements is formed, and a collective block formed by consolidating the plurality of mounting portions into one region is formed on the conductive foil. And a step of fixing a circuit element to each mounting portion of the desired conductive pattern, and collectively covering the circuit element of each mounting portion for each of the plurality of assembly blocks to form a separation groove. Forming a reinforcing part for preventing warpage on the back surface of the conductive foil for each of the plurality of aggregate blocks at the same time as performing common molding with an insulating resin so as to be filled; A step of removing the entire back surface of the conductive foil located in the area until the insulating resin is exposed, and a step of removing the reinforcing portion when the insulating resin is separated by dicing for each mounting portion. Method of manufacturing a circuit device which is characterized in that. 【請求項７】 前記補強部は、共通モールドされた前記
絶縁性樹脂の周端に形成されることを特徴とする請求項
６記載の回路装置の製造方法。7. The method of manufacturing a circuit device according to claim 6, wherein the reinforcing portion is formed at a peripheral edge of the commonly molded insulating resin. 【請求項８】 前記補強部は、共通モールドされた前記
絶縁性樹脂の両端に１組形成されることを特徴とする請
求項６記載の回路装置の製造方法。8. The method of manufacturing a circuit device according to claim 6, wherein one set of the reinforcing portions is formed at both ends of the commonly molded insulating resin. 【請求項９】 前記補強部は、前記導電箔表面に形成さ
れる前記絶縁性樹脂よりも厚く形成されることを特徴と
する請求項６記載の回路装置の製造方法。9. The method of manufacturing a circuit device according to claim 6, wherein the reinforcing portion is formed thicker than the insulating resin formed on the surface of the conductive foil. 【請求項１０】 前記補強部は、前記絶縁性樹脂と同じ
樹脂により形成されることを特徴とする請求項６から請
求項９のいずれかに記載の回路装置の製造方法。10. The method for manufacturing a circuit device according to claim 6, wherein the reinforcing portion is formed of the same resin as the insulating resin.
JP2001225464A 2001-07-26 2001-07-26 Method for manufacturing circuit device Pending JP2003037125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001225464A JP2003037125A (en) 2001-07-26 2001-07-26 Method for manufacturing circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001225464A JP2003037125A (en) 2001-07-26 2001-07-26 Method for manufacturing circuit device

Publications (1)

Publication Number Publication Date
JP2003037125A true JP2003037125A (en) 2003-02-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100736633B1 (en) 2005-12-19 2007-07-06 삼성전기주식회사 Reinforcement substrate and manufacturing method
JP2007266544A (en) * 2006-03-30 2007-10-11 Koa Corp Composite electronic component manufacturing method, and composite electronic component
JP2010153466A (en) * 2008-12-24 2010-07-08 Elpida Memory Inc Wiring board
CN101944489A (en) * 2009-07-07 2011-01-12 株式会社村田制作所 The manufacture method of composite base plate
JP2014024136A (en) * 2012-07-25 2014-02-06 Disco Abrasive Syst Ltd Method of processing package substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100736633B1 (en) 2005-12-19 2007-07-06 삼성전기주식회사 Reinforcement substrate and manufacturing method
JP2007266544A (en) * 2006-03-30 2007-10-11 Koa Corp Composite electronic component manufacturing method, and composite electronic component
JP2010153466A (en) * 2008-12-24 2010-07-08 Elpida Memory Inc Wiring board
US8351217B2 (en) 2008-12-24 2013-01-08 Elpida Memory, Inc. Wiring board
CN101944489A (en) * 2009-07-07 2011-01-12 株式会社村田制作所 The manufacture method of composite base plate
JP2014024136A (en) * 2012-07-25 2014-02-06 Disco Abrasive Syst Ltd Method of processing package substrate

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