JP2003007897A - Substrate for semiconductor device - Google Patents
Substrate for semiconductor deviceInfo
- Publication number
- JP2003007897A JP2003007897A JP2001194476A JP2001194476A JP2003007897A JP 2003007897 A JP2003007897 A JP 2003007897A JP 2001194476 A JP2001194476 A JP 2001194476A JP 2001194476 A JP2001194476 A JP 2001194476A JP 2003007897 A JP2003007897 A JP 2003007897A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- layer
- hole
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、支持基板の両側の
配線層を高密度で接続可能な半導体装置用基板に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device substrate capable of connecting wiring layers on both sides of a supporting substrate at a high density.
【０００２】[0002]
【従来の技術】近年、電子手帳や携帯電話等に代表され
るように、電子機器は、小型化、携帯化の傾向にある。
これに伴い、ＬＳＩ等を搭載するためのプリント配線板
のような半導体装置用基板も、例えば特開平７−１６２
１５４号公報に示されるように、より一層の高密度化が
図られている。2. Description of the Related Art In recent years, electronic devices such as electronic notebooks and mobile phones have tended to be smaller and more portable.
Along with this, a semiconductor device substrate such as a printed wiring board for mounting an LSI or the like is also disclosed in, for example, Japanese Patent Laid-Open No. 7-162.
As disclosed in Japanese Patent No. 154, further densification is attempted.
【０００３】図２は係る半導体装置用基板の断面図を模
式的に示す図である。 例えば、両面に銅箔１が貼着さ
れて内部にガラスクロス（ガラスエポキシ部）２を含ん
だ支持基板３にφ０．３ｍｍのドリルを用いて孔４があ
けられ、孔４内にめっきが施されて貫通スルーホールが
形成される。なお、ドリルは、φ０．３ｍｍ径に限ら
ず、φ０．２５からφ０．３５ｍｍ程度の径のものが適
宜使用される。FIG. 2 is a diagram schematically showing a cross-sectional view of such a semiconductor device substrate. For example, a hole 4 is formed in a supporting substrate 3 having a copper cloth 1 adhered on both sides and a glass cloth (glass epoxy portion) 2 inside by using a φ0.3 mm drill, and the hole 4 is plated. Then, a through through hole is formed. The diameter of the drill is not limited to φ0.3 mm, and a diameter of φ0.25 to φ0.35 mm is appropriately used.
【０００４】続いて、支持基板３の両面がエッチングさ
れ、銅箔１が所定の配線パターンをもつ下側配線層１に
形成される。また、下側配線層１は、その上層に形成さ
れる絶縁層との密着力を向上させるための黒化処理が施
される。Then, both surfaces of the support substrate 3 are etched to form the copper foil 1 on the lower wiring layer 1 having a predetermined wiring pattern. Further, the lower wiring layer 1 is subjected to a blackening treatment for improving the adhesion with the insulating layer formed on the lower wiring layer 1.
【０００５】次に、支持基板３の両面全体に絶縁層５が
形成される。この絶縁層５は、例えば露光、現像によ
り、下側配線層との電気的なコンタクトをとるためのバ
イアホール６が形成される。また、無電解めっき、電解
めっきにより銅層が形成され、銅層がレジスト塗布、露
光、現像、エッチングにより選択的に除去されて所定の
配線パターンをもつ上側配線層７が形成される。Next, the insulating layers 5 are formed on the entire surfaces of the support substrate 3. A via hole 6 for making electrical contact with the lower wiring layer is formed in the insulating layer 5 by, for example, exposure and development. Further, a copper layer is formed by electroless plating and electrolytic plating, and the copper layer is selectively removed by resist coating, exposure, development and etching to form an upper wiring layer 7 having a predetermined wiring pattern.
【０００６】続いて、支持基板３の両面全体にソルダレ
ジスト８が形成され、半導体装置用基板が完成する。Then, the solder resist 8 is formed on both surfaces of the supporting substrate 3 to complete the semiconductor device substrate.
【０００７】また、通常のプリント配線板であっても、
多層配線板では、貫通スルーホールが形成される。但
し、多層配線板の場合、例えば、内層に配線パターンの
形成された材料と外層になる材料とが互いに接着剤で加
熱、加圧されて多層化される工程を経ている。また、貫
通スルーホールの形成後、両面にソルダレジスト層が形
成される。Further, even in the case of a normal printed wiring board,
Through holes are formed in the multilayer wiring board. However, in the case of a multilayer wiring board, for example, a material having a wiring pattern formed in an inner layer and a material forming an outer layer are heated and pressed with an adhesive to form a multilayer. Also, after forming the through-holes, solder resist layers are formed on both surfaces.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、以上の
ような半導体装置用基板は、支持基板３にドリルで貫通
スルーホール４を形成する工程に起因し、次の（１）か
ら（４）に示すような問題がある。However, the above-described semiconductor device substrate is shown in the following (1) to (4) due to the step of forming the through through hole 4 in the support substrate 3 with a drill. There is such a problem.
【０００９】（１）半導体装置用基板は、製造コストに
占める小径ドリルの孔あけ加工に要する小径ドリル代の
割合は非常に大きいため、ドリルの使用に応じてコスト
を上昇させる問題がある。(1) Since the semiconductor device substrate has a very large share of the manufacturing cost in the drilling process of the small-diameter drill, the cost of the small-diameter drill increases according to the use of the drill.
【００１０】（２）また、通常、ドリル加工は、φ０．
１ｍｍやそれ以下の径のドリル加工を安定して行なうの
は困難であり、φ０．１５ｍｍがドリル径の最小限界で
ある問題がある。さらに、径が小さくなる程、コストを
指数関数的に上昇させる問題がある。(2) Further, normally, the drilling process is φ0.
It is difficult to stably perform drilling with a diameter of 1 mm or less, and there is a problem that φ0.15 mm is the minimum limit of the drill diameter. Further, there is a problem that the cost increases exponentially as the diameter becomes smaller.
【００１１】（３）また、支持基板３にガラスクロス２
が含まれるため、貫通スルーホール４間でマイグレーシ
ョンが発生し易く、これによっても、現状のスルーホー
ル間隙（０．５ｍｍから１ｍｍ程度）を狭めることがで
きない。すなわち、ドリル加工のストレスや材料に起因
したマイグレーションによって、貫通スルーホール４の
ピッチの狭小化に限界がある問題がある。(3) Further, the glass cloth 2 is formed on the supporting substrate 3.
Therefore, migration is likely to occur between the through-holes 4, which also cannot narrow the current through-hole gap (about 0.5 mm to 1 mm). That is, there is a problem that there is a limit to the narrowing of the pitch of the through-holes 4 due to the stress of drilling and the migration caused by the material.
【００１２】（４）小径ドリルの孔位置の精度が低いた
め、ランド切れの発生を阻止するには、ドリル径に１０
０μｍ〜２００μｍ以上の余裕分を加えた径をもつ大き
なランドを形成する必要がある。このため、小径化、狭
ピッチ化の限界を考慮すると、例えばφ０．３ｍｍのス
ルーホール を囲むφ０．６ｍｍのランド が０．８ｍｍ
ピッチ （及び０．２ｍｍ間隙 ）で格子状に形成される
というパターンの最小限界が決まってしまう。すなわ
ち、係る最小限界を越えてはパターン自体の高密度化を
図れない問題がある。(4) Since the precision of the hole position of the small diameter drill is low, the diameter of the drill should be 10 in order to prevent the land breakage.
It is necessary to form a large land having a diameter including a margin of 0 μm to 200 μm or more. Therefore, considering the limits of diameter reduction and pitch reduction, for example, a φ0.6 mm land surrounding a φ0.3 mm through hole is 0.8 mm.
The minimum limit of the pattern formed in a grid pattern with a pitch (and a gap of 0.2 mm) is determined. That is, there is a problem that the density of the pattern itself cannot be increased beyond the minimum limit.
【００１３】本発明は上記の問題点を考慮してなされた
もので、低コスト化と高密度化を同時に実現し得る半導
体装置用基板を提供することを課題とする。The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a substrate for a semiconductor device which can simultaneously realize low cost and high density.
【００１４】[0014]
【課題を解決するための手段】本発明の骨子は、表裏の
導通を図るための貫通スルーホールを形成するドリル孔
が小径で且つ多数あるため、高いドリル代を要すると共
に、これ以上の小径化が困難であることが考慮されてい
る。すなわち、本発明は、コア部よりガラスクロスを無
くし、強度を保つために外周部に額縁状に補強材を入
れ、貫通孔をレーザにて容易に形成可能にすることで、
基板の高密度化とコストの低減を図るものである。The skeleton of the present invention has a large number of drill holes that form through-holes for achieving conduction between the front and back, and therefore requires a high drill allowance and further reduces the diameter. Is considered difficult. That is, the present invention eliminates the glass cloth from the core portion, puts a reinforcing material in a frame shape in the outer peripheral portion in order to maintain strength, and makes it possible to easily form the through hole by laser.
It is intended to increase the density of the substrate and reduce the cost.
【００１５】以上のような本発明の骨子に基づいて具体
的には以下のような手段が講じられる。請求項１に対応
する発明は、額縁状支持基板の表裏および内側に絶縁層
が形成され、絶縁層上に配線層を備えるとともに、額縁
状支持基板の内側の領域に貫通スルーホールを備えるこ
とを特徴とする半導体装置用基板である。Based on the essence of the present invention as described above, the following means are specifically taken. The invention corresponding to claim 1 is characterized in that an insulating layer is formed on the front and back sides and inside of the frame-shaped support substrate, a wiring layer is provided on the insulating layer, and a through-hole is provided in an area inside the frame-shaped support substrate. A characteristic semiconductor device substrate.
【００１６】額縁状支持基板を覆う絶縁樹脂およびビル
ドアップ層をなす絶縁樹脂は、従来同様に、エポキシ
系、ポリイミド系又はアクリル系等の材料が適宜使用さ
れ、また、感光性を有する材料でも使用可能である。ま
た絶縁樹脂は額縁状支持基板を覆うとき、表裏に異なる
材料、例えばエポキシ系とポリイミド系を用いることも
可能である。ただし、ビルドアップ層の絶縁層の形成に
用いる絶縁樹脂は単一種類の材料を用いる方が、熱膨張
係数の違いに起因する樹脂剥離防止の観点から好まし
い。また、ソルダレジスト材料も絶縁樹脂と同一材料を
用いることが、熱膨張係数の違いに起因する樹脂剥離防
止の観点から好ましい。As the insulating resin covering the frame-shaped supporting substrate and the insulating resin forming the build-up layer, epoxy-based, polyimide-based or acrylic-based materials are appropriately used as in the prior art, and also photosensitive materials are used. It is possible. Further, when the insulating resin covers the frame-shaped support substrate, it is possible to use different materials on the front and back sides, for example, epoxy type and polyimide type. However, it is preferable to use a single type of insulating resin for forming the insulating layer of the build-up layer, from the viewpoint of preventing resin peeling due to the difference in thermal expansion coefficient. Further, it is preferable to use the same material as the insulating resin as the solder resist material from the viewpoint of preventing resin peeling due to the difference in thermal expansion coefficient.
【００１７】また、請求項２に対応する発明は、請求項
１に記載半導体装置用基板の両面に、絶縁層及び配線層
を備え、配線層間の導通のためのバイヤホールを有する
ことを特徴とする半導体装置用基板である。The invention according to claim 2 is characterized in that an insulating layer and a wiring layer are provided on both surfaces of the substrate for a semiconductor device according to claim 1, and that a via hole for conducting between the wiring layers is provided. It is a substrate for a semiconductor device.
【００１８】額縁状の支持基板としては、例えば、ガラ
スクロスに対してエポキシ樹脂、ポリイミド樹脂又はア
クリル樹脂等を含浸させた基板のように、剛性をもつも
のが製造の容易性の観点から好ましい。銅やステンレス
のような金属を用いる場合もある。この支持基板には配
線を形成してもよいが、製造を容易にするために、剛性
を付与する目的だけでもよい。As the frame-shaped supporting substrate, one having rigidity such as a substrate obtained by impregnating glass cloth with epoxy resin, polyimide resin, acrylic resin or the like is preferable from the viewpoint of ease of production. A metal such as copper or stainless steel may be used. Wiring may be formed on this support substrate, but it may be only for the purpose of imparting rigidity in order to facilitate manufacturing.
【００１９】額縁状支持基板を覆う絶縁樹脂およびビル
ドアップ層をなす絶縁樹脂は、従来同様に、エポキシ
系、ポリイミド系又はアクリル系等の材料が適宜使用さ
れ、また、感光性を有する材料でも使用可能である。ま
た絶縁樹脂は額縁状支持基板を覆うとき、表裏に異なる
材料、例えばエポキシ系とポリイミド系を用いることも
可能である。ただし、ビルドアップ層の絶縁層の形成に
用いる絶縁樹脂は単一種類の材料を用いる方が、熱膨張
係数の違いに起因する樹脂剥離防止の観点から好まし
い。また、ビルドアップ層を形成する絶縁材料およびソ
ルダレジスト材料も、絶縁樹脂と同一材料を用いること
が、熱膨張係数の違いに起因する樹脂剥離防止の観点か
ら好ましい。なお、この半導体装置用基板は、ビルドア
ップ基板に限定されず、一般のプリント配線板にも適用
させることができる。As the insulating resin covering the frame-shaped supporting substrate and the insulating resin forming the build-up layer, an epoxy-based, polyimide-based or acrylic-based material is appropriately used as in the conventional case, and a photosensitive material is also used. It is possible. Further, when the insulating resin covers the frame-shaped support substrate, it is possible to use different materials on the front and back sides, for example, epoxy type and polyimide type. However, it is preferable to use a single type of insulating resin for forming the insulating layer of the build-up layer, from the viewpoint of preventing resin peeling due to the difference in thermal expansion coefficient. Also, it is preferable to use the same material as the insulating resin for the insulating material and the solder resist material forming the build-up layer, from the viewpoint of preventing resin peeling due to the difference in thermal expansion coefficient. The substrate for semiconductor device is not limited to the build-up substrate and can be applied to a general printed wiring board.
【００２０】[0020]
【発明の実施の形態】以下、本発明の各実施形態につい
て図面を参照しながら説明する。
＜第１の実施形態＞図１は本発明の第１の実施形態に係
る半導体装置用基板の構成を示す断面図である。この半
導体装置用基板は、額縁状のガラスエポキシ部からなる
支持基板２１の表裏および内側に絶縁層２２を有し、絶
縁層の表裏に配線層２４を設け、配線層間の絶縁層部に
表裏の導通をとるための貫通スルーホール２３が設けら
れている。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a sectional view showing the structure of a semiconductor device substrate according to the first embodiment of the present invention. This semiconductor device substrate has an insulating layer 22 on the front and back sides and inside of a supporting substrate 21 made of a frame-shaped glass epoxy part, a wiring layer 24 is provided on the front and back sides of the insulating layer, and front and back sides of the insulating layer portion between the wiring layers Through-holes 23 are provided for electrical continuity.
【００２１】本実施形態例の半導体装置用基板の製造方
法を述べる。まず、支持基板２１として、ガラスエポキ
シ部の両面に銅層が貼着された０．４ｍｍ厚の銅張積層
板（ＣＣＬ−ＥＬ１７０；三菱ガス化学製）を用意す
る。銅層は無くとも良い。次に、絶縁樹脂２２として、
ドライフィルム化した樹脂インキ（太陽インキ；ＰＳＲ
−４０００）を使用し、額縁状支持基板の表裏にドライ
フィルム化した樹脂インキを仮張りし、真空ラミネータ
ーにて加熱・加圧して成膜する。このとき、ドライフィ
ルムを用いず、液状の樹脂インクを用いてもよい。絶縁
樹脂を成膜後、べとつきがなくなるまで加熱乾燥を行
う。A method of manufacturing the semiconductor device substrate of this embodiment will be described. First, as the support substrate 21, a 0.4 mm-thick copper clad laminate (CCL-EL170; manufactured by Mitsubishi Gas Chemical Co., Ltd.) having copper layers attached to both surfaces of the glass epoxy part is prepared. No copper layer is required. Next, as the insulating resin 22,
Dry film resin ink (Taiyo Ink; PSR
-4000) is used to temporarily apply a dry film resin ink to the front and back of the frame-shaped support substrate, and heat and pressurize with a vacuum laminator to form a film. At this time, liquid resin ink may be used instead of the dry film. After the insulating resin is formed into a film, it is heated and dried until it becomes tack-free.
【００２２】次に両面または片面に、所定のパターンの
形成されたフィルムマスクを重ね合せ、約８００ｍＪ／
ｃｍ2 の露光量で紫外線を照射する。Next, a film mask having a predetermined pattern is superposed on both sides or one side, and about 800 mJ /
Irradiate with ultraviolet rays at an exposure dose of cm 2 .
【００２３】紫外線の照射後、１％炭酸ナトリウム溶液
をスプレーで吹き付つけ、紫外線の非照射部分の絶縁樹
脂２２を除去する。０．１ｍｍの貫通スルーホール２３
となる孔（φ０．１５ｍｍのランド径）が０．２ｍｍ間
隔で形成される。After the irradiation of ultraviolet rays, a 1% sodium carbonate solution is sprayed to remove the insulating resin 22 in the portions not irradiated with ultraviolet rays. Through hole 23 of 0.1 mm
Holes (φ 0.15 mm land diameter) are formed at intervals of 0.2 mm.
【００２４】なお、従来とは異なり、ドリルを用いずに
絶縁樹脂の露光によって、小径の貫通スルーホール２３
が形成されるので、低コスト化及び高密度化を図ること
ができる。Unlike the conventional method, the through hole 23 having a small diameter is formed by exposing the insulating resin without using a drill.
As a result, the cost and the density can be reduced.
【００２５】次に、無電解銅めっきを施して絶縁樹脂２
２の表面に約０．５μｍの薄い銅膜が形成し、さらに、
電解銅めっきを施して表面の銅層２４の厚さが約２０μ
ｍに増加される。ここで、導電性の貫通スルーホール２
３が形成される。Next, electroless copper plating is applied to the insulating resin 2
A thin copper film of about 0.5 μm is formed on the surface of No. 2, and further,
The thickness of the copper layer 24 on the surface after electrolytic copper plating is about 20μ
is increased to m. Here, the conductive through-hole 2
3 is formed.
【００２６】以下、レジスト塗布、露光から現像、エッ
チングという通常のプロセスで銅層をパターニングし、
下側配線層２４が形成される。次に絶縁樹脂２２と同じ
材料（太陽インキ；ＰＳＲ−４０００）を用いて、両面
にスクリーン印刷を行ない、露光、現像によってパター
ニングすることにより、ソルダレジスト層２６を形成す
る。Hereinafter, the copper layer is patterned by the usual processes of resist coating, exposure, development and etching,
The lower wiring layer 24 is formed. Next, the same material as that of the insulating resin 22 (solar ink; PSR-4000) is used to screen-print both surfaces, and the solder resist layer 26 is formed by patterning by exposure and development.
【００２７】ソルダレジスト層２６は、熱膨脹係数の差
によるクラックの発生を阻止する観点から、絶縁樹脂２
２と同じ材料の使用が好ましい。また、この実施形態で
は、両面配線基板を例にとって説明しているが、複数枚
の銅張積層板を加熱、加圧して得られる多層配線板を用
いれば、さらに高密度な配線が可能となる。その場合、
層間の接続にはブラインドビアホールで接続を行うこと
が好ましい。The solder resist layer 26 is used as the insulating resin 2 from the viewpoint of preventing the generation of cracks due to the difference in thermal expansion coefficient.
The use of the same material as 2 is preferred. In this embodiment, a double-sided wiring board is described as an example, but a multilayer wiring board obtained by heating and pressing a plurality of copper-clad laminates can be used to achieve higher density wiring. . In that case,
It is preferable to connect the layers by using blind via holes.
【００２８】上述したように本実施形態によれば、額縁
状支持基板２１表裏および内部に絶縁樹脂２２が塗布さ
れ、絶縁樹脂２２の露光により、貫通スルーホール２３
が形成される構成としたので、小径ドリルを用いた工程
を無くすことができる。As described above, according to the present embodiment, the insulating resin 22 is applied to the front and back and inside of the frame-shaped support substrate 21, and the through holes 23 are formed by exposing the insulating resin 22.
Since the structure is formed, the process using a small diameter drill can be eliminated.
【００２９】すなわち、小径の貫通スルーホール２３を
低コストで形成でき、ドリルでは形成困難な小径（φ
０．１ｍｍ以下）の貫通スルーホール２３をも形成で
き、小径のランドであってもランド切れを起こさずに形
成することができる。よって、半導体装置用基板のコス
ト低減と高密度化を同時に実現させることができる。That is, the through-hole 23 having a small diameter can be formed at a low cost, and the small diameter (φ
It is also possible to form through-holes 23 of 0.1 mm or less), and even small-diameter lands can be formed without causing land breakage. Therefore, cost reduction and high density of the semiconductor device substrate can be realized at the same time.
【００３０】具体的には、φ０．１ｍｍやφ０．０８ｍ
ｍの貫通スルーホールを安定して容易に形成することが
できる。また、ドリルマシンに起因する（ビットのあば
れに起因する）穴ずれが、従来では±３０μｍ程度以上
となるのに対し、本実施形態では±５μｍ以内に収まる
ので、ランド切れを無くすことができる。Specifically, φ0.1 mm and φ0.08 m
The through-hole of m can be formed stably and easily. In addition, the hole deviation caused by the drill machine (due to the bit irregularity) is about ± 30 μm or more in the related art, but is within ± 5 μm in the present embodiment, so that the land breakage can be eliminated.
【００３１】さらに、従来のドリル加工で発生するスル
ーホールの周辺に起こるクラックや樹脂の変成などが避
けられ、貫通スルーホール２３のピッチを従来の０．７
ｍｍ程度から本発明では０．２５ｍｍ程度に縮小させる
ことができる。
＜第２の実施形態＞図３は本発明の第２の実施形態に係
る半導体装置用基板の構成を示す断面図であり、図１と
同一部分には同一符号を付してその詳しい説明を省略
し、ここでは異なる部分についてのみ述べる。なお、以
下の各実施形態も同様にして重複した説明を省略する。Furthermore, cracks and resin transformation that occur around the through holes generated by the conventional drilling are avoided, and the pitch of the through through holes 23 is set to 0.7.
In the present invention, the size can be reduced to about 0.25 mm. <Second Embodiment> FIG. 3 is a sectional view showing the structure of a semiconductor device substrate according to a second embodiment of the present invention. The same parts as those in FIG. It is omitted and only different parts will be described here. It should be noted that in each of the following embodiments as well, duplicated description will be omitted.
【００３２】本実施形態は、第１の実施形態の変形形態
であり、ビルドアップ法を用いた構造である。具体的に
は図３に示すような構成になっている。図１のソルダレ
ジスト層２６形成前までは図１と同様であって、ソルダ
レジスト層２６に代えて、実施例1で示した基板２２の
少なくとも一方の面上にて少なくとも下側配線層２４を
覆うように形成され、且つ下側配線層２４に電気的に接
続するためのバイアホール２８を有する絶縁層２９を備
えている。さらに、絶縁層２９上に形成され、バイアホ
ール２８を経由して下側配線層２４に電気的に接続され
る上側配線層３０を有している。This embodiment is a modification of the first embodiment and has a structure using the build-up method. Specifically, the configuration is as shown in FIG. 1 is the same as that of FIG. 1 before the formation of the solder resist layer 26. Instead of the solder resist layer 26, at least the lower wiring layer 24 is formed on at least one surface of the substrate 22 shown in the first embodiment. An insulating layer 29 is formed so as to cover and has a via hole 28 for electrically connecting to the lower wiring layer 24. Further, it has an upper wiring layer 30 formed on the insulating layer 29 and electrically connected to the lower wiring layer 24 via the via hole 28.
【００３３】なお、図３中、額縁状支持基板２１、絶縁
樹脂２２、スルーホール２３、配線層２４は、前述した
通りである。In FIG. 3, the frame-shaped support substrate 21, the insulating resin 22, the through holes 23, and the wiring layer 24 are as described above.
【００３４】次に、このような半導体装置用基板の製造
方法及び作用を説明する。始めに、図１を用いて前述し
た通り、支持基板２１における貫通孔２３の形成から下
側配線層２４の形成までの工程を行う。Next, the manufacturing method and operation of such a semiconductor device substrate will be described. First, as described above with reference to FIG. 1, steps from the formation of the through hole 23 in the support substrate 21 to the formation of the lower wiring layer 24 are performed.
【００３５】続いて、絶縁樹脂２２と同じ樹脂インキを
スクリーン印刷で基板表裏に塗布する。この時同時に貫
通スルーホールの内にも絶縁樹脂が充填される。その
後、絶縁樹脂を加熱乾燥し、バイアホールパターンの形
成されたフィルムマスクを用い露光し、現像というプロ
セスにより、図３に示すように、下側配線層２４を覆い
且つバイアホール２８を有して絶縁層２９が形成され
る。さらに、無電解銅めっき及び電解銅めっきによる全
面への銅層形成後、前述同様の通常プロセスにより銅層
をパターニングし、絶縁層２９上に上側配線層３０を形
成する。さらに、図３に示すように、ランドを残して上
側配線層３０及び絶縁層２９上にソルダレジスト層３１
を形成し、半導体装置用基板を完成する。しかる後、半
導体チップの搭載、樹脂による封止などの工程により、
半導体装置を完成する。Subsequently, the same resin ink as the insulating resin 22 is applied to the front and back of the substrate by screen printing. At this time, the insulating resin is also filled in the through-holes at the same time. After that, the insulating resin is heated and dried, exposed by using a film mask having a via hole pattern formed therein, and developed by a process of covering the lower wiring layer 24 and having a via hole 28 as shown in FIG. The insulating layer 29 is formed. Further, after the copper layer is formed on the entire surface by electroless copper plating and electrolytic copper plating, the copper layer is patterned by the same normal process as described above to form the upper wiring layer 30 on the insulating layer 29. Further, as shown in FIG. 3, a solder resist layer 31 is formed on the upper wiring layer 30 and the insulating layer 29 while leaving the land.
Are formed to complete the semiconductor device substrate. After that, by the process of mounting the semiconductor chip, sealing with resin, etc.,
Complete the semiconductor device.
【００３６】上述したように本実施形態によれば、額縁
状支持基板２１の内側に形成された絶縁樹脂２２に露光
により、小径の貫通スルーホール２３が形成される構成
としたので、小径ドリルを用いた工程を無くすことがで
きる。As described above, according to the present embodiment, since the insulating resin 22 formed inside the frame-shaped support substrate 21 is formed with the through holes 23 having a small diameter by exposure, a small diameter drill is used. The steps used can be eliminated.
【００３７】すなわち、小径の貫通スルーホール２３を
低コストで形成でき、ドリルでは形成困難な小径の貫通
スルーホール２３をも形成でき、小径のランドであって
もランド切れを起こさずに形成することができる。よっ
て、半導体装置用基板のコスト低減と高密度化を同時に
実現させることができる。That is, the through-hole 23 having a small diameter can be formed at a low cost, the through-hole 23 having a small diameter, which is difficult to form by a drill, can be formed, and even a land having a small diameter can be formed without causing land breakage. You can Therefore, cost reduction and high density of the semiconductor device substrate can be realized at the same time.
【００３８】具体的には、φ０．１ｍｍやφ０．０８ｍ
ｍの貫通スルーホールを安定して容易に形成することが
できる。また、ドリルマシンに起因する（ビットのあば
れに起因する）穴ずれが、従来では±３０μｍ程度以上
となるのに対し、本実施形態では±５μｍ以内に収まる
ので、ランド切れを無くすことができる。Specifically, φ0.1 mm and φ0.08 m
The through-hole of m can be formed stably and easily. Further, the hole deviation due to the drill machine (due to the bit irregularity) is about ± 30 μm or more in the related art, but is within ± 5 μm in the present embodiment, so that the land break can be eliminated.
【発明の効果】以上説明したように本発明によれば、高
密度化、高信頼性と低コスト化を同時に実現し得る半導
体装置用基板を提供できる。As described above, according to the present invention, it is possible to provide a substrate for a semiconductor device which can simultaneously realize high density, high reliability and low cost.
【図1】本発明の第１の実施形態に係る半導体装置用基
板の構成を示す断面図FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device substrate according to a first embodiment of the present invention.
【図2】従来の半導体装置用基板の工程を断面でしめし
た模式図FIG. 2 is a schematic view showing a step of a conventional semiconductor device substrate in a cross section.
【図3】本発明の第２の実施形態に係る半導体装置用基
板の構成を示す断面図FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device substrate according to a second embodiment of the present invention.
１・・・・銅箔 ２・・・・ガラスクロス ３・・・・支持基板 ４・・・・孔 ５・・・・絶縁層 ６・・・・バイアホール ７・・・・上側配線層 ８・・・・ソルダレジスト ２１・・・・支持基板 ２２・・・・絶縁層 ２３・・・・貫通スルーホール ２４・・・・配線層 ２６・・・・ソルダレジスト層 ２８・・・・バイアホール ２９・・・・絶縁層 ３０・・・・上側配線層 ３１・・・・ソルダレジスト層 1 ... Copper foil 2 ... Glass cloth 3 ... Support substrate 4 ... hole 5 ... Insulating layer 6 ... via hole 7 ... Upper wiring layer 8 ... Solder resist 21 .... Supporting substrate 22 ... Insulating layer 23 ... Through through holes 24 ... Wiring layer 26 ... Solder resist layer 28 ... via hole 29 ... Insulating layer 30 ... Upper wiring layer 31 ... Solder resist layer
Claims (2)
が形成され、絶縁層上に配線層を備えるとともに、額縁
状支持基板の内側の領域に貫通スルーホールを備えるこ
とを特徴とする半導体装置用基板。1. A semiconductor characterized in that an insulating layer is formed on the front and back and inside of a frame-shaped support substrate, a wiring layer is provided on the insulating layer, and a through-hole is provided in a region inside the frame-shaped support substrate. Substrate for equipment.
に、絶縁層及び配線層を備え、配線層間の導通のための
バイヤホールを有することを特徴とする半導体装置用基
板。2. A substrate for a semiconductor device, comprising an insulating layer and a wiring layer on both sides of the substrate for a semiconductor device according to claim 1, and having a via hole for conduction between the wiring layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001194476A JP2003007897A (en) | 2001-06-27 | 2001-06-27 | Substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001194476A JP2003007897A (en) | 2001-06-27 | 2001-06-27 | Substrate for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003007897A true JP2003007897A (en) | 2003-01-10 |
Family
ID=19032610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001194476A Pending JP2003007897A (en) | 2001-06-27 | 2001-06-27 | Substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003007897A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582370A (en) * | 2019-09-27 | 2021-03-30 | 恒劲科技股份有限公司 | Flip chip package substrate and manufacturing method thereof |
-
2001
- 2001-06-27 JP JP2001194476A patent/JP2003007897A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582370A (en) * | 2019-09-27 | 2021-03-30 | 恒劲科技股份有限公司 | Flip chip package substrate and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6518513B1 (en) | Single-sided circuit board and method for manufacturing the same | |
| US5258094A (en) | Method for producing multilayer printed wiring boards | |
| JPH10308576A (en) | Printed wiring board and its manufacture | |
| JPH10322027A (en) | Printed wiring board and its manufacture | |
| JP2014093512A (en) | Wiring board and manufacturing method of the same | |
| JP2006229115A (en) | Metal component used in manufacturing wiring substrate and method for manufacturing wiring substrate using it | |
| JP2013140955A (en) | Printed circuit board with built-in component and manufacturing method thereof | |
| JP4489899B2 (en) | Method for manufacturing double-sided circuit board for multilayer printed wiring board | |
| KR20100052835A (en) | Copper clad laminating substrate used for manufacturing a pcb by copper direct laser method, and manufacturing method of a pcb therewith | |
| JPH1075069A (en) | Manufacture of build-up multi-layer printed circuit board using yag laser | |
| TWI487451B (en) | Manufacturing method of multilayer printed wiring board | |
| JP2002094236A (en) | Method for manufacturing multilayer circuit board | |
| KR20050093595A (en) | The production method of double side flexible printed circuit board by partial and selected cupper plating | |
| JP4089198B2 (en) | Manufacturing method of substrate for semiconductor device | |
| JP2003007897A (en) | Substrate for semiconductor device | |
| JP2004152935A (en) | Printed wiring board | |
| JP2001168228A (en) | Printed-wiring board and its manufacturing method, semiconductor package and its manufacturing method, and semiconductor device | |
| JP2000124615A (en) | Multilayer printed wiring board and its manufacture | |
| JP2002271026A (en) | Multi-layer printed wiring board and manufacturing method therefor | |
| JPH10321970A (en) | Printed wiring board and manufacture thereof | |
| JPH11224919A (en) | Substrate for semiconductor device | |
| JP2003008208A (en) | Method of manufacturing high-density multilayer build- up wiring board | |
| JPH10126058A (en) | Manufacture of multilayered printed interconnection board | |
| JP4736251B2 (en) | Film carrier and manufacturing method thereof | |
| JP2012109509A (en) | Printed wiring board manufacturing method, the printed wiring board, and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050324 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050915 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060801 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060929 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061024 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20070123 |