JP2002527906A - Electronic module, especially multi-chip module having multilayer metal wiring layer and method of manufacturing the same - Google Patents

Electronic module, especially multi-chip module having multilayer metal wiring layer and method of manufacturing the same

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Publication number
JP2002527906A
JP2002527906A JP2000576488A JP2000576488A JP2002527906A JP 2002527906 A JP2002527906 A JP 2002527906A JP 2000576488 A JP2000576488 A JP 2000576488A JP 2000576488 A JP2000576488 A JP 2000576488A JP 2002527906 A JP2002527906 A JP 2002527906A
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Japan
Prior art keywords
metal wiring
module
wiring layer
multilayer metal
back side
Prior art date
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Pending
Application number
JP2000576488A
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Japanese (ja)
Inventor
ハリー ヘドラー
グレーゴル ファイアーターク
ペーター デムル
フランツ ペッター
Original Assignee
ティーワイシーオー エレクトロニクス ロジスティック エイジー
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Publication of JP2002527906A publication Critical patent/JP2002527906A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】 本発明は、電子モジュール、特に多層金属配線層を有するマルチチップ・モジュールおよびその製造方法に関する。多層金属配線層（２）の実装側の、構成素子と触れない部分に密閉ケース（４）を固着し、かつ、約１００μｍ未満の高さを有する多層金属配線層（２）の裏側が直接、つまり追加の金属配線基板（１）を必要とすることなく、モジュールの裏側を構成する。 (57) Abstract: The present invention relates to an electronic module, particularly to a multichip module having a multilayer metal wiring layer and a method of manufacturing the same. A sealed case (4) is fixed to a portion of the mounting side of the multilayer metal wiring layer (2) that does not come into contact with the component, and the back side of the multilayer metal wiring layer (2) having a height of less than about 100 μm is directly That is, the back side of the module is configured without requiring an additional metal wiring board (1).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】 （発明の属する技術分野） 本発明は電子モジュールに関し、より詳細に述べれば、その実装側に少なくと
も１つのＩＣ構成素子が取り付けられている多層金属配線層を包含するマルチチ
ップ・モジュールであって、実装側が片面だけ密閉ケースに覆われており、当該
モジュールの底面にコンタクト・パッドを備え、それを通じて接触を確保し、よ
り高レベルのアッセンブリ・グループへの集積を達成することを可能にしたモジ
ュールに関する。TECHNICAL FIELD The present invention relates to an electronic module, and more particularly, to a multichip module including a multilayer metal wiring layer having at least one IC component mounted on a mounting side thereof. The mounting side is covered on one side by a sealed case and has a contact pad on the bottom of the module, through which it is possible to ensure contact and achieve a higher level of integration in the assembly group Related to the module.

【０００２】 さらに本発明は、電子モジュール、特に多層金属配線層を包含するマルチチッ
プ・モジュールの製造方法に関する。[0002] The invention further relates to a method of manufacturing an electronic module, in particular a multichip module including a multilayer metal wiring layer.

【０００３】 （従来の技術） 集積回路の拡張および接続テクノロジに向けられた限りない要求に応えて、そ
の小サイズ化および高速化が続けられている。マルチチップ・モジュールは、高
いワイヤリング密度すなわちＨＤＩ（高密度相互接続）を有する中間キャリア基
板が追加のレベルとしてシステム構造の階層構造内にたびたび導入されていたこ
ととして知られている。その点に関しては、複数のパッケージ化されていないチ
ップをはじめ、マルチチップ・モジュールの広エリアのカバレッジが一般的であ
る。同様に周知のものとして、チップ・サイズ・パッケージ（ＣＳＰ）に関連す
る新しい開発があり、それにおいては単一のパッケージされていないチップが、
当該チップのチップ・エリアをほとんど超えない中間キャリア基板に取り付けら
れ、チップ・エリア直下の次のアーキテクチャ・レベルに対する省スペースの接
触が利用される。BACKGROUND OF THE INVENTION In response to the ever-increasing demands for integrated circuit expansion and connection technology, their size and speed have continued to decrease. Multi-chip modules are known to have an intermediate carrier substrate with a high wiring density or HDI (Dense Interconnect) often introduced as an additional level in the hierarchy of the system structure. In that regard, wide area coverage of multi-chip modules, including multiple unpackaged chips, is common. Also well known is a new development related to chip size packaging (CSP), in which a single unpackaged chip is
It is mounted on an intermediate carrier substrate that barely exceeds the chip area of the chip and utilizes space-saving contacts to the next architectural level just below the chip area.

【０００４】 シングルチップまたはマルチチップ応用に関する今日的なパッケージの基本と
なる特徴は、面方向の寸法、構造上の高さ、熱の散逸、および次のアーキテクチ
ャ・レベルにおけるピッチである。周知のクワッド・フラット・パック（ＱＦＰ
）パッケージの使用は、比較的低い程度のチップ・カバレッジ（チップ・エリア
／コンポーネント・エリア）および比較的高いチップの高さに加えて、チップの
ピン数が多いマザーボード上における極めて細かいピッチへの移行という更なる
不利を伴う。また、ボール・グリッド・アレイ（ＢＧＡ）と呼ばれる別のパッケ
ージ・タイプも知られている。その場合においては、モジュールの裏側に、比較
的粗いグリッド・パターンでエリア全体に小さいハンダ・ボールを取り付けるか
、シートに似た態様で端子を構成する。ＢＧＡ構造により、シートに似た態様の
接点の配列がピッチに関する問題の緩和に寄与し、基本的に構造高を抑えること
ができる。しかしながら、従来的なラミネート／プラスチック相互接続の製造は
、特に高密度ワイヤリングの場合に、技術的迂回を招き、かつ不都合な製品特性
をもたらす。総合的に、現在の状況は次のようであると言える。[0004] The basic features of today's packages for single-chip or multi-chip applications are in-plane dimensions, structural height, heat dissipation, and pitch at the next architectural level. Well-known Quad Flat Pack (QFP
2.) The use of packages translates to very fine pitch on motherboards with a high pin count of chips, in addition to a relatively low degree of chip coverage (chip area / component area) and relatively high chip height. With the additional disadvantage. Another package type called a ball grid array (BGA) is also known. In that case, a small solder ball is attached to the whole area in a relatively coarse grid pattern on the back side of the module, or the terminals are configured in a sheet-like manner. With the BGA structure, the arrangement of the contacts in a manner similar to the sheet contributes to alleviation of the pitch-related problem, and the structure height can be basically suppressed. However, the production of conventional laminate / plastic interconnects, especially in the case of high-density wiring, leads to technical detours and unfavorable product properties. Overall, it can be said that the current situation is as follows.

【０００５】 回路基板製造のテクノロジは、可能性のある金属配線基板による、比較的シン
プルな態様において作ることができるめっきスルーホールによってチップ側から
裏側への電気的なスルー‐コンタクトを可能にする。これらのテクニックは、面
方向の寸法が小さい構造的な形状を作り出す上で不利であり、特にマルチチップ
・モジュールに関しては、ワイヤリング密度が低すぎることから不利である。さ
らに詳細に述べれば、導体トラック・レベル間の通路が、ラミネート化された材
料の収縮に起因して、充分に正確な態様で配置されない。その不確実さは通常２
００μｍに達し、それが通路周囲の構造（ランド）のより粗い設計によって表面
化する。この収縮があることから、たとえば６００×６００ｍｍといった安価な
大型パネルではなく、たとえば１５０×１５０ｍｍといった極めて小さいパネル
を用いて製造が行われるときに限って高密度金属配線基板が現実的なものとなり
得る。このため、回路基板における大判製造テクノロジは、薄膜テクノロジに比
較すると高いコストを伴う。[0005] The technology of circuit board manufacturing allows for electrical through-contacts from the chip side to the back side with plated through holes, which can be made in a relatively simple manner, with a potential metal wiring board. These techniques are disadvantageous in creating structural features with small in-plane dimensions, especially for multi-chip modules because the wiring density is too low. More specifically, the passages between the conductor track levels are not arranged in a sufficiently accurate manner due to shrinkage of the laminated material. The uncertainty is usually 2
00 μm, which is surfaced by a coarser design of the structure (land) around the passage. Because of this shrinkage, a high-density metal wiring board can be realistic only when manufacturing is performed using an extremely small panel, for example, 150 × 150 mm, instead of an inexpensive large panel, for example, 600 × 600 mm. . For this reason, large format technology on circuit boards is associated with higher costs than thin film technology.

【０００６】 薄膜製造テクノロジにおいては、微細構造を採用するそのプロセスから、また
剛直な基板材料（多層金属配線層用の基板本体はセラミック、シリコン、ガラス
または金属からなる）に起因して収縮の問題がないことから、高いワイヤリング
密度が可能になる。しかしながら、このテクノロジは、別の点で問題を抱えてお
り、特にコスト集約的な技術的迂回に関して、たとえば剛直なコア材料における
穿孔またはホールのパンチング、調整の問題、基板の表側から裏側への電気的な
接続を実現する上で必要になるホールの金属化に関して問題を有している。それ
に加えて、めっきスルー・ホールの密度が基板の厚さによって、またホールの形
成に用いるそれぞれのテクノロジによって制限される。概して、ホールを伴う基
板に関するテクノロジと、薄膜テクニックにおけるスピン・コーティング等のプ
ロセスは、両立の可能性が薄い。さらに薄膜プロセスにおいては基板の破損の危
険性も高く、安価な大判製造への単純な変更も許されない。In thin film manufacturing technology, the problem of shrinkage due to the process employing microstructures and due to rigid substrate materials (substrate bodies for multilayer metal wiring layers consist of ceramic, silicon, glass or metal) The absence of a wire allows for a high wiring density. However, this technology is problematic in other respects, especially with regard to cost-intensive technical detours, for example, perforations or hole punching in rigid core materials, alignment issues, front-to-back electrical routing of substrates. There is a problem with regard to the metallization of holes required for realizing an efficient connection. In addition, the density of plated-through holes is limited by the thickness of the substrate and by the respective technology used to form the holes. In general, technology for substrates with holes and processes such as spin coating in thin film techniques are unlikely to be compatible. Further, in the thin film process, there is a high risk of damage to the substrate, and a simple change to inexpensive large format manufacturing is not allowed.

【０００７】 本発明は、初めに示したタイプの改善されたモジュールであって、特に構造高
が抑えられたモジュールを提供すること、およびその製造方法を示すことを目的
とする。The object of the present invention is to provide an improved module of the type indicated at the outset, in particular a module with a reduced structural height, and to show a method for its manufacture.

【０００８】 （課題を解決するための手段） 初めに示したタイプのモジュールについては、多層金属配線層の実装側の構成
素子と触れない部分に密閉ケースを固着すること、および、約１００μｍ未満の
高さを有する多層金属配線層の裏側が直接、つまり追加の金属配線基板を必要と
することなく、モジュールの裏側を構成することにおいて上記の目的が達成され
ている。(Means for Solving the Problems) For a module of the type shown at the beginning, a sealed case is fixed to a portion of the multilayer metal wiring layer which does not come into contact with a component on the mounting side, and a module having a size of less than about 100 μm The above object has been achieved in configuring the back side of a module directly on the back side of the multi-layer metal wiring layer having a height, that is, without requiring an additional metal wiring board.

【０００９】 当初示したタイプの方法については、その裏側にコンタクト・パッドを有する
多層金属配線層を剛直な材料からなるプレート状金属配線基板の表側にのみ取り
付け、ＩＣ構成素子および追加の電子構成素子をそれぞれ電気的に、かつ機械的
に多層金属配線層の構成素子レベルに接続し、多層金属配線層に、その実装側の
構成素子と触れない部分に密閉ケースを固着して備え、その後、剛直な金属基板
材料をそこから再び除去し、多層金属配線層の裏側、つまりモジュールの裏側を
構成する面を露出させることによってこの目的が達成されている。In a method of the type initially set forth, a multi-layer metal wiring layer having contact pads on the back side is mounted only on the front side of a plate-shaped metal wiring board made of a rigid material, and the IC component and the additional electronic component are provided. Are electrically and mechanically connected to the component level of the multi-layer metal wiring layer, and the multi-layer metal wiring layer is provided with a sealed case fixed to a portion not in contact with the component on the mounting side. This object has been achieved by removing the new metal substrate material therefrom again, exposing the back side of the multilayer metal wiring layer, that is, the surface constituting the back side of the module.

【００１０】 このほかの本発明による結果については、付随する特許請求の範囲に示す。[0010] Additional results according to the present invention are set forth in the appended claims.

【００１１】 以下、例を示す形で図面を参照し、本発明をさらに詳細に説明する。The present invention will now be described in more detail by way of example with reference to the drawings.

【００１２】 （実施例） 本発明は、相互接続本体製造のプロセスが考慮されているという点だけでなく
、ＢＧＡ標準パッケージを作るための全体的なプロセスが合理的に統合され、か
つ本発明に従ったプロセスのシーケンス、したがってモジュール自体の再構成と
いう点において望ましい改善を達成している。本発明によれば、超薄型のモジュ
ールの製造が可能であるにもかかわらず、一方においては薄膜技術の使用、つま
り特に剛直な金属基板材料あるいは高温安定材料（最高４００℃）の使用の利点
が維持され、他方においては、高ワイヤリング密度を制限のない態様で達成する
ことが可能になり、かつ、たとえば４００ｍｍ×４００ｍｍといった大型のパネ
ルを製造に用いることができる。それに加えて、プロセスのステップが省略でき
るという利点もある。Embodiments The present invention not only takes into account that the process of interconnect body manufacture is taken into account, but also rationally integrates the overall process for making a BGA standard package. A desirable improvement has been achieved in terms of a sequence of processes that follow, and thus a reconfiguration of the module itself. In spite of the possibility of producing ultra-thin modules according to the invention, on the one hand the advantages of using thin-film technology, in particular the use of rigid metal substrate materials or high-temperature stable materials (up to 400 ° C.). Is maintained, on the other hand, it is possible to achieve high wiring densities in an unrestricted manner, and large panels, for example 400 mm × 400 mm, can be used for the production. In addition, there is the advantage that the steps of the process can be omitted.

【００１３】 図１Ａを参照すると、すでにその表側に相互接続本体、つまり絶縁層によって
電気的に互いに分離された一連の形成された金属面またはレベルから構成された
、通路を介して互いの間の電気的な接続が意図的に設けられている多層金属配線
層２が取り付けられた金属配線基板１が示されている。適切な金属基板材料とし
ては、たとえば、銅またはアルミニウムを挙げることができる。多層金属配線層
２が実際に基板の表側のみに取り付けられ、金属配線基板１の表側から裏側に通
じるめっきスルー・ホールが形成されていないことは、極めて重要である。図１
Ｂは、図１Ａと比較するとわかるが、２つの追加の製造ステップ、つまり多層金
属配線層２の実装側に対する１ないしは複数のチップ３およびオプションとして
追加の電子構成素子の、たとえばチップ・アンド・ワイヤ・ボンディング・テク
ニック、あるいはフィリップ・チップ・テクニックによる機械的かつ電気的な接
続を行うステップおよび、それが取り付けられた後のシステムに対して片面プラ
スチック・モールディング（オーバーモールド）による標準パッケージ、すなわ
ちケース４を構成するステップが実行された後のモジュールが示されている。コ
ンポーネント・エリア、つまり多層金属配線層２の実装側のもっとも大きな部分
は、構成素子との接触がなく、そのため、取り付けられるキャスティングまたは
粘着性コンパウンド４は、多層金属配線層２に対する充分な接着エリア５を確保
することができる。より詳細に述べれば、通常のキャスティング・コンパウンド
が概して互換性を有することから、つまりポリイミド、ＰＢＯ、ＢＣＢあるいは
オルモシアといった多層金属配線層２の最上層に使用される絶縁材料と接着する
能力を有することから、それを使用することができる。Referring to FIG. 1A, there is already an interconnect body on its front side, ie, a series of formed metal surfaces or levels electrically separated from each other by an insulating layer, between each other via passages. 1 shows a metal wiring board 1 to which a multilayer metal wiring layer 2 to which an electrical connection is intentionally provided is attached. Suitable metal substrate materials can include, for example, copper or aluminum. It is extremely important that the multilayer metal wiring layer 2 is actually mounted only on the front side of the board, and that there is no plated through hole extending from the front side to the back side of the metal wiring board 1. FIG.
B can be seen in comparison with FIG. 1A, but with two additional manufacturing steps, namely one or more chips 3 and optionally additional electronic components for the mounting side of the multilayer metallization layer 2, for example chip and wire. A step of making a mechanical and electrical connection by means of a bonding technique or a philip chip technique and a standard package with a single-sided plastic molding (overmold) for the system after it has been installed, ie case 4 Are shown after the steps of constructing are performed. The component area, i.e. the largest part of the mounting side of the multilayer metal wiring layer 2, has no contact with the components, so that the casting or adhesive compound 4 to be mounted has a sufficient adhesion area 5 to the multilayer metal wiring layer 2. Can be secured. More specifically, the ordinary casting compound is generally compatible, i.e., has the ability to adhere to the insulating material used for the top layer of the multilayer metal wiring layer 2, such as polyimide, PBO, BCB or Ormocia. From, you can use it.

【００１４】 図１Ｃは、次のプロセス・ステップを実行して金属基板材料１の除去を行った
後のモジュールを示している。これは、たとえば金属基板材料の溶解によって、
より詳細にはたとえば高集積化半導体テクノロジに使用されるような、この分野
で一般的なエッチ・プラントの１つにおける湿式化学エッチングを用いて達成す
ることができる。その後それによって、多層金属配線層２の裏側にあるコンタク
ト・パッド６、つまり通路および導体トラック・システムへの接続を通じて、こ
のモジュールのコンポーネント３と次に高いアッセンブリ・グループ・レベルの
電気的な接触を確保するコンタクト・パッドが露出される。図１Ｄに示されるよ
うに、通常はこのモジュールに対する接触を確保するために、これに続いてハン
ダ付け可能な材料、より詳細にはハンダ・ボール７がコンタクト・パッド６に取
り付けられる。後に行うモジュールのテストを容易にするために、図１Ｂに示す
ように不活性層１５を備えることもできる。基本的に、たとえばプラスチック材
料を同様の基板材料として用いることも可能である。FIG. 1C shows the module after performing the following process steps to remove the metal substrate material 1. This is due, for example, to the dissolution of
More specifically, this can be achieved using wet chemical etching in one of the common etch plants in this field, such as used in highly integrated semiconductor technology. Thereafter, it makes contact with the components 3 of this module and the next higher assembly group level electrical contacts through the contact pads 6 on the underside of the multilayer metallization layer 2, i.e. via the track and conductor track system. The secured contact pads are exposed. As shown in FIG. 1D, a solderable material, more specifically a solder ball 7, is then attached to the contact pads 6, usually to ensure contact with the module. To facilitate later testing of the module, an inactive layer 15 may be provided as shown in FIG. 1B. Basically, it is also possible, for example, to use plastic materials as similar substrate materials.

【００１５】 図２Ａおよび図２Ｂは、図１Ａおよび図１Ｂに従った製造ステップに対応して
いるが、図２Ｃないし図２Ｆは、異なる実施態様を示している。図２Ｃは、裏側
から基板材料の内側にエッチング行った結果形成されたピット８を示しており、
それによって接触ロケーション、つまり多層金属配線層２の裏側にあるコンタク
ト・パッド６が露出されている。それに続いて、ピット８内に電気めっきによっ
てハンダ付け可能な材料９（たとえばＳｎＰｂ）を導入し、あるいは図１Ｄに示
したように、標準プロセスを使用してピット８内にハンダ・ボール７を導入する
ことができる。その後初めて、金属配線基板１の除去が行われ、選択したハンダ
材料のタイプ７または９に応じて、図２Ｅまたは２Ｆに示したモジュールが最終
的な結果として得られる。FIGS. 2A and 2B correspond to the manufacturing steps according to FIGS. 1A and 1B, while FIGS. 2C to 2F show different embodiments. FIG. 2C shows pits 8 formed as a result of etching the inside of the substrate material from the back side,
Thereby, the contact location, that is, the contact pad 6 on the back side of the multilayer metal wiring layer 2 is exposed. Subsequently, a material 9 (eg, SnPb) that can be soldered by electroplating is introduced into the pit 8 or, as shown in FIG. 1D, a solder ball 7 is introduced into the pit 8 using a standard process. can do. Only then is the metal wiring board 1 removed, depending on the type of solder material 7 or 9 selected, resulting in the final module shown in FIG. 2E or 2F.

【００１６】 前述した溶解による基板材料の除去に代わる別の適切な分離の可能性として、
基板材料１を多層金属配線層２から剥離する方法がある。これは、特に、多層金
属配線層２と金属配線基板１の間に中間層を適用することによって実現される。
たとえば、ハンダ等の低融点材料もしくは接着剤が適しており、それを用いれば
モールディング・プロセスの最後に、たとえば追加の熱処理ステップを行うこと
によって、金属配線基板１からモジュールを隔離させることが可能になる。図３
Ａ〜３Ｅに示したプロセスにおいては、当初ハンダ・レイヤ１０が中間層として
基板材料に塗布されており、続いてそれが形成された絶縁層１１によって覆われ
る。図３Ｃによれば、形成された金属面１２が作られ、図３Ｄによれば、そこに
電子構成素子が備えられた後、密閉ケース４によって覆われる。図３Ｅは、ハン
ダ・レイヤ１０を加熱して金属配線基板１を除去した最終的な結果を示しており
、害のないハンダ・レイヤ１０の残渣がハンダ・パッド６だけに残される。この
、特に安価な製造を可能にする特定のケースにおいては、多層金属配線層２の導
体トラック・システムが単一の金属および単一の絶縁層１２および１１のみから
なる、その中において金属ランド１３および１４が互いに接続されている。中間
層として接着剤を用いた場合には、可能な限り残渣のないものとするかあるいは
、ポスト‐クリーニングが必要になることに注意されたい。Another suitable separation possibility instead of the removal of substrate material by dissolution as described above,
There is a method of peeling the substrate material 1 from the multilayer metal wiring layer 2. This is realized in particular by applying an intermediate layer between the multilayer metal wiring layer 2 and the metal wiring board 1.
For example, a low melting point material such as solder or an adhesive is suitable and allows the module to be isolated from the metal wiring board 1 at the end of the molding process, for example by performing an additional heat treatment step. Become. FIG.
In the process illustrated in FIGS. 3A-3E, a solder layer 10 is initially applied to a substrate material as an intermediate layer, which is subsequently covered by an insulating layer 11 on which it is formed. According to FIG. 3C, the formed metal surface 12 is produced, and according to FIG. FIG. 3E shows the final result of removing the metal wiring board 1 by heating the solder layer 10, and the harmless residue of the solder layer 10 is left only on the solder pad 6. In this particular case, which allows a particularly inexpensive manufacture, the conductor track system of the multilayer metallization layer 2 consists of only a single metal and single insulating layers 12 and 11 in which the metal lands 13 And 14 are connected to each other. Note that the use of an adhesive as the intermediate layer should be as residue-free as possible or require post-cleaning.

【００１７】 本発明によれば、それによって達成される結果から、アッセンブリ高が、残さ
れた多層金属配線層２、つまり相互接続本体の高さだけになり、それが約１００
μｍ未満、ほとんどの場合は６０μｍよりも低くなることから、極めて低いアッ
センブリ高を持ったＢＧＡ標準パッケージ形式のモジュールが得られる。薄型の
チップ３の高さは、通常、約３００μｍであり、密閉ケース４の高さもそれと同
程度であることから、本発明によれば、約６００μｍの最低パッケージ高（ボー
ルを除く）を達成することが可能になり、これに対して、たとえばラミネート・
テクノロジにおいては、周知の相互接続のみ、つまり上に多層金属配線層が配置
される金属配線基板だけでも５００μｍから１０００μｍの高さを有している。According to the invention, the result achieved thereby is that the assembly height is only the height of the remaining multilayer metal wiring layer 2, ie the interconnect body, which is about 100
Since it is less than μm, and in most cases less than 60 μm, a BGA standard package type module with an extremely low assembly height is obtained. Since the height of the thin chip 3 is usually about 300 μm and the height of the sealed case 4 is also about the same, according to the present invention, a minimum package height (excluding balls) of about 600 μm is achieved. For example, a laminate
In technology, only the well-known interconnects, i.e. the metal wiring substrate alone on which the multilayer metal wiring layers are arranged, have a height of 500 μm to 1000 μm.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の第１の実施態様に従った製造プロセスにおける連続するステップを示
した横断面図である。FIG. 1 is a cross-sectional view showing successive steps in a manufacturing process according to a first embodiment of the present invention.

【図２】 別の実施態様における対応する断面図である。FIG. 2 is a corresponding cross-sectional view of another embodiment.

【図３】 さらに別の実施態様における対応する断面図である。FIG. 3 is a corresponding cross-sectional view in yet another embodiment.

【符号の説明】[Explanation of symbols]

１ 金属配線基板 ２ 多層金属配線層 ３ 電子構成素子 ４ 密閉ケース（粘着性コンパウンド） ５ 接着エリア ６ コンタクト・パッド ７ ハンダ・ボール ８ ピット ９ ハンダ付け可能な材料 １０ 中間層 １１ 形成された絶縁層 １２ 形成された金属面 １３、１４ 金属ランド １５ 不活性層 DESCRIPTION OF SYMBOLS 1 Metal wiring board 2 Multilayer metal wiring layer 3 Electronic component 4 Sealed case (adhesive compound) 5 Adhesion area 6 Contact pad 7 Solder ball 8 Pit 9 Solderable material 10 Intermediate layer 11 Formed insulating layer 12 Formed metal surface 13, 14 Metal land 15 Inactive layer

【手続補正書】特許協力条約第３４条補正の翻訳文提出書[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

【提出日】平成１２年１２月１９日（２０００．１２．１９）[Submission date] December 19, 2000 (200.12.19)

【手続補正１】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

【請求項８】 前記金属基板材料の除去は、多層金属配線層（２）から金属配
線基板（１）を剥離することによって行うことを特徴とする前記請求項４または
５記載の方法。8. The method according to claim 4, wherein the removal of the metal substrate material is performed by peeling the metal wiring substrate (1) from the multilayer metal wiring layer (2).

【手続補正書】[Procedure amendment]

【提出日】平成１３年８月１日（２００１．８．１）[Submission date] August 1, 2001 (2001.8.1)

【手続補正１】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

───────────────────────────────────────────────────── フロントページの続き (72)発明者 デムル ペーター ドイツ連邦共和国 デー−83620 フェル トキルヒェン イェガーヴェーク 11 (72)発明者 ペッター フランツ ドイツ連邦共和国 デー−85247 シュヴ ァブハウゼン ヘーエンヴェーク 20──────────────────────────────────────────────────続 き Continuing on the front page (72) Demur Peter, Germany Day-83620 Feldkirchen Jägerweg 11 (72) Inventor Petter Franz Germany Day-85247 Schwabhausen Heenweg 20

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 電子モジュール、特に、実装側に少なくとも１つのＩＣ構成素
子が取り付けられている多層金属配線層を有するマルチチップ・モジュールであ
って、前記モジュールは、前記実装側が片面だけ密閉ケースに覆われており、前
記モジュールの裏側にコンタクト・パッドを備え、それを通じて接触を確保し、
次のより高いレベルのアッセンブリ・グループへのモジュールの集積化を可能に
した電子モジュールにおいて： 前記多層金属配線層（２）の実装側の、構成素子と触れない部分に密閉ケース
（４）を固着したこと、および、約１００μｍ未満の高さを有する前記多層金属
配線層（２）の裏側が直接、つまり追加の金属配線基板（１）を必要とすること
なく、前記モジュールの裏側を構成することを特徴とするモジュール。An electronic module, particularly a multi-chip module having a multilayer metal wiring layer having at least one IC component mounted on a mounting side, wherein the mounting side of the module is closed on one side only in a closed case. Covered and provided with a contact pad on the back side of the module, to ensure contact therethrough,
In an electronic module that has enabled the integration of the module into the next higher level assembly group: A sealed case (4) is fixed to the mounting side of the multilayer metal wiring layer (2) on the part not in contact with the component. And the back side of said multilayer metal wiring layer (2) having a height of less than about 100 μm constitutes the back side of said module directly, ie without the need for an additional metal wiring board (1) A module characterized by the following. 【請求項２】 前記多層金属配線層（２）は、絶縁層（１１）によって互いに
電気的に絶縁され、互いの間が通路を介して意図的に設けられた電気接続によっ
て接続された一連の形成された金属面（１２）によって構成されることを特徴と
する前記請求項１記載のモジュール。2. The multi-layered metal wiring layers (2) are electrically insulated from each other by an insulating layer (11), and are connected to each other by an electrical connection intentionally provided through a passage. The module according to claim 1, characterized in that it is constituted by a formed metal surface (12). 【請求項３】 次のアッセンブリ・グループ・レベルとの接続を確立するため
、ハンダ付け可能な材料（７，９）、特にハンダ・ボール（７）が前記多層金属
配線層（２）の裏側にあるコンタクト・パッド（６）に取り付けられ、それが通
路を介して前記構成素子のレベルと電気的に接触することを特徴とする前記請求
項１または２記載のモジュール。3. A solderable material (7, 9), in particular a solder ball (7), on the back side of said multilayer metal wiring layer (2) to establish a connection with the next assembly group level. 3. The module according to claim 1, wherein the module is attached to a contact pad, which makes electrical contact with the level of the component via a passage. 【請求項４】 裏側にコンタクト・パッド（６）を有する多層金属配線層（２
）を、剛直な材料からなるプレート状金属配線基板（１）の表側にのみ取り付け
るステップ； ＩＣ構成素子および追加の電子構成素子（３）をそれぞれ電気的に、かつ機械
的に前記多層金属配線層（２）の金属配線層の構成素子レベルに接続するステッ
プ； 前記多層金属配線層（２）に、密閉ケース（４）を、前記実装側の構成素子に
触れない部分に固着して備えるステップ；および、 その後、前記剛直な金属基板材料を除去し、前記モジュールの裏側を構成する
前記多層金属配線層（２）の裏側を露出させるステップ； を特徴とする前記請求項１に従った電子モジュールを作成する方法。4. A multilayer metal wiring layer (2) having a contact pad (6) on the back side.
) Is mounted only on the front side of a plate-shaped metal wiring substrate (1) made of a rigid material; IC components and additional electronic components (3) are each electrically and mechanically connected to the multilayer metal wiring layer. (2) connecting to the component level of the metal wiring layer; and providing the hermetically sealed case (4) to the multilayer metal wiring layer (2) by fixing it to a portion that does not touch the component on the mounting side; And thereafter removing the rigid metal substrate material to expose the back side of the multilayer metal wiring layer (2) constituting the back side of the module. The electronic module according to claim 1, further comprising: How to create. 【請求項５】 特に金属基板材料の除去に先行して、前記コンタクト・パッド
（６）の下側に位置する部分において、裏側から金属配線基板（１）の内側にピ
ット（８）のエッチングを行い、その後、該ピット（８）内にハンダ付け可能な
材料（７，９）を導入することを特徴とする前記請求項４記載の方法。5. In particular, prior to the removal of the metal substrate material, in a portion located below the contact pad (6), a pit (8) is etched from the back side into the metal wiring substrate (1). 5. The method according to claim 4, wherein the method further comprises introducing solderable material (7, 9) into the pits (8). 【請求項６】 特に金属基板材料の除去を、その溶解によって行うことを特徴
とする前記請求項４または５記載の方法。6. The method according to claim 4, wherein the removal of the metal substrate material is carried out by melting. 【請求項７】 前記溶解を湿式化学エッチングによって行うことを特徴とする
前記請求項６記載の方法。7. The method according to claim 6, wherein said dissolving is performed by wet chemical etching. 【請求項８】 前記金属基板材料の除去は、多層金属配線層（２）から金属配
線基板（１）を剥離することによって行うことを特徴とする前記請求項４または
５記載の方法。8. The method according to claim 4, wherein the removal of the metal substrate material is performed by peeling the metal wiring substrate (1) from the multilayer metal wiring layer (2). 【請求項９】 前記モジュールの作成において、当初金属配線基板（１）に、
その後に行われる剥離を容易にする中間層（１０）を備え、その後にその上から
多層金属配線層（２）を取り付けることを特徴とする前記請求項８記載の方法。9. When the module is manufactured, the metal wiring board (1) is
9. The method according to claim 8, comprising an intermediate layer (10) for facilitating a subsequent peeling, after which a multilayer metal wiring layer (2) is applied thereon. 【請求項１０】 前記中間層（１０）として低融点材料、特にハンダを塗布す
ることを特徴とする前記請求項９記載の方法。10. The method according to claim 9, wherein a low-melting material, in particular solder, is applied as the intermediate layer (10). 【請求項１１】 前記中間層として接着剤を塗布し、続いて追加の加熱処理ス
テップによって、金属配線基板（１）からの多層金属配線層（２）の剥離を可能
にしたことを特徴とする前記請求項９記載の方法。11. The method according to claim 1, wherein an adhesive is applied as said intermediate layer, followed by an additional heat treatment step, whereby the multilayer metal wiring layer (2) can be separated from the metal wiring board (1). The method of claim 9. 【請求項１２】 前記密閉ケース（４）の形成は、プラスチックのオーバーモ
ールディングまたは粘着性コンパウンドを用いたカバーリングによって行われる
ことを特徴とする前記請求項４〜１１記載の方法。12. The method according to claim 4, wherein the formation of the closed case (4) is performed by plastic overmolding or covering with an adhesive compound.
JP2000576488A 1998-10-09 1999-10-08 Electronic module, especially multi-chip module having multilayer metal wiring layer and method of manufacturing the same Pending JP2002527906A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19846662.5 1998-10-09
DE19846662A DE19846662A1 (en) 1998-10-09 1998-10-09 Electronic module used in the production of high density interconnects and quad flat pack packages has the assembly side of the wiring adhered to a hermetic housing
PCT/DE1999/003247 WO2000022668A1 (en) 1998-10-09 1999-10-08 Electronic module, especially a multichip module, with multi-layer metallization and corresponding production method

Publications (1)

Publication Number Publication Date
JP2002527906A true JP2002527906A (en) 2002-08-27

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DE (1) DE19846662A1 (en)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810673B1 (en) * 2002-05-24 2008-03-07 후지쯔 가부시끼가이샤 Semiconductor device and manufacturing method thereof
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414479B1 (en) * 2000-08-09 2004-01-07 주식회사 코스타트반도체 Implantable circuit tapes for implanted semiconductor package and method for manufacturing thereof
DE10201782A1 (en) * 2002-01-17 2003-03-27 Infineon Technologies Ag Electronic component with one or more semiconductor chips, includes arrangement of through contacts forming edges of bond channel.
DE102006001429A1 (en) * 2006-01-10 2007-03-22 Infineon Technologies Ag Semiconductor component functional unit and production process has rows and columns of chips on a connection plate and a multi-layer wiring structure insulated by a hybrid organic-inorganic polymer dielectric
DE102015122282A1 (en) * 2015-12-18 2017-06-22 Infineon Technologies Ag Electronic component and method for its production

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2524707B1 (en) * 1982-04-01 1985-05-31 Cit Alcatel METHOD OF ENCAPSULATION OF SEMICONDUCTOR COMPONENTS, AND ENCAPSULATED COMPONENTS OBTAINED
FR2666173A1 (en) * 1990-08-21 1992-02-28 Thomson Csf HYBRID INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUITS AND MANUFACTURING METHOD.
US5218759A (en) * 1991-03-18 1993-06-15 Motorola, Inc. Method of making a transfer molded semiconductor device
US5796164A (en) * 1993-05-11 1998-08-18 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5492266A (en) * 1994-08-31 1996-02-20 International Business Machines Corporation Fine pitch solder deposits on printed circuit board process and product
FR2736206B1 (en) * 1995-06-30 1997-08-08 Commissariat Energie Atomique METHOD FOR PRODUCING AN INTERCONNECTION SUBSTRATE FOR CONNECTING A CHIP TO A RECEIVING SUBSTRATE
DE19702014A1 (en) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chip module and method for producing a chip module
JPH10163368A (en) * 1996-12-02 1998-06-19 Fujitsu Ltd Manufacture of semiconductor device and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810673B1 (en) * 2002-05-24 2008-03-07 후지쯔 가부시끼가이샤 Semiconductor device and manufacturing method thereof
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