JP2002335065A - Method for forming circuit - Google Patents
Method for forming circuitInfo
- Publication number
- JP2002335065A JP2002335065A JP2001136595A JP2001136595A JP2002335065A JP 2002335065 A JP2002335065 A JP 2002335065A JP 2001136595 A JP2001136595 A JP 2001136595A JP 2001136595 A JP2001136595 A JP 2001136595A JP 2002335065 A JP2002335065 A JP 2002335065A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- insulating
- insulating material
- conductive material
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は絶縁材に回路を形成
する方法に関する。The present invention relates to a method for forming a circuit on an insulating material.
【０００２】[0002]
【従来の技術】ノートパソコン、携帯電話、ビデオカメ
ラなどパーソナル電子機器の小型、軽量、高機能化に対
応して、電子部品が実装される基板に形成される回路は
高密度化しており、基板も絶縁シートを多数積層して構
成したものが多く用いられている。最近では、従来の多
層配線板に比し、体積当たり配線密度が数〜数十倍の高
密度、小型、軽量なビルドアップ式の多層プリント配線
板が開発されている。この方式は、フォトエッチング技
術を用いて、絶縁シート上に形成された銅層を除去して
回路パターンを形成するものである。2. Description of the Related Art Circuits formed on a substrate on which electronic components are mounted are becoming denser in response to the miniaturization, light weight, and high functionality of personal electronic devices such as notebook computers, mobile phones, and video cameras. Also, a large number of laminated insulating sheets are used. Recently, a high-density, small-sized, and light-weight build-up type multilayer printed wiring board having a wiring density per volume of several to several tens times that of a conventional multilayer wiring board has been developed. In this method, a circuit pattern is formed by removing a copper layer formed on an insulating sheet by using a photoetching technique.
【０００３】ビルドアップ式多層プリント基板の回路形
成工程を、５層のプリント基板を例にして、図２を参照
しながら説明する。５層のプリント基板の場合は、基本
的に同一の製造フローを３回繰返すことによって形成す
る。１回目のフローにおいて、最初に所定サイズに形成
された１枚の絶縁シート１０を第１の絶縁材１として準
備する（ａ）。所定箇所に導体パターン層間を電気的に
接続するための穴１１を明ける（ｂ）。無電解めっきで
穴１１の壁面を含む絶縁材１の全面に銅１２を析出させ
る（ｃ）。次いで、レジスト１３を塗布して乾燥させた
後、回路パターンで定まる所定形状に露光を行い、現
像、剥離をした後、エッチングでレジストに覆われてい
ない部分の銅を除去する（ｄ）〜（ｉ）。レジスト１３
を除去すると、回路パターン通りの銅層１２ａが露出す
る。次いで、露出した銅層１２ａに無電解銅めっきで厚
付けめっきを行って回路１２ｂを形成し、回路が形成さ
れた１層の第１の基板２を得る（ｊ）〜（ｋ）。A circuit formation process of a build-up type multilayer printed circuit board will be described with reference to FIG. 2 by taking a five-layer printed circuit board as an example. In the case of a five-layer printed circuit board, it is formed by basically repeating the same manufacturing flow three times. In the first flow, one insulating sheet 10 first formed in a predetermined size is prepared as the first insulating material 1 (a). A hole 11 for electrically connecting the conductor pattern layers is formed at a predetermined location (b). Copper 12 is deposited on the entire surface of the insulating material 1 including the wall surfaces of the holes 11 by electroless plating (c). Next, after the resist 13 is applied and dried, exposure is performed in a predetermined shape determined by a circuit pattern, development and peeling are performed, and copper in a portion that is not covered by the resist is removed by etching (d) to (d). i). Resist 13
Is removed, the copper layer 12a according to the circuit pattern is exposed. Next, the exposed copper layer 12a is subjected to thick plating by electroless copper plating to form a circuit 12b, and a single-layer first substrate 2 on which the circuit is formed is obtained (j) to (k).
【０００４】次いで２回目のフローに入る。前記で形成
した第１の基板２の表裏に、新たな絶縁シート２０、３
０を貼り付け、３層の絶縁シートからなる複合構造をし
た第２の絶縁材３を形成する。この第２の絶縁材３に対
し、前記（ｂ）〜（ｋ）の工程を繰返して新たな回路が
形成された３層の第２の基板４を得る。次いで３回目の
フローに入る。前記で形成した第２の基板４の表裏に新
たな絶縁シート４０、５０を貼り付け、５層の絶縁シー
トからなる複合構造をした第３の絶縁材５を形成する。
この第３の絶縁材５については、５層の絶縁シートを積
層接着し（ｌ）、全絶縁シートを貫通するスルーホール
５１を、ドリル工法等を用い所定位置に形成する
（ｍ）。次いで、前記（ｂ）〜（ｋ）の工程を繰返し、
新たな回路が形成されかつスルーホール５１壁面へ銅め
っきが被覆された５層のプリント基板６を得る。[0004] Next, a second flow is entered. On the front and back of the first substrate 2 formed above, new insulating sheets 20, 3
Then, a second insulating material 3 having a composite structure consisting of three layers of insulating sheets is formed. The steps (b) to (k) are repeated on the second insulating material 3 to obtain a three-layer second substrate 4 on which a new circuit is formed. Next, a third flow is entered. New insulating sheets 40 and 50 are adhered to the front and back of the second substrate 4 formed as described above, and a third insulating material 5 having a composite structure including five layers of insulating sheets is formed.
As for the third insulating material 5, five layers of insulating sheets are laminated and bonded (l), and through holes 51 penetrating all the insulating sheets are formed at predetermined positions using a drill method or the like (m). Next, the steps (b) to (k) are repeated,
A five-layer printed circuit board 6 in which a new circuit is formed and the wall surface of the through hole 51 is coated with copper plating is obtained.
【０００５】[0005]
【発明が解決しようとする課題】しかし、前記従来の回
路形成工程は、（ｄ）〜（ｊ）の工程にレジスト塗布、
露光、現像剥離などというフォトエッチング技術を用い
ており、５層のプリント基板の場合、工程数が約３４と
多く、かつレジスト剤やエッチング液など消耗材を多く
使用するため、製造時間が長くなるとともに製造コスト
が膨らむという問題があった。従って、本発明は、短い
製造時間で、かつ製造コストを抑制して、基板を構成す
る絶縁材に回路を形成するための方法を提供することを
目的としている。However, in the conventional circuit forming process, the steps (d) to (j) involve applying a resist,
A photo-etching technique such as exposure and development peeling is used. In the case of a five-layer printed circuit board, the number of steps is as large as about 34, and a large amount of consumables such as a resist agent and an etching solution are used. In addition, there is a problem that the manufacturing cost is increased. Therefore, an object of the present invention is to provide a method for forming a circuit on an insulating material constituting a substrate in a short manufacturing time and at a low manufacturing cost.
【０００６】[0006]
【課題を解決するための手段】本発明は、絶縁材表面の
導電材層の所定箇所を非化学的作用により除去し、回路
を形成することを特徴としている。また、本発明は絶縁
材表面の導電材層にレーザ光を照射し、照射箇所の導電
材を除去することにより回路を形成することを特徴とし
ている。また、本発明は絶縁材表面に形成された第１の
導電材層にレーザ光を照射し、照射箇所の導電材を除去
することにより回路パターンを形成し、回路パターン上
に第２の導電材層を形成して回路を形成することを特徴
としている。本発明は、絶縁シートを多層に積層した基
板において、絶縁シートを積層する毎に新たな絶縁シー
トに回路を形成する場合に用いると有効である。SUMMARY OF THE INVENTION The present invention is characterized in that a predetermined portion of a conductive material layer on the surface of an insulating material is removed by a non-chemical action to form a circuit. Further, the present invention is characterized in that a circuit is formed by irradiating a conductive material layer on a surface of an insulating material with a laser beam and removing the conductive material at an irradiated portion. Further, according to the present invention, a circuit pattern is formed by irradiating the first conductive material layer formed on the surface of the insulating material with a laser beam and removing the conductive material at the irradiated portion, and forming the second conductive material on the circuit pattern. It is characterized in that a circuit is formed by forming a layer. INDUSTRIAL APPLICABILITY The present invention is effective when used in a case where a circuit is formed on a new insulating sheet every time an insulating sheet is stacked on a substrate in which insulating sheets are stacked in multiple layers.
【０００７】[0007]
【発明の実施の形態】本発明を、従来例で述べたと同じ
５層の絶縁シートで構成された基板に適用した場合につ
いて、図１を参照しながら説明する。本発明を適用した
場合も、従来例で説明したと同様、基本的に同一の製造
フローを３回繰返すことによって形成するので、図１に
は１回目のフローのみを示す。絶縁シートは所定サイズ
に形成されたポリイミドフィルムを用い、１回目のフロ
ーにおいて、最初に１枚の絶縁シート１０を第１の絶縁
材１として準備する（Ａ）。次いで、所定箇所に導体パ
ターン層間を電気的に接続するための穴１１をレーザで
明ける（Ｂ）。レーザはＣＯ２レーザ、ＹＡＧ基本波、
高調波等を用いる。次いで、第１の絶縁材１の穴１１の
壁面を含むほぼ全面に、０．１〜数μｍの導電性薄膜１
２を形成する（Ｃ）。薄膜の材質としては、例えば銅を
用い、無電解めっき、イオンプレーティング、スパッタ
リング、蒸着などの方法で形成することができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The case where the present invention is applied to a substrate constituted by the same five-layer insulating sheet as described in the conventional example will be described with reference to FIG. Even when the present invention is applied, similarly to the conventional example, since the same manufacturing flow is formed by repeating the same three times, FIG. 1 shows only the first flow. As the insulating sheet, a polyimide film formed in a predetermined size is used, and in the first flow, one insulating sheet 10 is first prepared as the first insulating material 1 (A). Next, a hole 11 for electrically connecting the conductive pattern layers is formed at a predetermined position by a laser (B). Laser is CO 2 laser, YAG fundamental wave,
Use harmonics and the like. Next, the conductive thin film 1 having a thickness of 0.1 to several μm
2 is formed (C). As a material of the thin film, for example, copper can be used and formed by a method such as electroless plating, ion plating, sputtering, and vapor deposition.
【０００８】次いで、第１の絶縁材１上の銅薄膜１２を
所定形状除去し、回路パターン通りの銅薄膜１２ａを残
留させる（Ｄ）。銅薄膜１２の除去には、エッチングの
ような化学作用による除去方法ではなく、例えばレーザ
光によるような物理的作用による除去方法を用いる。使
用するレーザとしては、短パルスのＣＯ２、ＹＡＧ高調
波、エキシマレーザなどを用いることができ、銅薄膜１
２の厚さに応じた適切な条件とすることで、レーザ光が
照射された銅薄膜部分を第１の絶縁材１の表面から除去
することができる。銅薄膜１２は、厚さが薄い方が除去
時間は短くまた排除される銅の量も少ないため好まし
く、１μｍ以下の厚さに形成することが望ましい。Next, the copper thin film 12 on the first insulating material 1 is removed in a predetermined shape to leave a copper thin film 12a according to the circuit pattern (D). The copper thin film 12 is not removed by a chemical method such as etching, but by a physical method such as a laser beam. As the laser to be used, short pulse CO 2 , YAG harmonic, excimer laser, or the like can be used.
By setting appropriate conditions according to the thickness of the second layer 2, the copper thin film portion irradiated with the laser beam can be removed from the surface of the first insulating material 1. The thin copper film 12 is preferably thinner because the removal time is shorter and the amount of copper to be removed is smaller.
【０００９】所定形状に銅薄膜１２を除去するには、ス
ポットビームを用い位置制御をして行うことができる
が、ライン状やエリア状のビームを用い、回路パターン
と同形の開口部を有するマスク上から走査する方法を用
いると効率的である。マスクの材質は、用いるレーザ波
長を遮光するものであればよい。また、マスクに液晶を
利用して、レーザ光を遮光したり通過させたりするよう
に外部から制御すると、任意なパターンに簡単に対応で
きる。次いで、前記で形成された回路パターン形状の銅
薄膜１２ａの上に、１０〜３０μｍの所定の厚さに銅を
膜付けして回路１２ｂとし、回路が形成された１層の第
１の基板２を得る（Ｅ）。この銅厚膜の形成は、無電解
銅めっきや電気銅めっきで行うことができる。In order to remove the copper thin film 12 into a predetermined shape, the position can be controlled by using a spot beam. However, a mask having an opening having the same shape as the circuit pattern is formed by using a line or area beam. It is efficient to use the method of scanning from above. The material of the mask may be any as long as it blocks the laser wavelength to be used. In addition, when liquid crystal is used as a mask and laser light is externally controlled to block or pass laser light, an arbitrary pattern can be easily handled. Next, a copper film is formed to a predetermined thickness of 10 to 30 μm on the copper thin film 12a having the circuit pattern shape formed as described above to form a circuit 12b, and a single-layer first substrate 2 having the circuit formed thereon (E). This thick copper film can be formed by electroless copper plating or electrolytic copper plating.
【００１０】次に、前述した従来例の場合と同様に２回
目のフローに入る。第１の基板２の表裏に新たな絶縁シ
ート２０、３０を貼り付け、３層の絶縁シートからなる
複合構造をした第２の絶縁材３を形成する。この第２の
絶縁材３に対し、前記（Ｂ）〜（Ｅ）の工程を繰返して
新たな回路が形成された第２の基板４を得る。次いで３
回目のフローに入る。第２の基板４の表裏に新たな絶縁
シート４０、５０を貼り付け、５層の絶縁シートからな
る複合構造をした第３の絶縁材５を形成する。この第３
の絶縁材５については、５層の絶縁シートを積層接着
し、全絶縁シートを貫通するスルーホール５１を、ドリ
ル工法等を用い所定位置に形成する。次いで、前記
（Ｂ）〜（Ｅ）の工程を繰返し、新たな回路が形成され
かつスルーホール５１壁面へ銅めっきが被覆された５層
の基板６を得る。以上説明した工程数は全部で１６であ
り、従来例で説明した工程数が３４であるのに比べ、半
減以下となっている。Next, a second flow is entered as in the case of the above-described conventional example. New insulating sheets 20 and 30 are attached to the front and back of the first substrate 2 to form a second insulating material 3 having a composite structure including three layers of insulating sheets. The steps (B) to (E) are repeated on the second insulating material 3 to obtain a second substrate 4 on which a new circuit is formed. Then 3
Enter the first flow. New insulating sheets 40 and 50 are attached to the front and back of the second substrate 4 to form a third insulating material 5 having a composite structure including five layers of insulating sheets. This third
For the insulating material 5 described above, five layers of insulating sheets are laminated and bonded, and through holes 51 penetrating all the insulating sheets are formed at predetermined positions using a drill method or the like. Next, the steps (B) to (E) are repeated to obtain a five-layer substrate 6 in which a new circuit is formed and the wall surface of the through hole 51 is coated with copper plating. The number of steps described above is 16 in total, which is less than half the number of steps described in the conventional example is 34.
【００１１】上記における回路は、銅材を用い、銅薄膜
の上に銅厚膜を積層して形成した例で説明したが、他の
形態の回路に対しても対応可能である。例えば、回路材
料としては、銅又は銅合金だけでなく、ニッケル合金、
アルミニウム合金なども用いることもできる。また、薄
膜と厚膜の２層構造によるものだけでなく、１層だけか
ら成るものでも適応できる。この場合は、前述した２回
目の膜付け工程は不要となる。また、絶縁材としては、
導電材層除去時に損傷を受け難いものであればよく、レ
ーザ光の波長等を選択すれば、ポリイミドだけでなく、
セラミックス材、ＰＥＴ材、ＰＰＳ材等の樹脂も使用す
ることができる。Although the above-described circuit has been described with an example in which a copper material is used and a thick copper film is formed on a thin copper film, the circuit can be applied to other types of circuits. For example, circuit materials include not only copper or copper alloy, but also nickel alloy,
An aluminum alloy or the like can also be used. Further, not only a two-layer structure of a thin film and a thick film but also a one-layer structure can be applied. In this case, the second film forming step described above becomes unnecessary. Also, as the insulating material,
Any material that is not easily damaged at the time of removing the conductive material layer may be used.
Resins such as ceramic materials, PET materials, and PPS materials can also be used.
【００１２】本発明は、前述したような、回路を絶縁材
の両面に形成した後、その両面に新たな絶縁シートを貼
り合せる操作を繰返して製造するような基板だけでな
く、回路を絶縁材の片面に形成した後、その片面に新た
な絶縁シートを貼り合せる操作を繰返して製造するよう
な基板にも適用可能である。また、前記のような絶縁シ
ートを貼り合せる毎にその絶縁シートに回路を形成して
製造するような基板だけでなく、所定の回路を形成した
絶縁シートを用い、これを順次積層して製造するような
基板に対しても適用できる。また、製造フローの回数を
変えることにより、１枚の絶縁材からなる基板への回路
形成から多層の基板への回路形成まで幅広く適用できる
ことは言うまでもない。According to the present invention, not only a substrate manufactured by repeating the operation of forming a circuit on both surfaces of an insulating material and then bonding a new insulating sheet to both surfaces as described above, but also a circuit formed of an insulating material. It is also applicable to a substrate manufactured by repeating the operation of forming a new insulating sheet on one side after forming it on one side. In addition, not only a substrate manufactured by forming a circuit on the insulating sheet every time the insulating sheet is bonded as described above, but also an insulating sheet on which a predetermined circuit is formed is sequentially laminated and manufactured. It can be applied to such substrates. In addition, it is needless to say that by changing the number of times of the manufacturing flow, it can be widely applied from circuit formation on a substrate made of one insulating material to circuit formation on a multilayer substrate.
【００１３】また、基板の製造方法によっては、導電材
膜は、前述した無電解めっきなどの湿式めっきや、イオ
ンプレーティングなどの乾式めっきなど広義のめっきで
形成されたものに限定されず、ラミネート形成されたも
のであってもよい。また、無電解めっきで形成する場合
Ｐｄ等による活性点処理を行わず、穴明けシート材にパ
ターンに応じたレーザ照射部を形成した後無電解めっき
すると、レーザ照射部のみにめっき金属が析出するの
で、（Ｃ）（Ｄ）工程を一度に行うことができる。Further, depending on the manufacturing method of the substrate, the conductive material film is not limited to a film formed by plating in a broad sense such as wet plating such as the above-described electroless plating or dry plating such as ion plating. It may be formed. Also, when forming by electroless plating, without performing the active point treatment by Pd or the like, and forming the laser irradiation part according to the pattern on the perforated sheet material and then electroless plating, the plating metal is deposited only on the laser irradiation part. Therefore, the steps (C) and (D) can be performed at once.
【００１４】[0014]
【発明の効果】以上説明したように、本発明によると、
回路形成のための工程が従来の方法に比し半減するの
で、製造のための工数が減少し、製造コストも低下させ
ることができる。また、レジストやエッチング液など廃
棄処理物がなく、環境を考慮した製法でもある。As described above, according to the present invention,
Since the number of steps for forming a circuit is halved compared to the conventional method, the number of steps for manufacturing is reduced, and the manufacturing cost can be reduced. In addition, there is no waste product such as a resist or an etching solution, and the manufacturing method is environmentally friendly.
【図１】本発明による回路形成プロセスの一例を示す図FIG. 1 shows an example of a circuit forming process according to the present invention.
【図２】従来の方法による回路形成プロセスの一例を示
す図FIG. 2 is a diagram showing an example of a circuit forming process according to a conventional method.
１…第１の絶縁材、 ２…第１の基板、 ３…第２の絶
縁材、４…第２の基板、 ５…第３の絶縁材、 ６…５
層の基板、１０、２０、３０、４０、５０…絶縁シー
ト、 １１…穴、１２…銅薄膜、 １２ａ…回路パター
ン形状の銅薄膜、 １２ｂ…回路、１３…レジスト、
５１…スルーホールDESCRIPTION OF SYMBOLS 1 ... 1st insulating material, 2 ... 1st board | substrate, 3 ... 2nd insulating material, 4 ... 2nd board | substrate, 5 ... 3rd insulating material, 6 ... 5
Layer substrate, 10, 20, 30, 40, 50: insulating sheet, 11: hole, 12: copper thin film, 12a: copper thin film having a circuit pattern shape, 12b: circuit, 13: resist,
51 ... Through-hole
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｃ２５Ｄ 7/00 Ｃ２５Ｄ 7/00 Ｊ ５Ｅ３４６ Ｈ０５Ｋ 3/18 Ｈ０５Ｋ 3/18 Ｇ Ｊ 3/46 3/46 Ｂ // Ｂ２３Ｋ 101:42 Ｂ２３Ｋ 101:42 Ｆターム(参考） 4E068 AH00 DA11 4K022 AA15 AA42 BA08 BA31 BA35 BA36 CA12 CA29 DA01 4K024 AA09 AB02 AB08 AB15 AB17 BA12 BB11 DA10 GA16 5E339 AA02 AB02 AC01 AD03 AD05 BC02 BD03 BD05 BD08 BE05 DD03 5E343 AA07 AA18 BB24 BB28 BB44 DD23 DD24 DD25 DD33 DD43 EE42 GG11 5E346 AA15 AA41 CC10 CC32 DD15 DD16 DD17 DD23 DD24 DD32 GG15 HH32 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) C25D 7/00 C25D 7/00 J 5E346 H05K 3/18 H05K 3/18 G J 3/46 3/46 B // B23K 101: 42 B23K 101: 42 F term (reference) 4E068 AH00 DA11 4K022 AA15 AA42 BA08 BA31 BA35 BA36 CA12 CA29 DA01 4K024 AA09 AB02 AB08 AB15 AB17 BA12 BB11 DA10 GA16 5E339 AA02 AB02 AC01 AD03 AD05 BC02 BD03 BD05 BD05 5E343 AA07 AA18 BB24 BB28 BB44 DD23 DD24 DD25 DD33 DD43 EE42 GG11 5E346 AA15 AA41 CC10 CC32 DD15 DD16 DD17 DD23 DD24 DD32 GG15 HH32
Claims (4)
学的作用により除去し、回路を形成することを特徴とす
る回路形成方法。1. A circuit forming method, comprising: removing a predetermined portion of a conductive material layer on an insulating material surface by a non-chemical action to form a circuit.
し、照射箇所の導電材を除去することにより回路を形成
することを特徴とする回路形成方法。2. A circuit forming method, wherein a circuit is formed by irradiating a laser beam to a conductive material layer on an insulating material surface and removing the conductive material at an irradiated portion.
にレーザ光を照射し、照射箇所の導電材を除去すること
により回路パターンを形成し、回路パターン上に第２の
導電材層を形成して回路を形成することを特徴とする回
路形成方法。3. A circuit pattern is formed by irradiating a laser beam to a first conductive material layer formed on a surface of an insulating material and removing the conductive material at an irradiated portion, and forming a second conductive material on the circuit pattern. A circuit forming method, wherein a circuit is formed by forming a layer.
て、絶縁シートを積層する毎に新たな絶縁シートに回路
を形成する請求項１乃至３のいずれかに記載の回路形成
方法。4. The circuit forming method according to claim 1, wherein a circuit is formed on a new insulating sheet each time the insulating sheet is stacked on a substrate in which insulating sheets are stacked in multiple layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001136595A JP2002335065A (en) | 2001-05-07 | 2001-05-07 | Method for forming circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001136595A JP2002335065A (en) | 2001-05-07 | 2001-05-07 | Method for forming circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002335065A true JP2002335065A (en) | 2002-11-22 |
Family
ID=18983843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001136595A Pending JP2002335065A (en) | 2001-05-07 | 2001-05-07 | Method for forming circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002335065A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005290454A (en) * | 2004-03-31 | 2005-10-20 | Advanced Materials Processing Inst Kinki Japan | Method for forming thin film circuit |
| JP2016035998A (en) * | 2014-08-05 | 2016-03-17 | 佳邦科技股▲ふん▼有限公司Ｉｎｐａｑ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ． | Method of manufacturing three-dimensional circuit by laser engraving |
-
2001
- 2001-05-07 JP JP2001136595A patent/JP2002335065A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005290454A (en) * | 2004-03-31 | 2005-10-20 | Advanced Materials Processing Inst Kinki Japan | Method for forming thin film circuit |
| JP2016035998A (en) * | 2014-08-05 | 2016-03-17 | 佳邦科技股▲ふん▼有限公司Ｉｎｐａｑ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ． | Method of manufacturing three-dimensional circuit by laser engraving |
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