JP2002290037A - Method of manufacturing circuit board - Google Patents
Method of manufacturing circuit boardInfo
- Publication number
- JP2002290037A JP2002290037A JP2001083750A JP2001083750A JP2002290037A JP 2002290037 A JP2002290037 A JP 2002290037A JP 2001083750 A JP2001083750 A JP 2001083750A JP 2001083750 A JP2001083750 A JP 2001083750A JP 2002290037 A JP2002290037 A JP 2002290037A
- Authority
- JP
- Japan
- Prior art keywords
- shrinkage
- circuit board
- firing
- conductor layer
- insulating layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、内部導体層を具備
する回路基板において、平面方向での焼成収縮を抑制す
るとともに、焼成に伴うクラックの発生を防止した回路
基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit board having an internal conductor layer, which suppresses firing shrinkage in a planar direction and prevents cracks caused by firing.
【０００２】[0002]
【従来技術】従来、セラミック回路基板は、例えば、ア
ルミナ等のセラミック層間にＷやＭｏ等の高融点金属か
らなる配線導体を形成して構成されており、その表面に
ＬＳＩ等の半導体素子を実装した配線基板として用いら
れてきた。2. Description of the Related Art Conventionally, a ceramic circuit board is formed by forming a wiring conductor made of a high melting point metal such as W or Mo between ceramic layers such as alumina, and mounting a semiconductor element such as an LSI on the surface thereof. Has been used as a wiring board.
【０００３】近年、携帯電話をはじめとする移動体通信
等の発達及び普及に伴い、通信機器や電子機器等の小型
化、高機能化、低価格化、低電力化等が進められ、Ａｕ
やＡｇ、Ｃｕ、Ｐｄ、Ｐｔ等の低融点、低抵抗の導体材
料と、ガラスセラミックス等の低温焼成セラミックスに
より、共振器、コンデンサ、コイル、フィルタ等が形成
されたセラミック回路基板が用いられてきている。In recent years, with the development and spread of mobile communications such as mobile phones, miniaturization, higher functionality, lower cost, lower power, etc. of communication equipment and electronic equipment have been promoted.
A ceramic circuit board on which a resonator, a capacitor, a coil, a filter, and the like are formed using a low-melting-point, low-resistance conductor material such as Ag, Cu, Pd, or Pt and a low-temperature fired ceramic such as glass ceramic has been used. I have.
【０００４】このような回路基板において、基板に形成
される素子は、セラミック絶縁層上に導体材料によって
形成されるラインや電極パッド等の寸法によって性能が
左右される。寸法精度を劣化させる要因としては、焼成
収縮率のバラツキが大きく、特に、低温焼成セラミック
スの焼成収縮率は、１３〜２０％程度と大きいため、収
縮率のバラツキにより、寸法精度が著しく劣化する。[0004] In such a circuit board, the performance of an element formed on the board depends on the dimensions of lines, electrode pads and the like formed of a conductive material on a ceramic insulating layer. As a factor that deteriorates the dimensional accuracy, there is a large variation in the firing shrinkage. In particular, since the firing shrinkage of the low-temperature fired ceramics is as large as about 13 to 20%, the dimensional accuracy is significantly deteriorated due to the variation in the shrinkage.
【０００５】近年においては、回路基板の積層成形体を
Ａｌ2Ｏ3基板等で挟持して焼成する加圧焼成法（特開昭
６２−２６０７７７号公報）や、回路基板の積層成形体
の表面に、この積層成形体の焼成温度では焼結しないグ
リーンシートを積層し、焼成後にそれを削り取る方法
（特開平４−２４３９７８号公報）によって、回路基板
のｘ−ｙ方向における焼成収縮率をほとんど零にし、焼
成収縮率のバラツキによる寸法精度の劣化を防止する方
法が採用されてきている。In recent years, a pressure firing method (Japanese Patent Laid-Open No. 62-260777) in which a laminate of a circuit board is sandwiched between Al 2 O 3 substrates or the like and fired, Then, a green sheet which is not sintered at the firing temperature of the laminated molded body is laminated, and after firing, the green sheet is scraped off (JP-A-4-243978) to reduce the firing shrinkage in the xy direction of the circuit board to almost zero. In addition, a method for preventing deterioration in dimensional accuracy due to variation in firing shrinkage has been adopted.
【０００６】さらに、収縮開始温度の異なる材料を同時
焼成することにより、互いの材料のｘ−ｙ方向の焼成収
縮率を抑制し、電極等の寸法精度の劣化を防止する方法
も提案されている。この方法は、収縮開始温度の低い方
の基板材料が収縮を開始し、他方の基板材料が収縮を開
始してない温度領域では、ｘ−ｙ方向の収縮が抑制され
ｚ方向にだけ収縮し、さらに、収縮開始温度の高い方の
基板材料は、収縮を開始するとき、他方の基板材料の焼
結がほとんど完了しているため、その拘束を受けて、ｘ
−ｙ方向の収縮が抑制されｚ方向にだけ収縮するため
に、全体としてｘ−ｙ方向の収縮を抑制するものであ
る。Further, a method has been proposed in which materials having different shrinkage start temperatures are simultaneously fired, whereby the shrinkage ratios of the materials in the xy directions are suppressed, and deterioration of the dimensional accuracy of the electrodes and the like is prevented. . In this method, in a temperature region in which the lower substrate material of the contraction start temperature starts to contract and the other substrate material does not start to contract, contraction in the xy direction is suppressed and contracts only in the z direction, Further, when the substrate material having the higher shrinkage start temperature starts shrinking, the other substrate material is almost completely sintered, so that it is restrained by x.
Since contraction in the −y direction is suppressed and contraction is performed only in the z direction, the contraction in the xy direction is suppressed as a whole.
【０００７】この方法は、上記２つの方法と比較して、
Ａｌ2Ｏ3基板等が必要なく、また焼結しないグリーンシ
ートを削り取る必要もないため、工程削減によるコスト
ダウンができ、さらに、基板の表裏面に予め配線導体を
形成し、同時焼成できるというメリットがある。This method is different from the above two methods in that
Since there is no need for an Al 2 O 3 substrate or the like, and it is not necessary to cut off a green sheet that does not sinter, the cost can be reduced by reducing the number of processes. There is.
【０００８】上記のようなｘ−ｙ方向の焼成収縮を抑制
した回路基板において、配線導体層は、ほとんど収縮し
ない金属箔を基板に貼りつける方法（特開平７−８６７
４３号）や、厚膜印刷法等によって形成される。In a circuit board in which the shrinkage in firing in the xy directions is suppressed as described above, the wiring conductor layer is formed by attaching a metal foil which hardly shrinks to the board (Japanese Patent Laid-Open No. 7-867).
No. 43) or a thick film printing method.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、ほとん
ど収縮しない金属箔を用いると、基板のｚ方向の収縮に
より、配線導体層近傍のセラミックスに応力が発生し、
焼成降温時の熱衝撃で基板にクラックが生じるという問
題がある。また、基板材料と金属箔の接着性が悪いた
め、界面にデラミネーションが生じ、耐湿信頼性が劣化
するという問題がある。However, when a metal foil that hardly shrinks is used, the shrinkage of the substrate in the z direction generates stress in the ceramics near the wiring conductor layer,
There is a problem that a crack is generated in the substrate due to a thermal shock at the time of firing. In addition, since the adhesion between the substrate material and the metal foil is poor, there is a problem that delamination occurs at the interface, and the moisture resistance reliability is deteriorated.
【００１０】一方、厚膜印刷法によって形成された配線
導体層は、基板材料に入り込みアンカーを形成するた
め、基板材料との接着性は良好である。しかしながら、
焼成における収縮開始温度の異なる材料を用いた基板に
おいて、その異なる材料層間に配線導体層が形成された
場合、厚膜印刷法によって形成された配線導体層は、焼
成過程で大きく収縮するため、異なる基板材料層相互間
のｘ−ｙ方向の焼成収縮抑制効果を阻害するという問題
があった。On the other hand, since the wiring conductor layer formed by the thick film printing method enters the substrate material and forms an anchor, the adhesion to the substrate material is good. However,
In a substrate using materials having different shrinkage onset temperatures in firing, when a wiring conductor layer is formed between different material layers, the wiring conductor layer formed by the thick film printing method shrinks greatly during the firing process, and thus differs. There is a problem in that the effect of suppressing the firing shrinkage in the xy directions between the substrate material layers is hindered.
【００１１】つまり、収縮開始温度の異なる基板材料層
間に、基板の焼成収縮温度領域で大きく収縮する導体材
料からなる配線導体層が配置されると、前述したような
ｘ−ｙ方向の収縮拘束力が弱まり、配線導体層付近では
ｘ−ｙ方向に収縮し、その他の部分ではｘ−ｙ方向に収
縮しないため、配線導体層近傍にクラック等の欠陥が生
じる、あるいは、配線導体層が配置された部分が反る、
歪むといった問題があった。特に、収縮開始温度の異な
る基板材料層間に配置される配線導体層の面積や体積が
大きくなるほど、この傾向は大きくなっていた。In other words, when a wiring conductor layer made of a conductor material that largely shrinks in the firing shrinkage temperature region of the substrate is disposed between the substrate material layers having different shrinkage initiation temperatures, the shrinkage restraining force in the xy direction as described above is obtained. Is weakened, and shrinks in the xy direction near the wiring conductor layer, and does not shrink in the xy direction in other portions. Therefore, defects such as cracks occur near the wiring conductor layer, or the wiring conductor layer is disposed. Part warps,
There was a problem of distortion. In particular, the larger the area and volume of the wiring conductor layer disposed between the substrate material layers having different shrinkage starting temperatures, the larger the tendency.
【００１２】従って、本発明は、焼成収縮開始温度の異
なるセラミック基板材料からなる絶縁層を積層してなる
ｘ−ｙ方向に無収縮のセラミック回路基板において、異
なる絶縁層間に配線導体層を形成した場合においても、
収縮抑制効果を阻害することなく、また、基板の反り、
歪みを抑制でき、かつ、基板にクラックやデラミネーシ
ョンの生じることがない寸法精度に優れた回路基板の製
造方法を提供することを目的とするものである。Therefore, according to the present invention, a wiring conductor layer is formed between different insulating layers in a non-shrinking ceramic circuit board in the x-y direction formed by laminating insulating layers made of ceramic substrate materials having different firing shrinkage starting temperatures. In some cases,
Without hindering the effect of suppressing shrinkage,
It is an object of the present invention to provide a method of manufacturing a circuit board which can suppress distortion and has excellent dimensional accuracy without causing cracks and delamination on the board.
【００１３】[0013]
【課題を解決するための手段】本発明は、焼成収縮開始
温度の異なるセラミック基板材料からなる絶縁層を積層
してなるｘ−ｙ方向に無収縮のセラミック回路基板にお
いて、異なる絶縁層間に配置される配線導体層を焼成収
縮率の小さい導体材料によって形成することによって、
基板の反り、歪み、クラックおよびデラミネーションの
発生を抑制した寸法精度の高い回路基板が得られること
を見いだした。SUMMARY OF THE INVENTION According to the present invention, there is provided a ceramic circuit board which is formed by laminating insulating layers made of ceramic substrate materials having different firing shrinkage starting temperatures and which is not shrunk in the xy directions. By forming the wiring conductor layer from a conductor material having a small firing shrinkage,
It has been found that a circuit board with high dimensional accuracy in which warpage, distortion, cracks and delamination of the board is suppressed can be obtained.
【００１４】即ち、本発明の回路基板の製造方法は、焼
成収縮開始温度がそれぞれＴ１、Ｔ２（Ｔ１＜Ｔ２）か
らなる２種の未焼成のセラミック絶縁層の界面に、導体
材料を塗布して内部導体層を形成した積層体を作製した
後、該積層体の平面方向の収縮を抑制しながら最高焼成
温度Ｔ３で焼成する回路基板の製造方法において、前記
内部導体層をＴ１〜Ｔ３における焼成体積収縮率が１５
％以下の導体材料によって形成することを特徴とするも
のである。That is, in the method of manufacturing a circuit board according to the present invention, a conductive material is applied to the interface between two types of unfired ceramic insulating layers having firing shrinkage starting temperatures T1 and T2 (T1 <T2), respectively. A method for manufacturing a circuit board, comprising: manufacturing a laminate having an internal conductor layer formed thereon, and then firing the laminate at a maximum firing temperature T3 while suppressing shrinkage in the planar direction of the laminate, wherein the internal conductor layer is fired at T1 to T3. 15 shrinkage
% Or less of a conductive material.
【００１５】これによって、内部導体層が存在する部分
が、内部導体層のない部分と同様に、一方の絶縁層が収
縮を開始しても、ｘ−ｙ方向の収縮を抑制し、基板の反
り、歪み、さらに、配線導体層近傍のクラック等の欠陥
を抑制できる。[0015] Thus, even when one of the insulating layers starts to contract, the portion in which the internal conductor layer is present is suppressed from shrinking in the xy direction, and the substrate is warped. , Distortion, and defects such as cracks near the wiring conductor layer can be suppressed.
【００１６】また、前記内部導体層を形成する導体材料
の室温からＴ１まで昇温する過程での焼成体積収縮率が
１０％以下であることによって、導体材料の収縮率が十
分小さく、絶縁層と配線導体層の焼成収縮挙動のミスマ
ッチが小さいため、配線導体層付近でのクラックの発生
や、配線導体層と絶縁層間のデラミネーション等が生じ
ることのない回路基板を得ることができる。The shrinkage rate of the conductive material forming the internal conductor layer in the process of raising the temperature from room temperature to T1 is 10% or less, so that the shrinkage rate of the conductive material is sufficiently small, and Since the mismatch of the firing shrinkage behavior of the wiring conductor layer is small, it is possible to obtain a circuit board free from cracks near the wiring conductor layer and delamination between the wiring conductor layer and the insulating layer.
【００１７】さらに、焼成体積収縮率を前記範囲に制御
する上で、前記内部導体層を構成する導体材料の金属粉
末は、平均粒径が０．５〜５μｍ、ＢＥＴ比表面積が
０．１〜０．７ｍ2／ｇであることによって、微細配線
や配線導体端部の印刷精度のよい内部導体層が得られ、
かつ、基板のｘ−ｙ方向の収縮を抑制し、基板の反り、
歪み、さらに、導体近傍のクラック等の欠陥を抑制でき
る。Further, in controlling the firing volume shrinkage ratio to the above range, the metal powder of the conductor material constituting the inner conductor layer has an average particle size of 0.5 to 5 μm and a BET specific surface area of 0.1 to 5 μm. By being 0.7 m 2 / g, a fine wiring and an inner conductor layer with good printing accuracy at the end of the wiring conductor can be obtained,
In addition, it suppresses the shrinkage of the substrate in the xy directions, and warps the substrate,
Distortion and defects such as cracks near the conductor can be suppressed.
【００１８】また、前記内部導体層を構成する導体材料
としては、Ａｕ、Ａｇ、Ｃｕ、ＰｄおよびＰｔの中から
選ばれる少なくとも１種類以上の導体を主成分とするこ
とが配線導体層の低抵抗化を図る上で望ましい。また、
前記内部導体層を構成する導体材料中に、Ｒｈ及び／あ
るいはＲｕを含有することによって、収縮開始温度や収
縮率を制御できるため、基板のｘ−ｙ方向の収縮を抑制
して、欠陥のない基板を得ることができる。The conductor material constituting the internal conductor layer is preferably composed mainly of at least one kind of conductor selected from Au, Ag, Cu, Pd and Pt. It is desirable in achieving the goal. Also,
By containing Rh and / or Ru in the conductor material constituting the internal conductor layer, the shrinkage start temperature and the shrinkage rate can be controlled, so that the shrinkage of the substrate in the xy direction is suppressed, and there is no defect. A substrate can be obtained.
【００１９】また、前記積層体中に、焼成収縮挙動が異
なる未焼成の絶縁層同士が接する界面が２箇所以上存在
することが互いの絶縁層の焼成収縮を均一に抑制する上
で望ましい。また、界面内に形成された内部導体層の焼
成後の厚みは、３０μｍ以下であることがクラックや剥
離の発生を抑える上で望ましい。It is desirable for the laminated body to have two or more interfaces where unfired insulating layers having different firing shrinkage behavior contact each other in order to uniformly suppress firing shrinkage of the insulating layers. The thickness of the internal conductor layer formed in the interface after firing is preferably 30 μm or less from the viewpoint of suppressing the occurrence of cracks and peeling.
【００２０】なお、本発明の方法は、比誘電率が異なる
２種以上のセラミック絶縁層を積層してなる場合等に有
利である。The method of the present invention is advantageous when two or more types of ceramic insulating layers having different relative dielectric constants are laminated.
【００２１】[0021]
【発明の実施の形態】図１は、本発明による回路基板の
一例の概略断面図を示すもので、図１において、回路基
板１０は、セラミック絶縁層１ａ〜１ｇが積層されたセ
ラミック絶縁基板１と、絶縁基板１の表裏面に形成され
た表面導体層２、基板１の内部に形成された内部導体層
３、導体層間を接続するためのビアホール導体４を有す
る。FIG. 1 is a schematic cross-sectional view of an example of a circuit board according to the present invention. In FIG. 1, a circuit board 10 includes a ceramic insulating substrate 1 on which ceramic insulating layers 1a to 1g are laminated. And a front conductor layer 2 formed on the front and back surfaces of the insulating substrate 1, an internal conductor layer 3 formed inside the substrate 1, and a via-hole conductor 4 for connecting the conductor layers.
【００２２】セラミック絶縁基板１は、焼成収縮挙動が
異なる２種以上のセラミック絶縁層によって形成されて
おり、この図１の回路基板１０では、絶縁層１ａ〜１ｇ
のうち、絶縁層１ａ、１ｇが、他の絶縁層１ｂ〜１ｆと
収縮開始温度が異なるセラミック材料から形成されてい
る。例えば、絶縁層１ａ、１ｇは、収縮開始温度Ｔ１の
セラミック材料ａによって形成され、また他の絶縁層１
ｂ〜１ｆは収縮開始温度Ｔ２のセラミック材料ｂによっ
て形成されており、Ｔ１＜Ｔ２の関係にある。The ceramic insulating substrate 1 is formed of two or more types of ceramic insulating layers having different firing shrinkage behaviors. In the circuit board 10 of FIG. 1, the insulating layers 1a to 1g are provided.
Among them, the insulating layers 1a and 1g are formed of a ceramic material having a different shrinkage start temperature from the other insulating layers 1b to 1f. For example, the insulating layers 1a and 1g are formed of a ceramic material a having a shrinkage start temperature T1.
b to 1f are formed of the ceramic material b at the contraction start temperature T2, and have a relationship of T1 <T2.
【００２３】本発明の上記の回路基板１０は、焼成収縮
挙動が異なる、特に焼成収縮開始温度が異なる２種以上
のセラミック絶縁層１ａ〜１ｇの積層構造によって、焼
成収縮開始温度Ｔ１のセラミック絶縁層１ａ、１ｇがＴ
１到達後に焼結収縮する時、焼成収縮開始温度Ｔ２のセ
ラミック絶縁層１ｂ〜１ｆが平面方向の収縮を抑制し、
セラミック絶縁層１ｂ〜１ｆがＴ２到達後に、最高焼成
温度Ｔ３に保持されて焼成収縮する時、焼成によって収
縮が完了した焼成収縮開始温度Ｔ１のセラミック絶縁層
１ａ、１ｇによって平面方向の収縮が抑制される結果、
回路基板全体として平面方向の収縮が抑制された高寸法
精度の回路基板が得られる。The circuit board 10 of the present invention has a laminated structure of two or more types of ceramic insulating layers 1a to 1g having different firing shrinkage behaviors, particularly different firing shrinkage start temperatures. 1a and 1g are T
When sintering shrinks after reaching 1, the ceramic insulating layers 1b to 1f at the firing shrinkage start temperature T2 suppress shrinkage in the planar direction,
After the ceramic insulating layers 1b to 1f reach T2 and shrink while being held at the highest firing temperature T3, shrinkage in the planar direction is suppressed by the ceramic insulating layers 1a and 1g at the firing shrinkage starting temperature T1 where shrinkage is completed by firing. As a result,
A circuit board with high dimensional accuracy in which shrinkage in the planar direction is suppressed for the entire circuit board is obtained.
【００２４】このような回路基板１０において、本発明
によれば、焼成収縮挙動が異なる２種のセラミック絶縁
層の界面、即ち、絶縁層１ａと絶縁層１ｂとの界面に存
在する導体層３ａ、絶縁層１ｇと絶縁層１ｆとの界面に
存在する導体層３ｂを、いずれも低い方の焼成収縮開始
温度Ｔ１から最高焼成温度Ｔ３までの温度領域における
焼成体積収縮率が１５％以下の導体材料によって形成す
ることが必要である。これは、導体材料の焼成による体
積収縮率が１５％を超えると、導体材料のｘ−ｙ方向の
焼成収縮が大きくなりすぎ、絶縁層１ａ、１ｇと絶縁層
１ｂ〜１ｆの界面におけるｘ−ｙ方向の焼成収縮の拘束
力が弱くなり、内部導体層３ａ、３ｂ近傍の絶縁層にク
ラックが生じる、あるいは、内部導体層３ａ、３ｂ近傍
の絶縁層が反る、歪むといった問題が生じるからであ
る。とりわけ、基板の反り、歪みの観点から、導体材料
の焼成による体積収縮率は１０％以下であることが望ま
しい。In such a circuit board 10, according to the present invention, the conductor layer 3a, which exists at the interface between the two types of ceramic insulating layers having different firing shrinkage behavior, that is, at the interface between the insulating layers 1a and 1b, The conductor layer 3b existing at the interface between the insulating layer 1g and the insulating layer 1f is made of a conductive material having a firing volume shrinkage of 15% or less in a temperature range from the lower firing shrinkage starting temperature T1 to the highest firing temperature T3. It is necessary to form. This is because, when the volume shrinkage due to the firing of the conductive material exceeds 15%, the firing shrinkage of the conductive material in the x-y direction becomes too large, and the x-y at the interface between the insulating layers 1a and 1g and the insulating layers 1b to 1f. This is because the binding force of the firing shrinkage in the direction becomes weak, and cracks occur in the insulating layers near the internal conductor layers 3a and 3b, or the insulating layers near the internal conductor layers 3a and 3b are warped or distorted. . In particular, from the viewpoints of substrate warpage and distortion, it is desirable that the volume shrinkage due to firing of the conductive material be 10% or less.
【００２５】また、絶縁層１ａと絶縁層１ｂに挟まれた
内部導体層３ａ、絶縁層１ｆと絶縁層１ｇに挟まれた内
部導体層３ｂを構成する導体材料は、室温からＴ１まで
昇温する過程での焼成体積収縮率が１０％以下であるこ
とが望ましい。The temperature of the conductor material constituting the internal conductor layer 3a sandwiched between the insulating layers 1a and 1b and the internal conductor layer 3b sandwiched between the insulating layers 1f and 1g rises from room temperature to T1. The firing volume shrinkage rate in the process is desirably 10% or less.
【００２６】これは、導体材料がＴ１到達までに１０％
を超えて体積収縮してしまうと、絶縁層１ａ、１ｇが焼
成収縮を開始する前に、内部導体層３ａ、３ｂと絶縁層
１ａ、１ｇの間に隙間が生じるため、ｘ−ｙ方向の拘束
力が弱まる、あるいは、上記隙間が生じない場合には、
絶縁層１ａ、１ｂ、１ｆ、１ｇにクラックが生じる等の
問題があるからである。とりわけ、デラミネーションや
クラック防止の観点から、絶縁層のＴ１以下での導体材
料の焼成による体積収縮率は６％以下が望ましい。This is because the conductor material is 10% by the time T1 is reached.
When the volume shrinks beyond the limit, a gap is formed between the internal conductor layers 3a, 3b and the insulating layers 1a, 1g before the insulating layers 1a, 1g start firing shrinkage. If the force weakens or the gap does not occur,
This is because there is a problem that cracks occur in the insulating layers 1a, 1b, 1f, and 1g. In particular, from the viewpoint of preventing delamination and cracking, it is desirable that the volume shrinkage of the insulating layer by firing the conductive material at T1 or less is 6% or less.
【００２７】さらに、この内部導体層３ａ、３ｂを構成
する導体材料は、金属粉末、あるいは金属粉末とガラス
などの添加成分とからなり、これらに有機バインダーや
溶媒を加えてペースト状にして塗布し、焼成することに
よって形成されるが、この導体材料に配合する金属粉末
の平均粒径が０．５〜５μｍであり、またＢＥＴ比表面
積が０．１〜０．７ｍ2／ｇであることが望ましい。こ
れは、平均粒径が０．５μｍ未満になると、焼成におけ
る収縮率が大きくなりすぎ、絶縁層にクラックが生じ
る、あるいは、基板に反り、歪みが生じるからであり、
５μｍを超えると、粒径が大きすぎるため、微細配線や
配線端部の印刷精度が劣化するからである。また、ＢＥ
Ｔ比表面積が０．１ｍ2／ｇ未満になると、粉末の表面
エネルギーが低くなり、焼結しにくくなるからであり、
０．７ｍ2／ｇを超えると、粉末の表面エネルギーが高
くなり、焼成における収縮率が大きくなりすぎる、ある
いは、焼成における収縮開始温度が低くなりすぎるから
である。とりわけ、焼成における収縮率、焼結性、印刷
精度の観点から、金属粉末の平均粒径は１〜３μｍ、Ｂ
ＥＴ比表面積は０．１〜０．３ｍ2／ｇが好ましい。Further, the conductor material constituting the inner conductor layers 3a and 3b is composed of metal powder or an additive component such as metal powder and glass. The metal powder mixed with the conductor material has an average particle size of 0.5 to 5 μm and a BET specific surface area of 0.1 to 0.7 m 2 / g. desirable. This is because, when the average particle size is less than 0.5 μm, the shrinkage ratio during firing becomes too large, cracks are generated in the insulating layer, or the substrate is warped and strained,
If the thickness exceeds 5 μm, the particle size is too large, and the printing accuracy of fine wiring and wiring end portions deteriorates. Also, BE
If the T specific surface area is less than 0.1 m 2 / g, the surface energy of the powder becomes low, and sintering becomes difficult.
If it exceeds 0.7 m 2 / g, the surface energy of the powder increases, and the shrinkage ratio during firing becomes too large, or the shrinkage starting temperature during firing becomes too low. In particular, from the viewpoints of shrinkage ratio in sintering, sinterability, and printing accuracy, the average particle size of the metal powder is 1 to 3 μm, and B
ET specific surface area 0.1~0.3m 2 / g are preferred.
【００２８】また、内部導体層３ａ、３ｂを構成する導
体材料は、Ａｕ、Ａｇ、Ｃｕ、Ｐｄ、Ｐｔの中から選ば
れる少なくとも１種以上の金属を主成分とすることが望
ましい。これは、上記のような低抵抗の金属材料を用い
ることにより、低抵抗の回路が形成できるため、素子の
消費電力を低減でき、また、λ／４ストリップライン共
振器等の高周波回路を基板内部に形成した場合にも、挿
入損失が小さい等の優れた特性の回路を得ることができ
るからである。とりわけ、回路特性の観点から、Ａｇ、
Ａｕ、Ｃｕが好ましい。It is desirable that the conductor material constituting the internal conductor layers 3a and 3b contains at least one metal selected from Au, Ag, Cu, Pd and Pt as a main component. This is because a low-resistance circuit can be formed by using a low-resistance metal material as described above, so that the power consumption of the element can be reduced, and a high-frequency circuit such as a λ / 4 strip line resonator is mounted inside the substrate. This is because a circuit having excellent characteristics such as a small insertion loss can be obtained even when the circuit is formed as described above. Above all, from the viewpoint of circuit characteristics, Ag,
Au and Cu are preferred.
【００２９】また、導体材料中に、Ｒｈ及び／あるい
は、Ｒｕを添加含有することが望ましい。これは、Ｒｈ
やＲｕには、上記金属粉末の収縮を抑制する効果があ
り、収縮開始温度や焼成体積収縮率を制御できるため、
基板のｘ−ｙ方向の収縮を抑制して、欠陥のない基板を
得ることができるからである。Ｒｈ、Ｒｕの供給源とし
て、有機物、酸化物、金属等があり、これらは、導体材
料中に金属換算で０．０１〜５重量％の割合で配合する
ことが適当である。It is desirable that Rh and / or Ru be added to the conductor material. This is Rh
And Ru have the effect of suppressing the shrinkage of the metal powder, and can control the shrinkage start temperature and the firing volume shrinkage ratio.
This is because a substrate free from defects can be obtained by suppressing shrinkage of the substrate in the xy directions. As sources of Rh and Ru, there are organic substances, oxides, metals and the like, and it is appropriate to mix these in the conductor material at a ratio of 0.01 to 5% by weight in terms of metal.
【００３０】また、この導体層３ａ、３ｂの厚みは３０
μｍ以下、特に２５μｍ以下であることが望ましい。こ
れは、界面に存在する導体層３ａ、３ｂの厚みが厚くな
りすぎると、導体層３ａ、３ｂ自体の収縮を制御するこ
とが難しくなる結果、収縮が抑制された絶縁層間で応力
が発生し、導体層３ａ、３ｂの剥離や絶縁層間の剥離を
引き起こすおそれがあるためである。The thickness of the conductor layers 3a and 3b is 30
It is desirable that it is not more than 25 μm, especially not more than 25 μm. This is because if the thickness of the conductor layers 3a and 3b existing at the interface is too large, it becomes difficult to control the contraction of the conductor layers 3a and 3b itself, and as a result, stress is generated between the insulating layers where the contraction is suppressed, This is because there is a possibility that peeling of the conductor layers 3a and 3b and peeling between the insulating layers may occur.
【００３１】また、両絶縁層１ａ−１ｂ、１ｇ−１ｆ同
士の拘束力を高める上では、界面の導体層３ａ、３ｂ
は、絶縁層１ａ、１ｂ、１ｇ、１ｆの周縁から０．２ｍ
ｍ以上、特に０．５ｍｍ以上内側領域に形成することが
望ましい。これは、焼成収縮挙動が異なる２つの絶縁層
が周縁部で互いに結合することができるために、焼成収
縮抑制効果を均一化することができるために、クラック
などの発生をさらに防止することができる。In order to increase the binding force between the insulating layers 1a-1b, 1g-1f, the conductor layers 3a, 3b
Is 0.2 m from the periphery of the insulating layers 1a, 1b, 1g, 1f.
It is desirable to form it in an area not less than m, especially not less than 0.5 mm. This is because two insulating layers having different firing shrinkage behaviors can be bonded to each other at the peripheral portion, and the effect of suppressing firing shrinkage can be made uniform, so that the occurrence of cracks and the like can be further prevented. .
【００３２】なお、本発明において、上記焼成体積収縮
率を制御された導体材料は、焼成収縮開始温度が異なる
界面の内部導体層３ａ、３ｂのみならず、同一材料の絶
縁層間、表面導体層、裏面導体層に適用することも当然
可能である。In the present invention, the conductor material whose sintering volume shrinkage rate is controlled includes not only the inner conductor layers 3a and 3b at the interfaces where the sintering shrinkage initiation temperatures are different, but also the insulating layer, the surface conductor layer, and the same material. Of course, it is also possible to apply to the back conductor layer.
【００３３】なお、焼成収縮挙動が異なる２種のセラミ
ック材料ａ、ｂの積層順序は、図１の回路基板では、ａ
ｂｂｂｂｂａにて積層したが、ａｂａｂａｂ、ａａａｂ
ａａａ、ａａｂｂｂａａ、ａａｂａｂａａ、ａａｂｂａ
ａａ、ａｂａａａａａのいずれでもよく、また、ａとｂ
とを反対に入れ換えてもよい。ただし、焼成収縮挙動の
異なる絶縁層同士が接する界面が１箇所では、拘束力の
偏在によって回路基板に反りが発生する場合があるため
に、界面が２箇所以上、特に偶数箇所に存在することが
望ましい。または界面が２箇所以上存在する場合、回路
基板の厚み中心に対して対称的な位置に界面が存在する
ことが望ましい。The order of lamination of the two types of ceramic materials a and b having different firing shrinkage behaviors is as follows in the circuit board of FIG.
bbbbba was laminated, but ababab, aaab
aaa, aabbbbaa, aababaa, aabba
aa or abaaaaaa, and a and b
And may be interchanged. However, if there is one interface where the insulating layers having different firing shrinkage behavior contact each other, the circuit board may be warped due to uneven distribution of the restraining force. Therefore, the interface may be present at two or more locations, especially at even locations. desirable. Alternatively, when there are two or more interfaces, it is desirable that the interfaces be symmetrical with respect to the thickness center of the circuit board.
【００３４】本発明における絶縁基板１を構成するセラ
ミック材料は、絶縁体、誘電体、磁性体のいずれでも良
く、焼成収縮開始温度が異なる少なくとも２種のセラミ
ック材料は、例えば異なる組成のセラミック材料であっ
たり、組成が全く同一であってセラミック粒子の粒度分
布や比表面積の相違によって焼成収縮開始温度が異なる
セラミック材料であってもよい。特に組成が異なること
が最も焼成収縮開始温度の制御が容易であり、あらゆる
要求特性に対応できる。なお、焼成収縮開始温度が異な
る２種以上のセラミック材料は、例えば、焼結収縮開始
温度の相違のみならず、目的に応じて、比誘電率が異な
る、強度が異なる、誘電損失が異なるなどの他の特性が
異なっていてもよい。The ceramic material constituting the insulating substrate 1 in the present invention may be any of an insulator, a dielectric, and a magnetic material. At least two types of ceramic materials having different firing shrinkage starting temperatures are, for example, ceramic materials having different compositions. Alternatively, ceramic materials having exactly the same composition but different firing start temperatures due to differences in the particle size distribution and specific surface area of the ceramic particles may be used. In particular, when the compositions are different, the control of the firing shrinkage starting temperature is the easiest, and it can meet all required characteristics. In addition, two or more types of ceramic materials having different firing shrinkage temperatures include, for example, different dielectric constants, different strengths, different dielectric losses, etc., depending on the purpose as well as the difference in sintering shrinkage start temperatures. Other characteristics may be different.
【００３５】また、このセラミック材料は、前記の低抵
抗の導体層と同時焼成が可能であることが望ましいため
に、１０５０℃以下の低温で焼成可能なセラミック材
料、とりわけ、大気中で焼成できるＡｇと同時焼成が可
能な９６０℃以下、特に９２０℃以下で焼成が可能なセ
ラミック材料が良い。Since it is desirable that this ceramic material can be co-fired with the low-resistance conductor layer, a ceramic material that can be fired at a low temperature of 1050 ° C. or less, especially Ag that can be fired in the air. A ceramic material that can be fired at 960 ° C. or lower, particularly 920 ° C. or lower, which can be fired simultaneously, is preferable.
【００３６】上記のような低温焼成セラミック材料とし
ては、ガラス粉末系、ガラス粉末とセラミック粉末との
混合粉末系、酸化物粉末混合系などの周知の低温焼成セ
ラミック材料が用いられる。なお、上記ガラスとして
は、非晶質ガラス、結晶化ガラスのいずれでもよい。例
えば、ガラス粉末５０〜１００重量部とセラミック粉末
０〜５０重量部からなることが望ましい。As the low-temperature fired ceramic material as described above, a well-known low-temperature fired ceramic material such as a glass powder, a mixed powder of a glass powder and a ceramic powder, and a mixed oxide powder may be used. The glass may be either amorphous glass or crystallized glass. For example, it is desirable that the powder comprises 50 to 100 parts by weight of glass powder and 0 to 50 parts by weight of ceramic powder.
【００３７】ガラス粉末の具体的な組成例としては、こ
れに限られるものではないが、例えば、ＳｉＯ2２０〜
７０重量部、Ａｌ2Ｏ3０．５〜３０重量部、ＭｇＯ３〜
６０重量部、任意成分として、ＣａＯ０〜３５重量部、
ＢａＯ０〜３０重量部、ＳｒＯ０〜３０重量部、Ｂ2Ｏ3
０〜２０重量部、ＺｎＯ０〜３０重量部、ＴｉＯ2０〜
１０重量部、Ｎａ2Ｏ０〜３重量部、Ｌｉ2Ｏ０〜５重量
部を含むものが挙げられる。[0037] As specific composition examples of the glass powder include, but are not limited to, for example, SiO 2. 20 to
70 parts by weight, Al 2 O 3 0.5~30 weight parts, MgO3～
60 parts by weight, as an optional component, 0 to 35 parts by weight of CaO,
0-30 parts by weight of BaO, 0-30 parts by weight of SrO, B 2 O 3
0-20 parts by weight, ZnO 0-30 parts by weight, TiO 2 0
10 parts by weight, Na 2 O0~3 parts, include those containing Li 2 O0~5 parts.
【００３８】また、セラミック粉末としては、Ａｌ
2Ｏ3、ＳｉＯ2、ＭｇＴｉＯ3、ＣａＺｒＯ3、ＣａＴｉ
Ｏ3、Ｍｇ2ＳｉＯ4、ＢａＴｉ4Ｏ9、ＺｒＴｉＯ4、Ｓｒ
ＴｉＯ3、ＢａＴｉＯ3、ＴｉＯ2から選ばれる１種以上
が挙げられる。As the ceramic powder, Al is used.
2 O 3 , SiO 2 , MgTiO 3 , CaZrO 3 , CaTi
O 3 , Mg 2 SiO 4 , BaTi 4 O 9 , ZrTiO 4 , Sr
One or more selected from TiO 3 , BaTiO 3 , and TiO 2 may be used.
【００３９】上記組成のガラス粉末とセラミック粉末と
の組み合わせによれば、１０００℃以下での低温焼結が
可能となるとともに、導体層として、Ｃｕ、Ａｇ、Ａｕ
などの低抵抗導体を用いて形成することが可能となり、
また、低誘電率化も可能であり、高速伝送化に適してい
る。しかも、上記の範囲で種々組成を制御することによ
って、焼成収縮挙動を容易に制御、変更することができ
る。According to the combination of the glass powder and the ceramic powder having the above composition, sintering at a low temperature of 1000 ° C. or less is possible, and Cu, Ag, Au
It can be formed using a low resistance conductor such as
Further, the dielectric constant can be reduced, which is suitable for high-speed transmission. In addition, by controlling various compositions within the above range, the firing shrinkage behavior can be easily controlled and changed.
【００４０】本発明の回路基板の製造方法についてより
具体的に説明すると、上記焼成収縮挙動が異なる２種以
上のセラミック材料、たとえば焼成収縮開始温度Ｔ１
（℃）のセラミック材料ａ、焼成収縮開始温度Ｔ２
（℃）のセラミック材料ｂからなり、Ｔ１＜Ｔ２の関係
にあるセラミック材料を準備し、各セラミック材料を用
いてグリーンシートＡ、Ｂを作製する。グリーンシート
Ａ、Ｂは、所定のセラミック粉末組成物と有機バインダ
ーと有機溶剤及び必要に応じて可塑剤とを混合し、スラ
リー化する。このスラリーを用いてドクターブレード法
などによりテープ成形を行い、所定寸法に切断しグリー
ンシートを作製する。The method for manufacturing a circuit board according to the present invention will be described in more detail.
(° C.) ceramic material a, firing shrinkage start temperature T2
A ceramic material b of (° C.) and having a relationship of T1 <T2 is prepared, and green sheets A and B are manufactured using each ceramic material. The green sheets A and B are made into a slurry by mixing a predetermined ceramic powder composition, an organic binder, an organic solvent, and, if necessary, a plasticizer. Using this slurry, a tape is formed by a doctor blade method or the like, and cut into a predetermined size to produce a green sheet.
【００４１】次に、このグリーンシートＡ、Ｂにパンチ
ングなどによって貫通孔を形成し、その貫通孔内に導体
ペーストを充填し、表面導体層や内部導体層および電極
導体層を所定の導体材料を用いてペースト化したものを
スクリーン印刷法などによって被着形成する。その際
に、導体材料として、Ｔ１から焼成最高温度Ｔ３までの
焼成体積収縮率が１５％以下となるように、導体組成、
導体の粉末粒径や比表面積などを制御する。Next, through-holes are formed in the green sheets A and B by punching or the like, and a conductive paste is filled in the through-holes. The surface conductive layer, the internal conductive layer, and the electrode conductive layer are made of a predetermined conductive material. The paste that is used is adhered and formed by a screen printing method or the like. At that time, the conductor composition and the conductor material were selected so that the firing volume shrinkage from T1 to the highest firing temperature T3 was 15% or less.
It controls the powder size and specific surface area of the conductor.
【００４２】このようにして得られた各グリーンシート
Ａ、Ｂを、所定の積層順序に応じて積層して積層成形体
を形成した後、焼成する。The green sheets A and B thus obtained are laminated in a predetermined lamination order to form a laminated molded body, and then fired.
【００４３】また、積層成形体の製造方法としては、所
定の基板表面にセラミックペーストおよび導体ペースト
を順次塗布することにより積層化したり、セラミック材
料と光硬化性樹脂を含有するスリップ材を塗布乾燥し、
露光、硬化、現像を行い、さらに前記スリップ材を塗布
乾燥、露光、硬化、現像を繰り返して積層成形体を作成
しても良い。この場合に、必要に応じて現像して絶縁層
成形体に形成された貫通孔内に導電性ペーストを充填し
たり、絶縁層成形体表面に導体ペーストを用いて内部導
体層を形成してもよい。As a method of manufacturing a laminated molded body, a ceramic paste and a conductive paste are sequentially applied to a predetermined substrate surface to laminate the laminate, or a slip material containing a ceramic material and a photocurable resin is applied and dried. ,
Exposure, curing, and development may be performed, and the slip material may be coated, dried, exposed, cured, and developed repeatedly to form a laminated molded article. In this case, if necessary, the conductive paste may be filled into the through-holes formed in the insulating layer molded body by developing, or the internal conductive layer may be formed on the surface of the insulating layer molded body using the conductive paste. Good.
【００４４】焼成にあたっては、まず、収縮開始温度が
低いシートＡの収縮開始温度ＳAに到達後、徐々に昇温
するか、焼成収縮開始温度ＳAよりも高く、シートＢの
焼成収縮開始温度ＳBよりも低い温度で、一次的に炉内
温度を保持してシートＡを焼成収縮させる。この時、シ
ートＡは、その温度で焼成収縮しないシートＢによって
ｘ−ｙ方向への収縮が抑制されｚ方向に焼成収縮する。In firing, first, after reaching the shrinkage start temperature S A of the sheet A whose shrinkage start temperature is low, the temperature is gradually increased or is higher than the bake shrinkage start temperature S A , and the bake shrinkage start temperature of the sheet B is increased. at a temperature lower than the S B, to firing shrinkage of sheet a holds temporarily furnace temperature. At this time, the sheet A shrinks in the xy direction and shrinks in the z direction by the sheet B that does not shrink at firing at that temperature.
【００４５】その後、シートＡの焼結が進行し、望まし
くは最終焼成体積収縮量の９０％以上収縮した後、シー
トＢの焼結開始温度ＳB以上に昇温して焼成する。この
焼成によって、シートＢは、焼結がほぼ完了したシート
Ａによってｘ−ｙ方向への焼成収縮が抑制されｚ方向に
焼成収縮する。その結果、シートＡおよびシートＢとも
にｘ−ｙ方向への焼成収縮が抑制されｚ方向に焼成収縮
した、寸法精度の高い基板を作製することができる。[0045] Thereafter, the sintering process advances sheet A, preferably after 90% shrinkage of the final sintered volumetric shrinkage amount, calcined by heating to above the sintering start temperature S B of sheet B. By this firing, the sheet B, which has been substantially sintered, suppresses shrinkage in the xy directions and shrinks in the z direction. As a result, it is possible to manufacture a substrate with high dimensional accuracy, in which both the sheet A and the sheet B are suppressed from firing shrinkage in the xy directions and shrinkage in the z direction.
【００４６】[0046]
【実施例】以下の方法により、図１の構造の回路基板を
作製した。まず、ＳｉＯ2−Ａｌ2Ｏ3−ＭｇＯ−ＺｎＯ
−ＢａＯ−Ｂ2Ｏ3ガラス粉末８２重量％と、平均粒径が
約１μｍのＳｉＯ2粉末１８重量％からなるセラミック
材料ａ（焼成収縮開始温度７６０℃、比誘電率６．５）
と、モル比で０．９２ＭｇＴｉＯ3−０．０８ＣａＴｉ
Ｏ3の主成分１００重量部に対して、Ｂ2Ｏ3１４重量
部、Ｌｉ2ＣＯ3７重量部、ＳｉＯ2０．０１重量部、Ｂ
ａＯ１．６重量部、Ａｌ2Ｏ3０．５重量部、ＭｎＯ
2１．５重量部からなる平均粒径が約１μｍのセラミッ
ク材料ｂ（焼成収縮開始温度８５０℃、比誘電率１９）
を準備した。このセラミック材料ａ、ｂに対して各々バ
インダー等を混練したスラリーをドクターブレード法に
てグリーンシートａ、ｂに加工した。EXAMPLE A circuit board having the structure shown in FIG. 1 was manufactured by the following method. First, SiO 2 —Al 2 O 3 —MgO—ZnO
2 and O 3 glass powder 82 wt% -BaO-B, average particle size ceramic material a of SiO 2 powder 18 weight percent to about 1 [mu] m (firing shrinkage initiation temperature of 760 ° C., a dielectric constant 6.5)
And a molar ratio of 0.92 MgTiO 3 -0.08 CaTi
Relative to 100 parts by weight of the main component of O 3, B 2 O 3 14 parts by weight, Li 2 CO 3 7 parts by weight, SiO 2 0.01 part by weight, B
1.6 parts by weight of aO, 0.5 parts by weight of Al 2 O 3 , MnO
2 Ceramic material b consisting of 1.5 parts by weight and having an average particle size of about 1 μm (firing shrinkage start temperature 850 ° C., relative dielectric constant 19)
Was prepared. A slurry obtained by kneading a binder and the like with each of the ceramic materials a and b was processed into green sheets a and b by a doctor blade method.
【００４７】層構成は、ａｂｂｂｂｂａとして、各シー
トに貫通孔を形成し、その貫通孔内にＡｇ粉末を含む導
体ペーストを充填した。そして、各グリーンシートの表
面に上記の導体ペーストを用いて表面導体層、内部導体
層および裏面導体層を印刷形成した。The layer structure was abbbbba, in which a through hole was formed in each sheet, and the through hole was filled with a conductive paste containing Ag powder. Then, a surface conductor layer, an internal conductor layer, and a back surface conductor layer were printed on the surface of each green sheet using the conductor paste described above.
【００４８】これらのグリーンシートを位置合わせした
後、積層して積層成形体を作製し、これを大気中４００
℃で脱バインダー処理し、さらに、大気中で９１０℃
（＝Ｔ 3）で焼成し、セラミック回路基板を作製した。These green sheets were aligned.
Thereafter, lamination is performed to produce a laminated molded body, which is
Debinding treatment at 910 ° C.
(= T Three) To produce a ceramic circuit board.
【００４９】なお、ここで、各シートの厚みはすべて
０．１０ｍｍとした。また、シートＡとシートＢ間に位
置する内部導体層を形成する導体材料として、銀粉末を
用い、有機ビヒクルと界面活性剤を添加して、銀粉末の
凝集体がなくなるまで３本ロールミルで混合しペースト
化した。The thickness of each sheet was 0.10 mm. In addition, silver powder was used as a conductor material for forming an internal conductor layer located between sheet A and sheet B, an organic vehicle and a surfactant were added, and the mixture was mixed with a three-roll mill until the aggregates of silver powder disappeared. And then turned into a paste.
【００５０】なお、導体材料中の、銀粉末の粒径、比表
面積、充填密度を表１のように変えることにより、焼成
温度プロファイルに基づき、Ｔ1到達時点、Ｔ1〜Ｔ3の
各焼成体積収縮率を表１のように変化させた。導体材料
の焼成体積収縮率は、導体材料をフィルム上に塗布して
乾燥させ、各温度で処理後の寸法から体積をもとめ、初
期体積値に対する比率を焼成体積収縮率として求めた。
また、各シートの導体層の形成は、各グリーンシートの
周縁から０．５ｍｍ以上内側の領域に形成した。[0050] Incidentally, in the conductive material, silver powder having a particle size, specific surface area, by varying as shown in Table 1 the packing density, based on the firing temperature profile, T 1 reaches point, the firing of T 1 through T 3 The volume shrinkage was changed as shown in Table 1. The firing volume shrinkage of the conductive material was determined by applying the conductive material onto a film, drying the film, measuring the volume from the dimensions after processing at each temperature, and calculating the ratio to the initial volume value as the firing volume shrinkage.
The conductor layer of each sheet was formed in a region 0.5 mm or more inside the periphery of each green sheet.
【００５１】作製した回路基板に対して平面方向の収縮
率（ｘ方向、ｙ方向の収縮率の平均値）と、クラックの
有無、反り量を評価した。With respect to the produced circuit board, the shrinkage in the plane direction (average value of the shrinkage in the x and y directions), the presence or absence of cracks, and the amount of warpage were evaluated.
【００５２】ここで、回路基板の側面、表面、あるいは
研磨した研磨面において、金属顕微鏡あるいは走査型電
子顕微鏡（ＳＥＭ）によって、シートＡ、シートＢ界面
の剥離や界面付近でのクラックの有無を調べた。反り量
は、シートＡ、Ｂ間に形成した７ｍｍ角の導体層の付近
の表面を表面粗さ計を用いて表面粗さを測定して、最
大、最小の差を反りとして表１に示した。Here, on the side surface, surface, or polished surface of the circuit board, the presence or absence of peeling at the interface between the sheets A and B and cracks near the interface is examined using a metal microscope or a scanning electron microscope (SEM). Was. The amount of warpage is shown in Table 1 by measuring the surface roughness of the surface near the 7 mm square conductor layer formed between sheets A and B using a surface roughness meter, and using the difference between the maximum and the minimum as the warpage. .
【００５３】[0053]
【表１】 [Table 1]
【００５４】この表１から、本発明の試料は、Ｘ−Ｙ収
縮率が０．３％以下と小さく、しかも異種材料絶縁層及
び他の絶縁層と、導体層の間に層間剥離や内部導体層近
傍の絶縁層にクラック等の発生がなく、基板反りも１０
０μｍ以下と小さいことがわかる。一方、内部導体層の
焼成体積収縮率が１５％よりも大きいと、Ｘ−Ｙ収縮率
が本発明品よりも大きく、しかも層間剥離やクラックの
発生が認められるとともに、基板反りも３００μｍ以上
と大きいものであった。From Table 1, it can be seen that the sample of the present invention has a small XY shrinkage of 0.3% or less, and has a delamination or internal conductor between the different material insulating layer and other insulating layers and the conductive layer. No cracks or the like occur in the insulating layer near the layer, and the substrate warpage is 10
It can be seen that it is as small as 0 μm or less. On the other hand, when the firing volume shrinkage of the inner conductor layer is larger than 15%, the XY shrinkage is larger than that of the product of the present invention, and delamination and cracks are observed, and the substrate warpage is as large as 300 μm or more. Was something.
【００５５】[0055]
【発明の効果】以上の通り、本発明によれば、焼成収縮
挙動が異なる２種以上のセラミック絶縁層を積層してな
り、その絶縁層の界面に配設される導体層の焼成収縮率
を小さくすることによって、クラックや界面での剥離の
発生、さらには反りの発生を防止することができる。そ
の結果、焼成収縮挙動の相違を利用した寸法精度の高い
回路基板を作製することができる。As described above, according to the present invention, two or more types of ceramic insulating layers having different firing shrinkage behavior are laminated, and the firing shrinkage of the conductor layer disposed at the interface between the insulating layers is reduced. By reducing the size, occurrence of cracks and peeling at the interface, and further, occurrence of warpage can be prevented. As a result, a circuit board with high dimensional accuracy utilizing the difference in firing shrinkage behavior can be manufactured.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明のセラミック回路基板の一例を示す概略
断面図を示す。FIG. 1 is a schematic sectional view showing an example of a ceramic circuit board of the present invention.
１０・・・回路基板 １・・・絶縁層 ２・・・表面導体層 ３・・・内部導体層 ４・・・ビアホール導体 DESCRIPTION OF SYMBOLS 10 ... Circuit board 1 ... Insulating layer 2 ... Surface conductor layer 3 ... Inner conductor layer 4 ... Via hole conductor
───────────────────────────────────────────────────── フロントページの続き (72)発明者 井本 晃 鹿児島県国分市山下町１番４号 京セラ株 式会社総合研究所内 Ｆターム(参考） 5E346 AA15 AA38 AA43 BB01 BB02 CC17 CC18 CC31 CC32 CC38 CC39 DD13 EE27 EE29 HH11 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akira Imoto 1-4 term Yamashita-cho, Kokubu-shi, Kagoshima F-term in Kyocera Research Institute (reference) 5E346 AA15 AA38 AA43 BB01 BB02 CC17 CC18 CC31 CC32 CC38 CC39 DD13 EE27 EE29 HH11
Claims (8)
（Ｔ１＜Ｔ２）からなる２種の未焼成のセラミック絶縁
層の界面に、導体材料を塗布して内部導体層を形成した
積層体を作製した後、該積層体の平面方向の収縮を抑制
しながら最高焼成温度Ｔ３で焼成する回路基板の製造方
法において、前記内部導体層をＴ１〜Ｔ３における焼成
体積収縮率が１５％以下の導体材料によって形成するこ
とを特徴とする回路基板の製造方法。1. The firing shrinkage starting temperatures are T1 and T2, respectively.
After preparing a laminate in which an internal conductor layer is formed by applying a conductor material to an interface between two types of unfired ceramic insulating layers composed of (T1 <T2), shrinkage of the laminate in the planar direction is suppressed. A method of manufacturing a circuit board, wherein the internal conductor layer is formed of a conductive material having a firing volume shrinkage rate of 15% or less in T1 to T3 while firing at a maximum firing temperature T3.
からＴ１まで昇温する過程での焼成体積収縮率が１０％
以下であることを特徴とする請求項１記載の回路基板の
製造方法。2. A firing volume shrinkage rate of 10% in a process of raising the temperature of a conductive material forming the internal conductive layer from room temperature to T1.
2. The method for manufacturing a circuit board according to claim 1, wherein:
属粉末の平均粒径が０．５〜５μｍ、ＢＥＴ比表面積が
０．１〜０．７ｍ2／ｇであることを特徴とする請求項
１または請求項２記載の回路基板の製造方法。3. The method according to claim 1, wherein the metal powder in the conductor material constituting the inner conductor layer has an average particle size of 0.5 to 5 μm and a BET specific surface area of 0.1 to 0.7 m 2 / g. A method for manufacturing a circuit board according to claim 1.
属粉末が、Ａｕ、Ａｇ、Ｃｕ、ＰｄおよびＰｔの中から
選ばれる少なくとも１種を主成分とすることを特徴とす
る請求項１乃至請求項３のいずれか記載の回路基板の製
造方法。4. The method according to claim 1, wherein the metal powder in the conductor material constituting the inner conductor layer contains at least one selected from the group consisting of Au, Ag, Cu, Pd and Pt. The method for manufacturing a circuit board according to claim 3.
ｈ及び／あるいはＲｕを含有することを特徴とする請求
項１乃至請求項４のいずれか記載の回路基板の製造方
法。5. The conductive material constituting said internal conductor layer is R
The method for manufacturing a circuit board according to any one of claims 1 to 4, further comprising h and / or Ru.
焼成のセラミック絶縁層が接する界面が２箇所以上存在
することを特徴とする請求項１乃至請求項５のいずれか
記載の回路基板の製造方法。6. The circuit board according to claim 1, wherein the laminate has two or more interfaces where unfired ceramic insulating layers having different firing shrinkage behavior come into contact with each other. Manufacturing method.
以下であることを特徴とする請求項１乃至請求項６のい
ずれか記載の回路基板の製造方法。7. The fired thickness of the internal conductor layer is 30 μm.
The method for manufacturing a circuit board according to claim 1, wherein:
ミック絶縁層の比誘電率が異なることを特徴とする請求
項１乃至請求項７のいずれか記載の回路基板の製造方
法。8. The method for manufacturing a circuit board according to claim 1, wherein the relative dielectric constants of two or more types of ceramic insulating layers having different firing shrinkage starting temperatures are different.
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|---|---|---|---|
| JP2001083750A JP4416346B2 (en) | 2001-03-22 | 2001-03-22 | Circuit board manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001083750A JP4416346B2 (en) | 2001-03-22 | 2001-03-22 | Circuit board manufacturing method |
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| JP2002290037A true JP2002290037A (en) | 2002-10-04 |
| JP4416346B2 JP4416346B2 (en) | 2010-02-17 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687137B2 (en) | 2005-02-28 | 2010-03-30 | Kyocera Corporation | Insulating substrate and manufacturing method therefor, and multilayer wiring board and manufacturing method therefor |
| JP2011204847A (en) * | 2010-03-25 | 2011-10-13 | Murata Mfg Co Ltd | Method for manufacturing multilayer ceramic substrate |
| JP5364833B1 (en) * | 2012-10-03 | 2013-12-11 | Ｔｄｋ株式会社 | Conductive paste and ceramic substrate using the same |
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|---|---|---|---|---|
| US7687137B2 (en) | 2005-02-28 | 2010-03-30 | Kyocera Corporation | Insulating substrate and manufacturing method therefor, and multilayer wiring board and manufacturing method therefor |
| JP2011204847A (en) * | 2010-03-25 | 2011-10-13 | Murata Mfg Co Ltd | Method for manufacturing multilayer ceramic substrate |
| JP5364833B1 (en) * | 2012-10-03 | 2013-12-11 | Ｔｄｋ株式会社 | Conductive paste and ceramic substrate using the same |
| WO2014054671A1 (en) * | 2012-10-03 | 2014-04-10 | Tdk株式会社 | Conductive paste, and ceramic substrate produced using same |
| KR20150054935A (en) * | 2012-10-03 | 2015-05-20 | 티디케이가부시기가이샤 | Conductive paste, and ceramic substrate produced using same |
| CN104704932A (en) * | 2012-10-03 | 2015-06-10 | Tdk株式会社 | Conductive paste, and ceramic substrate produced using same |
| US9585250B2 (en) | 2012-10-03 | 2017-02-28 | Tdk Corporation | Conductive paste and ceramic substrate manufactured using the same |
| KR101716992B1 (en) | 2012-10-03 | 2017-03-15 | 티디케이가부시기가이샤 | Conductive paste, and ceramic substrate produced using same |
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| JP4416346B2 (en) | 2010-02-17 |
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