JP2002290006A - Method of manufacturing substrate with built-in parts - Google Patents
Method of manufacturing substrate with built-in partsInfo
- Publication number
- JP2002290006A JP2002290006A JP2001089832A JP2001089832A JP2002290006A JP 2002290006 A JP2002290006 A JP 2002290006A JP 2001089832 A JP2001089832 A JP 2001089832A JP 2001089832 A JP2001089832 A JP 2001089832A JP 2002290006 A JP2002290006 A JP 2002290006A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- wires
- electronic component
- chip
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電子部品を内蔵する
部品内蔵基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a component-embedded substrate incorporating electronic components.
【０００２】[0002]
【従来の技術】近年では、プリント基板の高密度化に伴
い、電子部品を絶縁性基板に内蔵させる技術の開発が盛
んとなっている。図２には、従来の部品内蔵基板１０１
の製造工程を示した。この部品内蔵基板１０１の製造方
法では、まず、絶縁性基板１０２の一部に形成された凹
所１０３の底面に接着剤１０４を塗布し、この接着剤１
０４上に電子部品１１１、１２１を固着させる（図２
Ａ）。そして、凹所１０３内に樹脂を注ぎこみ、固化さ
せて電子部品１１１、１２１を埋め込む（図２Ｂ）。こ
の後、樹脂層１０５の表面１０５Ａから電子部品１１
１、１２１の端子部１１２、１２２に連通するビアホー
ル１１３、１２３を形成し、このビアホール１１３、１
２３内にめっきによりめっき金属１１４、１２４を充填
することで、電子部品１１１、１２１と樹脂層１０５の
表面１０５Ａとを電気的に接続する導体路を形成させる
（図２Ｃ）。2. Description of the Related Art In recent years, with the increase in density of printed circuit boards, the development of technology for incorporating electronic components into an insulating substrate has been actively developed. FIG. 2 shows a conventional component built-in substrate 101.
The production process was described. In the method of manufacturing the component built-in substrate 101, first, an adhesive 104 is applied to the bottom surface of the recess 103 formed in a part of the insulating substrate 102, and the adhesive 1
The electronic components 111 and 121 are fixed on the substrate 04 (see FIG. 2).
A). Then, a resin is poured into the recess 103 and solidified to embed the electronic components 111 and 121 (FIG. 2B). Thereafter, the electronic component 11 is removed from the surface 105A of the resin layer 105.
Via holes 113 and 123 communicating with the terminal portions 112 and 122 of the first and second 121 are formed.
By filling plating metals 114 and 124 in plating 23, a conductive path for electrically connecting electronic components 111 and 121 and surface 105A of resin layer 105 is formed (FIG. 2C).
【０００３】[0003]
【発明が解決しようとする課題】ところで、各ビアホー
ル１１３、１２３内にめっきを行う際に、充填されるめ
っき金属１１４、１２４のめっき高さにばらつきが生じ
る場合がある。このような場合には、めっき高さが不足
したビアホール１１３、１２３においては、樹脂層１０
５の表面１０５Ａとの接続信頼性が低下するおそれがあ
り、問題となっていた。However, when plating the via holes 113 and 123, the plating heights of the plated metals 114 and 124 to be filled may vary. In such a case, in the via holes 113 and 123 where the plating height is insufficient, the resin layer 10
5, there is a possibility that the connection reliability with the surface 105A may be reduced, which is a problem.
【０００４】特に、厚さの異なる複数個の電子部品１１
１、１２１を内蔵させる場合には、電子部品１１１、１
２１の厚さの違いによって、ビアホール１１３、１２３
の長さが異なることとなるため、この問題が顕著とな
る。すなわち、薄い電子部品１１１の場合には、樹脂層
１０５の表面１０５Ａから端子部１１２の上端１１２Ａ
までの距離Ｌ１が長いため、ビアホール１１３は長くな
る。一方、厚い電子部品１２１の場合には、樹脂層１０
５の上面から端子部１２２の上端１２２Ａまでの距離Ｌ
２が短いため、ビアホール１２３は短くなる（図２
Ｂ）。In particular, a plurality of electronic components 11 having different thicknesses
When the electronic components 111 and 121 are incorporated,
The via holes 113, 123
Since the lengths are different, this problem becomes remarkable. That is, in the case of the thin electronic component 111, the upper end 112 </ b> A of the terminal portion 112 extends from the surface 105 </ b> A of the resin layer 105.
Because the distance L1 to the via hole 113 is long, the via hole 113 becomes long. On the other hand, in the case of the thick electronic component 121, the resin layer 10
5 from the upper surface of No. 5 to the upper end 122A of the terminal portion 122
2, the via hole 123 becomes short (see FIG. 2).
B).
【０００５】このようなビアホール１１３、１２３に同
時にめっきを施せば、短いビアホール１２３にメッキ金
属１２４を充填し終えた時点では、長いビアホール１１
３には充分にメッキ金属１１４が充填されていない状態
であり、めっき高さが不足することとなる（図２Ｃ）。
このため、厚さの大きく異なる部品同士は、同一工程で
埋め込みおよび導体路の形成を行うことが困難であり、
製造工程の複雑化を招いていた。また、めっきの速度向
上に限界があるために、生産性の向上に限界があった。If the via holes 113 and 123 are plated at the same time, when the short via holes 123 are completely filled with the plating metal 124, the long via holes 11
3 is not sufficiently filled with the plating metal 114, and the plating height is insufficient (FIG. 2C).
For this reason, it is difficult to embed parts and form conductor paths in the same process for parts having greatly different thicknesses.
This complicates the manufacturing process. In addition, there is a limit in improving the plating speed, which limits the improvement in productivity.
【０００６】本発明は上記事情に鑑みてなされたもので
あって、簡易な製造工程で接続信頼性の高い部品内蔵基
板を製造できる方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and has as its object to provide a method capable of manufacturing a component built-in board having high connection reliability by a simple manufacturing process.
【０００７】[0007]
【課題を解決するための手段】上記の課題を解決するた
めに請求項１の発明に係る部品内蔵基板の製造方法は、
端子部を備えた電子部品を内蔵する部品内蔵基板の製造
方法であって、絶縁層の一面側に電子部品を載置する部
品載置工程と、前記電子部品の前記端子部上に導電体を
立設する立設工程と、前記絶縁層上に前記電子部品およ
び前記導電体を埋没させるように樹脂層を形成する埋め
込み工程と、前記樹脂層の表面を研削することにより、
前記導電体の前記電子部品と接続された側と逆側の端部
が前記樹脂層の表面に露出され、かつ前記樹脂層の表面
と面一とされるようにする研削工程とを経ることを特徴
とする。According to a first aspect of the present invention, there is provided a method of manufacturing a component-embedded substrate.
A method for manufacturing a component built-in board incorporating an electronic component having a terminal portion, comprising: a component mounting step of mounting an electronic component on one surface side of an insulating layer; and a conductor on the terminal portion of the electronic component. An erecting step of erecting, an embedding step of forming a resin layer on the insulating layer so as to bury the electronic component and the conductor, and grinding the surface of the resin layer,
And a grinding step of exposing an end of the conductor opposite to the side connected to the electronic component to the surface of the resin layer and making the end flush with the surface of the resin layer. Features.
【０００８】ここで、導電体の材質しては、導電性を備
えたものであれば特に制限はなく、例えば導電性金属を
使用できる。また、導電体の形状には特に制限はなく、
例えば棒状、ワイヤ状のものを使用できる。Here, the material of the conductor is not particularly limited as long as it has conductivity, and for example, a conductive metal can be used. The shape of the conductor is not particularly limited,
For example, a rod-shaped or wire-shaped material can be used.
【０００９】また、「導電体を埋没させる」とは、必ず
しも導電体全体が樹脂層の内部に埋め込まれることを意
味せず、例えば、電子部品、および導電体の電子部品と
接続された側の端部のみが樹脂層の内部に埋め込まれて
いてもよい。Further, "to bury the conductor" does not necessarily mean that the entire conductor is buried in the resin layer. For example, the electronic component and the side of the conductor connected to the electronic component are not buried. Only the ends may be embedded in the resin layer.
【００１０】請求項２の発明は、請求項１に記載の部品
内蔵基板の製造方法であって、前記絶縁層がプリプレグ
であることを特徴とする。According to a second aspect of the present invention, there is provided the method of manufacturing a component-embedded substrate according to the first aspect, wherein the insulating layer is a prepreg.
【００１１】ここで、プリプレグとは、基材に熱硬化性
樹脂を含浸させて加熱により半硬化状態としたものであ
り、基材としては例えば紙、ガラス布、ガラス不織布、
合成繊維布等が、熱硬化性樹脂としては例えばエポキシ
樹脂、フェノール樹脂等が使用できる。Here, the prepreg is a material in which a base material is impregnated with a thermosetting resin to be in a semi-cured state by heating. Examples of the base material include paper, glass cloth, glass non-woven fabric,
For example, an epoxy resin, a phenol resin or the like can be used as the thermosetting resin.
【００１２】[0012]
【発明の作用、および発明の効果】請求項１の発明によ
れば、電子部品と樹脂層表面との導通を図るための導体
路となる導電体は、電子部品の端子部上に立設され、電
子部品とともに樹脂層に埋めこまれる。この後、研削工
程を行うことにより、導電体の端部が樹脂層の表面に露
出され、かつ樹脂層の表面と面一となるようにされる。
このようにすれば、導電体の端部が確実に樹脂層の表面
に位置するようにできるため、接続信頼性を確保でき
る。また、厚さの異なる部品同士であっても、同一の工
程で埋め込みおよび導体路の形成を行うことができ、製
造工程を簡略化できる。According to the first aspect of the present invention, the conductor serving as a conductor path for establishing conduction between the electronic component and the surface of the resin layer is provided upright on the terminal portion of the electronic component. Embedded in the resin layer together with the electronic components. Thereafter, by performing a grinding step, the end of the conductor is exposed on the surface of the resin layer and is made flush with the surface of the resin layer.
With this configuration, since the end of the conductor can be reliably positioned on the surface of the resin layer, connection reliability can be ensured. In addition, even in the case of parts having different thicknesses, embedding and formation of a conductor path can be performed in the same process, and the manufacturing process can be simplified.
【００１３】請求項２の発明によれば、絶縁層はプリプ
レグである。このため、接着層を介することなく、絶縁
層上に直接に電子部品を固着することができ、製造工程
を簡略化できる。According to the second aspect of the present invention, the insulating layer is a prepreg. Therefore, the electronic component can be fixed directly on the insulating layer without the intervention of the adhesive layer, and the manufacturing process can be simplified.
【００１４】[0014]
【発明の実施の形態】以下、本発明を具体化した一実施
形態について、図１を参照しつつ詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIG.
【００１５】部品内蔵基板１の出発材料は、例えばガラ
ス布基材にエポキシ樹脂を含浸し、加熱半硬化状態とし
て板状に形成されたプリプレグ２である（図１Ａ）。こ
のプリプレグ２の一面側（図１において上面側）に、例
えばマウンタ等の自動機器によって、ＭＰＵ（超小型演
算装置）チップ１０（本発明の電子部品に該当する）、
およびチップコンデンサ２０（本発明の電子部品に該当
する）を載置する（図１Ａ）。プリプレグ２は半硬化状
態であるので、ＭＰＵチップ１０およびチップコンデン
サ２０は、接着剤を使用することなく、直接にプリプレ
グ２上に固着される。The starting material of the component built-in substrate 1 is, for example, a prepreg 2 formed by impregnating a glass cloth base material with an epoxy resin and heating and semi-curing to form a plate (FIG. 1A). On one surface side (upper surface side in FIG. 1) of the prepreg 2, an MPU (microcomputer) chip 10 (corresponding to an electronic component of the present invention)
Then, the chip capacitor 20 (corresponding to the electronic component of the present invention) is placed (FIG. 1A). Since the prepreg 2 is in a semi-cured state, the MPU chip 10 and the chip capacitor 20 are directly fixed on the prepreg 2 without using an adhesive.
【００１６】このＭＰＵチップ１０は、１３ｍｍ角、厚
さ５００μｍであり、一面側（図１において上面側）に
は端子部１１が設けられている。また、チップコンデン
サ２０は、幅２ｍｍ、長さ１．２５ｍｍ、厚さ０．６〜
０．８μｍであり、左右両端部に一対の端子部２１が設
けられている。The MPU chip 10 has a size of 13 mm square and a thickness of 500 μm, and has a terminal portion 11 on one side (the upper side in FIG. 1). The chip capacitor 20 has a width of 2 mm, a length of 1.25 mm, and a thickness of 0.6 to 0.6 mm.
0.8 μm, and a pair of terminal portions 21 is provided at both left and right end portions.
【００１７】このＭＰＵチップ１０およびチップコンデ
ンサ２０の端子部１１、２１上に、スタッドバンプ１
２、２２を形成する。まず、ＭＰＵチップ１０およびチ
ップコンデンサ２０が載置されたプリプレグ２上に、図
示しない感光性樹脂を塗布する。そして、この感光性樹
脂を所定のパターンにより露光・現像処理することによ
り、端子部１１、２１の上面側が開放された孔部を形成
する。この孔部内に電解メッキを施すことにより、スタ
ッドバンプ１２、２２を形成する（図１Ｂ）。なお、こ
のスタッドバンプ１２、２２は、後述するワイヤ１３、
２３と同じ材質で形成させることが好ましい。The stud bumps 1 are formed on the terminals 11 and 21 of the MPU chip 10 and the chip capacitor 20.
2 and 22 are formed. First, a photosensitive resin (not shown) is applied on the prepreg 2 on which the MPU chip 10 and the chip capacitor 20 are mounted. Then, by exposing and developing the photosensitive resin in a predetermined pattern, a hole having an open upper surface side of the terminal portions 11 and 21 is formed. Stud bumps 12 and 22 are formed by applying electroplating in the holes (FIG. 1B). The stud bumps 12, 22 are connected to wires 13, which will be described later.
It is preferable to form them from the same material as 23.
【００１８】次いで、感光性樹脂をエッチングにより除
去した後に、このスタッドバンプ１２、２２上にワイヤ
１３、２３（本発明の導電体に該当する）を立設する
（図１Ｃ）。ワイヤ１３、２３としては、例えば金、ア
ルミニウム等の導電性金属により作製された長さ約５０
０μｍのものを使用できる。このワイヤ１３、２３は、
その一端部１３Ａ、２３Ａがスタッドバンプ１２、２２
の表面に接するようにされて、スタッドバンプ１２、２
２上に垂直に立設される。Next, after the photosensitive resin is removed by etching, wires 13 and 23 (corresponding to the conductor of the present invention) are erected on the stud bumps 12 and 22 (FIG. 1C). Each of the wires 13 and 23 has a length of about 50 made of a conductive metal such as gold or aluminum.
Those having a thickness of 0 μm can be used. These wires 13 and 23
One end 13A, 23A is stud bump 12,22.
Stud bumps 12, 2
2 vertically.
【００１９】次に、プリプレグ２の上面側に、例えば熱
硬化性のエポキシ樹脂を約１ｍｍの厚さに塗布して樹脂
層３を形成させる。ここで、塗布作業の際にワイヤ１
３、２３が倒されたり、流されたりすることを防止する
ため、エポキシ樹脂としては粘度の低いものを使用する
ことが好ましい。次いで、加熱することによりこの樹脂
層３を硬化させる。このとき、同時にプリプレグ２も硬
化される。これにより、ＭＰＵチップ１０、チップコン
デンサ２０、およびワイヤ１３、２３は樹脂層３内に埋
没された状態とされる（図１Ｄ）。Next, a resin layer 3 is formed on the upper surface side of the prepreg 2 by applying, for example, a thermosetting epoxy resin to a thickness of about 1 mm. Here, the wire 1
It is preferable to use epoxy resin having a low viscosity in order to prevent 3, 23 from falling down or being washed away. Next, the resin layer 3 is cured by heating. At this time, the prepreg 2 is also cured at the same time. As a result, the MPU chip 10, the chip capacitor 20, and the wires 13, 23 are buried in the resin layer 3 (FIG. 1D).
【００２０】このとき、厚さ０．６〜０．８μｍのチッ
プコンデンサ２０の上に立設されたワイヤ２３は、その
上端２３Ｂ（本発明の端部に該当する）まで完全に樹脂
層３に埋め込まれた状態となっている。一方、厚さ５０
０μｍのＭＰＵチップ１０上に立設されたワイヤ１３
は、その上端１３Ｂが樹脂層３の表面３Ａから突出され
た状態となっている。At this time, the wire 23 erected on the chip capacitor 20 having a thickness of 0.6 to 0.8 μm completely covers the resin layer 3 up to its upper end 23B (corresponding to the end of the present invention). It is in an embedded state. On the other hand, thickness 50
Wire 13 erected on 0 μm MPU chip 10
Are in a state where the upper end 13B protrudes from the surface 3A of the resin layer 3.
【００２１】最後に、樹脂層３の表面３Ａを研削する研
削工程が実行される。研削は、例えばベルトサンダー或
いはバフ研磨を利用して行うことができる。この研削工
程によって、樹脂層３から突出していたワイヤ１３は、
その上端１３Ｂが樹脂層３の表面３Ａとほぼ一致するま
で削られる。そして、さらに樹脂層３の表面３Ａを研削
することにより、樹脂層３に完全に埋め込まれていたワ
イヤ２３の上端２３Ｂが、樹脂層３の表面３Ａに露出す
るようにされる。Finally, a grinding step for grinding the surface 3A of the resin layer 3 is performed. The grinding can be performed using, for example, a belt sander or buffing. Due to this grinding step, the wire 13 projecting from the resin layer 3 becomes
The upper end 13B is shaved until it almost coincides with the surface 3A of the resin layer 3. Then, by further grinding the surface 3A of the resin layer 3, the upper ends 23B of the wires 23 completely embedded in the resin layer 3 are exposed on the surface 3A of the resin layer 3.
【００２２】これにより、すべてのワイヤ１３、２３に
ついて、その上端１３Ｂ、２３Ｂが樹脂層３の表面３Ａ
に露出され、かつ樹脂層３の表面３Ａと面一となるよう
にされる。（図１Ｅ）。このようにして、部品内蔵基板
１が完成される。なお、この部品内蔵基板１は、例えば
プリント配線板用の絶縁性基板として使用されてもよ
く、周知のビルドアップ配線板を形成するためのコア基
板として使用されてもよい。As a result, the upper ends 13B and 23B of all the wires 13 and 23 are
And is flush with the surface 3A of the resin layer 3. (FIG. 1E). Thus, the component built-in substrate 1 is completed. The component built-in board 1 may be used, for example, as an insulating board for a printed wiring board, or may be used as a core board for forming a known build-up wiring board.
【００２３】以上のように本実施形態によれば、電子部
品と樹脂層３の表面３Ａとの間の導体路となるワイヤ１
３、２３は、ＭＰＵチップ１０、およびチップコンデン
サ２０の端子部１１、２１上に立設され、ＭＰＵチップ
１０、およびチップコンデンサ２０とともに樹脂層３に
埋めこまれる。この後、研削工程を行うことにより、ワ
イヤ１３、２３の上端１３Ｂ、２３Ｂが樹脂層３の表面
３Ａに露出され、かつ樹脂層３の表面３Ａと面一となる
ようにされる。As described above, according to the present embodiment, the wire 1 serving as a conductor path between the electronic component and the surface 3A of the resin layer 3
The MPU chip 10 and the chip capacitor 20 are erected on the terminal portions 11 and 21 of the MPU chip 10 and the chip capacitor 20, and are embedded in the resin layer 3 together with the MPU chip 10 and the chip capacitor 20. Thereafter, by performing a grinding process, the upper ends 13B and 23B of the wires 13 and 23 are exposed to the surface 3A of the resin layer 3 and are flush with the surface 3A of the resin layer 3.
【００２４】このようにすれば、ワイヤ１３、２３の上
端１３Ｂ、２３Ｂが確実に樹脂層３の表面３Ａに位置す
るようにできるため、接続信頼性を確保できる。また、
厚さの異なる部品同士であっても、同一の工程で埋め込
みおよび導体路の形成を行うことができ、製造工程を簡
略化できる。In this way, since the upper ends 13B and 23B of the wires 13 and 23 can be reliably located on the surface 3A of the resin layer 3, connection reliability can be ensured. Also,
Embedding and formation of conductor paths can be performed in the same process even for components having different thicknesses, and the manufacturing process can be simplified.
【００２５】また、プリプレグ２は半硬化状態であるた
め、ＭＰＵチップ１０およびチップコンデンサ２０を、
接着剤を使用することなく、直接に固着することができ
る。このため、製造工程を簡略化できる。Since the prepreg 2 is in a semi-cured state, the MPU chip 10 and the chip capacitor 20 are
It can be directly fixed without using an adhesive. Therefore, the manufacturing process can be simplified.
【００２６】なお、本発明の技術的範囲は、上記した実
施形態によって限定されるものではなく、例えば、次に
記載するようなものも本発明の技術的範囲に含まれる。
その他、本発明の技術的範囲は、均等の範囲にまで及ぶ
ものである。It should be noted that the technical scope of the present invention is not limited by the above-described embodiment, and for example, the following ones are also included in the technical scope of the present invention.
In addition, the technical scope of the present invention extends to an equivalent range.
【００２７】（１）上記実施形態では、電子部品として
ＭＰＵチップ１０およびチップコンデンサ２０を使用し
たが、本発明によれば、電子部品の種類は本実施形態の
限りではなく、例えばトランジスタ、抵抗、コンデンサ
等であってもよい。また、同時に埋め込まれる電子部品
の数は本実施形態の限りではなく、１個、もしくは３個
以上であってもよい。さらに、異種の部品同士のみでな
く、同種の部品同士を使用する場合であっても、本発明
を適用することができる。(1) In the above embodiment, the MPU chip 10 and the chip capacitor 20 are used as the electronic components. However, according to the present invention, the types of the electronic components are not limited to those of the present embodiment. It may be a capacitor or the like. Further, the number of electronic components to be embedded simultaneously is not limited to this embodiment, and may be one, or three or more. Furthermore, the present invention can be applied not only to the case where different kinds of parts are used but also the case where the same kind of parts are used.
【００２８】（２）上記実施形態では、チップコンデン
サ２０上に立設されたワイヤ２３は、その上端２３Ｂま
で完全に樹脂層３に埋め込まれている一方、ＭＰＵチッ
プ１０上に立設されたワイヤ１３は、その上端１３Ｂが
樹脂層３の表面３Ａから突出されているが、本発明によ
れば、導電体の埋め込みの状態は本実施形態の限りでは
なく、例えばすべての導電体が完全に埋没するように樹
脂層を形成させてもよく、すべての導電体の上端を露出
するように樹脂層を形成させてもよい。(2) In the above embodiment, the wire 23 erected on the chip capacitor 20 is completely embedded in the resin layer 3 up to its upper end 23B, while the wire erected on the MPU chip 10 13 has an upper end 13B protruding from the surface 3A of the resin layer 3. However, according to the present invention, the state of embedding of the conductor is not limited to the present embodiment. For example, all the conductors are completely buried. The resin layer may be formed such that the upper ends of all the conductors are exposed.
【００２９】（３）上記実施形態では、プリプレグ２上
に直接にＭＰＵチップ１０およびチップコンデンサ２０
を固着させているが、本発明によれば、絶縁層の材質お
よび絶縁層上への電子部品の固着方法は本実施形態の限
りではなく、例えば絶縁層として硬化済みの樹脂基板を
用いて、接着剤を用いて電子部品を固着させてもよい。(3) In the above embodiment, the MPU chip 10 and the chip capacitor 20 are directly placed on the prepreg 2.
According to the present invention, the material of the insulating layer and the method of fixing the electronic component on the insulating layer are not limited to those in the present embodiment.For example, using a cured resin substrate as the insulating layer, The electronic component may be fixed using an adhesive.
【図１】本発明の部品内蔵基板の製造方法を示す図FIG. 1 is a diagram showing a method for manufacturing a component-embedded substrate of the present invention.
【図２】従来の部品内蔵基板の製造方法を示す図FIG. 2 is a diagram showing a conventional method for manufacturing a component-embedded substrate.
１…部品内蔵基板 ２…プリプレグ（絶縁層） ３…樹脂層 ３Ａ…表面 １０…ＭＰＵチップ（電子部品） １１、２１…端子部 １３Ｂ、２３Ｂ…上端（端部） ２０…チップコンデンサ（電子部品） ２３…ワイヤ（導電体） DESCRIPTION OF SYMBOLS 1 ... Component built-in board 2 ... Prepreg (insulating layer) 3 ... Resin layer 3A ... Surface 10 ... MPU chip (electronic part) 11, 21 ... Terminal part 13B, 23B ... Upper end (end part) 20 ... Chip capacitor (electronic part) 23 ... Wire (conductor)
Claims (2)
内蔵基板の製造方法であって、 絶縁層の一面側に前記電子部品を載置する部品載置工程
と、 前記電子部品の前記端子部上に導電体を立設する立設工
程と、 前記絶縁層上に前記電子部品および前記導電体を埋没さ
せるように樹脂層を形成する埋め込み工程と、 前記樹脂層の表面を研削することにより、前記導電体の
前記電子部品と接続された側と逆側の端部が前記樹脂層
の表面に露出され、かつ前記樹脂層の表面と面一とされ
るようにする研削工程とを経ることを特徴とする部品内
蔵基板の製造方法。1. A method for manufacturing a component-embedded substrate incorporating an electronic component having a terminal portion, comprising: a component mounting step of mounting the electronic component on one surface side of an insulating layer; and the terminal of the electronic component. An erecting step of erecting a conductor on the part; an embedding step of forming a resin layer on the insulating layer so as to bury the electronic component and the conductor; and grinding the surface of the resin layer. A grinding step of exposing an end of the conductor opposite to the side connected to the electronic component to the surface of the resin layer and making the end flush with the surface of the resin layer. A method for manufacturing a component-embedded substrate, characterized by the following.
徴とする請求項１に記載の部品内蔵基板の製造方法。2. The method according to claim 1, wherein the insulating layer is a prepreg.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001089832A JP2002290006A (en) | 2001-03-27 | 2001-03-27 | Method of manufacturing substrate with built-in parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001089832A JP2002290006A (en) | 2001-03-27 | 2001-03-27 | Method of manufacturing substrate with built-in parts |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002290006A true JP2002290006A (en) | 2002-10-04 |
Family
ID=18944702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001089832A Pending JP2002290006A (en) | 2001-03-27 | 2001-03-27 | Method of manufacturing substrate with built-in parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002290006A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7049224B2 (en) | 2003-09-22 | 2006-05-23 | Oki Electric Industry Co., Ltd. | Manufacturing method of electronic components embedded substrate |
| JP2008166589A (en) * | 2006-12-28 | 2008-07-17 | Murata Mfg Co Ltd | Component containing multilayer wiring board module and its manufacturing method |
| WO2011025037A1 (en) * | 2009-08-31 | 2011-03-03 | 株式会社村田製作所 | Method for production of chip component having conductive post, and method of production of substrate having built-in chip component |
| US8240030B2 (en) | 2009-08-07 | 2012-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing electronic device |
| US8345435B2 (en) | 2009-08-07 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Terminal structure and manufacturing method thereof, and electronic device and manufacturing method thereof |
| US8642899B2 (en) | 2009-10-21 | 2014-02-04 | Semiconductor Energy Laboratory Co., Ltd. | Terminal structure, electronic device, and manufacturing method thereof |
| WO2019186780A1 (en) * | 2018-03-28 | 2019-10-03 | 株式会社Ｆｕｊｉ | Circuit formation method and circuit formation device |
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| JPH10229161A (en) * | 1996-12-09 | 1998-08-25 | Sony Corp | Electronic component and manufacturing method of electronic component |
| JP2001332863A (en) * | 2000-02-25 | 2001-11-30 | Ibiden Co Ltd | Method for producing multilayer printed wiring board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS577147A (en) * | 1980-06-17 | 1982-01-14 | Citizen Watch Co Ltd | Mounting construction of semiconductor device |
| JPH10229161A (en) * | 1996-12-09 | 1998-08-25 | Sony Corp | Electronic component and manufacturing method of electronic component |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7049224B2 (en) | 2003-09-22 | 2006-05-23 | Oki Electric Industry Co., Ltd. | Manufacturing method of electronic components embedded substrate |
| JP2008166589A (en) * | 2006-12-28 | 2008-07-17 | Murata Mfg Co Ltd | Component containing multilayer wiring board module and its manufacturing method |
| US8240030B2 (en) | 2009-08-07 | 2012-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing electronic device |
| US8345435B2 (en) | 2009-08-07 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Terminal structure and manufacturing method thereof, and electronic device and manufacturing method thereof |
| WO2011025037A1 (en) * | 2009-08-31 | 2011-03-03 | 株式会社村田製作所 | Method for production of chip component having conductive post, and method of production of substrate having built-in chip component |
| US8642899B2 (en) | 2009-10-21 | 2014-02-04 | Semiconductor Energy Laboratory Co., Ltd. | Terminal structure, electronic device, and manufacturing method thereof |
| WO2019186780A1 (en) * | 2018-03-28 | 2019-10-03 | 株式会社Ｆｕｊｉ | Circuit formation method and circuit formation device |
| JPWO2019186780A1 (en) * | 2018-03-28 | 2020-12-03 | 株式会社Ｆｕｊｉ | Circuit formation method and circuit formation device |
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