JP2002289744A - Semiconductor package, its manufacturing method, semiconductor device and its manufacturing method - Google Patents
Semiconductor package, its manufacturing method, semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002289744A JP2002289744A JP2001093244A JP2001093244A JP2002289744A JP 2002289744 A JP2002289744 A JP 2002289744A JP 2001093244 A JP2001093244 A JP 2001093244A JP 2001093244 A JP2001093244 A JP 2001093244A JP 2002289744 A JP2002289744 A JP 2002289744A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor package
- semiconductor
- layer
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する利用分野】本発明は、半導体パッケージ
及びその製造方法並びに半導体装置及びその製造方法に
関する。The present invention relates to a semiconductor package and a method of manufacturing the same, and a semiconductor device and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、BGA(Ball・Grid・Array)タイプ、
CSP(Chip・Size・Package)等の半導体パッケージをプリ
ント配線板等に表面実装する場合、パッケージ側に接続
端子としてバンプを設けて基板実装することが行われて
いる。このバンプの一例として半導体パッケージの基板
にはんだボールを設けて実装基板のランド部にフリップ
チップ接続することが一般に行われている。はんだボー
ルは、予め所要の径で形成されたボールを吸着パッドな
どで吸着してパッケージの基板のランド部に載せた後リ
フローして接合される。半導体パッケージの接続信頼性
を確保するには、はんだボール径が均一であることやパ
ッケージの平坦度などが要求される。2. Description of the Related Art Conventionally, a BGA (Ball / Grid / Array) type
When a semiconductor package such as a CSP (Chip / Size / Package) is surface-mounted on a printed wiring board or the like, bumps are provided as connection terminals on the package side and mounted on a substrate. As an example of the bump, generally, a solder ball is provided on a substrate of a semiconductor package and flip-chip connected to a land portion of a mounting substrate. The solder balls are adsorbed by a suction pad or the like on a ball formed in a predetermined diameter in advance, placed on a land portion of a package substrate, and then reflowed and joined. In order to ensure the connection reliability of the semiconductor package, it is required that the diameter of the solder ball is uniform, the flatness of the package, and the like.
【０００３】[0003]
【発明が解決しようとする課題】近年の半導体パッケー
ジ小型化高集積化に伴い、はんだボール径も小径化が要
求され、ボールの直径が均一に製造するのが難しくな
り、製造コストが嵩む。また、パッケージの平坦度も要
求されるため、反り等が生じた場合には、基板に対する
接続信頼性が低下し易い。また、半導体パッケージを量
産する場合、はんだボールを吸着パッドに100〜 200個
程度いっぺんに吸着して基板に載せることが行われてい
るため、吸着ミスがあった場合には、リトライを繰り返
す必要があるため、生産効率も低下し易いという課題も
あった。また、はんだボールは、一旦パッケージの基板
に載せられた後、リフロー工程を経て接合されるため、
製造工程に時間と費用がかかるという課題もあった。With the recent trend toward miniaturization and high integration of semiconductor packages, it has been required to reduce the diameter of solder balls, making it difficult to manufacture balls with a uniform diameter and increasing the manufacturing cost. Further, since the flatness of the package is also required, when warpage or the like occurs, the connection reliability to the substrate is likely to decrease. Also, when mass-producing semiconductor packages, about 100 to 200 solder balls are sucked to the suction pad at once and placed on the board, so if there is a suction error, retry must be repeated For this reason, there has been a problem that the production efficiency is also likely to decrease. Also, since the solder balls are once mounted on the package substrate and then joined through a reflow process,
There is also a problem that the manufacturing process takes time and costs.
【０００４】本発明の目的は、上記従来技術の課題を解
決し、はんだボールを使用することなく基板の任意の箇
所に接続用の突起（バンプ）を形成した半導体パッケー
ジ及びその製造方法、並びに該半導体パッケージを用い
た半導体装置及びその製造方法を提供することにある。An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a semiconductor package in which connection projections (bumps) are formed at arbitrary portions of a substrate without using solder balls, a method of manufacturing the same, and a method of manufacturing the same. An object of the present invention is to provide a semiconductor device using a semiconductor package and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するた
め、本発明は次の構成を備える。即ち、半導体パッケー
ジにおいては、回路基板の一方側の面又は両側面に耐熱
性保護フィルムが積層され、これらを打ち抜いて形成さ
れた貫通孔に金属柱材が埋め込まれて導体パターンと接
続されていることを特徴とする。また、金属柱材は、基
板面及び／又は耐熱性保護フィルム面にほぼ面一にとな
るように埋め込まれていることを特徴とする。また、金
属柱材は、高融点金属層と低融点金属層が積層されて形
成された金属複合柱材であっても良く、高融点金属層の
上層及び下層に低融点金属層が積層されて形成された金
属複合柱材であっても良い。また、金属柱材は、貫通孔
に埋め込まれた両側端面がかしめられて、平坦面に形成
されていることを特徴とする。また、金属柱材は導体パ
ターンと接合され、パッケージの基板接続端子として形
成されていることを特徴とする。また、金属柱材は導体
パターンと接合され、パッケージのチップ接続端子とし
て形成されていることを特徴とする。To solve the above-mentioned problems, the present invention has the following arrangement. That is, in the semiconductor package, a heat-resistant protective film is laminated on one side or both sides of the circuit board, and a metal pillar material is embedded in a through hole formed by punching the heat-resistant protective film and connected to the conductor pattern. It is characterized by the following. Further, the metal pillar is embedded so as to be substantially flush with the substrate surface and / or the heat-resistant protective film surface. Further, the metal column material may be a metal composite column material formed by laminating a high melting point metal layer and a low melting point metal layer, and a low melting point metal layer is laminated on an upper layer and a lower layer of the high melting point metal layer. The formed metal composite column material may be used. Further, the metal pillar is characterized in that both end surfaces embedded in the through-hole are caulked and formed on a flat surface. Further, the metal pillar is bonded to the conductor pattern and is formed as a substrate connection terminal of the package. Further, the metal pillar is joined to the conductor pattern and formed as a chip connection terminal of the package.
【０００６】また、半導体装置においては、前述した半
導体パッケージに半導体チップが搭載され、耐熱性保護
フィルムが剥離されて、基板面に金属柱材が接続端子と
して突出形成されていることを特徴とする。A semiconductor device is characterized in that a semiconductor chip is mounted on the above-described semiconductor package, the heat-resistant protective film is peeled off, and metal pillars are formed as connection terminals on the substrate surface. .
【０００７】半導体パッケージの製造方法においては、
樹脂基材に導体層が積層されてなる基板の該導体層に導
体パターンを形成する工程と、導体パターンが形成され
た回路基板の一方側の面又は両側面に耐熱性保護フィル
ムを貼り合わせる工程と、耐熱性保護フィルムが貼り合
わされた回路基板を打ち抜いて貫通孔を形成する工程
と、貫通孔が形成された回路基板に金属シートを積層し
て打ち抜き、打ち抜かれた金属柱材を貫通孔内に埋め込
む工程と、埋め込まれた金属柱材をかしめる工程とを含
むことを特徴とする。また、金属柱材は高融点金属層と
低融点金属層が積層されて形成された金属複合柱材であ
り、高融点金属層の露出端面に金属めっき層を形成して
導体パターンと接合する工程を含むことを特徴とする。
また、金属柱材は高融点金属層の上層及び下層に低融点
金属層が積層されて形成された金属複合柱材であり、低
融点金属層の露出端面に加熱して導体パターンと接合す
る工程を含むことを特徴とする。In a method of manufacturing a semiconductor package,
A step of forming a conductor pattern on a conductor layer of a substrate formed by laminating a conductor layer on a resin base, and a step of bonding a heat-resistant protective film to one or both surfaces of the circuit board on which the conductor pattern is formed Forming a through-hole by punching a circuit board on which a heat-resistant protective film is bonded; and laminating and punching a metal sheet on the circuit board having the through-hole, and placing the punched-out metal pillar in the through-hole. And a step of caulking the embedded metal column material. The metal pillar is a metal composite pillar formed by laminating a high-melting metal layer and a low-melting metal layer. A step of forming a metal plating layer on an exposed end face of the high-melting metal layer and joining it to a conductor pattern It is characterized by including.
The metal pillar is a metal composite pillar formed by laminating a low-melting metal layer on the upper layer and the lower layer of the high-melting metal layer, and heating the exposed end face of the low-melting metal layer to join the conductor pattern. It is characterized by including.
【０００８】また、半導体装置の製造方法においては、
上述した製法で製造された半導体パッケージに半導体チ
ップを搭載する工程と、半導体チップと導体パターンと
を電気的に導通させる工程と、耐熱性保護フィルムを剥
離させて、金属柱材を基板の一方又は両面側に突設する
工程とを含むことを特徴とする。また、半導体チップを
基板面に搭載してワイヤボンディング接続する工程と、
半導体チップの周囲を樹脂封止する工程とを含むことを
特徴とする。また、半導体チップを基板面に形成された
ランド部にフリップチップ接続する工程と、半導体チッ
プと基板面との隙間を含む該半導体チップの周囲にアン
ダーフィルモールドを行う工程と含むことを特徴とす
る。In the method of manufacturing a semiconductor device,
A step of mounting a semiconductor chip on a semiconductor package manufactured by the above-described manufacturing method, a step of electrically connecting the semiconductor chip to a conductor pattern, and a step of peeling off a heat-resistant protective film, and forming a metal pillar on one or the other of a substrate. And protruding both sides. A step of mounting the semiconductor chip on the substrate surface and performing wire bonding connection;
Sealing the periphery of the semiconductor chip with a resin. Further, the method includes a step of flip-chip connecting the semiconductor chip to a land formed on the substrate surface, and a step of performing underfill molding around the semiconductor chip including a gap between the semiconductor chip and the substrate surface. .
【０００９】[0009]
【発明の実施の形態】以下、本発明の好適な実施の形態
について添付図面と共に詳述する。本実施例では、半導
体パッケージに半導体チップがワイヤボンディング接続
されている半導体装置を例示して説明する。図１（ａ）
〜（ｇ）は半導体パッケージ及び半導体装置の製造工程
を示す説明図、図２（ａ）（ｂ）（ｃ）は半導体パッケ
ージのバンプ形成の態様を例示する説明図、図３（ａ）
（ｂ）（ｃ）は半導体装置の態様を例示する説明図、図
４は半導体装置の応用例を示す説明図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In this embodiment, a semiconductor device in which a semiconductor chip is wire-bonded to a semiconductor package will be described as an example. FIG. 1 (a)
FIGS. 2A to 2G are explanatory views showing a manufacturing process of the semiconductor package and the semiconductor device, FIGS. 2A, 2B, and 3C are explanatory views illustrating a mode of forming bumps of the semiconductor package, and FIG.
FIGS. 4B and 4C are explanatory diagrams illustrating aspects of the semiconductor device, and FIG. 4 is an explanatory diagram illustrating an application example of the semiconductor device.
【００１０】先ず、半導体パッケージ及び半導体装置の
概略構成について図３（ａ）〜（ｃ）を参照して説明す
る。１は半導体パッケージであり、樹脂基材２に導体パ
ターン３が形成されている回路基板４が設けられてい
る。この回路基板４の中心部にはチップ搭載部５が形成
されており、その周辺部には貫通孔（スルーホール）６
が設けられている。この貫通孔６には、金属柱材７が埋
め込まれており、回路基板４の一方の面４ａに形成され
た導体パターン３に電気的に接続され、他方の面４ｂに
突設されて接続端子を形成している。金属柱材７として
は銅又は銅合金やはんだ又ははんだ合金などの金属材料
が用いられる。First, a schematic configuration of a semiconductor package and a semiconductor device will be described with reference to FIGS. Reference numeral 1 denotes a semiconductor package, on which a circuit board 4 having a conductive pattern 3 formed on a resin base material 2 is provided. A chip mounting portion 5 is formed in the center of the circuit board 4, and a through hole (through hole) 6 is formed in a peripheral portion thereof.
Is provided. A metal pillar 7 is embedded in the through hole 6 and is electrically connected to the conductor pattern 3 formed on one surface 4a of the circuit board 4 and protruded from the other surface 4b to form a connection terminal. Is formed. As the metal column member 7, a metal material such as copper or copper alloy, solder or solder alloy is used.
【００１１】金属柱材７は、図３（ｂ）に示すように、
高融点金属層（例えば銅又は銅合金層）７ａと低融点金
属層（例えばはんだ及びはんだ合金層）７ｂが積層され
て形成された金属複合柱材であっても良い。この場合高
融点金属層７ａの端面にはニッケルめっきや銅めっきが
施されて導体パターン３と接合されているのが接続信頼
性を確保するうえで好ましい。また、図３（ｃ）に示す
ように高融点金属層（例えば銅又は銅合金層）７ａの上
層及び下層に低融点金属層（例えばはんだ及びはんだ合
金層）７ｂが積層されて形成された金属複合柱材であっ
ても良い。この場合、下層側の低融点金属層７ｂは接続
端子を形成しているため、導体パターン３と接続された
上層側の低融点金属層７ｂより層厚が厚く形成されてい
ることが望ましい。また、導体パターン３に隣接する上
層側の低融点金属層７ｂは加熱されて導体パターン３と
接合されているのが接続信頼性を確保するうえで好まし
い。また、金属柱材７は、貫通孔６に埋め込まれた両側
端面がかしめられて、平坦面に形成されている。これに
より、半導体パッケージ１を基板実装する際の接続信頼
性を向上させることができる。As shown in FIG. 3B, the metal pillar 7 is
It may be a metal composite pillar formed by laminating a high melting point metal layer (eg, copper or copper alloy layer) 7a and a low melting point metal layer (eg, solder and solder alloy layer) 7b. In this case, it is preferable to apply nickel plating or copper plating to the end surface of the high melting point metal layer 7a and join it to the conductor pattern 3 in order to secure connection reliability. Further, as shown in FIG. 3C, a metal formed by laminating a low melting point metal layer (eg, solder and solder alloy layer) 7b on the upper and lower layers of a high melting point metal layer (eg, copper or copper alloy layer) 7a. It may be a composite pillar. In this case, since the lower-side low-melting-point metal layer 7b forms a connection terminal, it is preferable that the layer is formed to be thicker than the upper-side low-melting-point metal layer 7b connected to the conductor pattern 3. Further, it is preferable that the upper low-melting point metal layer 7b adjacent to the conductor pattern 3 is heated and joined to the conductor pattern 3 in order to secure connection reliability. In addition, the metal pillar 7 is formed to have a flat surface by caulking both side end surfaces embedded in the through hole 6. Thereby, the connection reliability when mounting the semiconductor package 1 on the substrate can be improved.
【００１２】このようにして形成された半導体パッケー
ジ１のチップ搭載部５に半導体チップ８が搭載され、該
半導体チップ８のチップ電極部と回路基板４の一方の面
４ａに形成されたチップパッドとがボンディングワイヤ
９により接続され、更には封止樹脂１０に封止されて半
導体装置１１が形成される（図３（ａ）〜（ｃ）参
照）。A semiconductor chip 8 is mounted on the chip mounting portion 5 of the semiconductor package 1 thus formed, and a chip electrode portion of the semiconductor chip 8 and a chip pad formed on one surface 4a of the circuit board 4 are provided. Are connected by bonding wires 9 and further sealed by a sealing resin 10 to form a semiconductor device 11 (see FIGS. 3A to 3C).
【００１３】次に、半導体パッケージ１並びに半導体装
置１１の製造工程について図１（ａ）〜（ｇ）を参照し
て説明する。先ず、半導体パッケージ１の製造工程につ
いて説明する。図１（ａ）において、基板１２は、樹脂
基材２に導体層１３が積層されてなる基板が用いられ
る。この基板１２は、樹脂基材２として例えばエポキシ
系絶縁樹脂基材やポリイミド系絶縁樹脂基材等が用いら
れ、導体層１３として銅箔などの金属薄膜が用いられた
片面銅張基板或いは両面銅張基板等が好適に用いられ
る。上記基板（本実施例では片面銅張基板）１２の導体
層１３に導体パターン３を形成する。導体パターン３
は、導体層１３にフォトマスクを形成して不要な導体層
をエッチングで除去する公知のフォトエッチング法など
を用いて形成される。この導体パターン３が形成された
回路基板４に、耐熱性保護フィルム１４を貼り合わせ
る。耐熱性保護フィルム１４は、絶縁樹脂フィルムであ
り、本実施例では回路基板４の一方側（樹脂基材２側）
の面４ｂに貼り合わされている。Next, a manufacturing process of the semiconductor package 1 and the semiconductor device 11 will be described with reference to FIGS. First, a manufacturing process of the semiconductor package 1 will be described. In FIG. 1A, a substrate 12 in which a conductor layer 13 is laminated on a resin base material 2 is used. The substrate 12 is a single-sided copper-clad substrate or a double-sided copper substrate in which, for example, an epoxy-based insulating resin base or a polyimide-based insulating resin base is used as the resin base 2 and a metal thin film such as a copper foil is used as the conductor layer 13. A stretched substrate or the like is preferably used. The conductor pattern 3 is formed on the conductor layer 13 of the substrate (in this embodiment, a single-sided copper-clad substrate) 12. Conductor pattern 3
Is formed using a known photoetching method or the like in which a photomask is formed on the conductor layer 13 and unnecessary conductor layers are removed by etching. The heat-resistant protective film 14 is bonded to the circuit board 4 on which the conductor pattern 3 is formed. The heat-resistant protective film 14 is an insulating resin film, and in this embodiment, one side of the circuit board 4 (the resin substrate 2 side).
Are bonded to the surface 4b.
【００１４】次に、図１（ｂ）において、耐熱性保護フ
ィルム１４が貼り合わされた回路基板４（以降の説明で
は、回路基板４というときは耐熱性保護フィルム１４が
剥離されない限り一体に貼り合わされた状態をいう）を
第１のプレス装置１５のダイ１６上へ搬入して位置決め
した後、パンチ１７を下動させて回路基板４及び耐熱性
保護フィルム１４を打ち抜いて貫通孔（スルーホール）
６を形成する。Next, in FIG. 1 (b), the circuit board 4 to which the heat-resistant protective film 14 is bonded (in the following description, the circuit board 4 is bonded together unless the heat-resistant protective film 14 is peeled off). Is transferred to the die 16 of the first press device 15 and positioned, and then the punch 17 is moved downward to punch out the circuit board 4 and the heat-resistant protective film 14 to form a through hole.
6 is formed.
【００１５】次に、図１（ｃ）において、貫通孔６が形
成された回路基板４を、第２のプレス装置１９のダイ２
０上へ搬入してダイ孔２０ａと貫通孔６が一致するよう
に位置決めした後、金属シート２１を回路基板４の一方
の面４ａ（導体パターン３が形成された面）に積層す
る。この金属シート２１は、金属柱材７を形成するもの
で、回路基板４及び耐熱性保護フィルム１４の厚さに相
当するシート厚を有する。また、金属シート２１は図３
（ａ）〜（ｃ）で示す層構成を有する金属材料よりな
る。本実施例では、図３（ｃ）に示す高融点金属層７ａ
の上下に低融点金属層７ｂが積層された３層構造の金属
シート２１が用いられている。パンチ２２を下動させて
金属シート２１を打ち抜き、打ち抜かれた金属柱材７を
回路基板４の貫通孔６内に埋め込む。金属シート２１の
厚さは、回路基板４及び耐熱性保護フィルム１４の厚さ
に相当するので、打ち抜かれた金属柱材７は回路基板４
及び耐熱性保護フィルム１４とほぼ面一に埋め込まれ
る。Next, in FIG. 1C, the circuit board 4 in which the through-hole 6 is formed is
Then, the metal sheet 21 is loaded onto the circuit board 4 on one surface 4a (the surface on which the conductor pattern 3 is formed) after the die hole 20a and the through hole 6 are positioned so as to coincide with each other. The metal sheet 21 forms the metal pillar 7, and has a sheet thickness corresponding to the thickness of the circuit board 4 and the heat-resistant protective film 14. The metal sheet 21 is shown in FIG.
It is made of a metal material having a layer configuration shown in (a) to (c). In this embodiment, the high melting point metal layer 7a shown in FIG.
A metal sheet 21 having a three-layer structure in which a low-melting metal layer 7b is laminated above and below is used. The metal sheet 21 is punched by moving the punch 22 downward, and the punched metal pillar 7 is embedded in the through hole 6 of the circuit board 4. Since the thickness of the metal sheet 21 is equivalent to the thickness of the circuit board 4 and the heat-resistant protective film 14, the punched metal pillars 7
And it is embedded almost flush with the heat-resistant protective film 14.
【００１６】次に、図１（ｄ）において、金属柱材７が
埋め込まれた回路基板４を、かしめ装置２３に搬入し
て、貫通孔６に埋め込まれた金属柱材７を上下より金型
２４でかしめて柱材端面の平坦度を出すようになってい
る。これによって、接続端子となる金属柱材７を基板実
装する際の接続信頼性を向上させることができる。Next, in FIG. 1D, the circuit board 4 in which the metal pillars 7 are embedded is carried into a caulking device 23, and the metal pillars 7 embedded in the through holes 6 are vertically inserted into a mold. At 24, the flatness of the end face of the pillar is obtained. Thereby, the connection reliability when mounting the metal pillar 7 serving as the connection terminal on the substrate can be improved.
【００１７】次に、図１（ｅ）において、金属柱材７は
高融点金属層７ａの上層及び下層に低融点金属層７ｂが
積層されて形成された金属複合柱材であり、導体パター
ン３側の低融点金属層３ｂの露出端面に加熱して導体パ
ターン３と接合する。これは、金属柱材７を貫通孔６に
埋め込んだだけでも導体パターン３と初期導通はすると
考えられるが、熱サイクル試験を行うことにより、導体
パターン３と金属柱材７との熱膨張率の相違により接続
信頼性が維持できなくなるおそれがあることを考慮した
ものである。尚、金属柱材７として、図３（ｂ）に示す
高融点金属層３ａに低融点金属層７ｂが積層された金属
複合柱材の場合には、高融点金属層３ａの露出端面に金
属めっき層（例えばニッケルめっき層、銅めっき層）を
形成して導体パターン３と接合するのが望ましい。Next, in FIG. 1E, the metal pillar 7 is a metal composite pillar formed by laminating a low melting metal layer 7b on the upper and lower layers of the high melting metal layer 7a. The exposed end surface of the low-melting-point metal layer 3b on the side is heated and joined to the conductor pattern 3. Although it is considered that the initial conduction with the conductor pattern 3 is achieved only by embedding the metal pillars 7 in the through holes 6, the thermal expansion test shows that the thermal expansion coefficient between the conductor pattern 3 and the metal pillars 7 can be reduced. The reason is that connection reliability may not be maintained due to the difference. In the case of a metal composite column having the low-melting metal layer 7b laminated on the high-melting metal layer 3a shown in FIG. 3B, the metal plating 7 is formed on the exposed end face of the high-melting metal layer 3a. It is desirable to form a layer (for example, a nickel plating layer or a copper plating layer) and join it to the conductor pattern 3.
【００１８】次いで、上述した製法で製造された半導体
パッケージ１を用いて半導体装置１１を製造する工程に
ついて説明する。図１（ｆ）において、回路基板４の一
方の面４ａに設けられたチップ搭載部５に、半導体チッ
プ８を搭載する（ダイボンディング）。そして、半導体
チップ８の電極部と導体パターン３のチップパッドとの
間にボンディングワイヤ９により電気的に接続する（ワ
イヤボンディング）。このとき、回路基板４には、ワイ
ヤボンディングの際に押圧力が加わるが、回路基板４の
他方の面４ｂには接続端子となる金属柱材７が設けられ
ているが、該他方の面４ｂには耐熱性保護フィルム１４
が貼り合わされて全体として平坦面に形成されているの
で、接続端子となる金属柱材７の端面の平坦度が失われ
るおそれはない。Next, a process of manufacturing the semiconductor device 11 using the semiconductor package 1 manufactured by the above-described manufacturing method will be described. In FIG. 1F, a semiconductor chip 8 is mounted on a chip mounting portion 5 provided on one surface 4a of the circuit board 4 (die bonding). Then, an electrical connection is made between the electrode portion of the semiconductor chip 8 and the chip pad of the conductor pattern 3 by a bonding wire 9 (wire bonding). At this time, a pressing force is applied to the circuit board 4 at the time of wire bonding. On the other face 4b of the circuit board 4, a metal pillar 7 serving as a connection terminal is provided. Has a heat-resistant protective film 14
Are bonded to form a flat surface as a whole, so that there is no possibility that the flatness of the end surface of the metal pillar 7 serving as the connection terminal is lost.
【００１９】また、回路基板４を、図示しない樹脂封止
装置に搬入して半導体チップ８の周囲を封止樹脂１０よ
り封止する。このとき、回路基板４をモールド金型によ
りクランプする際に、他方の面４ｂに耐熱性保護フィル
ム１４が貼り合わされて全体として平坦面に形成されて
いるので接続端子となる金属柱材７の端面の平坦度が失
われるおそれはない。Further, the circuit board 4 is carried into a resin sealing device (not shown) to seal the periphery of the semiconductor chip 8 with the sealing resin 10. At this time, when the circuit board 4 is clamped by the mold, the heat-resistant protective film 14 is adhered to the other surface 4b and the entire surface is formed as a flat surface. There is no danger that the flatness of this will be lost.
【００２０】次に、図１（ｇ）において、回路基板４の
他方の面４ｂに貼り合わされている耐熱性保護フィルム
１４を剥離させて、金属柱材７を回路基板４の他方の面
４ｂに突設する。これにより、図３（ｃ）に示すよう
に、回路基板４の一方の面４ａにパッケージ部（樹脂封
止部）が形成され、他方の面４ｂに接続端子（金属柱材
７）が形成された半導体装置１１が形成される。この半
導体装置１１は、従来のように、はんだボールを使用す
ることなくバンプ形成が行えるので、実装基板への接続
信頼性を高めることができる。また、半導体装置１１は
最終工程で回路基板４の他方の面４ｂから耐熱性保護フ
ィルム１４を剥離させるので、半導体パッケージ１の加
工工程を含めて接続端子部となる金属柱材７の平坦度を
維持でき、しかも回路基板４の両面を略平坦な状態で各
種加工を行えるので取扱いが容易であり、連続加工し易
いので、安価に大量生産することが可能である。Next, in FIG. 1 (g), the heat-resistant protective film 14 attached to the other surface 4b of the circuit board 4 is peeled off, and the metal pillar 7 is attached to the other surface 4b of the circuit board 4. To protrude. Thereby, as shown in FIG. 3C, a package portion (resin sealing portion) is formed on one surface 4a of the circuit board 4, and a connection terminal (metal column member 7) is formed on the other surface 4b. The semiconductor device 11 is formed. In the semiconductor device 11, bumps can be formed without using solder balls as in the related art, so that the reliability of connection to the mounting board can be improved. Further, since the semiconductor device 11 peels off the heat-resistant protective film 14 from the other surface 4b of the circuit board 4 in the final step, the flatness of the metal pillar 7 serving as a connection terminal part including the processing step of the semiconductor package 1 is reduced. Since various processes can be performed while maintaining both surfaces of the circuit board 4 in a substantially flat state, handling is easy, and continuous processing is easy, so mass production can be performed at low cost.
【００２１】前述した実施例は、図２（ｂ）に示すよう
に、耐熱性保護フィルム１４を回路基板４に対して樹脂
基材２側に貼り合わせて、半導体パッケージ１の回路基
板４の他方の面４ｂに接続端子を突設する場合について
説明した。これに対して、図２（ａ）に示すように、耐
熱性保護フィルム１４を回路基板４に対して導体パター
ン３側に貼り合わせることにより、半導体パッケージ１
の回路基板４の一方の面４ａに接続端子を突設するよう
にしても良い。この場合、金属柱材７として図３（ｃ）
に示す３層構造の金属複合柱材を用いた場合、低融点金
属層７ｂは上層側が接続端子となるため該上層側を下層
側より厚く形成するのが望ましい。In the above-described embodiment, as shown in FIG. 2B, a heat-resistant protective film 14 is attached to the circuit board 4 on the resin substrate 2 side, and the other side of the circuit board 4 of the semiconductor package 1 is formed. The case where the connection terminal protrudes from the surface 4b has been described. On the other hand, as shown in FIG. 2A, the heat-resistant protective film 14 is bonded to the circuit board 4 on the side of the conductor pattern 3 to form the semiconductor package 1.
The connection terminals may be protruded from one surface 4a of the circuit board 4 described above. In this case, as the metal pillar 7, FIG.
When a metal composite pillar having a three-layer structure shown in (1) is used, the lower melting metal layer 7b is desirably formed thicker on the upper layer side than on the lower layer side since the upper layer side serves as a connection terminal.
【００２２】また、図２（ｃ）に示すように、耐熱性保
護フィルム１４を回路基板４に対して導体パターン３側
及び樹脂基材２側に貼り合わせて、半導体パッケージ１
の回路基板４の両側４ａ、４ｂに接続端子を突設するよ
うにしても良い。この場合、図３（ｃ）に示す金属柱材
７の各層の厚さは、高融点金属層７ａの上層及び下層の
低融点金属層７ｂは共に接続端子となるため双方厚く形
成するのが望ましい。As shown in FIG. 2C, a heat-resistant protective film 14 is attached to the circuit board 4 on the side of the conductor pattern 3 and on the side of the resin substrate 2 to form the semiconductor package 1.
Connection terminals may be provided on both sides 4a and 4b of the circuit board 4 of FIG. In this case, it is desirable that the thickness of each layer of the metal pillar 7 shown in FIG. 3 (c) be both thick because the upper and lower low melting point metal layers 7b both serve as connection terminals. .
【００２３】このように、回路基板４に対して耐熱性保
護フィルム１４を何れの面に張り合わせるかによって、
回路基板４に対し任意の箇所に金属柱材７による接続用
の突起（バンプ）を形成でき、汎用性、利便性の高い半
導体パッケージ１を提供できる。回路基板４には耐熱性
保護フィルム１４を貼り合わせたまま、接続用の突起
（バンプ）を形成でき、最終工程で基板面から耐熱性保
護フィルム１４を剥離させるので、半導体パッケージ１
の加工工程を含めて接続用の突起（バンプ）となる金属
柱材７の平坦度を維持できる。また回路基板４の両面を
略平坦な状態で各種プレス加工を行えるので取扱いが容
易であり、しかも連続加工し易いので、安価に大量生産
することが可能である。As described above, depending on which surface the heat resistant protective film 14 is attached to the circuit board 4,
Protrusions (bumps) for connection by the metal pillars 7 can be formed at arbitrary positions on the circuit board 4, and the semiconductor package 1 with high versatility and convenience can be provided. The projections (bumps) for connection can be formed on the circuit board 4 with the heat-resistant protective film 14 attached thereto, and the heat-resistant protective film 14 is peeled off from the substrate surface in the final step.
It is possible to maintain the flatness of the metal pillars 7 that become the connection projections (bumps), including the processing step described above. In addition, since various press workings can be performed with both surfaces of the circuit board 4 being substantially flat, handling is easy, and continuous processing is easy, so mass production can be performed at low cost.
【００２４】上述した実施例は基板１２として片面銅張
基板を用いて説明したが（図１（ａ）参照）、両面銅張
基板を用いても良い。この場合、貫通孔６に埋め込まれ
た金属柱材７は接続用の突起（バンプ）として用いられ
る他に層間接続用の端子として用いることができる。Although the above embodiment has been described using a single-sided copper-clad substrate as the substrate 12 (see FIG. 1A), a double-sided copper-clad substrate may be used. In this case, the metal pillar 7 buried in the through hole 6 can be used not only as a projection (bump) for connection but also as a terminal for interlayer connection.
【００２５】また、半導体装置１１が、半導体チップ８
が半導体パッケージ１にフリップチップ接続されるタイ
プの場合には、金属柱材７はチップ搭載部５に形成さ
れ、導体パターン３と接合され、回路基板４のチップ接
続端子として形成されていても良い。また、フリップチ
ップ実装する場合には、半導体チップ８を回路基板４に
形成たれたランド部にフリップチップ接続し、半導体チ
ップ８と回路基板４面との隙間を含む該半導体チップ８
の周囲にアンダーフィルモールドが行われる。Further, the semiconductor device 11 is connected to the semiconductor chip 8
Is a type that is flip-chip connected to the semiconductor package 1, the metal pillar 7 may be formed on the chip mounting portion 5, joined to the conductor pattern 3, and formed as a chip connection terminal of the circuit board 4. . In the case of flip-chip mounting, the semiconductor chip 8 is flip-chip connected to a land formed on the circuit board 4, and the semiconductor chip 8 including a gap between the semiconductor chip 8 and the surface of the circuit board 4.
Is underfilled around the periphery of the substrate.
【００２６】また、図４に半導体装置１１の応用例を示
す。半導体チップ８がＲＡＭ等のメモリ素子の場合に
は、アドレスバス、データバスなどのバスラインが共有
できる。よって、半導体装置１１の回路基板４の一方側
及び両側に金属柱材７を突設して、該金属柱材７どうし
を接合して半導体装置１１を積層して設けることも可能
である。金属柱材７は端子間の接合性を考慮すると、図
３（ｃ）に示す３層構造の金属複合柱材が好適に用いら
れる。即ち、金属柱材７のうち、上層及び下層に設けら
れた低融点金属層７ｂどうしを接合することにより半導
体装置１１どうしを積層できる。この場合、金属柱材７
は、半導体チップ８と他の回路基板４との接触を防止す
るスペーサとして利用できる上に、各半導体装置１１間
の電気的接続をとることができる。この場合にも、はん
だボールに比べて、接続端子が安価で製造が容易であ
り、また、回路基板上の接続端子の設置面積をとらずに
しかも接続端子の平坦度を維持して形成されるので、パ
ッケージと基板間の高さが安定するので、接続信頼性も
向上させることができる。FIG. 4 shows an application example of the semiconductor device 11. When the semiconductor chip 8 is a memory element such as a RAM, bus lines such as an address bus and a data bus can be shared. Therefore, it is also possible to project the metal pillars 7 on one side and both sides of the circuit board 4 of the semiconductor device 11 and join the metal pillars 7 to form the semiconductor device 11 in a stacked manner. Considering the joining property between the terminals, a metal composite pillar having a three-layer structure shown in FIG. 3C is preferably used as the metal pillar 7. That is, the semiconductor devices 11 can be stacked together by joining the low-melting metal layers 7b provided in the upper layer and the lower layer in the metal column members 7. In this case, the metal pillar 7
Can be used as a spacer for preventing the contact between the semiconductor chip 8 and the other circuit board 4 and can establish an electrical connection between the semiconductor devices 11. Also in this case, the connection terminals are inexpensive and easy to manufacture as compared with the solder balls, and are formed without taking up the installation area of the connection terminals on the circuit board and maintaining the flatness of the connection terminals. Therefore, the height between the package and the substrate is stabilized, and the connection reliability can be improved.
【００２７】以上、本発明の好適な実施例について述べ
てきたが、本発明は上述した各実施例に限定されるのも
のではなく、例えば、金属柱材７の材質は、はんだやは
んだ合金、銅や銅合金に限らず他の導電材料であっても
良い等、発明の精神を逸脱しない範囲で多くの改変を施
し得るのはもちろんである。Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiments. For example, the material of the metal pillar 7 may be a solder, a solder alloy, Of course, many modifications can be made without departing from the spirit of the invention, such as not only copper or copper alloy but also other conductive materials.
【００２８】[0028]
【発明の効果】本発明に係る半導体パッケージを用いれ
ば、回路基板の一方側の面又は両側面に耐熱性保護フィ
ルムが積層され、これらを打ち抜いて形成された貫通孔
に金属柱材が埋め込まれて導体パターンと接続されて接
続用の突起（バンプ）が形成できるので、回路基板に対
して耐熱性保護フィルムを何れの面に張り合わせるかに
よって、任意の箇所に接続用の突起（バンプ）を形成で
き、汎用性、利便性の高い半導体パッケージを提供でき
る。また、はんだボールに比べて、接続端子が安価で製
造が容易であり、接続端子の設置面積をとらずにしかも
接続端子の平坦度を維持して形成できるので、接続信頼
性も向上させることができる。また、半導体パッケージ
の製造方法を用いれば、回路基板には耐熱性保護フィル
ムを貼り合わせたまま、接続用の突起（バンプ）を形成
でき、最終工程で基板面から耐熱性保護フィルムを剥離
させるので、半導体パッケージの加工工程を含めて接続
用の突起（バンプ）の平坦度を維持でき、回路基板の両
面を略平坦な状態で各種プレス加工を行えるので取扱い
が容易であり、しかも連続加工し易いので、安価に大量
生産することが可能である。When the semiconductor package according to the present invention is used, a heat-resistant protective film is laminated on one side or both sides of the circuit board, and a metal pillar is embedded in a through hole formed by punching them. The connection projections (bumps) can be formed by being connected to the conductor pattern, so that the connection projections (bumps) can be formed at any locations depending on which surface the heat-resistant protective film is attached to the circuit board. A semiconductor package which can be formed and has high versatility and convenience can be provided. Also, compared to solder balls, the connection terminals are inexpensive and easy to manufacture, and can be formed without taking up the installation area of the connection terminals and maintaining the flatness of the connection terminals, thereby improving the connection reliability. it can. In addition, if a semiconductor package manufacturing method is used, projections (bumps) for connection can be formed with the heat-resistant protective film attached to the circuit board, and the heat-resistant protective film is peeled off from the substrate surface in the final step. In addition, the flatness of the connection projections (bumps) can be maintained, including the processing steps of the semiconductor package, and various types of press processing can be performed while both surfaces of the circuit board are substantially flat, so that handling is easy and continuous processing is easy. Therefore, mass production is possible at low cost.
【００２９】また、半導体装置及びその製造方法によれ
ば、従来のように、はんだボールを使用することなく安
価に量産可能であり、しかも小径で高さ精度が良く端面
の平坦度を維持して接続端子が形成できるので、実装基
板への接続信頼性を高めることができる。また、半導体
装置は最終工程で基板面から耐熱性保護フィルムを剥離
させるので、半導体パッケージの加工工程を含めて接続
端子となる金属柱材の平坦度を維持でき、しかも基板の
両面に耐熱性保護フィルムを貼り合わせたまま略平坦な
状態で各種加工を行えるので取扱いが容易である。Further, according to the semiconductor device and the method of manufacturing the same, mass production can be performed at a low cost without using solder balls as in the prior art, and a small-diameter, high-precision and high-precision end face flatness can be maintained. Since connection terminals can be formed, the reliability of connection to the mounting board can be improved. In addition, since the semiconductor device peels off the heat-resistant protective film from the substrate surface in the final process, the flatness of the metal pillars that become the connection terminals can be maintained, including the semiconductor package processing step, and the heat-resistant protection is applied to both surfaces of the substrate. Since various processes can be performed in a substantially flat state with the film attached, the handling is easy.
【図１】半導体パッケージ及び半導体装置の製造工程を
示す説明図である。FIG. 1 is an explanatory diagram showing a manufacturing process of a semiconductor package and a semiconductor device.
【図２】半導体パッケージのバンプ形成の態様を例示す
る説明図である。FIG. 2 is an explanatory diagram illustrating a mode of forming a bump of a semiconductor package;
【図３】半導体装置の態様を例示する説明図である。FIG. 3 is an explanatory diagram illustrating an embodiment of a semiconductor device.
【図４】半導体装置の応用例を示す説明図である。FIG. 4 is an explanatory diagram illustrating an application example of a semiconductor device.
【符号の説明】 １ 半導体パッケージ ２ 樹脂基材 ３ 導体パターン ４ 回路基板 ５ チップ搭載部 ６ 貫通孔 ７ 金属柱材 ７ａ 高融点金属層 ７ｂ 低融点金属層 ８ 半導体チップ ９ ボンディングワイヤ １０ 封止樹脂 １１ 半導体装置 １２ 基板 １３ 導体層 １４ 耐熱性保護フィルム １５ 第１のプレス装置 １６、２０ ダイ １７、２２ パンチ １９ 第２のプレス装置 ２１ 金属シート ２３ かしめ装置 ２４ 金型[Description of Signs] 1 Semiconductor package 2 Resin base material 3 Conductor pattern 4 Circuit board 5 Chip mounting portion 6 Through hole 7 Metal column material 7a High melting point metal layer 7b Low melting point metal layer 8 Semiconductor chip 9 Bonding wire 10 Sealing resin 11 Semiconductor device 12 Substrate 13 Conductive layer 14 Heat-resistant protective film 15 First press device 16, 20 Die 17, 22 Punch 19 Second press device 21 Metal sheet 23 Caulking device 24 Mold
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/18 25/10 25/11 Ｆターム(参考） 5F067 AA13 DF01 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 25/18 25/10 25/11 F-term (Reference) 5F067 AA13 DF01
Claims (14)
路基板に半導体チップを搭載して基板実装可能な半導体
パッケージにおいて、 前記回路基板の一方側の面又は両側面に耐熱性保護フィ
ルムが積層され、これらを打ち抜いて形成された貫通孔
に金属柱材が埋め込まれて導体パターンと接続されてい
ることを特徴とする半導体パッケージ。1. A semiconductor package mountable by mounting a semiconductor chip on a circuit board having a conductive pattern laminated on a resin base material, wherein a heat-resistant protective film is laminated on one side or both sides of the circuit board. A semiconductor package characterized in that a metal pillar is embedded in a through-hole formed by punching these and connected to a conductor pattern.
性保護フィルム面にほぼ面一にとなるように埋め込まれ
ていることを特徴とする請求項１記載の半導体パッケー
ジ。2. The semiconductor package according to claim 1, wherein said metal column material is buried so as to be substantially flush with a substrate surface and / or a heat-resistant protective film surface.
金属層が積層されて形成された金属複合柱材であること
を特徴とする請求項１記載の半導体パッケージ。3. The semiconductor package according to claim 1, wherein said metal column material is a metal composite column material formed by laminating a high melting point metal layer and a low melting point metal layer.
び下層に低融点金属層が積層されて形成された金属複合
柱材であることを特徴とする請求項１記載の半導体パッ
ケージ。4. The semiconductor package according to claim 1, wherein said metal column material is a metal composite column material formed by laminating a low melting point metal layer on an upper layer and a lower layer of a high melting point metal layer.
両側端面がかしめられて、平坦面に形成されていること
を特徴とする請求項１記載の半導体パッケージ。5. The semiconductor package according to claim 1, wherein the metal pillar is formed with a flat surface by caulking both side surfaces embedded in the through hole.
れ、パッケージの基板接続端子として形成されているこ
とを特徴とする請求項１記載の半導体パッケージ。6. The semiconductor package according to claim 1, wherein the metal pillar is joined to a conductor pattern and formed as a substrate connection terminal of the package.
れ、パッケージのチップ接続端子として形成されている
ことを特徴とする請求項１記載の半導体パッケージ。7. The semiconductor package according to claim 1, wherein the metal pillar is joined to a conductor pattern and formed as a chip connection terminal of the package.
導体パッケージに半導体チップが搭載され、耐熱性保護
フィルムが剥離されて、基板面に金属柱材が接続端子と
して突出形成されていることを特徴とする半導体装置。8. A semiconductor chip is mounted on the semiconductor package according to claim 1, the heat-resistant protective film is peeled off, and a metal pillar is formed as a connection terminal on the substrate surface. A semiconductor device characterized in that:
半導体パッケージの製造方法において、 樹脂基材に導体層が積層されてなる基板の該導体層に導
体パターンを形成する工程と、 導体パターンが形成された回路基板の一方側の面又は両
側面に耐熱性保護フィルムを貼り合わせる工程と、 耐熱性保護フィルムが貼り合わされた回路基板を打ち抜
いて貫通孔を形成する工程と、 貫通孔が形成された回路基板に金属シートを積層して打
ち抜き、打ち抜かれた金属柱材を貫通孔内に埋め込む工
程と、 埋め込まれた金属柱材をかしめる工程とを含むことを特
徴とする半導体パッケージの製造方法。9. A method of manufacturing a semiconductor package in which a semiconductor chip can be mounted and mounted on a substrate, comprising: forming a conductive pattern on the conductive layer of a substrate having a conductive layer laminated on a resin base; A step of attaching a heat-resistant protective film to one side or both sides of the formed circuit board; a step of punching out the circuit board on which the heat-resistant protective film is attached to form a through-hole; A method of manufacturing a semiconductor package, comprising: laminating a metal sheet on a circuit board that has been punched out, embedding the punched metal pillar material in a through hole, and caulking the embedded metal pillar material. .
層が積層されて形成された金属複合柱材であり、高融点
金属層の露出端面に金属めっき層を形成して導体パター
ンと接合する工程を含むことを特徴とする請求項９記載
の半導体パッケージの製造方法。10. A metal column material is a metal composite column material formed by laminating a high melting point metal layer and a low melting point metal layer. A metal plating layer is formed on an exposed end face of the high melting point metal layer to form a conductive pattern. The method for manufacturing a semiconductor package according to claim 9, further comprising a joining step.
層に低融点金属層が積層されて形成された金属複合柱材
であり、低融点金属層の露出端面に加熱して導体パター
ンと接合する工程を含むことを特徴とする請求項９記載
の半導体パッケージの製造方法。11. The metal column material is a metal composite column material formed by laminating a low-melting metal layer on an upper layer and a lower layer of a high-melting metal layer. The method for manufacturing a semiconductor package according to claim 9, further comprising a joining step.
載の製造方法によって製造された半導体パッケージに半
導体チップを搭載する工程と、 半導体チップと導体パターンとを電気的に導通させる工
程と、 耐熱性保護フィルムを剥離させて、金属柱材を基板の一
方又は両面側に突設する工程とを含むことを特徴とする
半導体装置の製造方法。12. A step of mounting a semiconductor chip on a semiconductor package manufactured by the manufacturing method according to claim 9, and a step of electrically connecting the semiconductor chip to a conductor pattern. Peeling off the heat-resistant protective film, and projecting a metal pillar on one or both sides of the substrate.
ヤボンディング接続する工程と、半導体チップの周囲を
樹脂封止する工程とを含むことを特徴とする請求項１２
記載の半導体装置の製造方法。13. The method according to claim 12, further comprising the steps of: mounting the semiconductor chip on a substrate surface and performing wire bonding connection; and sealing the periphery of the semiconductor chip with a resin.
The manufacturing method of the semiconductor device described in the above.
ンド部にフリップチップ接続する工程と、半導体チップ
と基板面との隙間を含む該半導体チップの周囲にアンダ
ーフィルモールドを行う工程と含むことを特徴とする請
求項１２記載の半導体装置の製造方法。14. A method for flip-chip connecting a semiconductor chip to a land formed on a substrate surface, and performing an underfill molding around the semiconductor chip including a gap between the semiconductor chip and the substrate surface. The method of manufacturing a semiconductor device according to claim 12, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001093244A JP2002289744A (en) | 2001-03-28 | 2001-03-28 | Semiconductor package, its manufacturing method, semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001093244A JP2002289744A (en) | 2001-03-28 | 2001-03-28 | Semiconductor package, its manufacturing method, semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002289744A true JP2002289744A (en) | 2002-10-04 |
Family
ID=18947602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001093244A Pending JP2002289744A (en) | 2001-03-28 | 2001-03-28 | Semiconductor package, its manufacturing method, semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002289744A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002305361A (en) * | 2001-04-05 | 2002-10-18 | Casio Micronics Co Ltd | Flexible wiring board, manufacturing method therefor, joining structure of flexible wiring board and joining method therefor |
-
2001
- 2001-03-28 JP JP2001093244A patent/JP2002289744A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002305361A (en) * | 2001-04-05 | 2002-10-18 | Casio Micronics Co Ltd | Flexible wiring board, manufacturing method therefor, joining structure of flexible wiring board and joining method therefor |
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