JP2002246553A - Noise suppressor in semiconductor integrated circuit - Google Patents
Noise suppressor in semiconductor integrated circuitInfo
- Publication number
- JP2002246553A JP2002246553A JP2001040337A JP2001040337A JP2002246553A JP 2002246553 A JP2002246553 A JP 2002246553A JP 2001040337 A JP2001040337 A JP 2001040337A JP 2001040337 A JP2001040337 A JP 2001040337A JP 2002246553 A JP2002246553 A JP 2002246553A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- noise
- metal electrode
- electrode layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、アナログ・ディジ
タル混載半導体集積回路において、ディジタル回路が発
生するノイズのアナログ回路に対する影響を低減するノ
イズ低減装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reduction device for reducing the influence of noise generated by a digital circuit on an analog circuit in an analog / digital mixed semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】図８はアナログ・ディジタル混載半導体
集積回路における従来のノイズ低減装置の構成を示す図
である。図８において、アナログ・ディジタル混載のＰ
型半導体集積回路８００は、ディジタル回路であるノイ
ズ発生源８０１とアナログ回路であるノイズ保護対象回
路８０７を搭載する。各回路は接地用メタル電極層８０
２及び８０４でそれぞれ囲まれ、各接地用メタル電極層
はそれぞれ外部接続用パッド８０８及び８０５を介して
それぞれの回路用の接地電源８１０及び８１４に接続さ
れる。2. Description of the Related Art FIG. 8 is a diagram showing a configuration of a conventional noise reduction device in an analog / digital hybrid semiconductor integrated circuit. In FIG. 8, the analog / digital mixed P
The semiconductor integrated circuit 800 includes a noise source 801 as a digital circuit and a noise protection target circuit 807 as an analog circuit. Each circuit is a metal electrode layer 80 for grounding.
2 and 804, respectively, and the ground metal electrode layers are connected to ground power supplies 810 and 814 for the respective circuits via external connection pads 808 and 805, respectively.
【０００３】ノイズ発生源８０１が動作すると、ノイズ
発生源側の接地用メタル電極層８０２にノイズが発生す
る。接地用メタル電極層８０２に発生したノイズは、Ｐ
型基板寄生抵抗８０３、ノイズ保護対象回路側の接地用
メタル電極層８０４に到達し、接地用メタル電極層８０
４に到達した一部のノイズは、外部接続用パッド８０５
を通過し、半導体集積回路外部で駆動電源８１５と接地
電源８１４の間に接続されたバイパスコンデンサ８０６
に吸収される。接地用メタル電極層８０４に到達して残
った一部のノイズは、ノイズ保護対象回路８０７に到達
する。When the noise source 801 operates, noise is generated in the ground metal electrode layer 802 on the noise source side. The noise generated in the ground metal electrode layer 802 is P
The mold substrate parasitic resistance 803 reaches the grounding metal electrode layer 804 on the noise protection target circuit side, and
4 reach the external connection pad 805
And a bypass capacitor 806 connected between the drive power supply 815 and the ground power supply 814 outside the semiconductor integrated circuit.
Is absorbed by Part of the noise remaining after reaching the ground metal electrode layer 804 reaches the noise protection target circuit 807.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら従来のノ
イズ低減装置では、ノイズ発生源で発生した一部のノイ
ズはノイズ保護対象回路側の接地用メタル電極層から外
部接続用パッドを通過し、外部のバイパスコンデンサで
吸収される。しかし、接地用メタル電極層に残った一部
のノイズはＰ型半導体集積回路上でノイズ保護対象回路
の接地電源からコンタクトホールを通してノイズ保護対
象回路のソース電極に達するため、ノイズ保護対象回路
に悪影響を及ぼすという問題を有していた。However, in the conventional noise reduction device, a part of the noise generated by the noise source passes through the external connection pad from the ground metal electrode layer on the noise protection target circuit side, and the external noise is reduced. It is absorbed by the bypass capacitor. However, part of the noise remaining on the ground metal electrode layer reaches the source electrode of the noise protection target circuit through the contact hole from the ground power supply of the noise protection target circuit on the P-type semiconductor integrated circuit. Had the problem of causing
【０００５】本発明はこのような点に鑑みてなされたも
のであり、アナログ・ディジタル混載半導体集積回路で
ディジタル回路が発生するノイズのアナログ回路に対す
る影響を低減するノイズ低減装置において、ノイズがア
ナログ回路側の接地用メタル電極層あるいは駆動用メタ
ル電極層に到達する前にノイズの低減を図ることができ
る半導体集積回路のノイズ低減装置を提供することを目
的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a noise reduction apparatus for reducing the influence of noise generated by a digital circuit on an analog circuit in an analog / digital mixed semiconductor integrated circuit. It is an object of the present invention to provide a noise reduction device for a semiconductor integrated circuit capable of reducing noise before reaching a ground metal electrode layer or a driving metal electrode layer on the side.
【０００６】[0006]
【課題を解決するための手段】本発明の請求項１に係る
半導体集積回路のノイズ低減装置は、Ｐ型半導体基板
（Ｐ型半導体基板１００；２００）上にノイズ発生源と
なる第１の回路（ノイズ発生源１０１；２０１）及びノ
イズ保護対象となる第２の回路（ノイズ保護対象回路１
０３；２０３）を有し、前記第１の回路が発生したノイ
ズから前記第２の回路を保護するための半導体集積回路
のノイズ低減装置において、前記第１の回路及び第２の
回路から独立して形成された外部接続用パッド（外部接
続用パッド１０６，１０７）と、前記第１の回路と第２
の回路との間に形成され、前記外部接続用パッドを介し
て前記Ｐ型半導体基板外にある前記第２の回路用の接地
電源（ノイズ保護対象回路の接地電源１０８）に接続さ
れたメタル電極層（ガードバンド用メタル電極層１０
５；２０５）と、前記メタル電極層の直下に形成され、
コンタクトホール（コンタクトホール２０７）を介して
前記メタル電極層に接続されたＰ型拡散領域（Ｐ型拡散
領域２０６）と、前記Ｐ型半導体基板外にある前記第２
の回路用の接地電源（ノイズ保護対象回路の接地電源１
０８）と駆動電源（ノイズ保護対象回路の駆動電源１０
９）との間に接続されたコンデンサ（バイパスコンデン
サ１１０）と、を具備する。According to a first aspect of the present invention, there is provided a noise reduction device for a semiconductor integrated circuit, wherein a first circuit serving as a noise source is provided on a P-type semiconductor substrate (P-type semiconductor substrate 100; 200). (Noise source 101; 201) and a second circuit to be protected from noise (noise protection target circuit 1).
03; 203), wherein a noise reduction device for a semiconductor integrated circuit for protecting the second circuit from noise generated by the first circuit is provided independently of the first circuit and the second circuit. External connection pads (external connection pads 106 and 107) formed by the first circuit and the second circuit.
And a metal electrode connected to the second circuit ground power supply (ground power supply 108 of the circuit to be protected) outside the P-type semiconductor substrate via the external connection pad. Layer (metal electrode layer 10 for guard band)
5; 205), and formed immediately below the metal electrode layer;
A P-type diffusion region (P-type diffusion region 206) connected to the metal electrode layer via a contact hole (contact hole 207);
Power supply for the circuit (ground power supply 1 for the circuit to be protected)
08) and the drive power supply (the drive power supply 10 for the circuit to be protected for noise).
9) and a capacitor (bypass capacitor 110) connected between the first and second capacitors.
【０００７】請求項１に記載の半導体集積回路のノイズ
低減装置によれば、ガードバンド用メタル電極層とその
直下に形成したＰ型拡散領域を、Ｐ型半導体基板上で独
立した外部接続用パッドを介してＰ型半導体基板外にあ
るノイズ保護対象となる第２の回路用の接地電源に接続
することにより、Ｐ型半導体基板上の回路と独立に、ガ
ードバンド用メタル電極層とＰ型拡散領域の電位をＰ型
半導体基板外にある第２の回路用の接地電源の電位に維
持することができ、Ｐ型半導体基板内部の接地電源経由
で第２の回路のソース電極に伝わるノイズを低減するこ
とができる。さらに、Ｐ型半導体基板外で第２の回路の
接地電源と駆動電源との間に接続したコンデンサによ
り、第１の回路で発生したノイズが第２の回路の接地電
源に到達する前に吸収されるので、第２の回路に伝わる
ノイズを低減することができる。According to the noise reducing device for a semiconductor integrated circuit according to the first aspect, the guard band metal electrode layer and the P-type diffusion region formed immediately below the guard band metal electrode layer are formed on the P-type semiconductor substrate by independent external connection pads. And a ground power supply for the second circuit outside the P-type semiconductor substrate to be protected from noise via the P-type semiconductor substrate, so that the metal electrode layer for the guard band and the P-type diffusion are independent of the circuit on the P-type semiconductor substrate. The potential of the region can be maintained at the potential of the ground power supply for the second circuit outside the P-type semiconductor substrate, and noise transmitted to the source electrode of the second circuit via the ground power supply inside the P-type semiconductor substrate is reduced. can do. Further, the noise generated in the first circuit is absorbed before reaching the ground power supply of the second circuit by the capacitor connected between the ground power supply of the second circuit and the drive power supply outside the P-type semiconductor substrate. Therefore, noise transmitted to the second circuit can be reduced.
【０００８】本発明の請求項２に係る半導体集積回路の
ノイズ低減装置は、Ｎ型半導体基板（Ｎ型半導体基板３
００；４００）上にノイズ発生源となる第１の回路（ノ
イズ発生源３０１；４０１）及びノイズ保護対象となる
第２の回路（ノイズ保護対象回路３０３；４０３）を有
し、前記第１の回路が発生したノイズから前記第２の回
路を保護するための半導体集積回路のノイズ低減装置に
おいて、前記第１の回路及び第２の回路から独立して形
成された外部接続用パッド（外部接続用パッド３０６，
３０７）と、前記第１の回路と第２の回路との間に形成
され、前記外部接続用パッドを介して前記Ｎ型半導体基
板外にある前記第２の回路用の駆動電源（ノイズ保護対
象回路の駆動電源３０８）に接続されたメタル電極層
（ガードバンド用メタル電極層３０５；４０５）と、前
記メタル電極層の直下に形成され、コンタクトホール
（コンタクトホール４０７）を介して前記メタル電極層
に接続されたＮ型拡散領域（Ｎ型拡散領域４０６）と、
前記Ｎ型半導体基板外にある前記第２の回路用の駆動電
源と（ノイズ保護対象回路の駆動電源３０８）設置電源
（ノイズ保護対象回路の接地電源３０９）との間に接続
されたコンデンサ（バイパスコンデンサ３１０）と、を
具備する。According to a second aspect of the present invention, there is provided a noise reduction device for a semiconductor integrated circuit, comprising: an N-type semiconductor substrate;
00; 400), a first circuit (noise source 301; 401) serving as a noise generation source and a second circuit (noise protection target circuit 303; 403) serving as a noise protection target. In a noise reduction device for a semiconductor integrated circuit for protecting the second circuit from noise generated by a circuit, an external connection pad (external connection pad) formed independently of the first circuit and the second circuit. Pad 306,
307), and a drive power supply (for noise protection) for the second circuit which is formed between the first circuit and the second circuit and is outside the N-type semiconductor substrate via the external connection pad. A metal electrode layer (guard-band metal electrode layer 305; 405) connected to a circuit driving power supply 308); and a metal electrode layer formed immediately below the metal electrode layer and contact hole (contact hole 407). An N-type diffusion region (N-type diffusion region 406) connected to
A capacitor (bypass) connected between the driving power supply for the second circuit outside the N-type semiconductor substrate and the driving power supply (the driving power supply 308 for the noise protection target circuit) and the installation power supply (the ground power supply 309 for the noise protection target circuit) And a capacitor 310).
【０００９】請求項２に記載の半導体集積回路のノイズ
低減装置によれば、ガードバンド用メタル電極層とその
直下に形成したＮ型拡散領域を、Ｎ型半導体基板上で独
立した外部接続用パッドを介してＮ型半導体基板外にあ
るノイズ保護対象となる第２の回路用の駆動電源に接続
することにより、Ｎ型半導体基板上の回路と独立に、ガ
ードバンド用メタル電極層とＮ型拡散領域の電位をＮ型
半導体基板外にある第２の回路用の駆動電源の電位に維
持することができ、Ｎ型半導体基板内部の駆動電源経由
で第２の回路のソース電極に伝わるノイズを低減するこ
とができる。さらに、Ｎ型半導体基板外で第２の回路の
駆動電源と接地電源との間に接続したコンデンサによ
り、第１の回路で発生したノイズが第２の回路の駆動電
源に到達する前に吸収されるので、第２の回路に伝わる
ノイズを低減することができる。According to a second aspect of the present invention, a guard band metal electrode layer and an N-type diffusion region formed immediately below the guard band metal electrode layer are formed on an N-type semiconductor substrate by independent external connection pads. , A guard band metal electrode layer and an N-type diffusion are connected independently to the circuit on the N-type semiconductor substrate by connecting to a drive power supply for the second circuit outside the N-type semiconductor substrate and subject to noise protection. The potential of the region can be maintained at the potential of the drive power supply for the second circuit outside the N-type semiconductor substrate, reducing noise transmitted to the source electrode of the second circuit via the drive power supply inside the N-type semiconductor substrate. can do. Further, the noise generated in the first circuit is absorbed before reaching the drive power supply of the second circuit by the capacitor connected between the drive power supply of the second circuit and the ground power supply outside the N-type semiconductor substrate. Therefore, noise transmitted to the second circuit can be reduced.
【００１０】本発明の請求項３に係る半導体集積回路の
ノイズ低減装置は、前記メタル電極層が複数積層され、
かつ互いにコンタクトホールを介して接続されることを
特徴とする。According to a third aspect of the present invention, there is provided a noise reduction device for a semiconductor integrated circuit, wherein a plurality of the metal electrode layers are stacked,
In addition, they are connected to each other via a contact hole.
【００１１】請求項３に記載の半導体集積回路のノイズ
低減装置によれば、ガードバンド用メタル電極層を複数
層で構成することによりガードバンド用メタル電極層の
抵抗値を低減することができ、ガードバンド用メタル電
極層を介してコンデンサに吸収させるノイズの通過率が
向上するため、第２の回路に伝わるノイズを低減するこ
とができる。According to the third aspect of the present invention, the resistance value of the guard band metal electrode layer can be reduced by forming the guard band metal electrode layer with a plurality of layers. Since the transmittance of noise absorbed by the capacitor via the guard band metal electrode layer is improved, noise transmitted to the second circuit can be reduced.
【００１２】本発明の請求項４に係るアナログ・ディジ
タル混載半導体集積回路は、請求項１乃至請求項３の何
れか１項に記載の半導体集積回路のノイズ低減装置を用
いてアナログ・ディジタル混載半導体集積回路を構成す
る。According to a fourth aspect of the present invention, there is provided an analog / digital mixed semiconductor integrated circuit using the semiconductor integrated circuit noise reduction device according to any one of the first to third aspects. Construct an integrated circuit.
【００１３】請求項４に記載のアナログ・ディジタル混
載半導体集積回路によれば、請求項１乃至請求項３の何
れか１項に記載の半導体集積回路のノイズ低減装置をア
ナログ回路のノイズ保護手段として用いることができる
ので、アナログ回路に対するノイズを効果的に低減する
ことができる。According to a fourth aspect of the present invention, there is provided an analog / digital hybrid semiconductor integrated circuit, wherein the noise reduction device for a semiconductor integrated circuit according to any one of the first to third aspects is used as noise protection means for an analog circuit. Since it can be used, noise to an analog circuit can be effectively reduced.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１５】（実施の形態１）図１は、本発明の実施の
形態１に係るＰ型半導体基板を使用した半導体集積回路
のノイズ低減装置の構成を示す図であり、図２は、図１
のように構成された半導体集積回路のノイズ低減装置の
ＡＡ−ＢＢ断面図である。なお、図１に対応する図２の
部分を括弧内に示して説明する。(Embodiment 1) FIG. 1 is a diagram showing a configuration of a noise reduction device for a semiconductor integrated circuit using a P-type semiconductor substrate according to Embodiment 1 of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along line AA-BB of the noise reduction device for a semiconductor integrated circuit configured as described above. The description of FIG. 2 corresponding to FIG. 1 is given in parentheses.
【００１６】図１及び図２において、アナログ・ディジ
タル混載のＰ型半導体集積回路１００（２００）は、デ
ィジタル回路であるノイズ発生源１０１（２０１）とア
ナログ回路であるノイズ保護対象回路１０３（２０３）
を搭載する。ノイズ発生源は接地用メタル電極層１０２
（２０２）で囲まれ、ノイズ保護対象回路は接地用メタ
ル電極層１０４（２０４）で囲まれ、各接地用メタル電
極層はそれぞれの外部接続用パッド１１１及び１１７を
介してそれぞれの回路用の接地電源１１５及び１０８に
接続される。In FIG. 1 and FIG. 2, a P-type semiconductor integrated circuit 100 (200) in which analog and digital are mixed is a noise source 101 (201) which is a digital circuit and a noise protection target circuit 103 (203) which is an analog circuit.
With. The noise source is the ground metal electrode layer 102
(202), the circuit to be protected is surrounded by the ground metal electrode layer 104 (204), and each ground metal electrode layer is grounded for each circuit via the external connection pads 111 and 117. Connected to power supplies 115 and 108.
【００１７】上述のようにＰ型半導体基板１００（２０
０）上にノイズ発生源１０１（２０１）とノイズ保護対
象回路１０３（２０３）が存在する場合、以下の手段に
よりノイズ低減装置を構成する。As described above, the P-type semiconductor substrate 100 (20
If the noise source 101 (201) and the noise protection target circuit 103 (203) are present on (0), a noise reduction device is configured by the following means.
【００１８】第１に、ノイズ発生源１０１（２０１）と
ノイズ保護対象回路１０３（２０３）の間に挟まれて双
方を十分に分離するガードバンド用メタル電極層１０５
(２０５）を形成する。First, the guard band metal electrode layer 105 sandwiched between the noise source 101 (201) and the noise protection target circuit 103 (203) to sufficiently separate the two from each other.
(205) is formed.
【００１９】第２に、ガードバンド用メタル電極層１０
５（２０５）の両端を、Ｐ型半導体基板上で独立した外
部接続用パッド１０６及び１０７に接続し、Ｐ型半導体
基板外にあるノイズ保護対象回路用の接地電源１０８か
ら電位をとる。Second, guard band metal electrode layer 10
5 (205) are connected to independent external connection pads 106 and 107 on the P-type semiconductor substrate, and a potential is taken from the ground power supply 108 for the circuit to be protected outside the P-type semiconductor substrate.
【００２０】第３に、ガードバンド用メタル電極層１０
５（２０５）の直下にＰ型拡散領域２０６を形成し、ガ
ードバンド用メタル電極層１０５（２０５）とＰ型拡散
領域２０６とをコンタクトホール２０７を介して接続す
ることにより、Ｐ型拡散領域２０６の電位をＰ型半導体
基板外にあるノイズ保護対象回路用の接地電源１０８か
らとる。Third, guard band metal electrode layer 10
5 (205), and by connecting the guard band metal electrode layer 105 (205) and the P-type diffusion region 206 through the contact hole 207, the P-type diffusion region 206 is formed. Is taken from the ground power supply 108 for the circuit to be protected outside the P-type semiconductor substrate.
【００２１】第４に、Ｐ型半導体基板外で、ノイズ保護
対象回路用の接地電源１０８と駆動電源１０９との間に
ノイズ吸収用のバイパスコンデンサ１１０を接続する。Fourth, a noise absorbing bypass capacitor 110 is connected between the ground power supply 108 for the circuit to be protected and the drive power supply 109 outside the P-type semiconductor substrate.
【００２２】以上のように構成されたノイズ低減装置に
おいて、ノイズ発生源１０１（２０１）で発生したノイ
ズは、ノイズ発生源側の接地用メタル電極層１０２（２
０２）、コンタクトホール２０８、Ｐ型拡散層領域２０
９、Ｐ型半導体基板の寄生抵抗２１０を順に通過し、Ｐ
型拡散領域２０６に到達する。In the noise reduction device configured as described above, the noise generated by the noise source 101 (201) is reduced to the ground metal electrode layer 102 (2) on the noise source side.
02), contact hole 208, P-type diffusion layer region 20
9. Passing through the parasitic resistance 210 of the P-type semiconductor substrate in order,
The mold diffusion region 206 is reached.
【００２３】Ｐ型拡散領域２０６に到達した一部のノイ
ズは、Ｐ型半導体基板の寄生抵抗２１１、Ｐ型拡散領域
２１２、コンタクトホール２１３、ノイズ保護対象回路
側の接地用メタル電極層２０４を通過し、ノイズ保護対
象回路１０３（２０３）に到達する。また、Ｐ型拡散領
域２０６に到達した他のノイズは、コンタクトホール２
０７、ガードバンド用メタル電極層１０５（２０５）、
外部接続用パッド１０６又は１０７を順に通過し、Ｐ型
半導体基板外でノイズ吸収用のバイパスコンデンサ１１
０に吸収される。Part of the noise reaching the P-type diffusion region 206 passes through the parasitic resistance 211 of the P-type semiconductor substrate, the P-type diffusion region 212, the contact hole 213, and the grounding metal electrode layer 204 on the noise protection target circuit side. Then, the signal reaches the noise protection target circuit 103 (203). Other noises that have reached the P-type diffusion region 206 are
07, guard band metal electrode layer 105 (205),
The bypass capacitor 11 passes through the external connection pad 106 or 107 in order and is outside the P-type semiconductor substrate.
Absorbed to zero.
【００２４】このように、実施の形態１のノイズ低減装
置によれば、図８の従来例に比較して、ノイズがノイズ
保護対象回路１０３（２０３）に到達するまでに、コン
タクトホール２０７、ガードバンド用メタル電極層１０
５（２０５）、外部接続用パッド１０６又は１０７を順
に通過してバイパスコンデンサ１１０に吸収される分の
ノイズを低減することができ、ノイズ保護対象回路に伝
わるノイズを低減することができる。As described above, according to the noise reduction device of the first embodiment, as compared with the conventional example of FIG. 8, the contact hole 207 and the guard are provided before the noise reaches the noise protection target circuit 103 (203). Band metal electrode layer 10
5 (205), the noise that passes through the external connection pad 106 or 107 and is absorbed by the bypass capacitor 110 can be reduced, and the noise transmitted to the noise protection target circuit can be reduced.
【００２５】（実施の形態２）図３は、本発明の実施の
形態２に係るＮ型半導体基板を使用した半導体集積回路
のノイズ低減装置の構成を示す図であり、図４は、図３
のように構成された半導体集積回路のノイズ低減装置の
ＡＡ−ＢＢ断面図である。なお、図３に対応する図４の
部分を括弧内に示して説明する。(Embodiment 2) FIG. 3 is a diagram showing a configuration of a noise reduction device for a semiconductor integrated circuit using an N-type semiconductor substrate according to Embodiment 2 of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along line AA-BB of the noise reduction device for a semiconductor integrated circuit configured as described above. 4 will be described in parentheses.
【００２６】図３及び図４において、アナログ・ディジ
タル混載のＮ型半導体集積回路３００（４００）は、デ
ィジタル回路であるノイズ発生源３０１（４０１）とア
ナログ回路であるノイズ保護対象回路３０３（４０３）
を搭載する。ノイズ発生源は駆動用メタル電極層３０２
（４０２）で囲まれ、ノイズ保護対象回路は駆動用メタ
ル電極層３０４（４０４）で囲まれ、各メタル電極層は
それぞれの外部接続用パッド３１１及び３１７を介して
それぞれの回路用の駆動電源３１５及び３０８に接続さ
れる。3 and 4, an N-type semiconductor integrated circuit 300 (400) in which analog and digital are mixed is a noise source 301 (401) which is a digital circuit and a noise protection target circuit 303 (403) which is an analog circuit.
With. The noise source is the driving metal electrode layer 302
The circuit to be protected from noise is surrounded by (402), and the circuit to be protected by noise is surrounded by the driving metal electrode layer 304 (404). And 308.
【００２７】上述のようにＮ型半導体基板３００（４０
０）上にノイズ発生源３０１（４０１）とノイズ保護対
象回路３０３（４０３）が存在する場合、以下の手段に
よりノイズ低減装置を構成する。As described above, the N-type semiconductor substrate 300 (40
In the case where the noise source 301 (401) and the noise protection target circuit 303 (403) are present on (0), a noise reduction device is configured by the following means.
【００２８】第１に、ノイズ発生源３０１（４０１）と
ノイズ保護対象回路３０３（４０３）の間に挟まれて双
方を十分に分離するガードバンド用メタル電極層３０５
(４０５）を形成する。First, a guard band metal electrode layer 305 sandwiched between the noise source 301 (401) and the noise protection target circuit 303 (403) to sufficiently separate the two from each other.
(405) is formed.
【００２９】第２に、ガードバンド用メタル電極層３０
５（４０５）の両端を、Ｎ型半導体基板上で独立した外
部接続用パッド３０６及び３０７に接続し、Ｎ型半導体
基板外にあるノイズ保護対象回路用の駆動電源３０８か
ら電位をとる。Second, guard band metal electrode layer 30
5 (405) are connected to independent external connection pads 306 and 307 on the N-type semiconductor substrate, and a potential is taken from the drive power supply 308 for the circuit to be protected outside the N-type semiconductor substrate.
【００３０】第３に、ガードバンド用メタル電極層３０
５（４０５）の直下にＮ型拡散領域４０６を形成し、ガ
ードバンド用メタル電極層３０５（４０５）とＮ型拡散
領域４０６とをコンタクトホール４０７を介して接続す
ることにより、Ｎ型拡散領域４０６の電位をＮ型半導体
基板外にあるノイズ保護対象回路用の駆動電源３０８か
らとる。Third, guard band metal electrode layer 30
5 (405), and by connecting the guard band metal electrode layer 305 (405) and the N-type diffusion region 406 through the contact hole 407, the N-type diffusion region 406 is formed. Is taken from the driving power supply 308 for the circuit to be protected outside the N-type semiconductor substrate.
【００３１】第４に、Ｎ型半導体基板外で、ノイズ保護
対象回路用の駆動電源３０８と接地電源３０９との間に
ノイズ吸収用のバイパスコンデンサ３１０を接続する。Fourth, a bypass capacitor 310 for absorbing noise is connected between the drive power source 308 for the circuit to be protected and the ground power source 309 outside the N-type semiconductor substrate.
【００３２】以上のように構成されたノイズ低減装置に
おいて、ノイズ発生源３０１（４０１）で発生したノイ
ズは、ノイズ発生源側の駆動用メタル電極層３０２（４
０２）、コンタクトホール４０８、Ｎ型拡散層領域４０
９、Ｎ型半導体基板の寄生抵抗４１０を順に通過し、Ｎ
型拡散領域４０６に到達する。In the noise reduction device configured as described above, the noise generated by the noise source 301 (401) is reduced by the driving metal electrode layer 302 (4) on the noise source side.
02), contact hole 408, N-type diffusion layer region 40
9, passing through the parasitic resistance 410 of the N-type semiconductor substrate in order,
The mold diffusion region 406 is reached.
【００３３】Ｎ型拡散領域４０６に到達した一部のノイ
ズは、Ｎ型半導体基板の寄生抵抗４１１、Ｎ型拡散領域
４１２、コンタクトホール４１３、ノイズ保護対象回路
側の駆動用メタル電極層４０４を通過し、ノイズ保護対
象回路３０３（４０３）に到達する。また、Ｎ型拡散領
域４０６に到達した他のノイズは、コンタクトホール４
０７、ガードバンド用メタル電極層３０５（４０５）、
外部接続用パッド３０６又は３０７を順に通過し、Ｎ型
半導体基板外でノイズ吸収用のバイパスコンデンサ３１
０に吸収される。Part of the noise reaching the N-type diffusion region 406 passes through the parasitic resistance 411 of the N-type semiconductor substrate, the N-type diffusion region 412, the contact hole 413, and the driving metal electrode layer 404 on the noise protection target circuit side. Then, it reaches the noise protection target circuit 303 (403). Other noises reaching the N-type diffusion region 406 are
07, guard band metal electrode layer 305 (405),
Passing through the external connection pads 306 or 307 in order, the bypass capacitor 31 for noise absorption outside the N-type semiconductor substrate
Absorbed to zero.
【００３４】このように、実施の形態２のノイズ低減装
置によれば、図８の従来例に比較して、ノイズがノイズ
保護対象回路３０３（４０３）に到達するまでに、コン
タクトホール４０７、ガードバンド用メタル電極層３０
５（４０５）、外部接続用パッド３０６または又は３０
７を順に通過してバイパスコンデンサ３１０に吸収され
る分のノイズを低減することができ、ノイズ保護対象回
路に伝わるノイズを低減することができる。As described above, according to the noise reduction device of the second embodiment, the contact hole 407 and the guard are not provided until the noise reaches the noise protection target circuit 303 (403) as compared with the conventional example of FIG. Band metal electrode layer 30
5 (405), external connection pad 306 or 30
7, the noise absorbed by the bypass capacitor 310 can be reduced, and the noise transmitted to the noise protection target circuit can be reduced.
【００３５】（実施の形態３）図５は、本発明の実施の
形態３に係るＰ型半導体基板を使用した半導体集積回路
のノイズ低減装置を構成するガードバンド用メタル電極
層の図１におけるＡＡ−ＢＢ断面図である。(Embodiment 3) FIG. 5 shows an AA in FIG. 1 of a guard band metal electrode layer constituting a noise reduction device for a semiconductor integrated circuit using a P-type semiconductor substrate according to Embodiment 3 of the present invention. It is -BB sectional drawing.
【００３６】図５において、Ｐ型半導体基板５００上に
Ｐ型拡散領域５０３を形成し、第１コンタクトホール群
５０５を介してガードバンド用第１メタル電極層５０７
に接続する。次に、これを第２コンタクトホール群５０
８を介してガードバンド用第２メタル電極層５１０に接
続する。これをｎ回繰り返し、第ｎコンタクトホール群
５１１を介してガードバンド用第ｎメタル電極層５１３
に接続する。In FIG. 5, a P-type diffusion region 503 is formed on a P-type semiconductor substrate 500, and a first metal electrode layer 507 for a guard band is formed through a first contact hole group 505.
Connect to Next, this is connected to the second contact hole group 50.
8 to the second metal electrode layer 510 for guard band. This is repeated n times, and the guard band n-th metal electrode layer 513 is connected through the n-th contact hole group 511.
Connect to
【００３７】ノイズ発生源５０１で発生したノイズは、
Ｐ型半導体基板の寄生抵抗５０２、Ｐ型拡散領域５０
３、コンタクトホール群５０５を順に通り、ガードバン
ド用第１メタル電極層５０７に到達する。さらに、コン
タクトホール群５０８を通り、ガードバンド用第２メタ
ル電極層５１０に到達し、これをｎ回繰り返し、第ｎコ
ンタクトホール群５１１を通り、ガードバンド用第ｎメ
タル電極層５１３に到達する。The noise generated by the noise source 501 is
Parasitic resistance 502 of P-type semiconductor substrate, P-type diffusion region 50
3. The contact hole group 505 is sequentially passed to reach the first metal electrode layer 507 for the guard band. Further, it reaches the guard band second metal electrode layer 510 through the contact hole group 508, and repeats this n times, and reaches the guard band n-th metal electrode layer 513 through the n-th contact hole group 511.
【００３８】このように、実施の形態３のノイズ低減装
置によれば、実施の形態１で説明したガードバンド用メ
タル電極層１０５（２０５）に比較して、多層に重ね合
わせたガードバンド用第１メタル電極層５０７、ガード
バンド用第２メタル電極層５１０、ガードバンド用第ｎ
メタル電極層５１３の方がメタル電極層の抵抗値を相当
低減できるため、外部へのノイズの通過率を向上させる
ことができ、ノイズ保護対象回路に伝わるノイズをさら
に低減することができる。As described above, according to the noise reduction device of the third embodiment, the guard band metal electrode layer 105 (205) described in the first embodiment is compared with the guard band metal electrode layer 105 (205). 1 metal electrode layer 507, 2nd metal electrode layer 510 for guard band, nth guard band
Since the metal electrode layer 513 can considerably reduce the resistance value of the metal electrode layer, the transmittance of noise to the outside can be improved, and the noise transmitted to the noise protection target circuit can be further reduced.
【００３９】（実施の形態４）図６は、本発明の実施の
形態４に係るN型半導体基板を使用した半導体集積回路
のノイズ低減装置を構成するガードバンド用メタル電極
層の図３におけるＡＡ−ＢＢ断面図である。(Embodiment 4) FIG. 6 is a sectional view of a metal electrode layer for a guard band constituting a noise reduction device for a semiconductor integrated circuit using an N-type semiconductor substrate according to an embodiment 4 of the present invention, taken along the line AA in FIG. It is -BB sectional drawing.
【００４０】図６において、Ｎ型半導体基板６００上に
Ｎ型拡散領域６０３を形成し、第１コンタクトホール群
６０５を介してガードバンド用第１メタル電極層６０７
に接続する。次に、これを第２コンタクトホール群６０
８を介してガードバンド用第２メタル電極層６１０に接
続する。これをｎ回繰り返し、第ｎコンタクトホール群
６１１を介してガードバンド用第ｎメタル電極層６１３
に接続する。In FIG. 6, an N-type diffusion region 603 is formed on an N-type semiconductor substrate 600, and a first metal electrode layer 607 for a guard band is formed through a first contact hole group 605.
Connect to Next, this is transferred to the second contact hole group 60.
8 to the guard band second metal electrode layer 610. This is repeated n times, and the guard band n-th metal electrode layer 613 is passed through the n-th contact hole group 611.
Connect to
【００４１】ノイズ発生源６０１で発生したノイズは、
Ｎ型半導体基板の寄生抵抗６０２、Ｎ型拡散領域６０
３、コンタクトホール群６０５を順に通り、ガードバン
ド用第１メタル電極層６０７に到達する。さらに、コン
タクトホール群６０８を通り、ガードバンド用第２メタ
ル電極層６１０に到達し、これをｎ回繰り返し、第ｎコ
ンタクトホール群６１１を通り、ガードバンド用第ｎメ
タル電極層６１３に到達する。The noise generated by the noise source 601 is
Parasitic resistance 602 of N-type semiconductor substrate, N-type diffusion region 60
3. The first metal electrode layer 607 for the guard band passes through the contact hole group 605 in order. Further, it reaches the guard band second metal electrode layer 610 through the contact hole group 608, and repeats this n times, and reaches the guard band n-th metal electrode layer 613 through the n-th contact hole group 611.
【００４２】このように、実施の形態４のノイズ低減装
置によれば、実施の形態２で説明したガードバンド用メ
タル電極層３０５（４０５）に比較して、多層に重ね合
わせたガードバンド用第１メタル電極層６０７、ガード
バンド用第２メタル電極層６１０、ガードバンド用第ｎ
メタル電極層６１３の方がメタル電極層の抵抗値を相当
低減できるため、外部へのノイズの通過率を向上させる
ことができ、ノイズ保護対象回路に伝わるノイズをさら
に低減することができる。As described above, according to the noise reduction device of the fourth embodiment, the guard band metal electrode layer 305 (405) described in the second embodiment is compared with the guard band metal electrode layer 305 (405). 1 metal electrode layer 607, guard band second metal electrode layer 610, guard band n th
Since the metal electrode layer 613 can significantly reduce the resistance value of the metal electrode layer, the transmittance of noise to the outside can be improved, and the noise transmitted to the noise protection target circuit can be further reduced.
【００４３】（実施の形態５）図７は、本発明の実施の
形態５に係るアナログ・ディジタル回路混載半導体集積
回路の構成を示すブロック図である。図７において、半
導体基板７００はディジタル回路７０１とアナログ回路
７０５を搭載し、さらに、両回路の間に実施の形態１乃
至実施の形態４のノイズ低減装置７０３を搭載する。(Embodiment 5) FIG. 7 is a block diagram showing a configuration of an analog / digital circuit mixed semiconductor integrated circuit according to Embodiment 5 of the present invention. In FIG. 7, a semiconductor substrate 700 has a digital circuit 701 and an analog circuit 705 mounted thereon, and further has the noise reduction device 703 of Embodiments 1 to 4 mounted between the two circuits.
【００４４】上述のように同一の半導体基板７００上に
ディジタル回路７０１とアナログ回路７０５が存在する
場合において、ディジタル回路７０１で発生したノイズ
は半導体基板寄生抵抗７０２を通ってノイズ低減装置７
０３に到達し、ノイズ低減装置７０３の作用によりノイ
ズが低減される。このようにして低減されたノイズが、
半導体基板寄生抵抗７０４を通ってアナログ回路７０５
に到達する。As described above, when the digital circuit 701 and the analog circuit 705 exist on the same semiconductor substrate 700, the noise generated by the digital circuit 701 passes through the semiconductor substrate parasitic resistor 702 and the noise reduction device 7
03, and the noise is reduced by the operation of the noise reduction device 703. The noise reduced in this way is
Analog circuit 705 through semiconductor substrate parasitic resistor 704
To reach.
【００４５】したがって、実施の形態５のアナログ・デ
ィジタル回路混載半導体集積回路によれば、アナログ回
路７０５とディジタル回路７０１との間に設置された実
施の形態１乃至４のノイズ低減装置のノイズ低減効果に
より、アナログ回路に対するノイズの影響を効果的に低
減することができる。Therefore, according to the semiconductor integrated circuit with mixed analog and digital circuits of the fifth embodiment, the noise reduction effect of the noise reduction device of the first to fourth embodiments installed between the analog circuit 705 and the digital circuit 701. Thereby, the influence of noise on the analog circuit can be effectively reduced.
【００４６】[0046]
【発明の効果】以上説明したように、本発明によれば、
ノイズ発生源となる第１の回路が発生したノイズからノ
イズ保護対象となる第２の回路を保護するための半導体
集積回路のノイズ低減装置において、メタル電極層と、
このメタル電極層の直下に形成する拡散領域を半導体基
板上で独立した外部接続用パッドを介して半導体基板外
にあるノイズ保護対象回路用の電源に接続し、半導体基
板外で第２の回路用の駆動電源と接地電源との間にコン
デンサを接続することにより、半導体基板内で対策する
ノイズ低減装置に比較して、第１の回路で発生したノイ
ズの第２の回路に対する影響をより効果的に低減するこ
とができる。As described above, according to the present invention,
In a noise reduction device for a semiconductor integrated circuit for protecting a second circuit to be protected from noise generated by a first circuit as a noise source, a metal electrode layer;
A diffusion region formed immediately below the metal electrode layer is connected to a power supply for a circuit to be protected outside the semiconductor substrate through a separate external connection pad on the semiconductor substrate. By connecting a capacitor between the driving power supply and the ground power supply, the effect of the noise generated in the first circuit on the second circuit can be more effectively compared to a noise reduction device that takes measures in the semiconductor substrate. Can be reduced.
【図１】本発明の実施の形態１に係るＰ型半導体基板を
使用した半導体集積回路のノイズ低減装置の構成を示す
図。FIG. 1 is a diagram showing a configuration of a noise reduction device for a semiconductor integrated circuit using a P-type semiconductor substrate according to a first embodiment of the present invention.
【図２】本発明の実施の形態１に係る半導体集積回路の
ノイズ低減装置の断面図。FIG. 2 is a cross-sectional view of the semiconductor integrated circuit noise reduction device according to the first embodiment of the present invention.
【図３】本発明の実施の形態２に係るＮ型半導体基板を
使用した半導体集積回路のノイズ低減装置の構成を示す
図。FIG. 3 is a diagram showing a configuration of a noise reduction device for a semiconductor integrated circuit using an N-type semiconductor substrate according to a second embodiment of the present invention.
【図４】本発明の実施の形態２に係る半導体集積回路の
ノイズ低減装置の断面図。FIG. 4 is a sectional view of a noise reduction device for a semiconductor integrated circuit according to a second embodiment of the present invention;
【図５】本発明の実施の形態３に係るＰ型半導体基板を
使用した半導体集積回路のノイズ低減装置を構成するガ
ードバンド用メタル電極層の断面図。FIG. 5 is a cross-sectional view of a guard band metal electrode layer included in a noise reduction device for a semiconductor integrated circuit using a P-type semiconductor substrate according to a third embodiment of the present invention.
【図６】本発明の実施の形態４に係るN型半導体基板を
使用した半導体集積回路のノイズ低減装置を構成するガ
ードバンド用メタル電極層の断面図。FIG. 6 is a cross-sectional view of a guard band metal electrode layer included in a noise reduction device for a semiconductor integrated circuit using an N-type semiconductor substrate according to a fourth embodiment of the present invention.
【図７】本発明の実施の形態５に係るアナログ・ディジ
タル回路混載半導体集積回路の構成を示すブロック図。FIG. 7 is a block diagram showing a configuration of an analog / digital circuit mixed semiconductor integrated circuit according to a fifth embodiment of the present invention.
【図８】アナログ・ディジタル混載半導体集積回路にお
ける従来のノイズ低減装置の構成を示す図。FIG. 8 is a diagram showing a configuration of a conventional noise reduction device in an analog / digital mixed semiconductor integrated circuit.
１００、２００ Ｐ型半導体基板 １０１、２０１ ノイズ発生源 １０２、１０４、２０２、２０４ 接地用メタル電極層 １０３、２０３ ノイズ保護対象回路 １０５、２０５ ガードバンド用メタル電極層 １０６、１０７、１１１、１１２、１１７、１１８ 外
部接続用パッド １０８ ノイズ保護対象回路の接地電源 １０９ ノイズ保護対象回路の駆動電源 １１０ バイパスコンデンサ １１３、１１９ 駆動用メタル電極 １１４ コンデンサ １１５ ノイズ発生源の接地電源 １１６ ノイズ発生源の駆動電源 ２０６、２０９、２１２ Ｐ型拡散領域 ２０７、２０８、２１３ コンタクトホール ２１０、２１１ Ｐ型半導体基板寄生抵抗 ２１４ 絶縁膜 ３００、４００ Ｎ型半導体基板 ３０１、４０１ ノイズ発生源 ３０２、３０４、４０２、４０４ 駆動用メタル電極層 ３０３、４０３ ノイズ保護対象回路 ３０５、４０５ ガードバンド用メタル電極層 ３０６、３０７、３１１、３１２、３１７、３１８ 外
部接続用パッド ３０８ ノイズ保護対象回路の駆動電源 ３０９ ノイズ保護対象回路の接地電源 ３１０ バイパスコンデンサ ３１３、３１９ 接地用メタル電極 ３１４ コンデンサ ３１５ ノイズ発生源の駆動電源 ３１６ ノイズ発生源の接地電源 ４０６、４０９、４１２ Ｎ型拡散領域 ４０７、４０８、４１３ コンタクトホール ４１０、４１１ Ｎ型半導体基板寄生抵抗 ４１４ 絶縁膜 ５００ Ｐ型半導体基板 ５０１ ノイズ発生源 ５０２、５０４ Ｐ型半導体基板寄生抵抗 ５０３ Ｐ型拡散領域 ５０５、５０８、５１１ コンタクトホール群 ５０６、５０９、５１２ 絶縁膜 ５０７、５１０、５１３ ガードバンド用メタル電極層 ６００ Ｎ型半導体基板 ６０１ ノイズ発生源 ６０２、６０４ Ｎ型半導体基板寄生抵抗 ６０３ Ｎ型拡散領域 ６０５、６０８、６１１ コンタクトホール群 ６０６、６０９、６１２ 絶縁膜 ６０７、６１０、６１３ ガードバンド用メタル電極層 ７００ 半導体基板 ７０１ ディジタル回路 ７０２、７０４ 半導体基板寄生抵抗 ７０３ ノイズ低減装置 ７０５ アナログ回路 ８００ Ｐ型半導体基板 ８０１ ノイズ発生源 ８０２、８０４ 接地用メタル電極層 ８０３ Ｐ型半導体基板寄生抵抗 ８０５、８０８、８１３、８１７ 外部接続用パッド ８０６ バイパスコンデンサ ８０７ ノイズ保護対象回路 ８０９ コンデンサ ８１０ ノイズ発生源の接地電源 ８１１ ノイズ発生源の駆動電源 ８１２、８１６ 駆動用メタル電極 ８１４ ノイズ保護対象回路の接地電源 ８１５ ノイズ保護対象回路の駆動電源100, 200 P-type semiconductor substrate 101, 201 Noise source 102, 104, 202, 204 Metal electrode layer for ground 103, 203 Circuit to be protected for noise 105, 205 Metal electrode layer for guard band 106, 107, 111, 112, 117 , 118 External connection pad 108 Ground power supply for noise protection target circuit 109 Driving power supply for noise protection target circuit 110 Bypass capacitor 113, 119 Driving metal electrode 114 Capacitor 115 Noise generation source ground power supply 116 Noise generation source driving power supply 206, 209, 212 P-type diffusion region 207, 208, 213 Contact hole 210, 211 P-type semiconductor substrate parasitic resistance 214 Insulating film 300, 400 N-type semiconductor substrate 301, 401 Noise source 302, 304, 402, 404 For driving Ground electrode layer 303, 403 Noise protection target circuit 305, 405 Guard band metal electrode layer 306, 307, 311, 312, 317, 318 External connection pad 308 Driving power supply for noise protection target circuit 309 Ground power supply for noise protection target circuit 310 bypass capacitor 313, 319 ground metal electrode 314 capacitor 315 noise source driving power source 316 noise source ground power source 406, 409, 412 N-type diffusion region 407, 408, 413 contact hole 410, 411 N-type semiconductor substrate parasitic Resistance 414 Insulating film 500 P-type semiconductor substrate 501 Noise source 502, 504 P-type semiconductor substrate parasitic resistance 503 P-type diffusion region 505, 508, 511 Contact hole group 506, 509, 512 Insulating film 507, 510, 51 3 Metal electrode layer for guard band 600 N-type semiconductor substrate 601 Noise source 602, 604 N-type semiconductor substrate parasitic resistance 603 N-type diffusion region 605, 608, 611 Contact hole group 606, 609, 612 Insulating film 607, 610, 613 Guard band metal electrode layer 700 Semiconductor substrate 701 Digital circuit 702, 704 Semiconductor substrate parasitic resistance 703 Noise reduction device 705 Analog circuit 800 P-type semiconductor substrate 801 Noise source 802, 804 Grounding metal electrode layer 803 P-type semiconductor substrate parasitic resistance 805, 808, 813, 817 External connection pad 806 Bypass capacitor 807 Noise protection target circuit 809 Capacitor 810 Noise source ground power source 811 Noise source drive power source 812, 816 Drive metal electrode 814 driving power source of the ground power supply 815 noise protection target circuit of the noise protection target circuit
Claims (4)
第１の回路及びノイズ保護対象となる第２の回路を有
し、前記第１の回路が発生したノイズから前記第２の回
路を保護するための半導体集積回路のノイズ低減装置に
おいて、 前記第１の回路及び第２の回路から独立して形成された
外部接続用パッドと、 前記第１の回路と第２の回路との間に形成され、前記外
部接続用パッドを介して前記Ｐ型半導体基板外にある前
記第２の回路用の接地電源に接続されたメタル電極層
と、 前記メタル電極層の直下に形成され、コンタクトホール
を介して前記メタル電極層に接続されたＰ型拡散領域
と、 前記Ｐ型半導体基板外にある前記第２の回路用の接地電
源と駆動電源との間に接続されたコンデンサと、を具備
することを特徴とする半導体集積回路のノイズ低減装
置。A first circuit serving as a noise generation source and a second circuit serving as a noise protection target on a P-type semiconductor substrate, wherein the second circuit is configured based on noise generated by the first circuit; In a noise reduction device of a semiconductor integrated circuit for protection, an external connection pad formed independently of the first circuit and the second circuit, and between the first circuit and the second circuit A metal electrode layer formed and connected to the ground power supply for the second circuit outside the P-type semiconductor substrate via the external connection pad; and a contact hole formed immediately below the metal electrode layer, A P-type diffusion region connected to the metal electrode layer through the P-type semiconductor substrate, and a capacitor connected between a ground power supply for the second circuit and a drive power supply outside the P-type semiconductor substrate. Semiconductor integrated circuit characterized by the following Noise reduction device.
第１の回路及びノイズ保護対象となる第２の回路を有
し、前記第１の回路が発生したノイズから前記第２の回
路を保護するための半導体集積回路のノイズ低減装置に
おいて、 前記第１の回路及び第２の回路から独立して形成された
外部接続用パッドと、 前記第１の回路と第２の回路との間に形成され、前記外
部接続用パッドを介して前記Ｎ型半導体基板外にある前
記第２の回路用の駆動電源に接続されたメタル電極層
と、 前記メタル電極層の直下に形成され、コンタクトホール
を介して前記メタル電極層に接続されたＮ型拡散領域
と、 前記Ｎ型半導体基板外にある前記第２の回路用の駆動電
源と設置電源との間に接続されたコンデンサと、を具備
することを特徴とする半導体集積回路のノイズ低減装
置。2. A semiconductor device comprising: a first circuit serving as a noise source and a second circuit serving as a noise protection target on an N-type semiconductor substrate; wherein the second circuit is configured based on noise generated by the first circuit. In a noise reduction device of a semiconductor integrated circuit for protection, an external connection pad formed independently of the first circuit and the second circuit, and between the first circuit and the second circuit A metal electrode layer formed and connected to the drive power supply for the second circuit outside the N-type semiconductor substrate via the external connection pad; and a contact hole formed immediately below the metal electrode layer. An N-type diffusion region connected to the metal electrode layer through a capacitor, and a capacitor connected between a driving power supply for the second circuit outside the N-type semiconductor substrate and an installation power supply. Semiconductor integrated circuit characterized by the following Noise reduction device.
互いにコンタクトホールを介して接続されることを特徴
とする請求項１又は請求項２に記載の半導体集積回路の
ノイズ低減装置。3. The noise reduction device for a semiconductor integrated circuit according to claim 1, wherein the plurality of metal electrode layers are stacked and connected to each other via a contact hole.
載の半導体集積回路のノイズ低減装置を用いたアナログ
・ディジタル混載半導体集積回路。4. An analog / digital hybrid semiconductor integrated circuit using the device for reducing noise of a semiconductor integrated circuit according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001040337A JP2002246553A (en) | 2001-02-16 | 2001-02-16 | Noise suppressor in semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001040337A JP2002246553A (en) | 2001-02-16 | 2001-02-16 | Noise suppressor in semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002246553A true JP2002246553A (en) | 2002-08-30 |
Family
ID=18902968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001040337A Pending JP2002246553A (en) | 2001-02-16 | 2001-02-16 | Noise suppressor in semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002246553A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7408209B2 (en) | 2004-12-16 | 2008-08-05 | Canon Kabushiki Kaisha | Semiconductor device with noise control |
| JP2009124003A (en) * | 2007-11-16 | 2009-06-04 | Renesas Technology Corp | Semiconductor device |
| US7545653B2 (en) * | 2006-02-14 | 2009-06-09 | Mitsumi Electric Co., Ltd. | Semiconductor integrated circuit device |
| WO2021251081A1 (en) * | 2020-06-08 | 2021-12-16 | ローム株式会社 | Semiconductor device and electronic apparatus |
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| JPH06163823A (en) * | 1992-09-25 | 1994-06-10 | Toshiba Corp | Semiconductor integrated circuit device |
| JPH1155145A (en) * | 1997-08-06 | 1999-02-26 | Sony Corp | Integrated circuit for transmitter-receiver |
| JPH11154733A (en) * | 1997-11-20 | 1999-06-08 | Seiko Epson Corp | Semiconductor integrated device |
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2001
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|---|---|---|---|---|
| JPH0637258A (en) * | 1992-07-16 | 1994-02-10 | Kawasaki Steel Corp | Integrated circuit |
| JPH06163823A (en) * | 1992-09-25 | 1994-06-10 | Toshiba Corp | Semiconductor integrated circuit device |
| JPH1155145A (en) * | 1997-08-06 | 1999-02-26 | Sony Corp | Integrated circuit for transmitter-receiver |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7408209B2 (en) | 2004-12-16 | 2008-08-05 | Canon Kabushiki Kaisha | Semiconductor device with noise control |
| US7545653B2 (en) * | 2006-02-14 | 2009-06-09 | Mitsumi Electric Co., Ltd. | Semiconductor integrated circuit device |
| JP2009124003A (en) * | 2007-11-16 | 2009-06-04 | Renesas Technology Corp | Semiconductor device |
| WO2021251081A1 (en) * | 2020-06-08 | 2021-12-16 | ローム株式会社 | Semiconductor device and electronic apparatus |
| DE112021002303B4 (en) | 2020-06-08 | 2023-09-21 | Rohm Co. Ltd. | Semiconductor component |
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