JP2002231985A - Photovoltaic element - Google Patents
Photovoltaic elementInfo
- Publication number
- JP2002231985A JP2002231985A JP2001027680A JP2001027680A JP2002231985A JP 2002231985 A JP2002231985 A JP 2002231985A JP 2001027680 A JP2001027680 A JP 2001027680A JP 2001027680 A JP2001027680 A JP 2001027680A JP 2002231985 A JP2002231985 A JP 2002231985A
- Authority
- JP
- Japan
- Prior art keywords
- microcrystalline
- semiconductor
- type layer
- layer
- semiconductor layer
- Prior art date
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Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は主たる発電層が非単
結晶半導体からなる光起電力素子に関する。The present invention relates to a photovoltaic element in which a main power generation layer is made of a non-single-crystal semiconductor.
【０００２】[0002]
【従来の技術】光起電力素子やセンサー等の光電変換素
子として、基板上に電極となりうるＺｎＯ、Ａｇを代表
とする裏面反射層を成膜し、ｐｉｎあるいはｎｉｐ接合
を有する非晶質シリコンなどの非単結晶半導体膜をグロ
ー放電分解法などで形成し、その後、ＩＴＯやＳｎＯ2
を代表例とする透光性導電酸化膜による透明電極が積層
されたものが知られている。これらの非単結晶半導体か
ら構成される光電変換素子は光電変換効率（Ｅｆｆ．）
を高めることが重要な課題である。2. Description of the Related Art As a photoelectric conversion element such as a photovoltaic element or a sensor, a back reflection layer typified by ZnO or Ag, which can be an electrode, is formed on a substrate and amorphous silicon having a pin or nip junction is formed. Is formed by a glow discharge decomposition method or the like, and then ITO or SnO 2
A transparent electrode formed of a light-transmitting conductive oxide film as a typical example is known. The photoelectric conversion element composed of these non-single-crystal semiconductors has a photoelectric conversion efficiency (Eff.)
Is an important issue.
【０００３】従来、非晶質シリコンだけで構成された光
電変換素子においては、電極と非晶質シリコン導電層と
の界面抵抗が高いために曲性因子（Ｆ．Ｆ．）の向上が
妨げられていた。それを解決する一つの手段として、導
電層に結晶質のシリコンを用いることが推奨されてお
り、界面抵抗の低下によるＦ．Ｆ．の改善、さらには、
光透過率の改善による光電流（Ｊｓｃ）の増加、などに
よってＥｆｆ．が向上する。Conventionally, in a photoelectric conversion element composed only of amorphous silicon, the interface factor between the electrode and the amorphous silicon conductive layer is high, so that the improvement of the curvature factor (FF) is hindered. I was As one means for solving the problem, it is recommended to use crystalline silicon for the conductive layer. F. Improvements, and even
Due to an increase in photocurrent (Jsc) due to improvement in light transmittance, etc., Eff. Is improved.
【０００４】しかし、結晶質の半導体の一例として微結
晶シリコンを形成するには、グロー放電用電極に印加す
る高周波電力を増やす、水素を増やすなどの方法がとら
れるが、このような条件では下地の半導体層あるいは裏
面電極などの基板の表面が、グロー放電で生じるプラズ
マの高速荷電粒子の衝突によるダメージを受け、界面準
位の増加、下地材料の微結晶シリコンヘの混入などによ
る、Ｅｆｆ．の低下が起こっていた。また、微結晶シリ
コンは微細なクラックが発生し易く、これが漏洩電流を
発生させ、Ｅｆｆ．の低下を招いていた。However, in order to form microcrystalline silicon as an example of a crystalline semiconductor, a method of increasing the high-frequency power applied to the glow discharge electrode, increasing the amount of hydrogen, and the like are taken. The surface of the substrate such as the semiconductor layer or the back electrode is damaged by the collision of high-speed charged particles of the plasma generated by the glow discharge, and the interface level increases, and Eff. Had declined. In addition, microcrystalline silicon is liable to generate fine cracks, which generates a leakage current, and the Eff. Had been reduced.
【０００５】特開平１−２８０３６５号公報や特開昭６
３−５８９７４号公報には、導電半導体層を２層で構成
し、ｉ層側の上に形成する導電層を非晶質半導体とし、
さらにその上に導電層を微結晶半導体で構成する方法が
開示されている。この方法により、ｉ型層表面に与える
プラズマ・ダメージを低減し、ｉ型層と導電層との界面
における再結合中心となる界面準位の発生を抑制するこ
とができる。[0005] JP-A-1-280365 and JP-A-6-1985
Japanese Patent Application Laid-Open No. 3-58974 discloses that a conductive semiconductor layer is composed of two layers, and a conductive layer formed on the i-layer side is an amorphous semiconductor.
Further, a method of forming a conductive layer from a microcrystalline semiconductor thereon is disclosed. According to this method, plasma damage to the surface of the i-type layer can be reduced, and generation of an interface level serving as a recombination center at the interface between the i-type layer and the conductive layer can be suppressed.
【０００６】また、特開平７−１２２７６１号公報で
は、電極の上に非晶質の導電層を形成し、さらにその上
に微結晶の導電層を形成することで、下地層へのダメー
ジや導電層への電極材料の混入を抑制し、かつ滑らかな
非晶質シリコンで下地の被覆をより完全に行なうことが
でき、半導体中に生じる微細なクラックがなく、漏洩電
流の低減を図ることができることが開示されている。In Japanese Patent Application Laid-Open No. Hei 7-122761, an amorphous conductive layer is formed on an electrode, and a microcrystalline conductive layer is further formed on the amorphous conductive layer. The electrode material can be prevented from being mixed into the layer, and the underlayer can be more completely covered with smooth amorphous silicon, and there are no fine cracks in the semiconductor and the leakage current can be reduced. Is disclosed.
【０００７】また、ｉ型層においては、ｐ型層と接する
ｉ型層とバルクのｉ型層とで成膜速度を変えて成膜する
ことにより、ｉ型層の作製時間を低減することが可能に
なることが特公平７−９９７７６号公報で開示されてい
る。In the case of the i-type layer, the film formation speed of the i-type layer in contact with the p-type layer and the bulk i-type layer is changed at different film formation speeds, so that the time required to form the i-type layer can be reduced. The possibility has been disclosed in Japanese Patent Publication No. 7-99776.
【０００８】また、非晶質のｉ型層の上に微結晶のｉ型
層を成膜速度を減少しながら形成することで、ｉ型層に
おいて微結晶層の形成時間を短編することが可能である
ことが特開平１０−３１３１２９号公報に開示されてい
る。Further, by forming the microcrystalline i-type layer on the amorphous i-type layer while decreasing the film forming rate, it is possible to shorten the formation time of the microcrystalline layer in the i-type layer. Is disclosed in JP-A-10-313129.
【０００９】[0009]
【発明が解決しようとする課題】新エネルギーの一つと
して重要視されている太陽電池においては、高効率化だ
けでなく低価格化も重要な研究開発課題の一つである。
非晶質シリコンは低価格化が可能な材料として注目され
ているが、成膜速度が低く、作製時間が長いために低価
格化が実現できていなかった。しかし、近年、厚い膜厚
が必要なｉ型半導体層の作製時間を減らす工夫がなされ
つつある。特公平７−９９７７６号公報に開示されてい
る方法は、第１導電層と接するｉ型層を低い成膜速度で
形成し、その後、成膜速度を上げる方法であり、界面特
性を良好に維持しつつ、ｉ型層の作製時間を短縮するこ
とができる。In a solar cell which is regarded as one of the new energies, not only high efficiency but also low cost is one of the important research and development issues.
Amorphous silicon has been attracting attention as a material that can be reduced in cost, but has not been able to realize cost reduction due to a low film formation rate and a long manufacturing time. However, in recent years, some measures have been taken to reduce the time required to form an i-type semiconductor layer requiring a large film thickness. The method disclosed in Japanese Patent Publication No. 7-99776 is a method in which an i-type layer in contact with the first conductive layer is formed at a low film formation rate, and thereafter, the film formation rate is increased, and the interface characteristics are favorably maintained. In addition, the manufacturing time of the i-type layer can be reduced.
【００１０】さらに低価格化を実現するためには、今
や、問題はｉ型層の作製時間だけでなく、光起電力素子
全体として作製時間を短縮するために、ｐ型層やｎ型層
の導電層の作製時間も短縮する必要があるという課題が
生じてきた。In order to further reduce the cost, the problem now is not only the time required for forming the i-type layer but also the time required for forming the p-type layer and the n-type layer in order to shorten the time required for manufacturing the entire photovoltaic element. There has been a problem that the time for forming the conductive layer needs to be shortened.
【００１１】導電層の作製時間を短縮するためには、導
電層を高速成膜することが考えられる。しかしながら、
特開平７−１２２７６１号公報で開示された光起電力素
子の構成において、第１導電層を高速成膜した場合、非
晶質シリコンを高速成膜すると下地層の上に均一に膜が
形成されず、急速成長した島状部分の周囲にひびやクラ
ックなどが形成されることが指摘されている。さらにそ
の上に微結晶シリコンを高速成膜すると、前述のよう
に、微結晶シリコンの形成時にもクラックは発生し易い
ために半導体中に生じるクラックの低減が漏洩電流の原
因となり、Ｅｆｆ．の低下を招く。また、高い成膜速度
で微結晶シリコンを形成すると結晶化度が低下し、Ｅｆ
ｆ．の低下や光劣化率の増大を招いていた。In order to shorten the time for forming the conductive layer, it is conceivable to form the conductive layer at a high speed. However,
In the structure of the photovoltaic element disclosed in Japanese Patent Application Laid-Open No. 7-122761, when the first conductive layer is formed at a high speed, the amorphous silicon is formed at a high speed to form a uniform film on the underlayer. It is pointed out that cracks, cracks, and the like are formed around the rapidly growing island portion. Further, if microcrystalline silicon is formed thereon at a high speed, cracks are easily generated even when microcrystalline silicon is formed, as described above, so that reduction of cracks generated in the semiconductor causes leakage current, and Eff. Causes a decrease in Further, when microcrystalline silicon is formed at a high film forming rate, the crystallinity decreases, and Ef
f. And the deterioration rate of light is increased.
【００１２】本発明は、上記の問題を解決し、光電変換
効率の低下や光劣化率の増大を防止しつつ、導電半導体
層の作製時間を短縮し、より低価格の光起電力素子を実
現することを目的とする。The present invention solves the above-mentioned problems, reduces the photoelectric conversion efficiency and increases the photodegradation rate, shortens the manufacturing time of the conductive semiconductor layer, and realizes a lower-cost photovoltaic device. The purpose is to do.
【００１３】[0013]
【課題を解決するための手段】上記の目的を達成すべ
く、本発明の光起電力素子は、基板上に、少なくとも１
つの非単結晶半導体からなる第１の導電型半導体層、実
質的に真性な半導体層、および第２の導電型半導体層が
順次積層された構成を有する光起電力素子において、前
記第１の導電型半導体層を非晶質半導体で構成し、該第
１の導電型半導体層と前記実質的に真性な半導体層との
間に、非晶質を多く含む第１微結晶半導体を最初に形成
し、その後、前記第１の導電型半導体層および前記第１
微結晶半導体より低い成膜速度で第２微結晶半導体を形
成したことを特徴とする。In order to achieve the above object, a photovoltaic device of the present invention comprises at least one photovoltaic element on a substrate.
A photovoltaic element having a configuration in which a first conductive semiconductor layer made of two non-single-crystal semiconductors, a substantially intrinsic semiconductor layer, and a second conductive semiconductor layer are sequentially stacked; Forming a first microcrystalline semiconductor containing a large amount of amorphous material between the first conductivity type semiconductor layer and the substantially intrinsic semiconductor layer; After that, the first conductive type semiconductor layer and the first
The second microcrystalline semiconductor is formed at a lower deposition rate than the microcrystalline semiconductor.
【００１４】本発明の構成によれば、非晶質半導体の第
１の導電型半導体層を高速成膜し、その後の微結晶半導
体も高速成膜した後、より低速で微結晶半導体を形成す
るために、高速成膜した部分の周囲にあるひびやクラッ
クは低速成膜の微結晶層で覆われ、漏洩電流の発生を抑
制できる。また、高速成膜した微結晶半導体の表面欠陥
を低速成膜の微結晶半導体が覆うことで実質的に真性な
半導体層（ｉ型層）との界面準位を減らすことが可能と
なる。According to the structure of the present invention, the first conductive type semiconductor layer of the amorphous semiconductor is formed at a high speed, the microcrystalline semiconductor thereafter is also formed at a high speed, and then the microcrystalline semiconductor is formed at a lower speed. For this reason, cracks and cracks around the portion formed at a high speed are covered with the microcrystalline layer formed at a low speed, and the generation of leakage current can be suppressed. In addition, by covering a surface defect of a microcrystalline semiconductor formed at a high speed with a microcrystalline semiconductor formed at a low speed, an interface state with a substantially intrinsic semiconductor layer (i-type layer) can be reduced.
【００１５】本発明の特徴的構成は複数のｎｉｐ接合を
有する、ダブルセルやトリプルセルなどのタンデム型光
起電力素子におけるそれぞれの第１の導電型半導体層と
ｉ型層の界面層としても有効である。ボトムセルとトッ
プセルで構成されたダブルセルの場合を例にとると、ト
ップセルの第１の導電型半導体層として高速で非晶質半
導体を形成し、その後、高速で微結晶半導体を形成し、
さらにその上に低速で微結晶半導体を形成することで、
先に形成されているボトムセルの第２の導電型半導体層
にダメージを与えることなく、トップセルの第１の導電
型半導体層の低抵抗化と作製時間の低減を図ることが可
能になる。The characteristic structure of the present invention is also effective as an interface layer between the first conductive semiconductor layer and the i-type layer in a tandem photovoltaic element such as a double cell or a triple cell having a plurality of nip junctions. is there. Taking the case of a double cell composed of a bottom cell and a top cell as an example, an amorphous semiconductor is formed at a high speed as a first conductivity type semiconductor layer of the top cell, and then a microcrystalline semiconductor is formed at a high speed.
Furthermore, by forming a microcrystalline semiconductor on it at low speed,
It is possible to reduce the resistance of the first conductive semiconductor layer of the top cell and reduce the manufacturing time without damaging the second conductive semiconductor layer of the bottom cell formed earlier.
【００１６】上記本発明の光起電力素子は、さらなる特
徴として、「前記第１微結晶半導体および前記第２微結
晶半導体が前記第１の導電型半導体層と同じ導電型半導
体であること」、「前記第１微結晶半導体における導電
性を付与する不純物濃度が前記第２微結晶半導体のそれ
よりも高いこと」、「前記第１微結晶半導体の成膜速度
が連続的に前記第２微結晶半導体に向かって減少してい
ること」、を含む。The photovoltaic device of the present invention further has, as a further feature, that the first microcrystalline semiconductor and the second microcrystalline semiconductor are the same conductive semiconductor as the first conductive semiconductor layer. "The concentration of the impurity imparting conductivity in the first microcrystalline semiconductor is higher than that of the second microcrystalline semiconductor.""The film formation rate of the first microcrystalline semiconductor is continuously increased in the second microcrystalline semiconductor. Decreasing toward semiconductors ".
【００１７】[0017]
【発明の実施の形態】本発明の一実施形態に係る光起電
力素子の断面構成を図１に模式的に示す。図１におい
て、１０１は基板、１０２は高速で成膜された非晶質ｎ
型層、１０３は高速で成膜された微結晶ｎ型層、１０４
は低速で成膜された微結晶ｎ型層、１０５は非晶質ｉ型
層、１０６は微結晶ｐ型層、１０７は上部電極（透明電
極）である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically shows a cross-sectional structure of a photovoltaic device according to one embodiment of the present invention. In FIG. 1, 101 is a substrate, and 102 is an amorphous n film formed at a high speed.
Mold layer, 103 is a microcrystalline n-type layer formed at a high speed, 104
Is a microcrystalline n-type layer formed at a low speed, 105 is an amorphous i-type layer, 106 is a microcrystalline p-type layer, and 107 is an upper electrode (transparent electrode).
【００１８】図１に示したような構成を有する本発明の
光起電力素子では、非晶質ｎ型層１０２と非晶質ｉ型層
１０５との間には、非晶質ｎ型層１０２上に高速で成膜
されて非晶質を多く含む微結晶ｎ型層（第１微結晶半導
体）１０３が最初に形成されており、その後に非晶質ｎ
型層１０２と第１微結晶半導体１０３より低い成膜速度
で成膜された微結晶ｎ型層（第２微結晶半導体）１０４
が形成されている。In the photovoltaic device of the present invention having the structure shown in FIG. 1, an amorphous n-type layer 102 is provided between an amorphous n-type layer 102 and an amorphous i-type layer 105. A microcrystalline n-type layer (first microcrystalline semiconductor) 103, which is formed at a high speed and contains a large amount of amorphous material, is formed first, and then the amorphous n-type layer 103 is formed.
Microlayer n-type layer (second microcrystalline semiconductor) 104 formed at a lower deposition rate than mold layer 102 and first microcrystalline semiconductor 103
Are formed.
【００１９】以下に本発明の光起電力素子の構成要素を
簡単に説明するが、本発明はこれらに限定されるもので
はない。Hereinafter, the components of the photovoltaic device of the present invention will be briefly described, but the present invention is not limited thereto.
【００２０】（半導体層）半導体層１０２〜１０６は、
シリコン系材料の非晶質（いわゆる微結晶も含まれる）
から多結晶までの非単結晶材料で構成される。半導体層
の成膜法としては、蒸着法、スパッタ法、高周波プラズ
マＣＶＤ法、マイクロ波ＣＶＤ法、ホットワイヤーＣＶ
Ｄ法、光ＣＶＤ法など公知の方法を所望に応じて用いる
ことができる。工業的に採用されている方法としては、
原料ガスをプラズマで分解し、基板上に堆積させる高周
波プラズマＣＶＤ法が好んで用いられる。(Semiconductor Layer) The semiconductor layers 102 to 106 are
Silicon-based amorphous material (including microcrystals)
From non-single-crystal materials to polycrystals. As a method for forming a semiconductor layer, there are a vapor deposition method, a sputtering method, a high-frequency plasma CVD method, a microwave CVD method, and a hot wire CV.
Known methods such as the D method and the photo CVD method can be used as desired. Industrially adopted methods include:
A high frequency plasma CVD method in which a source gas is decomposed by plasma and deposited on a substrate is preferably used.
【００２１】高周波プラズマＣＶＤ法では、ＳｉＨ4や
Ｓｉ2Ｈ6、Ｈ2やＨｅなどの混合ガスで構成される原料
ガスをプラズマで分解し、実質的に真性なシリコン系非
単結晶半導体を形成することができる。ｎ型半導体を得
るための価電子制御剤としては、Ｐ、Ｎ、Ａｓ、Ｓｂな
どの周期律表第Ｖ族の元素を含む化合物ＰＨ3などが用
いられる。ｐ型半導体を得るための価電子制御剤として
は、Ｂ、Ａｌ、Ｇａ、Ｉｎなどの周期律表第ＩＩＩ族の
元素を含む化合物ＢＦ3、Ｂ2Ｈ6などが用いられる。In the high-frequency plasma CVD method, a source gas composed of a mixed gas of SiH 4 , Si 2 H 6 , H 2, and He is decomposed by plasma to form a substantially intrinsic silicon-based non-single-crystal semiconductor. can do. As a valence electron controlling agent for obtaining an n-type semiconductor, a compound PH 3 containing an element of Group V of the periodic table such as P, N, As, Sb, or the like is used. As a valence electron controlling agent for obtaining a p-type semiconductor, compounds BF 3 and B 2 H 6 containing elements of Group III of the periodic table such as B, Al, Ga and In are used.
【００２２】本発明の光起電力素子における第１及び第
２の導電型半導体層はそれぞれ、ｎ型層及びｐ型層とす
るか、又はその逆である。The first and second conductive semiconductor layers in the photovoltaic device of the present invention are respectively an n-type layer and a p-type layer, or vice versa.
【００２３】（基板）基板１０１は、ガラス基板などの
透光性絶縁体に導電性膜を形成したものや、ステンレス
基板などの非透光性導電体あるいは該非透光性導電体に
ＡｇやＡｌの反射層を設けたもの、さらにＺｎＯやＳｎ
Ｏ2などの透光性導電膜を形成したものが用いられる。(Substrate) The substrate 101 is formed by forming a conductive film on a light-transmitting insulator such as a glass substrate, a non-light-transmitting conductor such as a stainless steel substrate, or a non-light-transmitting conductor such as Ag or Al. Provided with a reflective layer of ZnO or Sn
A light-transmitting conductive film such as O 2 is used.
【００２４】（成膜速度）非晶質ｎ型層１０２、第１微
結晶半導体１０３および第２微結晶半導体１０４の成膜
速度の制御は、主に原料ガスの供給量を制御することに
よって行なわれ、所望の結晶化度を維持しつつ、成膜速
度を変化させることが可能である。具体的には、例えば
静止した基板上に半導体を形成する場合は、原料ガス供
給量を時間的に変化させ、移動する基板上に半導体を形
成する場合には、原料ガス供給量を基板の移動方向に空
間的に変化させる手段がとられる。さらに必要な場合
は、高周波電力を制御することも行なわれる。(Film Forming Rate) The film forming rate of the amorphous n-type layer 102, the first microcrystalline semiconductor 103, and the second microcrystalline semiconductor 104 is controlled mainly by controlling the supply amount of the source gas. Thus, it is possible to change the deposition rate while maintaining the desired crystallinity. Specifically, for example, when a semiconductor is formed on a stationary substrate, the supply amount of the source gas is changed with time, and when the semiconductor is formed on a moving substrate, the supply amount of the source gas is changed. Means for spatially changing the direction are taken. If necessary, high-frequency power is controlled.
【００２５】[0025]
【実施例】以下、本発明の実施例を説明するが、本発明
はこれらの実施例に限定されるものではない。EXAMPLES Examples of the present invention will be described below, but the present invention is not limited to these examples.
【００２６】（実施例１）本発明の一実施例として、図
１に示したような光起電力素子を作製した。本実施例で
は、図２に示すような帯状基板の上に連続的に半導体膜
を積層形成できるロール・ツー・ロール方式のプラズマ
ＣＶＤ装置を用いて光起電力素子を作製した。以下、図
２を用いて作製手順にしたがって説明する。Example 1 As an example of the present invention, a photovoltaic element as shown in FIG. 1 was manufactured. In this embodiment, a photovoltaic element was manufactured using a roll-to-roll type plasma CVD apparatus capable of continuously forming a semiconductor film on a strip-shaped substrate as shown in FIG. Hereinafter, description will be given in accordance with the manufacturing procedure with reference to FIG.
【００２７】（１）帯状のステンレス板の表面上に、不
図示のＤＣスパッタ装置によってＡｇとＺｎＯを堆積
し、微小な凹凸表面を有する帯状基板２０１を用意し
た。(1) Ag and ZnO were deposited on the surface of a belt-like stainless steel plate by a DC sputtering device (not shown) to prepare a belt-like substrate 201 having a fine uneven surface.
【００２８】（２）帯状基板２０１を巻き出しボビン２
０３に巻き付けた状態で、帯状基板の巻き出し室２０４
にセットした。(2) Unwinding the bobbin 2
03, the unwinding chamber 204 for the band-shaped substrate.
Set to
【００２９】（３）帯状基板２０１を各ガスゲート２０
２および各成膜室２０７〜２１０に通し、帯状基板の巻
き取り室２０６まで渡し、巻き取りボビン２０５に取り
付け、弛まない程度に張力をかけた。その後、装置内部
を真空排気した。(3) The belt-like substrate 201 is connected to each gas gate 20
2 and each of the film forming chambers 207 to 210, passed to a winding chamber 206 for a belt-like substrate, attached to a winding bobbin 205, and tensioned so as not to loosen. Thereafter, the inside of the apparatus was evacuated.
【００３０】（４）真空排気しながら各成膜室にＨｅガ
スを導入し、約２００ＰａのＨｅ雰囲気中で各成膜室内
部を約３５０℃に加熱ベーキングした。(4) He gas was introduced into each film forming chamber while evacuation was performed, and the inside of each film forming chamber was baked at about 350 ° C. in a He atmosphere of about 200 Pa.
【００３１】（５）加熱ベーキングの後、各ガスゲート
２０２にゲートガスとしてＨ2を５００ｓｃｃｍ、各成
膜室にそれぞれの原料ガスを所定流量導入し、各室の内
圧を所定圧力に設定した。(5) After the heating and baking, 500 sccm of H 2 was introduced as a gate gas into each gas gate 202, and a predetermined flow rate of each raw material gas was introduced into each film forming chamber, and the internal pressure of each chamber was set to a predetermined pressure.
【００３２】（６）帯状基板の巻き取り室２０６の巻き
取りボビン２０５を回転させ、帯状基板２０１を巻き出
し室２０４から巻き取り室２０６に向かう方向に１２０
ｃｍ／分の一定速度で連続的に移動させた。また、各成
膜室内に設けた不図示の温度制御装置により、移動する
帯状基板２０１が各成膜室の成膜空間内で所定の温度に
なるように温度制御を行った。(6) The take-up bobbin 205 in the take-up chamber 206 for the belt-like substrate is rotated to move the belt-like substrate 201 from the unwinding chamber 204 to the take-up chamber 206 in the direction 120.
It was moved continuously at a constant speed of cm / min. Further, temperature control was performed by a temperature control device (not shown) provided in each of the film forming chambers so that the moving strip-shaped substrate 201 had a predetermined temperature in the film forming space of each of the film forming chambers.
【００３３】（７）帯状基板２０１の温度が安定したと
ころで、各成膜室において高周波プラズマＣＶＤ法によ
り、それぞれの半導体膜の作製を開始する。(7) When the temperature of the strip-shaped substrate 201 is stabilized, the production of each semiconductor film is started in each film forming chamber by the high-frequency plasma CVD method.
【００３４】図２の各成膜室２０７〜２１０内に設置さ
れた放電室は図５に示すような構造を有している。図５
において帯状基板２０１は、真空容器５０２にガスゲー
ト５０３から入り、図中左方から右方へ移動して、ガス
ゲート５０４へ出る。真空容器５０２の内部には放電室
５０５が設けられ、電気的に接地された帯状基板２０１
と平行平板電極（放電電極）５０６との間に不図示の高
周波電源から高周波電力を投入することにより、放電室
５０５内にプラズマを形成し、帯状基板の下面（表面）
にシリコン系非単結晶半導体を形成する。放電室５０５
には不図示の原料ガス供給系に接続された原料ガス導入
管５０７および不図示の排気装置に接続された排気管５
０８が設けられ、帯状基板の移動方向と平行なガスの流
れを形成する。原料ガスの流入経路にはブロックヒータ
ー５０９が設けられ、プラズマ分解前の原料ガスの予熱
と放電室５０５の加熱行なう。排気ガスの排出経路には
放電室外部排気口５１０が設けられ、放電室５０５の外
部のガス（ガスゲートから流入したゲートガス、真空容
器５０２内壁からの放出ガス等）が放電室５０５を通る
ことなく排気管５０８へ排出されるようにし、堆積膜へ
の不純物の混入を防止している。また、放電室５０５の
上部の、帯状基板２０１の入口、出口にはプラズマ漏れ
ガード（成膜領域開口調整板）５１１が配設され、放電
室５０５内部のプラズマの外部への漏洩を阻止してい
る。The discharge chamber installed in each of the film forming chambers 207 to 210 in FIG. 2 has a structure as shown in FIG. FIG.
, The strip-shaped substrate 201 enters the vacuum vessel 502 from the gas gate 503, moves from left to right in the drawing, and exits to the gas gate 504. A discharge chamber 505 is provided inside the vacuum vessel 502, and the electrically grounded strip-shaped substrate 201 is provided.
High-frequency power is supplied from a high-frequency power supply (not shown) between the substrate and the parallel plate electrode (discharge electrode) 506 to form plasma in the discharge chamber 505, and the lower surface (front surface) of the strip substrate
Then, a silicon-based non-single-crystal semiconductor is formed. Discharge chamber 505
Is a source gas inlet pipe 507 connected to a source gas supply system (not shown) and an exhaust pipe 5 connected to an exhaust device (not shown).
08 is provided to form a gas flow parallel to the moving direction of the strip-shaped substrate. A block heater 509 is provided on the source gas inflow path to perform preheating of the source gas before plasma decomposition and heating of the discharge chamber 505. A discharge chamber outside exhaust port 510 is provided in a discharge path of the exhaust gas. The gas is discharged to the pipe 508 to prevent impurities from being mixed into the deposited film. In addition, a plasma leakage guard (film formation region opening adjusting plate) 511 is provided at the entrance and exit of the strip-shaped substrate 201 above the discharge chamber 505 to prevent the plasma inside the discharge chamber 505 from leaking to the outside. I have.
【００３５】各成膜室２０７〜２１０内に設置された図
５に示した構造を有する放電室は、連続的に移動する帯
状基板２０１の表面にガス供給側プラズマ、ガス排気側
プラズマの順序で半導体膜が形成されるように配置され
ており、放電電極５０６から１３．５６ＭＨｚの高周波
電力をそれぞれ不図示の電源からマッチング装置を介し
て投入した。この放電電力の投入により各成膜室内の原
料ガスをプラズマ化し、各成膜室内で連続的に移動する
帯状基板２０１の表面上に半導体膜の形成を行なった。The discharge chamber having the structure shown in FIG. 5 installed in each of the film forming chambers 207 to 210 is provided on the surface of the continuously moving strip-shaped substrate 201 in the order of plasma on the gas supply side and plasma on the gas exhaust side. 13.56 MHz high-frequency power was supplied from a discharge electrode 506 from a power supply (not shown) via a matching device. By supplying the discharge power, the source gas in each of the film forming chambers was turned into plasma, and a semiconductor film was formed on the surface of the belt-like substrate 201 which continuously moved in each of the film forming chambers.
【００３６】具体的には、ステンレス基板にＡｇとＺｎ
Ｏを積層した基板２０１（図１では基板１０１）の上
に、順に非晶質シリコンからなる高速で成膜した非晶質
ｎ型層１０２（成膜速度＝１．０ｎｍ／ｓｅｃ）、微結
晶シリコンからなる高速成膜した微結晶ｎ型層１０３
（成膜速度＝１．０ｎｍ／ｓｅｃ）と低速成膜した微結
晶ｎ型層１０４（成膜速度＝０．２ｎｍ／ｓｅｃ）、さ
らに非晶質シリコンからなるｉ型層１０５（成膜速度＝
１．５ｎｍ／ｓｅｃ）、微結晶シリコンからなるｐ型層
１０６（成膜速度＝０．２ｎｍ／ｓｅｃ）を形成した。
なお、本実施例では、ＳｉＨ4流量および高周波電力を
変化させることにより、成膜速度が異なる微結晶ｎ型層
１０３、１０４を形成した。Specifically, Ag and Zn are deposited on a stainless steel substrate.
An amorphous n-type layer 102 (film formation rate = 1.0 nm / sec) formed of amorphous silicon at a high speed in order on a substrate 201 (substrate 101 in FIG. 1) on which O is laminated, and microcrystals High-speed microcrystalline n-type layer 103 made of silicon
(Film formation rate = 1.0 nm / sec) and a microcrystalline n-type layer 104 formed at a low speed (film formation rate = 0.2 nm / sec), and further an i-type layer 105 made of amorphous silicon (film formation rate =
1.5 nm / sec), a p-type layer 106 of microcrystalline silicon (film formation rate = 0.2 nm / sec) was formed.
In this example, the microcrystalline n-type layers 103 and 104 having different deposition rates were formed by changing the flow rate of SiH 4 and the high-frequency power.
【００３７】図６に放電室内の成膜速度分布の例を示
す。図６にはラマン散乱分光の非晶質シリコンに起因す
るピークと結晶シリコンに起因するピークの強度比で表
した結晶化度の分布を併記した。微結晶シリコンが形成
されるような高周波電力が大きい成膜条件では、原料ガ
スは放電室５０５のガス吹き出し部付近で、大きな高周
波電力によって急速に分解され、微結晶シリコン膜とし
て帯状基板２０１に厚く堆積する。さらに、ガス吹き出
し部（原料ガス導入管）付近で分解されなかった原料ガ
スが順次、図５中の左方から右方へ移動し、放電室５０
５内を排気孔に向かって流れながら分解され、微結晶シ
リコン膜として帯状基板２０１に堆積していくが、原料
ガスは順次枯渇していくために、形成される膜厚は徐々
に薄くなる。高周波電力が大きく、Ｈ2希釈率が高い成
膜条件では図６と比べて、成膜速度が減少したが、分布
が少なくなった。このような成膜条件においては、Ｓｉ
Ｈ4流量を増加することや、放電周波数を高くする、あ
るいは放電電極と基板の距離を短縮することで成膜速度
を上げることができる。FIG. 6 shows an example of a film forming speed distribution in the discharge chamber. FIG. 6 also shows the distribution of crystallinity represented by the intensity ratio of the peak due to amorphous silicon and the peak due to crystalline silicon in Raman scattering spectroscopy. Under film-forming conditions in which high-frequency power is large such that microcrystalline silicon is formed, the raw material gas is rapidly decomposed by large high-frequency power in the vicinity of the gas blowing portion of the discharge chamber 505, and becomes thick as a microcrystalline silicon film on the belt-shaped substrate 201. accumulate. Further, the raw material gas that has not been decomposed in the vicinity of the gas blowing section (raw material gas introduction pipe) sequentially moves from left to right in FIG.
5, the gas is decomposed while flowing toward the exhaust hole, and is deposited as a microcrystalline silicon film on the belt-shaped substrate 201. However, since the source gas is gradually depleted, the formed film thickness gradually decreases. Under the film forming conditions in which the high-frequency power is large and the H 2 dilution ratio is high, the film forming speed is reduced as compared with FIG. 6, but the distribution is reduced. Under such film forming conditions, Si
The film formation rate can be increased by increasing the H 4 flow rate, increasing the discharge frequency, or shortening the distance between the discharge electrode and the substrate.
【００３８】以上のようにして、各成膜室で、図１に示
すような順番で各半導体層を帯状基板２０１（図１では
基板１０１）の上に積層した。As described above, the respective semiconductor layers were stacked on the belt-like substrate 201 (the substrate 101 in FIG. 1) in the order shown in FIG. 1 in each film forming chamber.
【００３９】（９）半導体積層膜を形成した後、放電電
力の投入と、原料ガスの導入と、帯状基板および成膜室
の加熱とを停止し、成膜室内のパージを行った。その
後、帯状基板および装置内部を十分冷却してから装置を
開け、巻き取りボビン２０５に巻かれた帯状基板２０１
を、帯状基板の巻き取り室２０６から大気中に取り出し
た。(9) After the formation of the semiconductor laminated film, the supply of the discharge power, the introduction of the raw material gas, and the heating of the belt-like substrate and the film forming chamber were stopped, and the film forming chamber was purged. Thereafter, the apparatus is opened after sufficiently cooling the band-shaped substrate and the inside of the apparatus, and the band-shaped substrate 201 wound on the take-up bobbin 205 is opened.
Was taken out from the winding chamber 206 of the belt-shaped substrate into the atmosphere.
【００４０】（１０）形成した半導体積層膜の上に、不
図示のスパッタ装置を用いて透明電極（上部電極）１０
７として全面にＩＴＯ薄膜を形成し、集電電極（不図
示）として一定間隔に細線状のＡｇ電極を形成し、単位
素子の直列化等のモジュール化を行うことにより、シン
グル型光起電力素子によって構成された太陽電池モジュ
ールを連続的に作製した。(10) A transparent electrode (upper electrode) 10 is formed on the formed semiconductor laminated film by using a sputtering device (not shown).
A single-type photovoltaic element 7 is formed by forming an ITO thin film on the entire surface, forming a thin line-shaped Ag electrode as a collecting electrode (not shown) at regular intervals, and performing modularization such as serialization of unit elements. Were continuously produced.
【００４１】以上のようにして作製した本実施例の太陽
電池モジュールを、ＡＭ１．５（１００ｍＷ／ｃｍ2）
の擬似太陽光照射下にて特性評価した。さらにはＡＭ
１．５（１００ｍＷ／ｃｍ2）の擬似太陽光を温度５０
℃にて連続照射し、５００時間光劣化させた状態の光電
変換効率Ｅｆｆ２を測定し、初期効率Ｅｆｆ１と比較し
た光劣化率（＝（Ｅｆｆ１−Ｅｆｆ２）／Ｅｆｆ１）を
求めた。The solar cell module according to the present embodiment manufactured as described above was manufactured using AM1.5 (100 mW / cm 2 ).
Were evaluated under simulated sunlight irradiation. And AM
1.5 (100 mW / cm 2 ) simulated sunlight at a temperature of 50
The photoelectric conversion efficiency Eff2 in the state of continuous irradiation at 500C and photodegradation for 500 hours was measured, and the photodegradation rate (= (Eff1−Eff2) / Eff1) in comparison with the initial efficiency Eff1 was obtained.
【００４２】比較のために、従来例として図３に示すよ
うな光起電力素子を作製した。すなわち非晶質ｎ型層３
０２（成膜速度＝１．０ｎｍ／ｓｅｃ）と低速で成膜し
た微結晶ｎ型層３０３（成膜速度＝０．２ｎｍ／ｓｅ
ｃ）の２層でｎ型層を構成した。このとき微結晶ｎ型層
３０３の形成時間を長くして、微結晶ｎ型層の膜厚は実
施例１と同じになるようにした（比較例１−１素子）。
それ以外は実施例１の素子と同様に作成し、また同様の
測定を行なった。For comparison, a photovoltaic element as shown in FIG. 3 was manufactured as a conventional example. That is, the amorphous n-type layer 3
02 (film formation rate = 1.0 nm / sec) and a microcrystalline n-type layer 303 formed at a low rate (film formation rate = 0.2 nm / sec).
An n-type layer was constituted by the two layers c). At this time, the formation time of the microcrystalline n-type layer 303 was lengthened so that the film thickness of the microcrystalline n-type layer was the same as in Example 1 (Comparative Example 1-1 device).
Except for this, the device was prepared in the same manner as in Example 1, and the same measurement was performed.
【００４３】さらなる比較のために、非晶質ｎ型層３０
２（成膜速度＝１．０ｎｍ／ｓｅｃ）と高速で成膜した
微結晶ｎ型層３０３（成膜速度＝１．０ｎｍ／ｓｅｃ）
の２層でｎ型層を構成した（比較例１−２素子）。それ
以外は実施例１の素子と同様に作成し、また同様の測定
を行なった。For further comparison, the amorphous n-type layer 30
Microcrystalline n-type layer 303 formed at a high speed of 2 (film formation rate = 1.0 nm / sec) (film formation rate = 1.0 nm / sec)
(Comparative Example 1-2 device). Except for this, the device was prepared in the same manner as in Example 1, and the same measurement was performed.
【００４４】その結果、実施例１の素子の値で規格化し
た比較例１−１素子の光電変換効率および光劣化率はほ
ぼ同等であった。すなわち微結晶ｎ型層の一部（微結晶
ｎ型層１０３）を高速で形成した本発明による実施例１
の素子でも、低速で全ての微結晶ｎ型層を形成した比較
例１−１素子と同様の良好な光電変換効率が得られた。As a result, the photoelectric conversion efficiency and the light deterioration rate of the device of Comparative Example 1-1 standardized with the values of the device of Example 1 were almost equal. That is, Example 1 of the present invention in which a part of the microcrystalline n-type layer (microcrystalline n-type layer 103) was formed at a high speed.
In the device of Comparative Example 1-1, good photoelectric conversion efficiency similar to that of the device of Comparative Example 1-1 in which all the microcrystalline n-type layers were formed at a low speed was obtained.
【００４５】つまり、本発明によれば、光電変換効率の
低下や光劣化率の増大を防止しつつ、より短時間で微結
晶ｎ型層を形成することが可能になった。That is, according to the present invention, it has become possible to form a microcrystalline n-type layer in a shorter time while preventing a decrease in photoelectric conversion efficiency and an increase in the rate of light degradation.
【００４６】また、実施例１の素子の値で規格化した比
較例１−２素子の光電変換効率は低かった。すなわち比
較例１−２素子のように高速で全ての微結晶ｎ型層を形
成した場合、漏洩電流や界面準位の発生により光電変換
効率が低下した。また、実施例１の素子の光劣化率は比
較例１−２素子よりも小さく、微結晶ｎ型層の一部（微
結晶ｎ型層１０４）を低速で成膜することにより、この
低速成膜により界面準位を有効に覆うことができ、光劣
化を低減することができた。The photoelectric conversion efficiency of the device of Comparative Example 1-2, which was normalized by the value of the device of Example 1, was low. That is, when all the microcrystalline n-type layers were formed at a high speed as in the device of Comparative Example 1-2, the photoelectric conversion efficiency was reduced due to the occurrence of leakage current and interface states. The light degradation rate of the device of Example 1 is smaller than that of the device of Comparative Example 1-2. By forming a part of the microcrystalline n-type layer (microcrystalline n-type layer 104) at a low speed, this low-speed growth is achieved. The interface states could be effectively covered by the film, and light degradation could be reduced.
【００４７】（実施例２）図４に示すような光起電力素
子を、図２のロール・ツー・ロール方式のプラズマＣＶ
Ｄ装置を用いて作製した。Example 2 A photovoltaic element as shown in FIG. 4 was replaced with a roll-to-roll type plasma CV shown in FIG.
It was produced using a D apparatus.
【００４８】ステンレス基板にＡｇとＺｎＯを積層した
基板４０１の上に、順に非晶質シリコンからなる高速で
成膜した非晶質ｎ型層４０２（成膜速度＝１．０ｎｍ／
ｓｅｃ）、微結晶シリコンからなる高速で成膜した微結
晶ｎ型層４０３（成膜速度＝１．０ｎｍ／ｓｅｃ）と低
速で成膜した微結晶ｎ型層４０４（成膜速度＝０．２ｎ
ｍ／ｓｅｃ）、微結晶シリコンからなるｉ型層４０５
（成膜速度＝３．０ｎｍ／ｓｅｃ）、微結晶シリコンか
らなるｐ型層４０６（成膜速度＝０．２ｎｍ／ｓｅｃ）
を形成した。An amorphous n-type layer 402 formed of amorphous silicon at a high speed in order on a stainless steel substrate 401 on which Ag and ZnO are laminated (film formation rate = 1.0 nm /
sec), a microcrystalline n-type layer 403 made of microcrystalline silicon formed at a high speed (film forming rate = 1.0 nm / sec) and a microcrystalline n-type layer 404 formed at a low speed (film forming rate = 0.2 n)
m / sec), i-type layer 405 made of microcrystalline silicon
(Film formation rate = 3.0 nm / sec), p-type layer 406 made of microcrystalline silicon (Film formation rate = 0.2 nm / sec)
Was formed.
【００４９】本実施例では、ＳｉＨ4流量および高周波
電力を変化させ、Ｈ2希釈率を変化させることにより、
成膜速度が異なる微結晶ｎ型層４０３、４０４を形成し
た。微結晶シリコンからなるｉ型層４０５は他の層と比
べて、放電電極と基板の距離を狭め、ＳｉＨ4流量を増
やすことで高い成膜速度を実現した。なお、高速で成膜
した微結晶ｎ型層４０３の不純物濃度を、非晶質ｎ型層
４０２や低速で成膜した微結晶ｎ型層４０４よりも多く
した（実施例２−１素子）。In this embodiment, by changing the flow rate of the SiH 4 and the high-frequency power and changing the H 2 dilution ratio,
Microcrystalline n-type layers 403 and 404 having different deposition rates were formed. The i-type layer 405 made of microcrystalline silicon has realized a higher film forming rate by narrowing the distance between the discharge electrode and the substrate and increasing the flow rate of SiH 4 as compared with other layers. The impurity concentration of the microcrystalline n-type layer 403 formed at a high speed was higher than that of the amorphous n-type layer 402 and the microcrystalline n-type layer 404 formed at a low speed (Example 2-1).
【００５０】また、高速で成膜した微結晶ｎ型層４０３
および低速で成膜した微結晶ｎ型層４０４の不純物濃度
をゼロとして光起電力素子を構成した（実施例２−２素
子）。The microcrystalline n-type layer 403 formed at a high speed
A photovoltaic element was formed with the impurity concentration of the microcrystalline n-type layer 404 formed at a low speed set to zero (Example 2-2 element).
【００５１】また、図６に示すような成膜速度分布と結
晶化度分布となるように成膜条件を調整し、１つの放電
室において、高速で成膜した微結晶ｎ型層４０３を高速
から低速まで成膜速度を連続的に変化させながら形成し
た後、低速で微結晶ｎ型層４０４を形成した光起電力素
子を構成した（実施例２−３素子）。The film forming conditions are adjusted so that the film forming rate distribution and the crystallinity distribution as shown in FIG. 6 are obtained, and the microcrystalline n-type layer 403 formed at a high speed is formed in one discharge chamber. After forming the film while changing the film formation rate continuously from low to low, a photovoltaic element was formed in which the microcrystalline n-type layer 404 was formed at low speed (Example 2-3 elements).
【００５２】また、比較のために、低速で成膜した微結
晶層４０４を形成せずに光起電力素子を構成した以外は
実施例２−１素子と同様に光起電力素子を作製した（比
較例２素子）。For comparison, a photovoltaic device was manufactured in the same manner as in Example 2-1 except that the photovoltaic device was formed without forming the microcrystalline layer 404 formed at a low speed. Comparative Example 2 element).
【００５３】以上の光起電力素子で形成した各太陽電池
モジュールを実施例１の素子と同様の測定を行なった。Each solar cell module formed with the above photovoltaic elements was subjected to the same measurement as that of the element of Example 1.
【００５４】その結果、比較例２素子の値と比べて、実
施例２−１、２−２、２−３の各素子では高い光電変換
効率が得られた。これは、高速で非晶質ｎ型層４０２を
形成した後、高速で微結晶シリコンを形成した比較例２
素子では、クラックやひびを覆うことができずに、漏洩
電流や界面準位が発生するためであると考えられる。す
なわち実施例２−１、２−２、２−３の各素子のよう
に、高速成膜した微結晶シリコンの上に低速で微結晶シ
リコンを形成すると、クラックなどを覆うことができ、
漏洩電流や界面準位が低減し、高い光電変換効率が得ら
れた。As a result, higher photoelectric conversion efficiencies were obtained in the devices of Examples 2-1, 2-2, and 2-3 than in the device of Comparative Example 2. This is because the amorphous n-type layer 402 was formed at a high speed, and then microcrystalline silicon was formed at a high speed.
It is considered that this is because the device cannot cover cracks and cracks and generates leakage current and interface states. That is, when microcrystalline silicon is formed at a low speed on microcrystalline silicon formed at a high speed as in the elements of Examples 2-1, 2-2, and 2-3, cracks and the like can be covered,
The leakage current and the interface state were reduced, and high photoelectric conversion efficiency was obtained.
【００５５】また、微結晶シリコンを高速で成膜すると
高い結晶性が得られず、その上により高速の微結晶シリ
コン（ｉ型層４０５）を成膜すると、さらに結晶性が低
下し、高い光電変換効率が得られない。すなわち実施例
２−１、２−２、２−３の各素子のように、高速で成膜
した微結晶シリコン上に更に微結晶半導体を低速で形成
することで、下地が隙間なく結晶性の高いシリコンで敷
き詰められ、その上に高速で微結晶シリコン（ｉ型層４
０５）を形成しても、高い結晶性を有する微結晶シリコ
ンを形成することができ、高い光電変換効率を有する光
起電力素子の作製が可能になった。When microcrystalline silicon is formed at a high speed, high crystallinity cannot be obtained, and when microcrystalline silicon (i-type layer 405) is formed thereon at a higher speed, the crystallinity further decreases, resulting in high photoelectricity. Conversion efficiency cannot be obtained. That is, as in the elements of Examples 2-1, 2-2, and 2-3, the microcrystalline semiconductor is further formed at a low speed on the microcrystalline silicon formed at a high speed, so that the underlayer can be formed without gaps and the crystallinity can be improved. High-crystal silicon (i-type layer 4)
05), microcrystalline silicon having high crystallinity can be formed, and a photovoltaic element having high photoelectric conversion efficiency can be manufactured.
【００５６】特に、高速で成膜した微結晶ｎ型層４０３
の不純物濃度を高めた実施例２−１素子は比較例２素子
よりも光劣化率が小さいものが得られた。これは、不純
物濃度を高めたことにより微結晶シリコンを形成する上
での結晶核が形成され易くなり、その上に成膜したｉ型
層４０５も結晶性の高い微結晶シリコンとなったため、
膜中の欠陥生成などが抑制され、光劣化率が小さな光起
電力素子が作製できた。基板４０１上に形成した下地層
あるいはｉ型層４０５への不純物拡散を考えると、３層
あるｎ型層の中間層である高速成膜微結晶ｎ型層４０３
の不純物濃度を高くすることが有効である。すなわち高
速成膜微結晶ｎ型層４０３で結晶核を形成した後、低速
で微結晶ｎ型層４０４を成膜した場合、高い結晶性を維
持したまま、半導体層が形成されるので、不純物濃度を
高くするのは高速成膜する微結晶ｎ型層４０３で十分と
いえる。In particular, the microcrystalline n-type layer 403 formed at a high speed
In Example 2-1 in which the impurity concentration was increased, a device having a smaller light degradation rate than the device in Comparative Example 2 was obtained. This is because crystal nuclei in forming microcrystalline silicon are easily formed by increasing the impurity concentration, and the i-type layer 405 formed thereon also becomes microcrystalline silicon having high crystallinity.
The generation of defects in the film was suppressed, and a photovoltaic element having a small photodegradation rate was produced. Considering the diffusion of impurities into the underlying layer or the i-type layer 405 formed on the substrate 401, the high-speed microcrystalline n-type layer 403 which is an intermediate layer of the three n-type layers
It is effective to increase the impurity concentration of. In other words, when a crystal nucleus is formed in the high-speed deposited microcrystalline n-type layer 403 and then the microcrystalline n-type layer 404 is formed at a low speed, a semiconductor layer is formed while maintaining high crystallinity. Can be said to be sufficient if the microcrystalline n-type layer 403 is formed at a high speed.
【００５７】また、実施例２−３素子では高い光電変換
効率が得られ、さらには実施例２−１素子よりも小さな
光劣化率であった。高速から低速まで連続的に成膜速度
を変化した微結晶ｎ型層で高速成膜微結晶ｎ型層４０３
を形成することで高い光電変換効率が得られ、高速成膜
で発生したクラックやひびを、微結晶シリコンの成膜速
度を変えながら連続的に覆っていくために、欠陥がより
少ない微結晶ｎ型層および微結晶ｉ型層で構成された光
起電力素子が得られる。In the device of Example 2-3, a high photoelectric conversion efficiency was obtained, and the light deterioration rate was smaller than that of the device of Example 2-1. High-speed microcrystalline n-type layer 403 with a microcrystalline n-type layer in which the deposition rate is continuously changed from high speed to low speed
Is formed, high photoelectric conversion efficiency is obtained, and cracks and cracks generated by high-speed film formation are continuously covered while changing the film formation speed of microcrystalline silicon, so that microcrystals n with less defects are formed. A photovoltaic element composed of a mold layer and a microcrystalline i-type layer is obtained.
【００５８】（実施例３）図７に示したような２つのｎ
ｉｐ接合を有するダブルセル型の光起電力素子を作製し
た。(Embodiment 3) Two n's as shown in FIG.
A double cell type photovoltaic element having an ip junction was manufactured.
【００５９】作製には図２のロール・ツー・ロール装置
を２台用意し、１台で実施例２と同様に、帯状基板２０
１（図７では基板７０１）上にｉ型層を微結晶シリコン
で構成した微結晶シリコンｎｉｐセル（７０２〜７０
６）を連続搬送しながら作製し、巻き取りボビンに巻き
上げた帯状基板を大気中に取り出し、他の１台の巻き出
し室にセットして、実施例１と同様に、ｉ型層を非晶質
シリコンで構成した非晶質シリコンｎｉｐセル（７０７
〜７１１）を連続搬送しながら作製し、２つのｎｉｐセ
ルで構成したダブルセルを作製した。さらに不図示のス
パッタ装置を用いてＩＴＯ薄膜を透明電極７１２として
全面に形成し、集電電極（不図示）として一定間隔に細
線状のＡｇ電極を形成し、実施例１と同様に太陽電池モ
ジュールとした。For the production, two roll-to-roll apparatuses shown in FIG. 2 are prepared, and one of them is used as in the second embodiment.
1 (a substrate 701 in FIG. 7), a microcrystalline silicon nip cell (702 to 70) in which an i-type layer is composed of microcrystalline silicon.
6) was manufactured while being continuously transported, and the strip-shaped substrate wound up on the take-up bobbin was taken out into the atmosphere, set in another unwinding chamber, and the i-type layer was made amorphous as in Example 1. Silicon nip cell (707) made of porous silicon
To 711) while transporting them continuously, to produce a double cell composed of two nip cells. Further, an ITO thin film was formed on the entire surface as a transparent electrode 712 by using a sputtering device (not shown), and a thin line-shaped Ag electrode was formed at regular intervals as a current collecting electrode (not shown). And
【００６０】非晶質シリコンｎｉｐセルのｎ型層７０２
〜７０４および微結晶シリコンｎｉｐセルのｎ型層７０
７〜７０９は、実施例１と同様、高速非晶質、高速微結
晶、低速微結晶の３層構造とした。微結晶シリコンｎｉ
ｐセルのｎ型層においては、下地層が導電性材料で構成
される基板７０１ではなく、ｐ型層７０６であることが
非晶質シリコンｎｉｐセルのｎ型層と異なる点である。
なお、非晶質シリコンｎｉｐセルのｐ型層は微結晶シリ
コンで構成した。The n-type layer 702 of the amorphous silicon nip cell
-704 and n-type layer 70 of microcrystalline silicon nip cell
7 to 709 had a three-layer structure of high-speed amorphous, high-speed microcrystal, and low-speed microcrystal as in Example 1. Microcrystalline silicon ni
The n-type layer of the p-cell is different from the n-type layer of the amorphous silicon nip cell in that the underlying layer is not the substrate 701 made of a conductive material but the p-type layer 706.
Note that the p-type layer of the amorphous silicon nip cell was made of microcrystalline silicon.
【００６１】本実施例のようなダブルセルでは、２つの
セルの接触界面、すなわち、非晶質シリコンｎｉｐセル
と微結晶シリコンｎｉｐセルの接触界面を形成するｐ／
ｎ逆接合部では、光起電力が発生しないことが求められ
ている。一般に非単結晶シリコンで構成されたｐ／ｎ逆
接合部ではｐ型層およびｎ型層各々における欠陥準位が
多く、その欠陥準位および界面準位を介してキャリアが
再結合し、オーミック接合となる。ただし、ｐ型、ｎ型
の各層の成膜条件によっては、オーミック接合とならず
にｐｎ接合となり、逆方向の光起電力を発生し、光起電
力素子の光電変換効率を低減させることがある。In the double cell as in this embodiment, the contact interface between the two cells, that is, p / which forms the contact interface between the amorphous silicon nip cell and the microcrystalline silicon nip cell.
It is required that no photovoltaic is generated at the n reverse junction. Generally, in a p / n reverse junction formed of non-single-crystal silicon, there are many defect levels in each of the p-type layer and the n-type layer, and carriers are recombined via the defect level and the interface level to form an ohmic junction. Becomes However, depending on the film formation conditions of each of the p-type and n-type layers, a pn junction may be formed instead of an ohmic junction, generating a photovoltaic force in the opposite direction and reducing the photoelectric conversion efficiency of the photovoltaic element. .
【００６２】参考のために、微結晶シリコンｎｉｐセル
のｎ型層の低速微結晶層７０９を形成せずに光起電力素
子を構成した（参考用素子）。これらの光起電力素子で
形成した各太陽電池モジュールを、実施例１と同様の測
定を行なった。For reference, a photovoltaic element was formed without forming the n-type low-speed microcrystalline layer 709 of the microcrystalline silicon nip cell (reference element). The same measurement as in Example 1 was performed for each solar cell module formed with these photovoltaic elements.
【００６３】参考用素子ではそれほど良好な変換効率は
得られなかったが、実施例３素子では高い光電変換効率
が得られた。これは微結晶シリコンで構成されたｐ型層
の上でも、高速で形成した非晶質シリコンと高速で形成
された微結晶シリコンだけではクラックなどが発生し、
漏洩電流が流れるためか、高い光電変換効率が得られな
い。すなわち非晶質シリコンｎｉｐセルを形成した後、
大気中に取り出す過程でｐ型層表面に形成される極めて
薄いシリコン酸化膜、あるいは付着した微小な異物を、
高速で成膜した非晶質シリコンと高速で成膜した微結晶
シリコンでは覆いきれず、ｐ／ｎ逆接合部で良好な界面
が形成されずに逆方向の光起電力が発生してしまい、光
電変換効率が低下する。Although the reference device did not provide so good conversion efficiency, the device of Example 3 obtained high photoelectric conversion efficiency. This is because even on a p-type layer composed of microcrystalline silicon, cracks occur only with amorphous silicon formed at high speed and microcrystalline silicon formed at high speed alone,
High photoelectric conversion efficiency cannot be obtained, probably because of leakage current. That is, after forming an amorphous silicon nip cell,
An extremely thin silicon oxide film formed on the surface of the p-type layer in the process of being taken out to the atmosphere,
Amorphous silicon formed at a high speed and microcrystalline silicon formed at a high speed cannot be covered, and a favorable interface is not formed at the p / n reverse junction, and a photovoltaic force in the opposite direction is generated. The photoelectric conversion efficiency decreases.
【００６４】[0064]
【発明の効果】本発明によると、従来よりも短い成膜時
間で、光劣化の少ない高い光電変換効率をもつ光起電力
素子を実現することができる。すなわち、本発明による
と、非晶質半導体の第１の導電型半導体層を高速成膜
し、その後の微結晶半導体も高速成膜した後、この上に
より低速で微結晶半導体を形成するために、急速成長し
た部分の周囲にあるひびやクラックは低速成膜の微結晶
層で覆われ、漏洩電流の発生を抑制できる。また、高速
成膜した微結晶半導体の表面欠陥を低速成膜の微結晶半
導体が覆うことでｉ型層との界面準位を減らすことがで
きる。さらには高い結晶性を維持した微結晶シリコンで
構成した光起電力素子を形成することが可能になる。ま
た、複数のｎｉｐ接合を有する、ダブルセルやトリプル
セルなどのタンデム型光起電力素子におけるそれぞれの
第１の導電型半導体層とｉ型層の界面層としても本発明
の構成は有効である。ボトムセルとトップセルで構成さ
れたダブルセルの場合を例にとると、トップセルの第１
の導電型半導体層として高速で非晶質半導体を形成し、
その後、高速で微結晶半導体を形成し、さらにその上に
低速で微結晶半導体を形成することで、ボトムセルの第
２の導電型半導体層にダメージを与えることなく、トッ
プセルの第１の導電型半導体層の低抵抗化と作製時間の
低減を図ることが可能になる。According to the present invention, it is possible to realize a photovoltaic element having a high photoelectric conversion efficiency with less photodeterioration in a shorter film formation time than in the prior art. That is, according to the present invention, the first conductive type semiconductor layer of the amorphous semiconductor is formed at a high speed, the microcrystalline semiconductor thereafter is formed at a high speed, and then the microcrystalline semiconductor is formed at a lower speed. Cracks and cracks around the rapidly grown portion are covered with a microcrystalline layer formed at a low speed, thereby suppressing generation of leakage current. Further, by covering a surface defect of a microcrystalline semiconductor formed at a high speed with a microcrystalline semiconductor formed at a low speed, an interface state with an i-type layer can be reduced. Further, it is possible to form a photovoltaic element made of microcrystalline silicon that maintains high crystallinity. The configuration of the present invention is also effective as an interface layer between each first conductive semiconductor layer and an i-type layer in a tandem photovoltaic element such as a double cell or a triple cell having a plurality of nip junctions. Taking the case of a double cell composed of a bottom cell and a top cell as an example, the first cell of the top cell
Forming an amorphous semiconductor at high speed as a conductive semiconductor layer of
Thereafter, a microcrystalline semiconductor is formed at a high speed, and a microcrystalline semiconductor is further formed thereon at a low speed, so that the first conductive type of the top cell is not damaged without damaging the second conductive type semiconductor layer of the bottom cell. It is possible to reduce the resistance of the semiconductor layer and reduce the manufacturing time.
【図１】本発明の光起電力素子の一実施例（実施例１）
の構成を模式的に示す断面図である。FIG. 1 shows an embodiment of a photovoltaic device of the present invention (Example 1).
FIG. 2 is a cross-sectional view schematically showing the configuration of FIG.
【図２】本発明の実施例１で用いた量産型成膜装置の模
式図である。FIG. 2 is a schematic diagram of a mass-production type film forming apparatus used in Example 1 of the present invention.
【図３】従来の光起電力素子の構成を模式的に示す断面
図である。FIG. 3 is a cross-sectional view schematically illustrating a configuration of a conventional photovoltaic element.
【図４】本発明の光起電力素子の他の実施例（実施例
２）の構成を模式的に示す断面図である。FIG. 4 is a cross-sectional view schematically showing a configuration of another embodiment (Example 2) of the photovoltaic device of the present invention.
【図５】本発明で用いた量産型成膜装置内に設置された
放電室の模式図である。FIG. 5 is a schematic diagram of a discharge chamber installed in a mass production type film forming apparatus used in the present invention.
【図６】放電室における成膜速度分布および結晶化度分
布を示す図である。FIG. 6 is a diagram showing a deposition rate distribution and a crystallinity distribution in a discharge chamber.
【図７】本発明の光起電力素子のさらに他の実施例（実
施例３）の構成を模式的に示す断面図である。FIG. 7 is a cross-sectional view schematically showing a configuration of still another embodiment (Example 3) of the photovoltaic device of the present invention.
１０１、３０１、４０１、７０１ 導電性基板 １０２、３０２、４０２、７０２、７０７ 非晶質ｎ型
層（高速成膜） １０３、３０３、４０３、７０３、７０８ 微結晶ｎ型
層（高速成膜） １０４、４０４、７０４、７０９ 微結晶ｎ型層（低速
成膜） １０５、３０５、７１０ 非晶質ｉ型層 ４０５、７０５ 微結晶ｉ型層 １０６、３０６、４０６、７０６、７１１ 微結晶ｐ型
層 １０７、３０７、４０７、７１２ 上部電極 ２０１ 帯状基板 ２０２ ガスゲート ２０３ 帯状基板の巻き出しボビン ２０４ 帯状基板の巻き出し室 ２０５ 帯状基板の巻き取りボビン ２０６ 帯状基板の巻き取り室 ２０７ ｎ型層成膜室 ２０８、２０９ ｉ型層成膜室 ２１０ ｐ型層成膜室 ５０２ 真空容器 ５０３、５０４ ガスゲート ５０５ 放電室 ５０６ 放電電極 ５０７ 原料ガス導入管 ５０８ 排気管 ５０９ ブロックヒーター ５１０ 放電室外部排気口 ５１１ 成膜領域開口調整板 ５１２ 蓋 ５１３ ランプヒーター ５１４ 熱電対 ５１５ リフレクター ５１６ 支持ローラー ５１７ ゲートガス導入管101, 301, 401, 701 Conductive substrate 102, 302, 402, 702, 707 Amorphous n-type layer (high-speed film formation) 103, 303, 403, 703, 708 Microcrystalline n-type layer (high-speed film formation) 104 , 404, 704, 709 Microcrystalline n-type layer (low-speed deposition) 105, 305, 710 Amorphous i-type layer 405, 705 Microcrystalline i-type layer 106, 306, 406, 706, 711 Microcrystalline p-type layer 107 , 307, 407, 712 Upper electrode 201 Strip substrate 202 Gas gate 203 Strip substrate unwinding bobbin 204 Strip substrate unwinding chamber 205 Strip substrate winding bobbin 206 Strip substrate winding chamber 207 N-type layer deposition chamber 208, 209 i-type layer deposition chamber 210 p-type layer deposition chamber 502 vacuum chamber 503, 504 gas gate 505 discharge chamber 506 discharge electrode 50 Raw material gas introduction pipe 508 exhaust pipe 509 block heater 510 discharge chamber external exhaust port 511 deposition region opening adjusting plate 512 lid 513 lamp heater 514 thermocouple 515 reflector 516 support rollers 517 gate gas introducing pipe
フロントページの続き Ｆターム(参考） 4K030 AA06 AA17 AA20 BA29 BA30 BB04 BB12 CA02 CA17 FA03 GA14 HA04 JA05 JA06 JA12 JA16 KA30 LA16 5F051 AA04 AA05 CA15 CA22 CB15 DA04 DA17 FA04 GA02 GA06Continued on the front page F term (reference) 4K030 AA06 AA17 AA20 BA29 BA30 BB04 BB12 CA02 CA17 FA03 GA14 HA04 JA05 JA06 JA12 JA16 KA30 LA16 5F051 AA04 AA05 CA15 CA22 CB15 DA04 DA17 FA04 GA02 GA06
Claims (4)
導体からなる第１の導電型半導体層、実質的に真性な半
導体層、および第２の導電型半導体層が順次積層された
構成を有する光起電力素子において、 前記第１の導電型半導体層を非晶質半導体で構成し、該
第１の導電型半導体層と前記実質的に真性な半導体層と
の間に、非晶質を多く含む第１微結晶半導体を最初に形
成し、その後、前記第１の導電型半導体層および前記第
１微結晶半導体より低い成膜速度で第２微結晶半導体を
形成したことを特徴とする光起電力素子。1. A semiconductor device having a structure in which at least one first conductive semiconductor layer made of a non-single-crystal semiconductor, a substantially intrinsic semiconductor layer, and a second conductive semiconductor layer are sequentially stacked on a substrate. In the photovoltaic element, the first conductivity type semiconductor layer is formed of an amorphous semiconductor, and a large amount of amorphous is present between the first conductivity type semiconductor layer and the substantially intrinsic semiconductor layer. A first microcrystalline semiconductor including the first microcrystalline semiconductor is formed first, and then a second microcrystalline semiconductor is formed at a lower deposition rate than the first conductive semiconductor layer and the first microcrystalline semiconductor. Power element.
結晶半導体が前記第１の導電型半導体層と同じ導電型半
導体であることを特徴とする請求項１に記載の光起電力
素子。2. The photovoltaic device according to claim 1, wherein said first microcrystalline semiconductor and said second microcrystalline semiconductor are the same conductivity type semiconductor as said first conductivity type semiconductor layer.
付与する不純物濃度が前記第２微結晶半導体のそれより
も高いことを特徴とする請求項２に記載の光起電力素
子。3. The photovoltaic device according to claim 2, wherein the concentration of the impurity imparting conductivity in the first microcrystalline semiconductor is higher than that of the second microcrystalline semiconductor.
的に前記第２微結晶半導体に向かって減少していること
を特徴とする請求項１乃至３のいずれかに記載の光起電
力素子。4. The photovoltaic device according to claim 1, wherein a film formation rate of said first microcrystalline semiconductor decreases continuously toward said second microcrystalline semiconductor. Power element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001027680A JP2002231985A (en) | 2001-02-05 | 2001-02-05 | Photovoltaic element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001027680A JP2002231985A (en) | 2001-02-05 | 2001-02-05 | Photovoltaic element |
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| Publication Number | Publication Date |
|---|---|
| JP2002231985A true JP2002231985A (en) | 2002-08-16 |
Family
ID=18892296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001027680A Withdrawn JP2002231985A (en) | 2001-02-05 | 2001-02-05 | Photovoltaic element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002231985A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310503A (en) * | 2005-04-28 | 2006-11-09 | Sanyo Electric Co Ltd | Laminate type photovoltaic device |
| JP2007214283A (en) * | 2006-02-08 | 2007-08-23 | Sanyo Electric Co Ltd | Photovoltaic element |
| US7923625B2 (en) | 2005-02-28 | 2011-04-12 | Sanyo Electric Co., Ltd. | Stacked photovoltaic device and method of manufacturing the same |
-
2001
- 2001-02-05 JP JP2001027680A patent/JP2002231985A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7923625B2 (en) | 2005-02-28 | 2011-04-12 | Sanyo Electric Co., Ltd. | Stacked photovoltaic device and method of manufacturing the same |
| US8124867B2 (en) | 2005-02-28 | 2012-02-28 | Sanyo Electric Co., Ltd. | Stacked photovoltaic device and method of manufacturing the same |
| US8383927B2 (en) | 2005-02-28 | 2013-02-26 | Sanyo Electric Co., Ltd. | Stacked photovoltaic device and method of manufacturing the same |
| JP2006310503A (en) * | 2005-04-28 | 2006-11-09 | Sanyo Electric Co Ltd | Laminate type photovoltaic device |
| EP1717868A3 (en) * | 2005-04-28 | 2015-03-04 | Sanyo Electric Co., Ltd. | Stacked photovoltaic device |
| JP2007214283A (en) * | 2006-02-08 | 2007-08-23 | Sanyo Electric Co Ltd | Photovoltaic element |
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