JP2002204003A - Method for manufacturing vertically conducting magnetoresistance effect element - Google Patents

Method for manufacturing vertically conducting magnetoresistance effect element

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Publication number
JP2002204003A
JP2002204003A JP2000401037A JP2000401037A JP2002204003A JP 2002204003 A JP2002204003 A JP 2002204003A JP 2000401037 A JP2000401037 A JP 2000401037A JP 2000401037 A JP2000401037 A JP 2000401037A JP 2002204003 A JP2002204003 A JP 2002204003A
Authority
JP
Japan
Prior art keywords
film
resistance
cppgmr
magnetoresistive
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000401037A
Other languages
Japanese (ja)
Other versions
JP3590768B2 (en
Inventor
Yuichi Osawa
沢 裕 一 大
Masayuki Kishi
雅 幸 岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000401037A priority Critical patent/JP3590768B2/en
Publication of JP2002204003A publication Critical patent/JP2002204003A/en
Application granted granted Critical
Publication of JP3590768B2 publication Critical patent/JP3590768B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y25/00—Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/14—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates
    • H01F41/30—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE]
    • H01F41/302—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Physics & Mathematics (AREA)
  • Non-Adjustable Resistors (AREA)
  • Thin Magnetic Films (AREA)
  • Hall/Mr Elements (AREA)
  • Measuring Magnetic Variables (AREA)
  • Magnetic Heads (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable to prevent dispersion of resistance and obtain a high process yield of a magnetoresistance effect element. SOLUTION: A manufacturing method comprises the steps of: forming a lower electrode 2, forming a magnetoresistance effect film 4 including a plurality of layers on the lower electrode; forming a mask 6 on the magnetoresistance effect film; patterning the magnetoresistance effect film with the mask; forming a high resistive film 10 having higher resistance than the magnetoresistance effect film at the side of the magnetoresistance effect film as the mask remain; removing the mask; removing the high resistive film existing on the magnetoresistance effect film; an forming an upper electrode 12 on the magnetoresistance effect film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、垂直通電型磁気抵抗効
果素子の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a current-perpendicular-to-the-plane type magnetoresistance effect element.

【０００２】[0002]

【従来の技術】近年、ハードディスクドライブにおける
磁気記録密度は急激に上昇し、それに伴い、要求される
単位トラック幅当たりの再生出力も急激に上昇してい
る。１インチ平方当たり１００Ｇｂｐｓｉ(Gigabits pe
r square inch)の時代には、トラック幅当たりの再生出
力は１０ｍＶ以上ときわめて高くなることが予想され
る。この高出力要求に対して、ＴＭＲ(Tunneling Magne
to-resistance)素子やＣＰＰ−ＧＭＲ(Current Perpend
icular to the Plane−Giant Magneto-resistance)など
膜積層界面に垂直センス電流を流す再生素子が提案され
ている。これら垂直通電方式のセンサーへのセンス電流
供給は再生素子の上下に電極をとる必要がある。しか
し、高磁気記録密度に伴い媒体上の磁化が小さいため、
再生素子の形状もディープサブミクロンレベルに小さく
する必要がある。2. Description of the Related Art In recent years, the magnetic recording density of a hard disk drive has rapidly increased, and accordingly, the required reproduction output per unit track width has also rapidly increased. 100 Gbps per inch square (Gigabits pe
In the age of (r square inch), the reproduction output per track width is expected to be as high as 10 mV or more. TMR (Tunneling Magne
to-resistance) element and CPP-GMR (Current Perpend
There has been proposed a reproducing element such as a specific to the plane-giant magneto-resistance) in which a vertical sense current flows through the interface of the film stack. To supply a sense current to these vertical conduction type sensors, it is necessary to take electrodes above and below the reproducing element. However, because the magnetization on the medium is small with high magnetic recording density,
The shape of the reproducing element also needs to be reduced to a deep submicron level.

【０００３】一方、再生素子の製造方法は面内通電方式
の時代から、そのプロセス簡便性の理由でＡｂｕｔｔｅ
ｄ Ｊｕｎｃｔｉｏｎ（以下、ＡＪとも言う）プロセス
が使用されており、垂直通電方式再生素子となってもそ
のプロセス簡便性に変わりないためＡＪプロセスが採用
される。面内通電型素子におけるＡＪプロセスとは、ま
ず図９（ａ）に示すように、下部ギャップ２２上に形成
されたＣＩＰ(CurrentIn Plane)磁気抵抗効果膜２４上
にＴ型レジストパターン２６を形成し、このＴ型レジス
トパターン２６をマスクとしてＣＩＰ磁気抵抗効果膜２
４をパターニングし、その後、このＴ型レジストパター
ン２６をパターニング後もそのまま残してその上からバ
イアス膜２８および電極膜３０を成膜し（図９（ｃ）参
照）、最後にＴ型レジストパターン２６を除去するプロ
セスを指す（図９（ｄ）参照）。On the other hand, a method for manufacturing a reproducing element has been developed since the era of the in-plane energization method because of the simplicity of the process.
The dJunction (hereinafter, also referred to as AJ) process is used, and the AJ process is adopted because even if it becomes a vertical conduction type reproducing element, its process simplicity does not change. The AJ process in the in-plane conduction type element is as follows. First, as shown in FIG. 9A, a T-type resist pattern 26 is formed on a CIP (Current In Plane) magnetoresistive film 24 formed on a lower gap 22. CIP magnetoresistive film 2 using this T-type resist pattern 26 as a mask.
4, after which the T-type resist pattern 26 is left as it is after patterning, and a bias film 28 and an electrode film 30 are formed thereon (see FIG. 9C). (See FIG. 9D).

【０００４】垂直通電型再生素子においては、特開２０
００−２２８００２号公報に示されるように、下部電極
２上にＣＰＰ磁気抵抗効果膜４を形成し、このＣＰＰ磁
気抵抗効果膜４上にＴ型レジストパターンを形成する。
そして、このＴ型レジストパターン６をマスクとしてＣ
ＰＰ磁気抵抗効果膜４をパターニングし、その後、この
Ｔ型レジストパターンをパターニング後もそのまま残し
てその上からバイアス膜８および絶縁膜１０を成膜し、
最後にＴ型レジストパターンを除去する（図１０参
照）。なお、絶縁膜１０を成膜する代わりにバイアス膜
８そのものが高電気抵抗材料で形成するように構成して
も良い。Japanese Patent Laid-Open Publication No.
As shown in JP-A-00-228002, a CPP magnetoresistive film 4 is formed on the lower electrode 2, and a T-type resist pattern is formed on the CPP magnetoresistive film 4.
Then, using this T-type resist pattern 6 as a mask, C
After patterning the PP magnetoresistive film 4, the bias film 8 and the insulating film 10 are formed on the T-type resist pattern from above while leaving the T-type resist pattern as it is after patterning.
Finally, the T-type resist pattern is removed (see FIG. 10). Note that, instead of forming the insulating film 10, the bias film 8 itself may be formed of a high electric resistance material.

【０００５】[0005]

【発明が解決しようとする課題】このように、ＣＰＰ磁
気抵抗効果素子の製造にＡＪプロセスを用いた場合、マ
スクの必然的形状から高抵抗材料膜８や絶縁膜１０がマ
スクの窪み部分に回り込んで磁気抵抗効果膜４のエッジ
付近にかかる。高抵抗材料膜８や絶縁膜１０が磁気抵抗
効果膜４上にかかる距離（オーバーラップ量）を制御す
ることが困難であるため、磁気抵抗効果膜４上に形成さ
れる上電極と磁気抵抗効果膜４との接触面積にばらつき
が生じる。その結果、センサー（磁気抵抗効果素子）の
抵抗がばらついてしまう。仮にセンサーのサイズが０．
１μｍ×０．１μｍであって、通常、絶縁膜１０のオー
バーラップ量がエッジより１０ｎｍのときに、そのオー
バーラップ量がもし２０ｎｍになったとすると、磁気抵
抗効果膜と上電極との接触面積は２乃至３割低くなって
しまう。しかも、このオーバーラップ量を１０ｎｍに制
御するのはプロセス的に非常に困難であり、実際に製造
しても歩留まりが悪く、コスト高をもたらす。As described above, when the AJ process is used for manufacturing a CPP magnetoresistive element, the high-resistance material film 8 and the insulating film 10 move around the recessed portion of the mask due to the inevitable shape of the mask. And is applied near the edge of the magnetoresistive film 4. Since it is difficult to control the distance (overlapping amount) of the high resistance material film 8 and the insulating film 10 on the magnetoresistive film 4, the upper electrode formed on the magnetoresistive film 4 and the magnetoresistive effect The contact area with the film 4 varies. As a result, the resistance of the sensor (magnetoresistive element) varies. If the size of the sensor is 0.
When the overlap amount of the insulating film 10 is 1 nm × 0.1 μm and the overlap amount of the insulating film 10 is usually 10 nm from the edge, and the overlap amount becomes 20 nm, the contact area between the magnetoresistive film and the upper electrode becomes 20 to 30% lower. In addition, it is very difficult to control the amount of overlap to 10 nm in terms of process. Even if it is actually manufactured, the yield is low and the cost is high.

【０００６】本発明は上記事情を考慮してなされたもの
であって、磁気抵抗効果素子の抵抗値がばらつくのを可
及的に防止し、歩留まりを可及的に高くすることのでき
る垂直通電型磁気抵抗効果素子の製造方法を提供するこ
とを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is intended to prevent the resistance value of a magnetoresistive element from varying as much as possible and to increase the yield as much as possible. It is an object of the present invention to provide a method of manufacturing a magnetoresistive effect element.

【０００７】[0007]

【課題を解決するための手段】本発明による垂直通電型
磁気抵抗効果素子の製造方法は、下部電極を形成し、前
記下部電極上に複数の層を有する磁気抵抗効果膜を形成
し、前記磁気抵抗効果膜上にマスクを形成し、このマス
クを用いて前記磁気抵抗効果膜をパターニングし、前記
マスクを残したまま前記磁気抵抗効果膜よりも抵抗の高
い高抵抗膜を前記磁気抵抗効果膜の脇に形成し、前記マ
スクを除去し、前記磁気抵抗効果膜上に存在する前記高
抵抗膜を除去し、前記磁気抵抗効果膜上に上部電極を形
成することを特徴とする。According to the present invention, there is provided a method of manufacturing a current-perpendicular-to-type magnetoresistive element, comprising: forming a lower electrode; forming a magnetoresistive film having a plurality of layers on the lower electrode; A mask is formed on the resistive effect film, and the magnetoresistive effect film is patterned using the mask, and a high-resistive film having a higher resistance than the magnetoresistive effect film is formed on the resistive film while the mask remains. Forming a side electrode, removing the mask, removing the high resistance film present on the magnetoresistive film, and forming an upper electrode on the magnetoresistive film.

【０００８】このように構成された本発明の製造方法に
おいては、マスクを残したまま高抵抗膜を堆積した後、
マスクを除去し、その後磁気抵抗効果膜上に存在する高
抵抗膜を除去する。これにより、磁気抵抗効果膜上に形
成される上部電極とのコンタクト面積が磁気抵抗効果膜
の上部面積で規定されるため、磁気抵抗効果素子の抵抗
が安定し、抵抗値がばらつくのを防止することができ
る。その結果、磁気抵抗効果素子を歩留まり良く製造す
ることができる。In the manufacturing method of the present invention having the above-described structure, after depositing the high-resistance film while leaving the mask,
The mask is removed, and then the high resistance film existing on the magnetoresistive film is removed. Thereby, the contact area with the upper electrode formed on the magnetoresistive film is defined by the upper area of the magnetoresistive film, so that the resistance of the magnetoresistive element is stabilized and the resistance value is prevented from varying. be able to. As a result, the magnetoresistive element can be manufactured with high yield.

【０００９】なお、前記高抵抗膜は、前記磁気抵抗効果
膜の最上層の除去速度に比べて大きい除去速度を有する
材料からなることが好ましい。Preferably, the high-resistance film is made of a material having a higher removal rate than the removal rate of the uppermost layer of the magneto-resistance effect film.

【００１０】また、前記高抵抗膜の除去にはリアクティ
ブイオンエッチング（以下、ＲＩＥともいう）法または
ケミカルメカニカルポリッシング（以下、ＣＭＰともい
う）法を用いても良い。The high resistance film may be removed by a reactive ion etching (hereinafter, also referred to as RIE) method or a chemical mechanical polishing (hereinafter, also referred to as CMP) method.

【００１１】なお、前記高抵抗膜は、イオンビームスパ
ッタ法、カソーディックアーク法、ロングスロースパッ
タ法、およびコリメーションスパッタ法のいずれか、あ
るいはこれらと同等に指向性の良い方法により成膜され
ることが好ましい。The high-resistance film is formed by any one of an ion beam sputtering method, a cathodic arc method, a long throw sputtering method, and a collimation sputtering method, or a method having the same directivity as these. Is preferred.

【００１２】[0012]

【発明の実施の形態】本発明の実施形態を以下、図面を
参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１３】（第１実施形態）本発明による垂直通電型
磁気抵抗効果素子の製造方法の第１の実施形態を図１乃
至３を参照して説明する。この実施形態の製造方法の製
造工程を図１に示す。(First Embodiment) A first embodiment of a method of manufacturing a current-perpendicular-to-plane type magnetoresistive element according to the present invention will be described with reference to FIGS. FIG. 1 shows a manufacturing process of the manufacturing method according to this embodiment.

【００１４】まず、図１（ａ）に示すように、アルチッ
ク基板１００上に、アルミナアンダーコート膜（図示せ
ず）、さらに下部シールド膜（図示せず）を形成した
後、この下部シールド膜上に、例えばＭｏＷ合金、また
はＴａからなる導体膜を下部電極２として形成する。さ
らに下部電極２の表面を例えばＣＭＰを用いて、表面粗
さ５ｎｍ以下となるように平滑化する。表面粗さを押さ
えることは特に素子サイズが小さくなってきたときに重
要で、例えば素子サイズが０．１μｍ×０．１μｍ角程
度になった場合、メッキなどで形成されるＮｉＦｅから
なる下部シールド膜のグレイン一つ一つの大きさが素子
の１／１０程度になってくるためグレイン凹凸をきれい
に制御することが垂直通電型再生素子の信頼性確保に重
要となってくる。ＣＭＰによる平滑化はＮｉＦｅからな
る下部シールド膜上で行っても良いし、ＭｏＷからなる
下電極２上で行っても良い。First, as shown in FIG. 1A, an alumina undercoat film (not shown) and a lower shield film (not shown) are formed on an AlTiC substrate 100, and then the lower shield film is formed. Then, a conductor film made of, for example, a MoW alloy or Ta is formed as the lower electrode 2. Further, the surface of the lower electrode 2 is smoothed using, for example, CMP so that the surface roughness becomes 5 nm or less. It is important to suppress the surface roughness especially when the element size is reduced. For example, when the element size is about 0.1 μm × 0.1 μm square, the lower shield film made of NiFe is formed by plating or the like. Since the size of each grain becomes about 1/10 of that of the element, it is important to control the roughness of the grain precisely in order to secure the reliability of the vertical conduction type reproducing element. The smoothing by CMP may be performed on the lower shield film made of NiFe, or may be performed on the lower electrode 2 made of MoW.

【００１５】次に、図１（ｂ）に示すように、下部電極
２上に垂直通電型磁気抵抗効果膜、例えばＣＰＰＧＭＲ
膜４を形成する。このＣＰＰＧＭＲ膜４の積層構造は、
例えば、下から、膜厚が５ｎｍのTa層、膜厚が１ｎｍの
CoFe層、膜厚が１ｎｍのCu層、膜厚が１ｎｍのCoFe層、
膜厚が１ｎｍのCu層、膜厚が１ｎｍの CoFe層、膜厚が
７ｎｍのCu層、膜厚が１ｎｍのCoFe層、膜厚が１ｎｍの
Cu層、膜厚が１ｎｍのCoFe層、膜厚が１ｎｍのCu層、膜
厚が１ｎｍのCoFe層、膜厚が２３ｎｍのPtMn層、および
膜厚が５ｎｍのTa層をからなっている。Next, as shown in FIG. 1B, a perpendicular conduction type magnetoresistive film, for example, CPPGMR is formed on the lower electrode 2.
The film 4 is formed. The laminated structure of the CPPGMR film 4 is as follows.
For example, from below, a Ta layer having a thickness of 5 nm and a Ta layer having a thickness of 1 nm
A CoFe layer, a Cu layer having a thickness of 1 nm, a CoFe layer having a thickness of 1 nm,
Cu layer 1 nm thick, CoFe layer 1 nm thick, Cu layer 7 nm thick, CoFe layer 1 nm thick, 1 nm thick CoFe layer
It comprises a Cu layer, a CoFe layer having a thickness of 1 nm, a Cu layer having a thickness of 1 nm, a CoFe layer having a thickness of 1 nm, a PtMn layer having a thickness of 23 nm, and a Ta layer having a thickness of 5 nm.

【００１６】続いて、このＣＰＰＧＭＲ膜４上にフォト
レジストからなる下方にリセス６ａを有するフォトレジ
ストパターン６を形成しこのフォトレジストパターン６
をマスクとしてＣＰＰＧＭＲ膜４を、例えばイオンミリ
ングにてパターニングする（図１（ｂ）参照）。なお、
図１（ｂ）以降においては、基板１００は省略されてい
る。Subsequently, a photoresist pattern 6 having a recess 6a below the photoresist is formed on the CPPGMR film 4, and the photoresist pattern 6 is formed.
Is used as a mask to pattern the CPPGMR film 4 by, for example, ion milling (see FIG. 1B). In addition,
1B and thereafter, the substrate 100 is omitted.

【００１７】次に、図１（ｃ）に示すように、フォトレ
ジストパターン６をそのまま残して例えばＣｏＰｔから
なる膜厚が５０ｎｍのバイアス膜８を形成し、更に、Ｃ
ＰＰＧＭＲ膜よりも抵抗の高い高抵抗膜、例えばＳｉＯ
２からなる膜厚が５０ｎｍの絶縁膜１０を形成する。そ
して、フォトレジストパターン６を除去すると、図１
（ｄ）に示すようにＣＰＰＧＭＲ膜４上にＳｉＯ２から
なる絶縁膜１０がわずかにかかり、オーバーラップ状態
となる。このときのオーバーラップ量はフォトレジスト
パターン６の形状およびＳｉＯ２ からなる絶縁膜１０
の成膜工程での絶縁膜１０の回り込みで決まる。一般
に、オーバーラップ量必要制御量が約１０ｎｍのオーダ
ーになるとコントロールが極めて困難となってくる。Next, as shown in FIG. 1C, a bias film 8 of, for example, 50 nm in thickness made of CoPt is formed while leaving the photoresist pattern 6 as it is.
High resistance film having higher resistance than PPGMR film, for example, SiO 2
An insulating film 10 made of 2 and having a thickness of 50 nm is formed. Then, when the photoresist pattern 6 is removed, FIG.
As shown in FIG. 3D, the insulating film 10 made of SiO 2 slightly covers the CPPGMR film 4 and enters an overlapping state. The amount of overlap at this time depends on the shape of the photoresist pattern 6 and the insulating film 10 made of SiO 2.
Of the insulating film 10 in the film forming process. In general, when the required amount of overlap control is on the order of about 10 nm, control becomes extremely difficult.

【００１８】このように、絶縁膜１０がＣＰＰＧＭＲ膜
４上でオーバーラップしている状態で、図２に示すよう
に上部電極１２の形成工程を行うと、絶縁膜１０がオー
バーラップしている部分ａには上部電極１２からのセン
ス電流は流れず、ＣＰＰＧＭＲ膜４は、絶縁膜１０がオ
ーバーラップしていない部分ｂのみで上部電極１２との
コンタクトがなされる。そのため電流が流れる部分が小
さくなることやコンタクトエリアが小さくなってしまい
素子抵抗（コンタクト抵抗含む）が上昇してしまう。When the upper electrode 12 is formed as shown in FIG. 2 with the insulating film 10 overlapping on the CPPGMR film 4, the portion where the insulating film 10 overlaps is formed. The sense current from the upper electrode 12 does not flow through a, and the CPPGMR film 4 makes contact with the upper electrode 12 only at the portion b where the insulating film 10 does not overlap. For this reason, a portion through which a current flows becomes small, and a contact area becomes small, and element resistance (including contact resistance) increases.

【００１９】そこで、本実施形態では、図１（ｅ）に示
すように、上部電極１２が形成される前に、 例えばＣ
ＨＦ３などフレオン系ガスを用いたＲＩＥを基板全面に
行った。エッチング量はＳｉＯ２膜１０で約１０ｎｍ行
った。また、物理的なイオンの衝突がＣＰＰＧＭＲ膜４
に悪影響を及ぼす可能性もあるためより化学的なドライ
エッチングであるＣＤＥ(Chemical Dry Etching)を適用
することはさらに望ましい。ＣＰＰＧＭＲ膜４の最上層
のＴａ保護膜とＳｉＯ２膜１０とのＲＩＥにおける選択
比は約１０であった。したがって、膜厚が１０ｎｍのＳ
ｉＯ２膜１０のエッチングはＴａ保護膜の１ｎｍのエッ
チングに相当する。このエッチングにより、図１（ｆ）
に示すように、ＣＰＰＧＭＲ膜４上の絶縁膜はＣＰＰＧ
ＭＲ膜４のエッジまで後退した。その結果、センサー抵
抗はＣＰＰＧＭＲ膜４の上面の面積で規定されるため、
抵抗値がばらつくのを可及的に防止でき、歩留まりを可
及的に高くすることができる。なお、ＣＰＰＧＭＲ膜４
上に残存する絶縁膜１０を除去した後、ＣＰＰＧＭＲ膜
４上に上部電極（図示せず）を形成する。Therefore, in this embodiment, for example, as shown in FIG.
RIE using a Freon-based gas such as HF 3 was performed on the entire surface of the substrate. The etching amount was about 10 nm for the SiO 2 film 10. In addition, physical ion collision causes the CPPGMR film 4
It is more desirable to apply CDE (Chemical Dry Etching), which is a more chemical dry etching, because it may adversely affect the etching. The selectivity of the uppermost Ta protection film of the CPPGMR film 4 and the SiO 2 film 10 in RIE was about 10. Therefore, the S film having a thickness of 10 nm
The etching of the iO 2 film 10 corresponds to the etching of the Ta protective film by 1 nm. By this etching, FIG.
As shown in FIG.
It receded to the edge of the MR film 4. As a result, the sensor resistance is defined by the area of the upper surface of the CPPGMR film 4,
Variation in resistance can be prevented as much as possible, and the yield can be increased as much as possible. The CPPGMR film 4
After removing the insulating film 10 remaining thereon, an upper electrode (not shown) is formed on the CPPGMR film 4.

【００２０】ＣＰＰＧＭＲ膜４上に回り込んでくるＳｉ
Ｏ２からなる絶縁膜１０の厚さは平坦な部分に比べて数
分の１以下であるため、ＲＩＥを少し行うことによって
素子上の絶縁膜１０は容易に除去することができる。な
お、バイアス膜８上の絶縁膜１０はその分エッチングさ
れることになるが、ＣＰＰＧＭＲ膜４上に回り込む量は
数分の１以下と僅かであるため、予め厚く形成しておく
ことで上部電極１２とバイアス膜８との絶縁を確保する
ことができる。Si wrapping around the CPPGMR film 4
Since the thickness of the insulating film 10 made of O 2 is less than a fraction of the thickness of a flat portion, the insulating film 10 on the element can be easily removed by slightly performing RIE. The insulating film 10 on the bias film 8 is etched by that much, but the amount of the insulating film 10 that wraps around the CPPGMR film 4 is as small as a fraction or less. Insulation between the bias film 12 and the bias film 8 can be ensured.

【００２１】また、イオンビームスパッタリングなど指
向性の良好な成膜方法、すなわちターゲットから飛び出
る物質の方向が所定の一方向となる成膜方法を用いれ
ば、絶縁膜１０の分布は、ＣＰＰＧＭＲ膜４をはずれる
と急激に厚くなるように形成することができる。その結
果、ＲＩＥ時間のプロセス幅を広げることができる。こ
れを図３（ａ）を参照して説明する。 図３（ａ）に絶
縁膜１０をイオンビームスパッタなど指向性の良い方法
で成膜した場合を示す。ＣＰＰＧＭＲ膜４上の絶縁膜を
除去するためＲＩＥ法を用いて異方性エッチングを行
う。これにより絶縁膜１０はＣＰＰＧＭＲ膜４上をエッ
ジに向かって後退する。ジャストエッチング状態をちょ
うどＣＰＰＧＭＲ膜４のエッジに絶縁膜１０が係った時
間とする。さらにオーバーエッチングとなるようにＲＩ
Ｅを行った場合、ＣＰＰＧＭＲ膜４のエッジで絶縁膜１
０の膜厚分布が急峻なとき、すなわち絶縁膜４が指向性
の良い成膜方法で形成されたときは、オーバーエッチン
グとなるようにＲＩＥを行っても絶縁膜縁１０はＣＰＰ
ＧＭＲ膜４のエッジよりほとんど後退しない。その結
果、絶縁膜１０下のＣｏＰｔからなるバイアス膜８がエ
ッチング表面に出てこないため、上部電極（図示せず）
から流れ込んでくるセンス電流はＣＰＰＧＭＲ膜４に流
入し、バイアス導体膜８に分流しない。このため、セン
ス電流の損失が無く、ＣＰＰＧＭＲ素子の抵抗値がばら
つくのを防止することができる。Further, if a film forming method having good directivity such as ion beam sputtering, that is, a film forming method in which the direction of a substance protruding from a target is a predetermined direction is used, the distribution of the insulating film When it comes off, it can be formed to be rapidly thick. As a result, the process width of the RIE time can be increased. This will be described with reference to FIG. FIG. 3A shows a case where the insulating film 10 is formed by a method having good directivity such as ion beam sputtering. Anisotropic etching is performed using the RIE method to remove the insulating film on the CPPGMR film 4. As a result, the insulating film 10 recedes on the CPPGMR film 4 toward the edge. The just-etched state is the time when the insulating film 10 is engaged with the edge of the CPPGMR film 4. RI so that it is over-etched
When E is performed, the insulating film 1 is formed at the edge of the CPPGMR film 4.
When the film thickness distribution of 0 is steep, that is, when the insulating film 4 is formed by a film forming method having good directivity, even if RIE is performed so that over-etching is performed, the insulating film edge 10 remains at CPP.
It hardly recedes from the edge of the GMR film 4. As a result, since the bias film 8 made of CoPt under the insulating film 10 does not come out on the etching surface, the upper electrode (not shown)
The sense current flowing from the semiconductor device flows into the CPPGMR film 4 and does not branch into the bias conductor film 8. For this reason, there is no sense current loss, and it is possible to prevent the resistance value of the CPPGMR element from varying.

【００２２】一方、絶縁膜１０をＲＦ(Radio Frequenc
y)スパッタ法などで形成した場合は、図３（ｂ）に示す
ように、ＲＩＥにより絶縁膜１０がＣＰＰＧＭＲ膜４の
エッジにかかるジャストエッチングの状態から、さら
に、オーバーエッチングとなるようにＲＩＥを行ったと
きには、ＣＰＰＧＭＲ膜４のエッジ近傍における絶縁膜
１０の膜厚分布が緩やかなためオーバーエッチングによ
り絶縁膜１０の縁が後退してＣｏＰｔからなるバイアス
導体膜８がエッチング表面にでてくる。この結果、上部
電極（図示せず）より流入するセンス電流はＣＰＰＧＭ
Ｒ膜４のみならずＣｏＰｔからなるバイアス膜８にも流
れてしまうため、センス電流をロスすることとなる。On the other hand, the insulating film 10 is made of RF (Radio Frequenc
y) When formed by sputtering or the like, as shown in FIG. 3B, RIE is performed so that the insulating film 10 is over-etched from the just-etched state where the insulating film 10 reaches the edge of the CPPGMR film 4 by RIE. When this is performed, since the thickness distribution of the insulating film 10 near the edge of the CPPGMR film 4 is gentle, the edge of the insulating film 10 recedes due to overetching, and the bias conductor film 8 made of CoPt comes to the etched surface. As a result, the sense current flowing from the upper electrode (not shown) is CPPGM
Since the current flows not only in the R film 4 but also in the bias film 8 made of CoPt, the sense current is lost.

【００２３】以上のことから、本発明を通用するに当た
りイオンビームスパッタ法など指向性の良好な成膜方法
によって形成された絶縁膜１０は、通常のＲＦスパッタ
リング成膜との膜質比較による耐圧性向上以外に、この
ＣＰＰＧＭＲ膜４のエッジでの急峻な膜厚プロファイル
を形成することにより、プロセスウィンドウの拡大をも
たらし、その結果センサー抵抗をより安定化させること
ができる。As described above, when the present invention is applied, the insulating film 10 formed by a film forming method having a good directivity such as an ion beam sputtering method has an improved withstand voltage property by comparing the film quality with a normal RF sputtering film forming method. In addition, by forming a steep film thickness profile at the edge of the CPPGMR film 4, the process window can be expanded, and as a result, the sensor resistance can be further stabilized.

【００２４】指向性の良好な成膜方法としては、イオン
ビームスパッタ法の他に、カソーディックアーク法、ロ
ングスロースパッタ法、またはコリメーションスパッタ
法等があり、これらのいずれか、あるいはこれらと同等
に指向性の良い方法を用いることが好ましい。As a film forming method having good directivity, in addition to the ion beam sputtering method, there are a cathodic arc method, a long throw sputtering method, a collimation sputtering method, and the like. It is preferable to use a method with good directivity.

【００２５】なお、この実施形態では絶縁膜１０をＳｉ
Ｏ２ 、エッチングガスをＣＨＦ ３であったが、エッチ
ングガスは他のフレオン系ガスや塩素系ガス等も使用す
ることができる。また、絶縁膜１０はアルミナ、ジルコ
ニアなどを用いても良い。In this embodiment, the insulating film 10 is made of Si.
O2CHF etching gas 3It was an etch
Other freon-based gas, chlorine-based gas, etc.
Can be The insulating film 10 is made of alumina or zircon.
Near or the like may be used.

【００２６】（第２の実施形態）次に、本発明による垂
直通電型磁気抵抗効果素子の製造方法の第２の実施形態
を図４を参照して説明する。図４は本実施形態の製造方
法の製造工程を示す断面図である。(Second Embodiment) Next, a second embodiment of the method of manufacturing a perpendicular conduction type magnetoresistive element according to the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view illustrating a manufacturing process of the manufacturing method according to the present embodiment.

【００２７】本実施形態の製造方法は、第１の実施形態
の製造方法において、ＲＩＥによるオーバーエッチング
を防止するために、絶縁膜１０の代わりに材質の異なる
２つの材料を積層させた絶縁膜１１を形成したものであ
る。ＣｏＰｔからなるバイアス膜８の成膜までは第１の
実施形態と同様の工程で行う。そして、フォトレジスト
パターン６を残した状態で膜厚が３０ｎｍのＳｉＯ２か
らなる膜１１ａを形成し、さらに膜厚が３０ｎｍのＡｌ
２Ｏ３からなる絶縁膜膜１１ｂを積層させ、その後、第
１の実施形態と同様にフォトレジストパターン６を除去
すること、すなわちリフトオフ法によって絶縁膜１１を
形成する（図４（ａ）参照）。The manufacturing method of this embodiment is different from the manufacturing method of the first embodiment in that the insulating film 11 is formed by laminating two different materials in place of the insulating film 10 in order to prevent over-etching by RIE. Is formed. The same steps as in the first embodiment are performed up to the formation of the bias film 8 made of CoPt. Then, a film 11a made of SiO 2 having a thickness of 30 nm is formed in a state where the photoresist pattern 6 is left.
An insulating film 11b made of 2 O 3 is laminated, and then the photoresist pattern 6 is removed as in the first embodiment, that is, the insulating film 11 is formed by a lift-off method (see FIG. 4A). .

【００２８】次に、図４（ｂ）に示すように、絶縁膜１
１の表面をＣＨＦ３ガスを用いたＲＩＥ法によってエッ
チングすることでＣＰＰＧＭＲ膜４上に回り込んだ絶縁
膜を除去する。このエッチングによる除去は、まず、表
層にあるアルミナ（Ａｌ２Ｏ ３）膜１１ｂをＣＨＦ３ガ
スを用いてＲＩＥを行う。このエッチングはＩＣＰプラ
ズマエッチング装置を用いてＣＨＦ３ガス１５ｓｃｃ
ｍ、コイルパワー３００Ｗ、プラテンパワー３００Ｗの
条件で行った。このエッチング条件において、Ａｌ２Ｏ
３膜１１ｂのＳｉＯ２膜１１ａに対する選択比は約４で
ある。ＣＰＰＧＭＲ膜４上のアルミナ膜１１ｂを数１０
ｎｍをエッチングの後（図４（ｂ）参照）、ＳｉＯ２膜
１１ａが断続的にエッチングされる。このとき、図４
（ｂ）に示すようにＣＰＰＧＭＲ膜４の脇には、まだ厚
いアルミナ膜１１ｂが残っている。引き続き、同条件に
てエッチングが行われる場合は、この残存しているアル
ミナ膜１１ｂがマスクの代わりをして、アルミナ膜１１
ｂに比較して約４倍の速さでＳｉＯ２膜１１ａをエッチ
ングする（図４（ｃ））。こうすることで絶縁膜１１の
後退はアルミナ膜１１ｂがマスクの役割をして制御する
ことができる。その結果、オーバーエッチングにより開
口部面積が広がり、ＣＰＰＧＭＲ膜４以外にセンス電流
が流れてセンス電流が損失することを防ぐことができ
る。Next, as shown in FIG.
1 was etched by RIE using CHF3 gas.
Insulation around the CPPGMR film 4
Remove the film. The removal by this etching first
Alumina (Al2O 3) CHF3Moth
RIE is performed using the This etching is ICP
CHF using Zuma etching equipment3Gas 15scc
m, coil power 300W, platen power 300W
Performed under conditions. Under these etching conditions, Al2O
3SiO of the film 11b2The selectivity for the film 11a is about 4
is there. The alumina film 11b on the CPPGMR film 4 has several tens of
nm after etching (see FIG. 4 (b)).2film
11a is intermittently etched. At this time, FIG.
As shown in (b), the side of the CPPGMR film 4 is still thick.
The remaining alumina film 11b remains. Continue to meet the same conditions
If etching is performed by
The alumina film 11b replaces the mask with the mina film 11b.
about 4 times faster than SiO2Etch the film 11a
(FIG. 4C). By doing so, the insulating film 11
The retreat is controlled by the alumina film 11b acting as a mask.
be able to. As a result, it is opened by over-etching.
The mouth area is widened, and the sense current
To prevent the sense current from being lost
You.

【００２９】以上のように、絶縁層１１を複数層にし
て、上層１１ｂが下層１１ａのマスクの役をするよう
に、上層のエッチングレートを下層のエッチングレート
より低くすることで、オーバーエッチングによる開口部
の広がりを抑制することができる。さらに、複数層にな
ることでピンホールによる絶縁不良を低減することが容
易となる。As described above, the etching rate of the upper layer is made lower than the etching rate of the lower layer so that the insulating layer 11 has a plurality of layers and the upper layer 11b serves as a mask for the lower layer 11a. The spread of the portion can be suppressed. Further, by using a plurality of layers, it becomes easy to reduce insulation failure due to pinholes.

【００３０】また、この第２の実施形態も第１の実施形
態と同様に、磁気抵抗効果素子の抵抗値がばらつくのを
可及的に防止することができ、歩留まりを可及的に高く
することができる。Also, in the second embodiment, as in the first embodiment, it is possible to prevent the resistance value of the magnetoresistive element from varying as much as possible, and to increase the yield as much as possible. be able to.

【００３１】なお、第１および第２の実施形態では、Ｃ
ＰＰＧＭＲ膜４上の絶縁膜を除去するエッチングとして
ドライエッチングを用いたが、ウエットエッチングを用
いて加工することも可能である。In the first and second embodiments, C
Although dry etching is used as the etching for removing the insulating film on the PPGMR film 4, processing using wet etching is also possible.

【００３２】（第３の実施形態）次に、本発明による垂
直通電型磁気抵抗効果素子の製造方法の第３の実施形態
を図５を参照して説明する。この実施形態の製造方法の
製造工程を図５に示す。(Third Embodiment) Next, a third embodiment of a method of manufacturing a perpendicular conduction type magnetoresistive element according to the present invention will be described with reference to FIG. FIG. 5 shows a manufacturing process of the manufacturing method according to this embodiment.

【００３３】この実施形態の製造方法は、第１の実施形
態において、ＣＰＰＧＭＲ膜４上の絶縁膜１０の除去
に、ＲＩＥ法の代わりにＣＭＰ法を用いて行うものであ
る。In the manufacturing method of this embodiment, in the first embodiment, the insulating film 10 on the CPPGMR film 4 is removed by using the CMP method instead of the RIE method.

【００３４】まず、図５（ａ）に示すように、膜厚が５
０ｎｍのＳｉＯ２膜１０を形成するまでは、第１の実施
形態と同じ工程で行う。なお、図５（ａ）はリフトオフ
した形状を示す。次に、ＳｉＯ２からなるベーススラリ
を用いてＣＭＰを行った。ＳｉＯ２膜１０と、ＣＰＰＧ
ＭＲ膜４の最上層であるＴａ膜との加工レートは約４：
１である。クロスをやわらかい材料に設定することで、
絶縁膜１０からＣＰＰＧＭＲ膜４にかけての凹凸に影響
されず全面にＣＭＰが行われやすくなる。ＣＭＰ加工後
の形状を図５（ｂ）に示す。ＣＭＰは約１０ｎｍ行っ
た。ＣＰＰＧＭＲ膜４上の薄いＳｉＯ２絶縁膜がＣＰＰ
ＧＭＲ膜４のエッジまで後退していることがわかる。Ｃ
ＰＰＧＭＲ膜４の最上層に形成された保護膜であるＴａ
膜の加工量は２．５ｎｍであった。以上のことからＣＭ
Ｐによっても、ＧＭＲ膜４の保護膜との加工選択比を取
ることで、ＣＰＰＧＭＲ膜４上の絶縁膜を除去すること
ができる。First, as shown in FIG.
Until the 0 nm SiO 2 film 10 is formed, the same steps as in the first embodiment are performed. FIG. 5 (a) shows the shape after lift-off. Next, CMP was performed using a base slurry made of SiO 2 . SiO 2 film 10 and CPPG
The processing rate with the Ta film which is the uppermost layer of the MR film 4 is about 4:
It is one. By setting the cloth to a soft material,
CMP is easily performed on the entire surface without being affected by the unevenness from the insulating film 10 to the CPPGMR film 4. FIG. 5B shows the shape after the CMP processing. CMP was performed about 10 nm. The thin SiO 2 insulating film on the CPPGMR film 4 is CPP
It can be seen that it has receded to the edge of the GMR film 4. C
Ta, which is a protective film formed on the uppermost layer of the PPGMR film 4,
The processing amount of the film was 2.5 nm. From the above, CM
The insulating film on the CPPGMR film 4 can also be removed by setting the processing selectivity of the GMR film 4 with respect to the protective film depending on P.

【００３５】この第３の実施形態においても、第１の実
施形態と同様に、磁気抵抗効果素子の抵抗値がばらつく
のを可及的に防止することができ、歩留まりを可及的に
高くすることができる。Also in the third embodiment, as in the first embodiment, it is possible to prevent the resistance value of the magnetoresistive element from varying as much as possible, and to increase the yield as much as possible. be able to.

【００３６】なお、第１の実施形態において、CoPtから
なるバイアス膜８の形成方法によっては、図６（ａ）に
示すように、絶縁膜１０と同様にバイアス膜８がＣＰＰ
ＧＭＲ膜４の端部にかかってしまう場合がある。この場
合、ＲＩＥ法などで絶縁膜１０を除去してもその下にバ
イアス膜８が残存することになる（図６（ｂ）参照）。
基本的にCoPtからなるバイアス膜８には導電性があるた
め絶縁膜１０をＣＰＰＧＭＲ膜４上から除去すれば素子
抵抗は安定して製造される。しかしながら、バイアス膜
８の製造方法により、バイアス膜８の電気抵抗が高く設
定される場合や、厚くＣＰＰＧＭＲ膜４上に形成された
場合、絶縁膜１０がかかっているときと同様に素子抵抗
の上昇を生じる。In the first embodiment, depending on the method of forming the bias film 8 made of CoPt, as shown in FIG.
In some cases, it may cover the end of the GMR film 4. In this case, even if the insulating film 10 is removed by the RIE method or the like, the bias film 8 remains under the insulating film 10 (see FIG. 6B).
Basically, since the bias film 8 made of CoPt has conductivity, if the insulating film 10 is removed from the CPPGMR film 4, the element resistance can be manufactured stably. However, when the electrical resistance of the bias film 8 is set high or thickly formed on the CPPGMR film 4 depending on the manufacturing method of the bias film 8, the device resistance increases similarly to the case where the insulating film 10 is applied. Is generated.

【００３７】以下に、素子抵抗値を±10%（レンジ20
％）に押さえるための、CoPtからなるバイアス膜が積層
された部分の単位面積あたりの素子抵抗の上昇許容値を
説明する。Below, the element resistance is set to ± 10% (range 20
%), The allowable value of the element resistance per unit area of the portion where the bias film made of CoPt is laminated is described.

【００３８】プロセスによる素子の面積均一性およびＣ
ＰＰＧＭＲ膜４の電気抵抗率の成膜再現性は十分あると
仮定するとして、CoPtからなるバイアス膜８の回り込み
によるＣＰＰＧＭＲ膜４の抵抗の変動をレンジで20％以
内に押さえるために必要なCoPtからなる膜８のＣＰＰＧ
ＭＲ膜４上における残存膜厚許容値を求める。The uniformity of the area of the device by the process and C
Assuming that the film reproducibility of the electrical resistivity of the PPGMR film 4 is sufficient, it is assumed that the variation in the resistance of the CPPGMR film 4 due to the wraparound of the bias film 8 made of CoPt is reduced from CoPt required to keep within 20% in the range. CPPG of film 8
An allowable value of the remaining film thickness on the MR film 4 is obtained.

【００３９】以下、図７を参照して説明する。Hereinafter, description will be made with reference to FIG.

【００４０】ＣＰＰＧＭＲ膜４のエッジからのバイアス
膜８の回り込み量をｗ（一辺の長さに対する規格値）と
し、回り込んだ部分にはCoPtからなるバイアス膜８が膜
厚ｔにて均一に成膜されているとする。またCoPtからな
る膜が回り込んでいない部分：エリアA（=(1−2w)×1）
において単位面積あたりの膜面垂直方向の抵抗Raとす
る。The amount of wrap around of the bias film 8 from the edge of the CPPGMR film 4 is defined as w (a standard value for the length of one side), and a bias film 8 made of CoPt is uniformly formed at the wraparound portion with a film thickness t. It is assumed that the film is formed. Area where the film made of CoPt does not wrap around: Area A (= (1-2w) × 1)
Is the resistance Ra in the direction perpendicular to the film surface per unit area.

【００４１】エリアAにおける膜面垂直方向の抵抗RA
は、RA＝Ra / Sa（ただし、SaはエリアAのＣＰＰＧＭＲ
膜４のサイズに対する規格化面積）となる。Resistance RA in the direction perpendicular to the film surface in area A
Is RA = Ra / Sa (where Sa is the CPPGMR of area A)
(Standardized area with respect to the size of the film 4).

【００４２】また、CoPtからなる膜８が回り込んでいる
部分：エリアB (=1−エリアA)において、単位面積あた
りの膜面垂直方向の抵抗Rbは、 Rb= c× Ra (=Ra+Rbias) ・・・（１） ここで、cはRbのRaに対する係数、RbiasはCoPt膜による
膜面垂直方向の抵抗を示す。そして、エリアBでの総合
抵抗RB（膜面垂直方向）は、RB＝Rb / Sb（ただし、Sb
はエリアBのＣＰＰＧＭＲ膜４のサイズに対する規格化
面積）となる。In the area where the film 8 made of CoPt wraps around: In the area B (= 1−area A), the resistance Rb in the direction perpendicular to the film surface per unit area is Rb = c × Ra (= Ra + Rbias) (1) where c is a coefficient of Rb with respect to Ra, and Rbias is a resistance of the CoPt film in a direction perpendicular to the film surface. Then, the total resistance RB (in the direction perpendicular to the film surface) in the area B is RB = Rb / Sb (where Sb
Is the standardized area for the size of the CPPGMR film 4 in the area B).

【００４３】CoPtからなるバイアス膜８が回り込んだこ
とによるＣＰＰＧＭＲ膜４の総合抵抗Rtotは、エリアA
とエリアBの並列抵抗であり、Rtot＝RA×RB/(RA+RB)と
なる。したがって、回り込み無しの場合に比べての素子
抵抗増加比をDとすると、次の（２）式となる。The total resistance Rtot of the CPPGMR film 4 due to the bias of the bias film 8 made of CoPt is equal to the area A
And the parallel resistance of area B, where Rtot = RA × RB / (RA + RB). Therefore, if the element resistance increase ratio is D as compared with the case where there is no wraparound, the following equation (2) is obtained.

【００４４】 D=Rtot / (Ra/(Sa+Sb))＝（RA×RB/(RA+RB)）/ (Ra/(Sa+Sb)) ・・・（２） （２）式を書き直して D=((Ra/Sa)(Rb/Sb) / ((Ra/Sa)+(Rb/Sb)))/Ra =RaRb/((RaSb+RbSa)Ra) =c/(Sb+cSa) したがって、 c=DSb/(1−DSa) ・・・（３） を得る。ここで、（１）式より ｃRa=Ra+Rbias すなわち、 ｃ＝１＋Rbias/Ra ・・・（４） となる。（３）式と（４）式から Rbias/Ra＝DSb/(1−DSa)−１ ・・・（５） を得る。D = Rtot / (Ra / (Sa + Sb)) = (RA × RB / (RA + RB)) / (Ra / (Sa + Sb)) (2) Expression (2) is rewritten. D = ((Ra / Sa) (Rb / Sb) / ((Ra / Sa) + (Rb / Sb))) / Ra = RaRb / ((RaSb + RbSa) Ra) = c / (Sb + cSa) Therefore, c = DSb / (1−DSa) (3) is obtained. Here, from equation (1), cRa = Ra + Rbias, that is, c = 1 + Rbias / Ra (4). Rbias / Ra = DSb / (1−DSa) −1 (5) is obtained from the equations (3) and (4).

【００４５】したがって、許容できる素子抵抗増加比
D、単位面積あたりのＣＰＰＧＭＲ膜の抵抗Ra、CoPt回
り込み面積Sa、Sbがわかれば許容できるCoPtからなる膜
の抵抗が導き出せる。Therefore, an acceptable element resistance increase ratio
D, the resistance Ra of the CPPGMR film per unit area, and the wraparound areas Sa and Sb of the CoPt are known, so that an acceptable resistance of the film made of CoPt can be derived.

【００４６】以下の仮定の元でCoPtからなる膜８のＣＰ
ＰＧＭＲ膜４上の残存膜厚許容値を求めてみる。Under the following assumptions, the CP of the film 8 made of CoPt
The allowable value of the remaining film thickness on the PGMR film 4 will be obtained.

【００４７】ＣＰＰＧＭＲ膜４の垂直通電方向の単位面
積あたりの抵抗値は、材料の電気抵抗率が高い反強磁性
膜（たとえばPtMn合金やIrMn合金など）厚さと下地やキ
ャップ層に用いられるTa膜の厚さによる影響がほとんど
として PtMnの電気抵抗率：230（μΩ・cm）、膜厚25nm Taの電気抵抗率：150（μΩ・cm）、膜厚が10nm(保護膜
＋下地膜) CoPtの電気抵抗率：150（μΩ・cm）、回り込み膜厚t、 エリアAにおける単位面積あたりのCPPGMR積層直列抵抗R
aが、 Ra =230×25+150×10=7250 であり、エリアBにおけるCPPGMR、バイアス膜積層単位
面積あたりの積層直列抵抗Rbが、 Rb =Ra+150t=230x25+150x10+150t= c Ra=7250c であり、また、CoPtからなるバイアス膜８はそれぞれの
エッジからＣＰＰＧＭＲ膜４の上面の一辺の20％だけ回
り込んだとしてw=0.2、したがって、 エリアA面積：Sa=(1−0.2×2)×1=0.6 エリアB面積：Sb=1−Sa=1−0.6=0.4 となる。ここで、(５)式にSa=0.6、Sb=0.4、D=1.2（素
子抵抗増加比20%として）を代入すると、 Rbias/Ra＝DSb/(1−DSa)−１ =(1.2×0.4)/(1−1.2×0.6) −1 =0.71 Rbias=150t=0.71×7250 t=34.5 nm したがって、ＣＰＰＧＭＲ膜４上にはCoPtからなる膜８
が34.5nmまで存在しても許容できることになり、CoPtか
らなる膜８の成膜プロセスによっては除去を行わなくて
も良い結果となる。The resistance value per unit area of the CPPGMR film 4 in the vertical conduction direction is determined by the thickness of an antiferromagnetic film (for example, a PtMn alloy or an IrMn alloy) having a high electric resistivity of a material and a Ta film used as an underlayer or a cap layer. Almost all of the effects of the thickness of PtMn are 230 (μΩ · cm), the electrical resistivity of 25 nm Ta is 150 (μΩ · cm), and the thickness is 10 nm (protective film + underlayer). Electrical resistivity: 150 (μΩ · cm), wraparound film thickness t, CPPGMR laminated series resistance R per unit area in area A
a is Ra = 230 × 25 + 150 × 10 = 7250, and CPPGMR in the area B, the laminated series resistance Rb per unit area of the bias film lamination, Rb = Ra + 150t = 230x25 + 150x10 + 150t = c Ra = 7250c, and the bias film 8 made of CoPt wraps around each edge by 20% of one side of the upper surface of the CPPGMR film 4, w = 0.2. Therefore, the area A area: Sa = (1−0.2 × 2 ) × 1 = 0.6 Area B area: Sb = 1−Sa = 1−0.6 = 0.4. Here, when Sa = 0.6, Sb = 0.4, and D = 1.2 (assuming the element resistance increase ratio is 20%) in the equation (5), Rbias / Ra = DSb / (1−DSa) −1 = (1.2 × 0.4 ) / (1−1.2 × 0.6) −1 = 0.71 Rbias = 150t = 0.71 × 7250 t = 34.5 nm Therefore, the CoPt film 8 is formed on the CPPGMR film 4.
Is allowable up to 34.5 nm, and it is not necessary to remove the CoPt film 8 depending on the film forming process.

【００４８】また、成膜プロセスによりバイアス膜部分
の抵抗値が上昇し、素子抵抗許容値を超える場合はバイ
アス膜の除去もしくは減少を行う必要がある。この場
合、バイアス膜も高抵抗膜となる。Further, when the resistance value of the bias film increases due to the film forming process and exceeds the allowable value of the element resistance, it is necessary to remove or reduce the bias film. In this case, the bias film also becomes a high resistance film.

【００４９】一般にCoPtからなる膜をケミカルなエッチ
ングで除去するのは困難であるため、たとえば、Taなど
ＣＰＰＧＭＲ膜の最上層の保護膜とバイアス膜８との選
択比が十分取れる角度でのイオンミリング、また、図８
（ａ）に示すように、バイアス膜８を成膜後、絶縁膜１
０の成膜前に、もしくは絶縁膜１０を成膜しない場合の
レジストパターン６の除去前に基板に対して浅い角度で
角度でイオンミリングを行い（図８（ｂ）参照）、ＣＰ
ＰＧＭＲ膜４上に形成されているバイアス膜８の除去も
しくは減少を行うことは効果的である(図８（ｂ）参
照）。以降、絶縁膜１０を成膜する場合（図８（ｃ）参
照）、レジストパターン６の除去後にＲＩＥ等を用いて
ＣＰＰＧＭＲ膜４上の絶縁膜の除去を行うことにより
（図８（ｄ）参照）、CoPtからなるバイアス膜８および
絶縁膜１０をＣＰＰＧＭＲ膜４上から除去せしめ、安定
な素子抵抗で製造することが可能となる。Since it is generally difficult to remove a film made of CoPt by chemical etching, for example, ion milling at an angle at which a selectivity between the uppermost protective film of a CPPGMR film such as Ta and the bias film 8 can be sufficiently obtained. And FIG.
As shown in (a), after forming the bias film 8, the insulating film 1 is formed.
Prior to the formation of the resist pattern 6 when the insulating film 10 is not formed or before the resist pattern 6 is removed, ion milling is performed at a shallow angle with respect to the substrate (see FIG. 8B).
It is effective to remove or reduce the bias film 8 formed on the PGMR film 4 (see FIG. 8B). Thereafter, when the insulating film 10 is formed (see FIG. 8C), the insulating film on the CPPGMR film 4 is removed by using RIE or the like after removing the resist pattern 6 (see FIG. 8D). ), The bias film 8 and the insulating film 10 made of CoPt are removed from the CPPGMR film 4 so that the device can be manufactured with stable element resistance.

【００５０】なお、上記の実施形態においては、マスク
６はＴ型形状であったが、本発明はこれに限定されるも
のではなく、磁気抵抗効果膜上に高抵抗膜が回り込む形
状のものであれば、本発明を適用できる。In the above embodiment, the mask 6 has a T-shape. However, the present invention is not limited to this. The mask 6 may have a shape in which a high-resistance film wraps around a magneto-resistance effect film. If so, the present invention can be applied.

【００５１】[0051]

【発明の効果】以上、述べたように本発明によれば、磁
気抵抗効果素子の抵抗値がばらつくのを可及的に防止す
ることができ、歩留まりを可及的に高くすることができ
る。As described above, according to the present invention, it is possible to prevent variations in the resistance value of the magnetoresistive element as much as possible, and to increase the yield as much as possible.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による垂直通電型磁気抵抗効果素子の製
造方法の第１の実施形態の製造工程断面図。FIG. 1 is a cross-sectional view illustrating a manufacturing process of a first embodiment of a method for manufacturing a perpendicular conduction type magnetoresistance effect element according to the present invention.

【図２】従来の製造方法の問題点を説明する断面図。FIG. 2 is a cross-sectional view illustrating a problem of a conventional manufacturing method.

【図３】第１の実施形態の変形例を説明する断面図。FIG. 3 is a cross-sectional view illustrating a modification of the first embodiment.

【図４】本発明による垂直通電型磁気抵抗効果素子の製
造方法の第２の実施形態の製造工程断面図。FIG. 4 is a cross-sectional view illustrating a manufacturing process of a second embodiment of the method of manufacturing the perpendicular conduction type magnetoresistive element according to the present invention.

【図５】本発明による垂直通電型磁気抵抗効果素子の製
造方法の第３の実施形態の製造工程断面図。FIG. 5 is a sectional view showing a manufacturing process of a third embodiment of the method of manufacturing the perpendicular conduction type magnetoresistance effect element according to the present invention.

【図６】第１の実施形態の他の変形例を説明する工程断
面図。FIG. 6 is a process cross-sectional view for explaining another modification of the first embodiment.

【図７】バイアス膜がＣＰＰＧＭＲ膜上に残存許容膜厚
値を求めるのに用いた模式図。FIG. 7 is a schematic diagram showing a bias film used for obtaining a remaining allowable film thickness value on a CPPGMR film.

【図８】第１の実施形態の他の変形例を説明する工程断
面図。FIG. 8 is a process cross-sectional view for explaining another modification of the first embodiment.

【図９】従来の面内通電型ＧＭＲ素子の製造工程断面
図。FIG. 9 is a sectional view showing a manufacturing process of a conventional in-plane conduction type GMR element.

【図１０】従来の製造方法によって製造された垂直通電
型ＧＭＲ素子の断面図。FIG. 10 is a cross-sectional view of a vertical conduction type GMR element manufactured by a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

２ 下部電極 ４ ＣＰＰＧＭＲ膜 ６ フォトレジストパターン ６ａ リセス ８ バイアス膜 １０ 絶縁膜 １１ 絶縁膜 １１ａ ＳｉＯ２膜 １１ｂ Ａｌ２Ｏ３膜 １００ 基板Reference Signs List 2 lower electrode 4 CPPGMR film 6 photoresist pattern 6a recess 8 bias film 10 insulating film 11 insulating film 11a SiO 2 film 11b Al 2 O 3 film 100 substrate

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 43/12 Ｇ０１Ｒ 33/06 Ｒ Ｆターム(参考） 2G017 AA01 AB07 AD55 AD65 5D034 AA03 BA06 BA15 DA07 5E033 AA02 5E049 AA01 BA12 CB01 GC01 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 43/12 G01R 33/06 LF Term (Reference) 2G017 AA01 AB07 AD55 AD65 5D034 AA03 BA06 BA15 DA07 5E033 AA02 5E049 AA01 BA12 CB01 GC01

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】下部電極を形成し、前記下部電極上に複数
の層を有する磁気抵抗効果膜を形成し、前記磁気抵抗効
果膜上にマスクを形成し、このマスクを用いて前記磁気
抵抗効果膜をパターニングし、前記マスクを残したまま
前記磁気抵抗効果膜よりも抵抗の高い高抵抗膜を前記磁
気抵抗効果膜の脇に形成し、前記マスクを除去し、前記
磁気抵抗効果膜上に存在する前記高抵抗膜を除去し、前
記磁気抵抗効果膜上に上部電極を形成することを特徴と
する垂直通電型磁気抵抗効果素子の製造方法。1. A lower electrode is formed, a magnetoresistive film having a plurality of layers is formed on the lower electrode, a mask is formed on the magnetoresistive film, and the magnetoresistive effect is formed using the mask. Patterning a film, forming a high-resistance film having a higher resistance than the magnetoresistive effect film beside the magnetoresistive effect film while leaving the mask, removing the mask, and presenting on the magnetoresistive effect film; Removing the high-resistance film and forming an upper electrode on the magneto-resistance effect film. 【請求項２】前記磁気抵抗効果膜上に存在する前記高抵
抗膜を、前記磁気抵抗効果膜の最上層の除去速度に比べ
て大きい速度で除去することを特徴とする請求項１記載
の垂直通電型磁気抵抗効果素子の製造方法。2. The method according to claim 1, wherein said high-resistance film existing on said magnetoresistive film is removed at a higher speed than a removal speed of an uppermost layer of said magnetoresistive film. A method for manufacturing a current-carrying magnetoresistive element. 【請求項３】前記高抵抗膜を、指向性の良い方法により
形成することを特徴とする請求項１記載の垂直通電型磁
気抵抗効果素子の製造方法。3. The method according to claim 1, wherein the high resistance film is formed by a method having good directivity.
JP2000401037A 2000-12-28 2000-12-28 Manufacturing method of perpendicular conduction type magnetoresistive element Expired - Fee Related JP3590768B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7134183B2 (en) 2002-12-19 2006-11-14 Tdk Corporation Method of making a thin-film magnetic head
US7231705B2 (en) 2003-02-18 2007-06-19 Tdk Corporation Method for forming a resist pattern of magnetic device
US7575853B2 (en) 2004-04-08 2009-08-18 Tdk Corporation Method of forming thin film pattern and method of forming magnetoresistive element
US7894167B2 (en) 2006-03-16 2011-02-22 Tdk Corporation Thin-film magnetic head with little reattachment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7134183B2 (en) 2002-12-19 2006-11-14 Tdk Corporation Method of making a thin-film magnetic head
US7352539B2 (en) 2002-12-19 2008-04-01 Tdk Corporation Thin-film magnetic head having a covered insulating layer
US7231705B2 (en) 2003-02-18 2007-06-19 Tdk Corporation Method for forming a resist pattern of magnetic device
US7784170B2 (en) 2003-02-18 2010-08-31 Tdk Corporation Method for forming a resist pattern of magnetic device by etching with a gas cluster ion beam
US7575853B2 (en) 2004-04-08 2009-08-18 Tdk Corporation Method of forming thin film pattern and method of forming magnetoresistive element
US7894167B2 (en) 2006-03-16 2011-02-22 Tdk Corporation Thin-film magnetic head with little reattachment

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