JP2002185148A - Multilayer wiring board, interlayer short circuit preventing method thereof multilayer wiring board, method of manufacturing the same, and electronic apparatus using the same - Google Patents
Multilayer wiring board, interlayer short circuit preventing method thereof multilayer wiring board, method of manufacturing the same, and electronic apparatus using the sameInfo
- Publication number
- JP2002185148A JP2002185148A JP2000376082A JP2000376082A JP2002185148A JP 2002185148 A JP2002185148 A JP 2002185148A JP 2000376082 A JP2000376082 A JP 2000376082A JP 2000376082 A JP2000376082 A JP 2000376082A JP 2002185148 A JP2002185148 A JP 2002185148A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- wiring board
- insulating
- insulating layer
- conductive pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層配線基板の層
間短絡防止方法および多層配線基板および多層配線基板
の製造方法およびこれらを用いた電子機器に係り、特
に、部品実装用や各種半導体用等々の多層配線基板にお
ける、層間絶縁層あるいは層間誘電体層の欠損欠陥の補
修にかかわる技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing an interlayer short circuit in a multilayer wiring board, a method for manufacturing a multilayer wiring board, a method for manufacturing a multilayer wiring board, and an electronic device using the same. The present invention relates to a technique for repairing a defect in an interlayer insulating layer or an interlayer dielectric layer in a multilayer wiring board.
【０００２】[0002]
【従来の技術】近年、電子回路に用いられる多層配線基
板は、機器の高性能化および小型化に伴い、配線の微細
化による高密度配線の実現が重要な課題となっている。
配線の高密度化においては、配線の微細化に付随して絶
縁層も薄くなるため、プロセス中で付着する異物の付着
や、フォトリソ加工時に発生するレジスト欠陥の影響に
より、絶縁層に微小な穴のような形状欠陥（欠損欠陥）
が起こりやすくなる。このような絶縁層の欠損欠陥の上
下に配線が形成されると、配線層間での短絡不良となる
が、配線の微細化に伴いこのような短絡不良が増える傾
向にあり、製造歩留まりの低下、ひいてはコストの増加
を招く主要な要因になっている。2. Description of the Related Art In recent years, with respect to multilayer wiring boards used in electronic circuits, realization of high-density wiring by miniaturization of wiring has become an important issue along with high performance and miniaturization of equipment.
In high-density wiring, the thickness of the insulating layer becomes thinner as the wiring becomes finer. Therefore, fine holes in the insulating layer may be formed due to the adhesion of foreign substances that adhere during the process and resist defects generated during photolithography. Shape defect (defect defect)
Is more likely to occur. When wirings are formed above and below such a defect in the insulating layer, a short-circuit failure occurs between the wiring layers. However, such short-circuit failures tend to increase with the miniaturization of the wiring, and a decrease in manufacturing yield. This is a major factor that leads to an increase in costs.
【０００３】この問題に対し、液晶デバイス用薄膜トラ
ンジスタアレイにおける層間短絡防止法が、特開平１０
−１３３２３１号公報に記載されている。この先願公報
に開示された層間短絡防止の手法を、図５によって説明
する。To solve this problem, a method for preventing interlayer short circuit in a thin film transistor array for a liquid crystal device is disclosed in
No. 133231. The method of preventing interlayer short circuit disclosed in the prior application will be described with reference to FIG.
【０００４】図５の（ａ）に示すように、基板５１上に
下層の導体パターンを形成するための下部導体層５２を
成膜した後、下部導体層５２の全面上にホトレジスト５
３を被着し、このホトレジスト５３を選択的に感光硬化
させた後、未硬化部分を除去して、図５の（ｂ）に示す
ように、少なくとも上から見て上層の導体パターンと重
なる箇所となる下層の導体パターン（下部導体層５２）
部分、つまり設計的に見て層間短絡不良を発生する可能
性のある下部導体層５２の部分を露呈させる。次に、図
５の（ｃ）に示すように、露呈した下部導体層５２の部
分に、陽極酸化法を用いて絶縁性の酸化皮膜５４を形成
し、然る後、図５の（ｄ）に示すように、ホトレジスト
５３を除去する。次に、再びホトレジスト５５を下部導
体層５２の全面に被着した後、ホトレジスト５５を選択
的に感光硬化させて未硬化部分を除去し、図５の（ｅ）
に示すように、下層の導体パターンとなる部分の上のみ
にホトレジスト５５を残す。次に、図５の（ｆ）に示す
ように、下部導体層５２をエッチングして下層の導体パ
ターン５６を形成した後、ホトレジスト５５を除去す
る。次に、図５の（ｇ）に示すように、下層の導体パタ
ーン５６を覆うように絶縁層５７を成膜形成し、続い
て、絶縁層５７の上に上部導体層を成膜した後、図５の
（ｈ）に示すように、ホトリソ技術により上層の導体パ
ターン５８を形成する。As shown in FIG. 5A, after a lower conductor layer 52 for forming a lower conductor pattern is formed on a substrate 51, a photoresist 5 is formed on the entire surface of the lower conductor layer 52.
3 and the photoresist 53 is selectively photosensitive-cured, and then the uncured portion is removed. As shown in FIG. 5B, at least a portion overlapping the upper conductor pattern when viewed from above. Lower conductor pattern (lower conductor layer 52)
A portion, that is, a portion of the lower conductor layer 52 which is likely to cause an interlayer short circuit failure in design is exposed. Next, as shown in FIG. 5C, an insulating oxide film 54 is formed on the exposed lower conductor layer 52 by using an anodic oxidation method, and then, as shown in FIG. As shown in FIG. 7, the photoresist 53 is removed. Next, after a photoresist 55 is applied again on the entire surface of the lower conductor layer 52, the photoresist 55 is selectively photosensitive-cured to remove the uncured portion, and FIG.
As shown in (5), the photoresist 55 is left only on the portion to be the lower conductive pattern. Next, as shown in FIG. 5F, the lower conductor layer 52 is etched to form a lower conductor pattern 56, and then the photoresist 55 is removed. Next, as shown in FIG. 5G, an insulating layer 57 is formed and formed so as to cover the lower conductive pattern 56, and then an upper conductive layer is formed on the insulating layer 57. As shown in FIG. 5H, an upper conductive pattern 58 is formed by photolithography.
【０００５】上記したような手法をとると、図５の
（ｇ）中に示すように、絶縁層（層間絶縁層）５７に欠
損欠陥（穴）５９が発生しても、上層の導体パターン５
８と重なる下層の導体パターン５６の部分には、予め酸
化皮膜５４が形成されているため、この酸化被膜５４が
絶縁を保つため、下層の導体パターン５６と上層の導体
パターン５８が短絡する層間短絡不良の発生を防止でき
る。According to the above-mentioned method, as shown in FIG. 5 (g), even if a defect defect (hole) 59 occurs in the insulating layer (interlayer insulating layer) 57, the upper conductive pattern 5
Since the oxide film 54 is formed in advance on the portion of the lower conductor pattern 56 that overlaps with the layer 8, the oxide film 54 maintains insulation, so that the lower conductor pattern 56 and the upper conductor pattern 58 are short-circuited. The occurrence of defects can be prevented.
【０００６】前記特開平１０−１３３２３１号公報にお
ける記載によれば、層間絶縁層５７は５００ｎｍ以下と
非常に薄い薄膜であり、また、下層の導体パターン５６
（下部導体層５２）の厚さも層間絶縁膜５７と同等の膜
厚のため、下層の導体パターン５６による段差部分で欠
損欠陥５９が発生する可能性があり、このような場合に
は、図５に示すような製造方法をとると、歩留まり確保
のために有効であるとしている。According to the description in Japanese Patent Application Laid-Open No. Hei 10-133231, the interlayer insulating layer 57 is a very thin thin film having a thickness of 500 nm or less.
Since the thickness of the (lower conductor layer 52) is also the same as that of the interlayer insulating film 57, there is a possibility that a defect 59 may occur at a stepped portion due to the lower conductor pattern 56. In such a case, FIG. It is stated that the following manufacturing method is effective for securing the yield.
【０００７】また、特開平４−１０２３９５号公報に
は、多層配線基板の形成に際し、絶縁層（層間絶縁層）
の形成を終えた後に、形状欠陥を光学的に検査し、見つ
けた欠陥を個別に補修するようにした技術が開示されて
いる。Japanese Patent Application Laid-Open No. 4-102395 discloses an insulating layer (interlayer insulating layer) for forming a multilayer wiring board.
There is disclosed a technique in which a shape defect is optically inspected after the formation of the defect, and the found defect is individually repaired.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上述し
た従来技術による手法は、各々以下のような欠点がある
ため、広く用いられるには至っていない。However, the above-mentioned prior art methods have not been widely used because of the following disadvantages.
【０００９】すなわち、特開平１０−１３３２３１号公
報に示された例では、まず、下層の導体パターンを構成
する材料が、陽極酸化により緻密な絶縁性酸化膜を形成
できる材料であることが必須である。実用的には、アル
ミ、タンタル、チタンの何れかを主成分とすることが必
須であり、より低抵抗且つ一般的な配線材料である銅は
適用できない。また、スルーホール部分は酸化膜が形成
されると導通がとれなくなるため、陽極酸化処理時には
少なくともスルーホール部分には酸化皮膜を形成しない
ような処置が必要となり、レジストのように後で除去で
きる絶縁性皮膜で、予め部分的に下部導体層を被覆した
後に、陽極酸化処理を行う必要がある。従って、少なく
とも酸化皮膜５４を形成するためにフォトリソグラフま
たは印刷等による絶縁性皮膜のパターン形成とその除去
が必要であるため、少なからず工程数が増加することに
なり、コストの大きな増加をもたらす。That is, in the example disclosed in Japanese Patent Application Laid-Open No. 10-133231, first, it is essential that the material constituting the lower conductive pattern is a material capable of forming a dense insulating oxide film by anodic oxidation. is there. Practically, it is essential that any one of aluminum, tantalum, and titanium be the main component, and copper, which has a lower resistance and is a general wiring material, cannot be applied. In addition, since the through-hole portion becomes incapable of conducting when an oxide film is formed, it is necessary to take measures to prevent the formation of an oxide film at least in the through-hole portion during the anodic oxidation treatment. After partially covering the lower conductor layer with a conductive film in advance, it is necessary to perform anodizing treatment. Therefore, it is necessary to form a pattern of the insulating film by photolithography or printing and remove it at least in order to form the oxide film 54, so that the number of steps increases to a considerable extent, resulting in a large increase in cost.
【００１０】また、特開平４−１０２３９５号公報に示
された例においては、層間絶縁層として用いられる材料
は、多くの場合に、可視光域またはその近傍の波長で透
明または半透明のため、欠陥を見つけにくい。従って、
小さな欠陥を見逃しやすいため、全ての欠陥を光学検査
によって検出するのは難しい。このような光学検査の欠
点を補うために、照明の方法や各種の画像処理を工夫し
た検査装置も存在するが、装置が高価である上に検査速
度が遅く、１枚の基板で検査に数１０分程度かかること
もある。従って、この方法は検出漏れの危険性がある
上、多額の設備投資が必要でありながら、スループット
が小さいと言う大きな問題点を抱えている。さらに、基
本的には絶縁層の形状の異常を検出して補修するため、
配線がない部分に発生した不良、つまり層間短絡不良と
はならない形状異常に関しても検出して補修することに
なり、無駄な時間と手間がかかってしまうことから、更
なるコストの増加要因を抱えている。In the example disclosed in Japanese Patent Application Laid-Open No. 4-102395, the material used as the interlayer insulating layer is often transparent or translucent in the visible light range or a wavelength in the vicinity thereof. Difficult to find defects. Therefore,
It is difficult to detect all defects by optical inspection because small defects are easily missed. In order to make up for the drawbacks of optical inspection, there are inspection devices that devised lighting methods and various types of image processing. However, these devices are expensive and the inspection speed is slow. It can take up to 10 minutes. Therefore, this method has a serious problem that the throughput is small while there is a risk of detection omission and a large capital investment is required. Furthermore, in order to basically detect and repair abnormalities in the shape of the insulating layer,
Detects and repairs defects that occur in areas where there is no wiring, that is, shape abnormalities that do not result in interlayer short-circuit defects, which wastes time and effort, and causes additional cost increase factors. I have.
【００１１】本発明は上記の点に鑑みなされたもので、
その目的とするところは、絶縁層の欠陥そのものを検査
することなく、層間短絡不良に至る欠陥を修復すること
を、低コストで実現可能とすることにある。[0011] The present invention has been made in view of the above points,
An object of the present invention is to make it possible to repair a defect leading to an interlayer short-circuit defect at a low cost without inspecting the defect itself of the insulating layer.
【００１２】[0012]
【課題を解決するための手段】本願発明者等は、絶縁層
の欠陥そのものを検査することなく、層間短絡不良に至
る欠陥を修復することを、低コストで実現可能とするた
めに、いくつかの方法を比較検討した。In order to make it possible to repair a defect leading to an interlayer short-circuit failure at a low cost without inspecting the defect itself of the insulating layer, the present inventors have made several studies. Method was compared and studied.
【００１３】まず、最も一般的な方法として、１層の絶
縁層の形成を、薄い層を複数回にわたって重ねて成膜す
ることで行い、薄い下層の膜欠陥を上に重ねる膜で覆う
ことを検討した。この方法は、多少の効果はあるもの
の、特に異物起因で形成される欠陥については、異物の
大きさおよび形状によっては下層の欠陥を上層の膜で常
に完全に被覆できるわけではなく、優れた欠陥防止法と
は言えない。さらに、この方法を改良し、薄い層を１層
成膜する毎に超音波洗浄を行い、下層の不良の原因とな
った異物を除去することでその上の層への影響を無くす
ことを試みたが、異物が下層の膜に埋め込まれてしっか
り付着しているため除去できなくなることが多く、殆ど
効果が無かった。First, as the most general method, a single insulating layer is formed by stacking thin layers a plurality of times, and covering a thin lower layer film defect with an upper layer. investigated. Although this method has some effects, particularly for defects formed due to foreign matter, depending on the size and shape of the foreign matter, the lower layer defect cannot always be completely covered with the upper layer film. It is not a prevention law. Furthermore, this method was improved, and ultrasonic cleaning was performed every time one thin layer was formed, and an attempt was made to eliminate the foreign matter that caused the failure of the lower layer to eliminate the influence on the layer above it. However, foreign substances were often embedded in the lower layer film and firmly adhered to the film, making it difficult to remove them.
【００１４】そこで、絶縁層形成手段の１つである陽極
化成法を参考にすることを考えた。陽極化成法による酸
化皮膜は、１μｍ以下の非常に薄い膜厚でも欠陥が少な
いことが知られているが、これは陽極化成法の本質的な
特性による。つまり、ＴａやＡｌのような金属膜表面に
おける酸化皮膜形成の過程において、酸化皮膜に欠陥
（欠損欠陥）が発生しても、欠陥部分は即ち電流が流れ
る部分であるために、他の部分では絶縁層が形成されて
電流が流れなくなるために酸化反応が止まっても、欠陥
部分は電流が流れる限り陽極化成による酸化反応は進行
し、欠陥部分に電流が流れなくなるまで反応が継続する
ためである。つまり、酸化皮膜形成と酸化皮膜の欠陥補
修を、同時且つ自己整合的に行っていることになる。従
って、絶縁耐圧の局所的ばらつきを別にすれば、原理的
には無欠陥の絶縁性皮膜が得られる。Therefore, it was considered to refer to the anodization method, which is one of means for forming an insulating layer. It is known that the oxide film formed by the anodization method has few defects even at a very thin film thickness of 1 μm or less, but this is due to the essential characteristics of the anodization method. In other words, in the process of forming an oxide film on the surface of a metal film such as Ta or Al, even if a defect (defective defect) occurs in the oxide film, the defective portion is a portion through which current flows. Even if the oxidation reaction stops because the insulating layer is formed and the current stops flowing, the oxidation reaction by anodization proceeds as long as the current flows in the defective portion, and the reaction continues until the current stops flowing in the defective portion. . That is, the formation of the oxide film and the repair of the oxide film are performed simultaneously and in a self-aligned manner. Therefore, except for the local variation of the dielectric strength, an insulating film having no defect can be obtained in principle.
【００１５】この陽極化成法のように、電気的に導通の
ある部分を自動的に絶縁化するような手法を、絶縁層そ
のものに対して実現できる方法を探索した。その結果、
絶縁性物質を溶液中で極性を持たせることにより溶液中
で電気的に移動させることができる電気泳動現象に着目
した。[0015] We have searched for a method that can realize a method of automatically insulating electrically conductive portions, such as the anodization method, for the insulating layer itself. as a result,
We focused on the electrophoresis phenomenon in which an insulating substance can be electrically moved in a solution by giving polarity in the solution.
【００１６】一般的には、鋼板の塗装において電気泳動
現象を利用した絶縁性皮膜の形成法を応用した電着法が
用いられており、自動車などの耐候性塗装として付き回
り性良く無欠陥の塗膜が得られる方法として、多くのメ
ーカーが採用している。但し、形成した塗膜は、そのま
まではある程度の電流が流れるぶよぶよの半絶縁状態の
膜であるため、化学的に安定化させて電気的絶縁性を確
保するために、焼き付けといわれる熱工程が必要とな
る。この工程では、不要な成分の分解脱離や残った成分
の架橋・重合等のために体積変化が生じるため、この段
階で僅かながら膜欠陥が発生する。このため、一般的に
は電着塗装と言えども吹き付け塗装等と組み合わせて用
いることが多く、下地塗装に電着膜、その上に吹き付け
塗装膜等を重ねて塗装することが一般的である。In general, in the coating of a steel sheet, an electrodeposition method applying a method of forming an insulating film utilizing an electrophoretic phenomenon is used. Many manufacturers have adopted a method for obtaining a coating film. However, since the formed coating is a semi-insulating film in which a certain amount of current flows as it is, a thermal process called baking is necessary to stabilize it chemically and ensure electrical insulation. Becomes In this step, a volume change occurs due to decomposition and desorption of unnecessary components and crosslinking / polymerization of remaining components, so that a slight film defect occurs at this stage. Therefore, in general, electrodeposition coating is often used in combination with spray coating or the like, and it is common to apply an electrodeposition film on a base coat and a spray coating film or the like on top of it.
【００１７】本発明では、電着膜と言えども広い面積に
形成した場合は上記のような現象により無欠陥化するこ
とが難しいことと、既存の電着できる材料の熱的特性、
機械的特性および電気的特性が、単独で多層配線基板の
層間絶縁層を形成するためには決して十分な特性ではな
いということを考慮した結果、層間絶縁層は従来の絶縁
膜を用い、絶縁層の欠陥部分に電着法を用いて絶縁性材
料を充填することを考案した。According to the present invention, when an electrodeposited film is formed over a large area, it is difficult to eliminate defects due to the above-mentioned phenomenon.
Taking into account that the mechanical and electrical characteristics are by no means sufficient to form an interlayer insulating layer of a multilayer wiring board by itself, the interlayer insulating layer uses a conventional insulating film, It has been devised to fill the defective portion with an insulating material by using an electrodeposition method.
【００１８】[0018]
【発明の実施の形態】図１は、本発明に基づく薄膜多層
配線基板の製造方法を示す工程説明図である。まず、本
発明の具体的な実施の形態の説明に先立ち、本発明の概
要を図１を用いて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a process explanatory view showing a method for manufacturing a thin-film multilayer wiring board according to the present invention. First, prior to description of a specific embodiment of the present invention, an outline of the present invention will be described with reference to FIG.
【００１９】まず、基板１上に、公知の薄膜形成技術を
用いて下部導体層（例えば、Ｃｕ等の低抵抗の金属）を
成膜した後、ホトリソ技術により下部導体層を所定形状
にパターニングして、図１の（ａ）に示すように、基板
１上に下層の導体パターン２を形成する。First, a lower conductor layer (for example, a low-resistance metal such as Cu) is formed on the substrate 1 by using a known thin film forming technique, and then the lower conductor layer is patterned into a predetermined shape by photolithography. Then, as shown in FIG. 1A, a lower conductive pattern 2 is formed on a substrate 1.
【００２０】次に、図１の（ｂ）に示すように、下層の
導体パターン２を形成した基板１上に、公知の薄膜形成
技術を用いて絶縁層（例えば、シリコン等の絶縁性無機
材料やポリイミド等の絶縁性樹脂）または誘電体を所定
厚みで成膜し（ここでは、絶縁層３を形成し）、これに
よって下層の導体パターン２上に絶縁層３を積層する。
この段階では、異物４の存在等によって欠損欠陥５があ
る確率で存在する。Next, as shown in FIG. 1B, an insulating layer (for example, an insulating inorganic material such as silicon) is formed on the substrate 1 on which the lower conductive pattern 2 is formed by using a known thin film forming technique. Or an insulating resin such as polyimide) or a dielectric with a predetermined thickness (here, the insulating layer 3 is formed), and thereby the insulating layer 3 is laminated on the lower conductive pattern 2.
At this stage, there is a probability that the defect 5 exists due to the presence of the foreign matter 4 or the like.
【００２１】そこで、次に図１の（ｃ）に示すように、
下層の導体パターン２を一方の電極とした電着法を用い
て、欠損欠陥５の部分に絶縁性物質６を電着する。電着
法では、電流が流れる部分（下部の導体パターン２が露
呈または露呈に近い状態の部位）にのみ絶縁性物質６が
付着するため、欠損欠陥５が無い部分は本来の絶縁層３
のままの状態が保たれる。Then, next, as shown in FIG.
An insulating material 6 is electrodeposited on the defect 5 using an electrodeposition method using the lower conductor pattern 2 as one electrode. In the electrodeposition method, since the insulating material 6 adheres only to a portion where a current flows (a portion where the lower conductive pattern 2 is exposed or nearly exposed), a portion having no defect 5 is replaced with the original insulating layer 3.
As it is.
【００２２】下層の導体パターン２に電流を流すため
に、図２に示すように、導体パターン２の配線エリアの
外側に導出された電流供給線２ａと、この電流供給線２
ａと連なり外部からの電流供給点となる接続端子部２ｂ
とを、導体パターン２と同時に予め形成しておき、接続
端子部２ｂは基板１の端部に位置づけておくようにされ
る。そして、接続端子部２ｂや電流供給線２ａの一部は
絶縁層３で覆わず露出させておき、電着工程の終了後
に、例えば、上層の導体パターンの形成工程において、
上部導体層のフォトエッチングを行う際に、同時に除去
してしまうようにされる。なお、個別の導体パターン２
から引き出された電流供給線２ａが電流供給点に至る前
に統合されて電流供給点における供給線の本数を減らす
ように構成されている場合には、電着工程の後の工程に
おいて、電流供給線２ａの統合された部分または電流供
給線２ａの全てが除去され、個別の導体パターンが電気
的に独立するようされる。なおまた、接続端子部２ｂや
電流供給線２ａは、導体パターンを２形成してある基板
１の裏面側に形成する構成であってもよい。As shown in FIG. 2, a current supply line 2a led out of the wiring area of the conductor pattern 2 and a current supply line 2
connection terminal portion 2b connected to a and serving as an external current supply point
Are formed beforehand at the same time as the conductor pattern 2, and the connection terminal portion 2 b is positioned at the end of the substrate 1. Then, the connection terminal portion 2b and a part of the current supply line 2a are exposed without being covered with the insulating layer 3, and after the electrodeposition step is completed, for example, in a step of forming an upper conductor pattern,
When the upper conductive layer is subjected to photoetching, it is removed at the same time. Note that individual conductor patterns 2
If the current supply lines 2a drawn out of the current supply point are integrated before reaching the current supply point to reduce the number of supply lines at the current supply point, the current supply line The integrated part of the line 2a or all of the current supply line 2a is removed, leaving the individual conductor patterns electrically independent. The connection terminal 2b and the current supply line 2a may be formed on the back surface of the substrate 1 on which the conductor pattern 2 is formed.
【００２３】ここで、電流供給線２ａは、配線レイアウ
トの都合上、全ての下層の導体パターン２に対して設け
ることができない場合もあるが、その場合でも、接地用
の導体パターン等のように面積の大きいパターンに対し
て優先的に電流供給線２ａを設けることで、層間短絡不
良を大幅に低減できる。Here, the current supply line 2a may not be provided for all the lower conductive patterns 2 due to the wiring layout. However, even in such a case, the current supply line 2a may be provided like a ground conductive pattern. By preferentially providing the current supply line 2a for a pattern having a large area, interlayer short-circuit defects can be significantly reduced.
【００２４】電着が終わった後に、熱処理を施すこと
で、付着した絶縁性物質６を緻密化すると同時に、下地
との密着性を高める。なお、電着で付着させた絶縁性物
質６は、次の工程での薄膜形成までの間、欠損欠陥５の
部分に付着していることを保証されればよいので、さほ
どの密着性は求められない。なおまた、この熱処理工程
の後に、ポリイミド等による絶縁層を成膜する工程を入
れてもよい。After the electrodeposition is completed, a heat treatment is performed to densify the attached insulating material 6 and at the same time to enhance the adhesion to the base. Note that the insulating material 6 deposited by electrodeposition only needs to be guaranteed to adhere to the defect defect 5 until the formation of a thin film in the next step. I can't. After the heat treatment step, a step of forming an insulating layer of polyimide or the like may be inserted.
【００２５】上記のようにして欠損欠陥５を補修した
後、公知の薄膜形成技術を用いて上部導体層を成膜した
後、ホトリソ技術により上部導体層（例えば、Ｃｕ等の
低抵抗の金属）を所定形状にパターニングして、図１の
（ｄ）に示すように、絶縁層３上に上層の導体パターン
７を形成する。After the defect 5 is repaired as described above, an upper conductor layer is formed by using a known thin film forming technique, and then the upper conductor layer (for example, a low-resistance metal such as Cu) is formed by photolithography. Is patterned into a predetermined shape to form an upper conductive pattern 7 on the insulating layer 3 as shown in FIG.
【００２６】本発明では、上述したように、下層の導体
パターン２を一方の電極とした電着法を用いて、欠損欠
陥５の部分に絶縁性物質６を電着するようにしている。
そこで、下層の導体パターン２が接地用の導体パターン
であり、上層の導体パターン７が電源用の導体パターン
であり、かつ、両者２、７間の絶縁層（層間絶縁層）３
の膜厚が非常に薄く、絶縁層３の欠損欠陥５が生じ易い
ような多層配線基板に適用すると、接地用の導体パター
ンと電源用の導体パターンとの間の層間短絡不良を略完
全に無くすことができ、効果的である。このような多層
配線基板は、高速クロックで動作するＭＰＵを搭載する
基板などが挙げられる。In the present invention, as described above, the insulating material 6 is electrodeposited on the defect 5 by using the electrodeposition method using the lower conductor pattern 2 as one electrode.
Therefore, the lower conductor pattern 2 is a conductor pattern for grounding, the upper conductor pattern 7 is a conductor pattern for power supply, and an insulating layer (interlayer insulating layer) 3 between the two 2 and 7 is provided.
When the present invention is applied to a multilayer wiring board having a very thin film thickness and easily causing a defect 5 in the insulating layer 3, an interlayer short circuit between the conductor pattern for grounding and the conductor pattern for power supply is almost completely eliminated. Can be effective. Examples of such a multilayer wiring board include a board on which an MPU operated by a high-speed clock is mounted.
【００２７】また、下層の導体パターンが一方の電極
（下部電極）で、上層の導体パターンが他方の電極（上
部電極）であり、この下部電極と上部電極との間に誘電
体層を形成する薄膜コンデンサの場合にも、本発明を適
用すると、層間短絡不良を略完全に無くすことができ
る。The lower conductor pattern is one electrode (lower electrode) and the upper conductor pattern is the other electrode (upper electrode), and a dielectric layer is formed between the lower electrode and the upper electrode. Even in the case of a thin film capacitor, when the present invention is applied, the interlayer short-circuit defect can be almost completely eliminated.
【００２８】図３は、薄膜多層配線基板としての薄膜コ
ンデンサへの適用例を示す製造工程の説明図である。図
３に示す製造工程は、図１と基本的に同様のものであ
り、図３の（ａ）に示すように、基板１上に下部電極と
しての下層の導体パターン２（例えば、ＰｔまたはＣｒ
／Ｃｕ／ＣｒまたはＣｕ／Ｎｉ等）が形成され、図３の
（ｂ）に示すように、この上に誘電体層８（例えば、Ｓ
ＴＯ（ストロンチウムとチタンの複合酸化物）またはＢ
ＳＴ（バリウムとストロンチウムとチタンの複合酸化
物）等）が公知の薄膜形成技術により成膜された後、図
３の（ｃ）に示すように、電着法により欠損欠陥５に絶
縁性物質６が付着され、然る後、図３の（ｄ）に示すよ
うに、上部電極としての上層の導体パターン７（例え
ば、ＰｔまたはＣｒ／Ｃｕ／ＣｒまたはＣｕ／Ｎｉ）等
が形成される。FIG. 3 is an explanatory view of a manufacturing process showing an example of application to a thin film capacitor as a thin film multilayer wiring board. The manufacturing process shown in FIG. 3 is basically the same as that shown in FIG. 1, and as shown in FIG. 3A, a lower conductive pattern 2 (for example, Pt or Cr) is formed on a substrate 1 as a lower electrode.
/ Cu / Cr or Cu / Ni, etc.) and a dielectric layer 8 (for example, S
TO (composite oxide of strontium and titanium) or B
ST (composite oxide of barium, strontium and titanium) or the like is formed by a known thin film forming technique, and then, as shown in FIG. Then, as shown in FIG. 3D, an upper conductive pattern 7 (for example, Pt or Cr / Cu / Cr or Cu / Ni) or the like is formed as an upper electrode.
【００２９】＜第１実施形態＞図４は、絶縁性物質６と
して、無機物の微粉末を電着する１つの例としての、ア
ルミナの微粉末を電着する際に用いる装置の概略と、こ
の際に用いる電着液の組成の例とを、示したものであ
る。図４において、４１は電着用の漕、４２は電着液、
４３は電極板、４４は基板保持手段、４５は直流電源、
４６はポンプ等の撹拌手段である。<First Embodiment> FIG. 4 shows an outline of an apparatus used for electrodepositing fine alumina powder as one example of electrodepositing inorganic fine powder as the insulating material 6, and FIG. And an example of the composition of the electrodeposition liquid used in this case. In FIG. 4, reference numeral 41 denotes a tank for electrodeposition, 42 denotes an electrodeposition liquid,
43 is an electrode plate, 44 is a substrate holding means, 45 is a DC power supply,
46 is a stirring means such as a pump.
【００３０】基本的には、基板１に形成した下層の導電
パターン２が一方の電極となるように、基板保持手段４
４に保持された基板１に直流電源の一方の極を接続した
状態で、基板１を漕４１の電着液４２中に浸漬させ、基
板１を極性の異なる電極板４３と対向させる。電着液４
２に懸濁するアルミナの微粉末は、できるだけ細かい方
が付着性および膜の緻密性の点で良好であり、粒径１μ
ｍ以下の粉末が望ましい。上記アルミナ粉末を懸濁した
電着液４２は、アルミナ粉末が沈殿しやすいので、常に
ポンプ等の撹拌手段４６により撹拌することが必要であ
るが、基板１に対して強い流れが当たると粒子の付着性
に影響を及ぼすため、撹拌は沈殿を防げる範囲で、でき
るだけ弱いことが望ましい。Basically, the substrate holding means 4 is provided so that the lower conductive pattern 2 formed on the substrate 1 becomes one electrode.
The substrate 1 is immersed in the electrodeposition liquid 42 of the tank 41 in a state where one pole of the DC power supply is connected to the substrate 1 held by the substrate 4, and the substrate 1 is opposed to the electrode plate 43 having a different polarity. Electrodeposition liquid 4
The fine powder of alumina suspended in 2 is better in terms of adhesion and film density if it is as fine as possible.
m or less is desirable. The electrodeposition liquid 42 in which the alumina powder is suspended must be constantly stirred by the stirring means 46 such as a pump, because the alumina powder is likely to precipitate. In order to affect the adhesion, it is desirable that the stirring is as weak as possible as long as precipitation can be prevented.
【００３１】アルミナの場合、付着する膜は条件によっ
ては数ｍｍの厚さにすることもできるが、本特許の目的
に対しては数μｍの厚さで十分であり、厚過ぎると上部
導体層の形成に支障を来たすため、電着の時間を厳密に
制御する必要がある。１例として、例えば、図４中に示
した組成の電着液４２を用いて、電圧１２０Ｖ、電流密
度０．３ｍＡ／ｃｍ２で、１５分間の電着により、厚さ
５ｍｍの膜を得ることができる。この場合は、約２秒で
１０μｍの膜が付着していることになるが、電着の速度
がかなり早いために、電圧を約半分に下げることで同時
に電流密度もほぼ半分に下げることができ、そのときの
成膜速度は、約１０秒で１０μｍであった。この他に
も、液組成を変えて液の電気電導度を下げても、付着速
度を下げることが可能であった。また、アルミナ粉末を
懸濁する量を減らしても同様の効果がある。なお、電着
においては、１０〜２００Ｖのバイアス電圧範囲が良好
な条件であった。In the case of alumina, the thickness of the deposited film can be several mm depending on the conditions, but a thickness of several μm is sufficient for the purpose of the present patent. It is necessary to strictly control the time of electrodeposition in order to hinder the formation of the electrodeposition. As an example, a film having a thickness of 5 mm is obtained by electrodeposition at a voltage of 120 V and a current density of 0.3 mA / cm 2 for 15 minutes using, for example, the electrodeposition solution 42 having the composition shown in FIG. Can be. In this case, a film of 10 μm is deposited in about 2 seconds. However, since the electrodeposition speed is very high, the current density can be reduced to almost half by reducing the voltage to about half at the same time. The film forming speed at that time was 10 μm in about 10 seconds. In addition to this, even when the liquid composition was changed to lower the electric conductivity of the liquid, the deposition rate could be reduced. The same effect can be obtained even if the amount of the alumina powder suspended is reduced. In the electrodeposition, a favorable bias voltage range of 10 to 200 V was a good condition.
【００３２】無機物を電着した場合、無機物の微粒子を
完全に焼結するためには１０００℃を超える焼結温度が
必要となり、アルミナの場合はこれが特に高く、１５０
０℃程度が望ましい温度ではあるが、多層配線基板にお
いてはそのような温度による焼結は、絶縁層３（または
誘電体層８）および下層の導体パターン２を破壊するこ
とになるため、完全な焼結はできないことになる。ただ
し、本発明の目的である欠損欠陥部分の絶縁化という意
味では、付着した粒子が完全に一体化する必要は無く、
微粒子が後の処理で剥がれない程度に欠損欠陥部分に付
着しているだけでも良いと考えることができる。従っ
て、最低限必要な熱処理としては、水分および有機物を
飛ばすために、１００℃以上の温度で加熱することが必
要であり、例えば、２００〜３００℃の温度範囲で加熱
することが望ましい。When an inorganic material is electrodeposited, a sintering temperature exceeding 1000 ° C. is required in order to completely sinter the inorganic fine particles.
Although about 0 ° C. is a desirable temperature, in the case of a multilayer wiring board, sintering at such a temperature destroys the insulating layer 3 (or the dielectric layer 8) and the lower conductive pattern 2, so that complete sintering is not possible. Sintering will not be possible. However, it is not necessary to completely integrate the adhered particles in the sense of insulating the defect defect portion, which is the object of the present invention,
It can be considered that the fine particles may only be attached to the defective defect portion to such an extent that they do not peel off in the subsequent processing. Therefore, as a minimum required heat treatment, it is necessary to heat at a temperature of 100 ° C. or more in order to remove moisture and organic substances, and for example, it is desirable to heat in a temperature range of 200 to 300 ° C.
【００３３】なお、ここでは無機物の例としてアルミナ
を示したが、これ以外にも、二酸化珪素、窒化珪素、ガ
ラス等の無機物の微粉末であっても、あるいは、複数種
の絶縁性の無機物の混合微粉末であってもよい。Although alumina is shown here as an example of the inorganic substance, other than this, fine powder of an inorganic substance such as silicon dioxide, silicon nitride, glass or the like, or plural kinds of insulating inorganic substances may be used. It may be a mixed fine powder.
【００３４】＜第２実施形態＞近年、電着可能なポリイ
ミド系材料が開発されたため、これを用いて第１実施形
態と同様に、基板１上に電着を行った。その結果、電着
時に基板１にかけるバイアス電圧が１０Ｖを下回ると、
下地金属との接着性が極端に低下し、ポリイミドが付着
するものの、その後の処理中に付着したポリイミドが脱
落してしまうことが判った。また、電着時にバイアス電
圧をあまり上げすぎると、電着中に欠損欠陥部分で絶縁
破壊を生じ、かえって欠陥を大きくしてしまうことがあ
った。これらのことから、電着においては１０〜２００
Ｖのバイアス電圧範囲が良好な条件であった。付着した
ポリイミドは、２００〜２５０℃で３０分程度加熱する
ことで、一体化し絶縁膜として（２００〜２５０℃の耐
熱性をもつ絶縁層として）とり扱えるようになり、その
後に上層のポリイミド層を積層しても異常は生じなかっ
た。<Second Embodiment> In recent years, an electrodepositable polyimide-based material has been developed. Using this, an electrodeposition is performed on the substrate 1 as in the first embodiment. As a result, when the bias voltage applied to the substrate 1 during electrodeposition falls below 10 V,
It was found that the adhesion to the underlying metal was extremely reduced, and the polyimide adhered, but the polyimide adhered during the subsequent treatment was dropped. Also, if the bias voltage is too high during electrodeposition, dielectric breakdown may occur at a defective defect portion during electrodeposition, resulting in a larger defect. From these, in electrodeposition, 10 to 200
The bias voltage range of V was favorable. By heating the adhered polyimide at 200 to 250 ° C. for about 30 minutes, it can be integrated and handled as an insulating film (as an insulating layer having heat resistance of 200 to 250 ° C.). No abnormality occurred even after lamination.
【００３５】なお、ポリイミド系材料を用いた電着液
は、ブロック共重合によりポリイミド分子とされた状態
の材料を溶媒中に溶かし、極性を与えるための適宜の添
加物を付加したものが、用いられる。The electrodeposition solution using a polyimide-based material is obtained by dissolving a material in a state of being made into polyimide molecules by block copolymerization in a solvent and adding an appropriate additive for imparting polarity. Can be
【００３６】＜第３実施形態＞電着できる絶縁性材料と
して、電着レジストとして広く用いられるエポキシ系の
材料を用いて、第１実施形態と同様に、基板１上に電着
を行った。その結果、穴を埋め込むということでは、上
記ポリイミド系材料と同等であり、さらに、下地との接
着力は非常に良好であったが、これを加熱硬化させた後
に上層の絶縁層としてポリイミド層を形成したところ、
エポキシ系材料が熱分解を起こして上層の絶縁層が膨れ
る欠陥が発生した。そこで、エポキシ系材料を電着した
後、純粋な窒素雰囲気中あるいは真空中で１５０℃以上
に加熱することで、エポキシ材料を炭化させ、熱的に安
定化することを試みた。この処理を行った後に上層の絶
縁層としてポリイミド層を形成したところ、膨れを起こ
さずに絶縁層を積層することができた。<Third Embodiment> An epoxy material widely used as an electrodeposition resist was used as an insulating material that can be electrodeposited, and electrodeposition was performed on the substrate 1 as in the first embodiment. As a result, the fact that the holes were buried was equivalent to the above-mentioned polyimide-based material, and furthermore, the adhesive force with the base was very good. When formed,
The epoxy-based material was thermally decomposed, causing a defect that the upper insulating layer swelled. Then, after electrodeposition of the epoxy-based material, an attempt was made to carbonize the epoxy material and thermally stabilize it by heating it to 150 ° C. or more in a pure nitrogen atmosphere or vacuum. After performing this treatment, when a polyimide layer was formed as an upper insulating layer, the insulating layer could be laminated without causing swelling.
【００３７】なお、エポキシ系材料を用いた電着液も、
エポキシ分子とされた状態の材料を溶媒中に溶かし、極
性を与えるための適宜の添加物を付加したものが、用い
られる。また、電着においては１０〜２００Ｖのバイア
ス電圧範囲が良好な条件であった。An electrodeposition solution using an epoxy material is also used.
A material obtained by dissolving a material in an epoxy molecule state in a solvent and adding an appropriate additive for imparting polarity is used. In the electrodeposition, a bias voltage range of 10 to 200 V was a good condition.
【００３８】以上に記述した手法を用いて作製された本
発明による多層配線基板は、パソコン、サーバー、通信
機器等の各種電子機器に内蔵され、その適用範囲は多岐
であることは、言うまでもない。The multilayer wiring board according to the present invention manufactured by using the above-described method is built in various electronic devices such as a personal computer, a server, and a communication device, and it is needless to say that the applicable range is wide.
【００３９】[0039]
【発明の効果】以上のように本発明によれば、電着法と
いう簡単な処理により、欠損欠陥の形状、数等にかかわ
らず層間短絡不良を自動的に補修できるため、高密度な
多層配線を、高い歩留まりで形成することが可能にな
る。特に、グランド層および電源層のように、導体パタ
ーンの面積が広く、層間短絡不良が発生しやすい部分に
対しては、歩留まり確保の点で非常に有効である。ま
た、このような特性のため、回路基板の電気特性として
非常に薄い絶縁層が必要な場合でも、低コストで層間短
絡不良の発生を可及的に防止できる。さらに、本発明は
層間絶縁層に代替して誘電体を用いた場合にも適用でき
ることから、非常に薄い誘電体層を有する高容量のコン
デンサを、高歩留まりで製造することも可能となる。As described above, according to the present invention, an interlayer short-circuit defect can be automatically repaired irrespective of the shape and number of defective defects by a simple process called an electrodeposition method. Can be formed with a high yield. In particular, for a portion such as a ground layer and a power supply layer where the conductor pattern has a large area and an interlayer short-circuit defect is likely to occur, it is very effective in securing the yield. In addition, due to such characteristics, even when an extremely thin insulating layer is required as an electrical characteristic of the circuit board, occurrence of interlayer short-circuit failure can be prevented as much as possible at low cost. Further, since the present invention can be applied to a case where a dielectric is used instead of an interlayer insulating layer, a high-capacity capacitor having a very thin dielectric layer can be manufactured with a high yield.
【図１】本発明による薄膜多層配線基板の製造方法の概
要の１例を示す工程説明図である。FIG. 1 is a process explanatory view showing one example of an outline of a method for manufacturing a thin-film multilayer wiring board according to the present invention.
【図２】基板上の下層の導電パターンと、電着のための
電流供給線、接続端子部とを示す説明図である。FIG. 2 is an explanatory view showing a lower conductive pattern on a substrate, a current supply line for electrodeposition, and a connection terminal portion.
【図３】本発明による薄膜多層配線基板の製造方法の概
要の他の１例を示す工程説明図である。FIG. 3 is a process explanatory view showing another example of the outline of the method for manufacturing a thin-film multilayer wiring board according to the present invention.
【図４】電着を行うための装置の１例の概略と、電着液
の組成の１例とを示す説明図である。FIG. 4 is an explanatory diagram showing an outline of an example of an apparatus for performing electrodeposition and an example of a composition of an electrodeposition liquid.
【図５】従来技術による多層配線基板の製造方法の概要
を示す工程説明図である。FIG. 5 is a process explanatory view showing an outline of a method for manufacturing a multilayer wiring board according to a conventional technique.
１ 基板 ２ 下層の導体パターン ２ａ 電流供給線 ２ｂ 接続端子部 ３ 絶縁層 ４ 異物 ５ 欠損欠陥 ６ 電着により付着された絶縁性物質 ７ 上層の導体パターン ８ 誘電体層 DESCRIPTION OF SYMBOLS 1 Substrate 2 Lower conductor pattern 2a Current supply line 2b Connection terminal part 3 Insulating layer 4 Foreign material 5 Defect defect 6 Insulating substance adhered by electrodeposition 7 Upper conductor pattern 8 Dielectric layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/22 Ｈ０５Ｋ 3/22 Ｚ (72)発明者 松山 治彦 神奈川県秦野市堀山下１番地 株式会社日 立製作所エンタープライズサーバ事業部内 (72)発明者 香月 真理亜 神奈川県秦野市堀山下１番地 株式会社日 立製作所エンタープライズサーバ事業部内 (72)発明者 鶴子 昌宣 神奈川県秦野市堀山下１番地 株式会社日 立製作所エンタープライズサーバ事業部内 Ｆターム(参考） 5E343 AA02 AA11 BB21 BB61 BB62 EE60 ER21 ER25 ER60 GG14 5E346 AA02 AA12 AA13 AA15 AA32 AA33 AA38 BB01 BB20 CC09 CC16 CC31 DD01 DD11 EE31 EE39 FF45 GG01 GG36 HH08──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/22 H05K 3/22 Z (72) Inventor Haruhiko Matsuyama 1st Horiyamashita, Hadano-shi, Kanagawa Japan (72) Inventor Mari Server Kazuki Maria 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Incorporated Company Enterprise Server Division (72) Inventor Masanori Tsuruko 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Hitachi, Ltd. F-term in the Enterprise Server Division of the Works (reference)
Claims (15)
絶縁層または誘電体層を積層し、この絶縁層または誘電
体上に上層の導電パターンを積層してなる多層配線基板
において、 絶縁層または誘電体層の形成後に、下層の導体パターン
上の絶縁層または誘電体層の欠損部分に、下層の導体パ
ターンを一方の電極とした電着法を用いて、電気的に絶
縁性の物質を付着させることを特徴とする多層配線基板
の層間短絡防止方法。At least on a lower conductive pattern,
In a multilayer wiring board having an insulating layer or a dielectric layer laminated and an upper conductive pattern laminated on the insulating layer or the dielectric, after forming the insulating layer or the dielectric layer, the insulating layer on the lower conductive pattern is formed. Alternatively, a method for preventing an interlayer short circuit in a multilayer wiring board, wherein an electrically insulating substance is attached to a defective portion of a dielectric layer using an electrodeposition method using a lower conductive pattern as one electrode.
の導体パターンと、これと対向する他方の電極との間に
かける電圧を、１０Ｖ以上且つ２００Ｖ以下の範囲とす
ることを特徴とする多層配線基板の層間短絡防止方法。2. The method according to claim 1, wherein the condition for performing the electrodeposition is that a voltage applied between the lower conductive pattern to be one electrode and the other electrode facing the lower electrode is 10 V or more and 200 V or more. A method for preventing an interlayer short-circuit in a multilayer wiring board, wherein the method has the following range.
せる前記絶縁性の物質が、２００℃以上の耐熱性を有す
る樹脂であることを特徴とする多層配線基板の層間短絡
防止方法。3. The insulating material according to claim 1, wherein the insulating substance attached to the defective portion of the insulating layer or the dielectric layer is a resin having a heat resistance of 200 ° C. or higher. To prevent short circuit between layers of a multilayer wiring board.
せる前記絶縁性の物質が、エポキシ系の樹脂であること
を特徴とする多層配線基板の層間短絡防止方法。4. The multilayer wiring board according to claim 1, wherein the insulating material to be attached to the defective portion of the insulating layer or the dielectric layer is an epoxy resin. Interlayer short circuit prevention method.
たは真空中で１５０℃以上に加熱することを特徴とする
多層配線基板の層間短絡防止方法。5. The method according to claim 4, wherein the epoxy resin is heated to 150 ° C. or more in a non-oxidizing atmosphere or in a vacuum after the electrodeposition of the epoxy resin.
せる前記絶縁性の物質が、アルミナ、二酸化珪素、窒化
珪素、ガラス等の無機物の微粉末あるいは複数種の絶縁
性の無機物の混合微粉末であることを特徴とする多層配
線基板の層間短絡防止方法。6. The fine powder of an inorganic substance, such as alumina, silicon dioxide, silicon nitride, or glass, according to claim 1, wherein the insulating substance to be attached to the defective portion of the insulating layer or the dielectric layer is Alternatively, a method for preventing interlayer short-circuit of a multilayer wiring board, wherein the method is a mixed fine powder of a plurality of kinds of insulating inorganic substances.
いて、 前記下層の導体パターンに対して外部から電流を供給で
きるように、導体パターンから配線エリアの外または導
体パターンを形成してある基板の裏面に電流供給線を導
出したことを特徴とする多層配線基板の層間短絡防止方
法。7. The conductive pattern according to claim 1, wherein a conductive pattern is formed outside the wiring area or the conductive pattern so that a current can be supplied to the lower conductive pattern from the outside. A method for preventing an interlayer short circuit in a multilayer wiring board, wherein a current supply line is led out to a back surface of a certain board.
電流供給点に至る前に統合されて電流供給点における供
給線の本数を減らすように構成され、電着工程の後の工
程において前記電流供給線の統合された部分または全て
が除去され、導体パターンが電気的に独立するようされ
ることを特徴とする多層配線基板の層間短絡防止方法。8. The current supply line according to claim 7, wherein the current supply lines drawn from the individual conductor patterns are integrated before reaching a current supply point to reduce the number of supply lines at the current supply point. A method for preventing an interlayer short-circuit in a multilayer wiring board, wherein in a step after the attaching step, an integrated part or all of the current supply line is removed, and the conductor pattern is made electrically independent.
絶縁層または誘電体層を積層し、この絶縁層または誘電
体層上に上層の導体パターンを積層してなる多層配線基
板において、 前記下層の導体パターン上に形成された前記絶縁層また
は前記誘電体層における欠損部分を、下層の導体パター
ンを一方の電極とする電着法により付着された電気的に
絶縁性の物質によって被覆したことを特徴とする多層配
線基板。9. At least on a lower conductive pattern,
In a multilayer wiring board formed by laminating an insulating layer or a dielectric layer and laminating an upper conductive pattern on the insulating layer or the dielectric layer, the insulating layer or the dielectric formed on the lower conductive pattern A multilayer wiring board wherein a defective portion in a layer is covered with an electrically insulating substance attached by an electrodeposition method using a lower conductor pattern as one electrode.
せる前記絶縁性の物質が、アルミナ、二酸化珪素、窒化
珪素、ガラス等の無機物の微粉末あるいは複数種の絶縁
性の無機物の混合微粉末、または、ポリイミド系の樹
脂、または、エポキシ系の樹脂であることを特徴とする
多層配線基板。10. The method according to claim 9, wherein the insulating substance to be attached to the defective portion of the insulating layer or the dielectric layer is a fine powder or a plurality of inorganic substances such as alumina, silicon dioxide, silicon nitride, and glass. A multilayer wiring board comprising a mixed fine powder of a kind of insulating inorganic substance, a polyimide resin, or an epoxy resin.
方は、接地用の導体パターンであり、他方は、電源用の
導体パターンであることを特徴とする多層配線基板。11. The multilayer wiring according to claim 9, wherein one of the lower conductor pattern and the upper conductor pattern is a conductor pattern for grounding, and the other is a conductor pattern for power supply. substrate.
に、絶縁層または誘電体層を積層し、この絶縁層または
誘電体層上に上層の導体パターンを積層してなる多層配
線基板の製造方法において（ａ）基板上に前記下層の導
体パターンを形成する工程と、（ｂ）前記下層の導体パ
ターン上に前記絶縁層または前記誘電体層を形成する工
程と、（ｃ）前記下層の導体パターンを一方の電極とす
る電着法により、前記絶縁層または前記誘電体層の欠損
部分に、電気的に絶縁性の物質を付着させる工程と、
（ｄ）前記絶縁層または前記誘電体層上に前記上層の導
体パターンを形成する工程とを、備えたことを特徴とす
る多層配線基板の製造方法。12. A method for manufacturing a multilayer wiring board, comprising: laminating an insulating layer or a dielectric layer on at least a lower conductor pattern and laminating an upper conductor pattern on the insulating layer or the dielectric layer. a) forming the lower conductive pattern on a substrate, (b) forming the insulating layer or the dielectric layer on the lower conductive pattern, and (c) forming the lower conductive pattern on one side. A step of attaching an electrically insulating substance to the insulating layer or the defective portion of the dielectric layer by electrodeposition as an electrode,
(D) forming the conductive pattern of the upper layer on the insulating layer or the dielectric layer.
せる前記絶縁性の物質が、アルミナ、二酸化珪素、窒化
珪素、ガラス等の無機物の微粉末あるいは複数種の絶縁
性の無機物の混合微粉末、または、ポリイミド系の樹
脂、または、エポキシ系の樹脂であることを特徴とする
多層配線基板の製造方法。13. The method according to claim 12, wherein the insulating substance to be attached to the defective portion of the insulating layer or the dielectric layer is a fine powder or a plurality of inorganic substances such as alumina, silicon dioxide, silicon nitride, and glass. What is claimed is: 1. A method for manufacturing a multilayer wiring board, comprising a mixed fine powder of a kind of insulating inorganic material, a polyimide resin, or an epoxy resin.
縁性の物質を付着させた後、加熱処理を施すことを特徴
とする多層配線基板の製造方法。14. The method for manufacturing a multilayer wiring board according to claim 12, wherein a heat treatment is performed after attaching the insulating material to the defective portion of the insulating layer or the dielectric layer. .
層間短絡防止方法を用いた多層配線基板、または、請求
項９乃至１１の何れか１つに記載の多層配線基板、また
は、請求項１２乃至１４の何れか１つに記載の製造方法
を用いた多層配線基板を搭載してなることを特徴とする
電子機器。15. A multilayer wiring board using the interlayer short-circuit preventing method according to any one of claims 1 to 8, or a multilayer wiring board according to any one of claims 9 to 11, or An electronic device comprising a multilayer wiring board using the manufacturing method according to claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000376082A JP2002185148A (en) | 2000-12-11 | 2000-12-11 | Multilayer wiring board, interlayer short circuit preventing method thereof multilayer wiring board, method of manufacturing the same, and electronic apparatus using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000376082A JP2002185148A (en) | 2000-12-11 | 2000-12-11 | Multilayer wiring board, interlayer short circuit preventing method thereof multilayer wiring board, method of manufacturing the same, and electronic apparatus using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002185148A true JP2002185148A (en) | 2002-06-28 |
Family
ID=18844997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000376082A Pending JP2002185148A (en) | 2000-12-11 | 2000-12-11 | Multilayer wiring board, interlayer short circuit preventing method thereof multilayer wiring board, method of manufacturing the same, and electronic apparatus using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002185148A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004296952A (en) * | 2003-03-28 | 2004-10-21 | Tdk Corp | Electronic component and its outer layer forming method |
| JP2007189199A (en) * | 2005-12-12 | 2007-07-26 | Tdk Corp | Capacitor and method of manufacturing same |
| JP2008160040A (en) * | 2006-12-26 | 2008-07-10 | Tdk Corp | Manufacturing method of capacitor |
| JP2009194146A (en) * | 2008-02-14 | 2009-08-27 | Ngk Insulators Ltd | Piezoelectric/electrostrictive element and its manufacturing method |
| WO2013005468A1 (en) * | 2011-07-05 | 2013-01-10 | 株式会社村田製作所 | Dielectric thin film, dielectric thin film element, and thin film capacitor |
| JP2013042181A (en) * | 2005-12-12 | 2013-02-28 | Tdk Corp | Method of manufacturing a capacitor |
| JP2016082032A (en) * | 2014-10-15 | 2016-05-16 | Tdk株式会社 | Thin film capacitor |
| US9564270B2 (en) | 2013-12-27 | 2017-02-07 | Tdk Corporation | Thin film capacitor |
| US9620291B2 (en) | 2014-07-16 | 2017-04-11 | Tdk Corporation | Thin film capacitor |
| US10014113B2 (en) | 2015-10-15 | 2018-07-03 | Tdk Corporation | Electronic device sheet having insulation patch member on dielectric layer |
-
2000
- 2000-12-11 JP JP2000376082A patent/JP2002185148A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004296952A (en) * | 2003-03-28 | 2004-10-21 | Tdk Corp | Electronic component and its outer layer forming method |
| JP2013042181A (en) * | 2005-12-12 | 2013-02-28 | Tdk Corp | Method of manufacturing a capacitor |
| JP2007189199A (en) * | 2005-12-12 | 2007-07-26 | Tdk Corp | Capacitor and method of manufacturing same |
| JP2013062531A (en) * | 2005-12-12 | 2013-04-04 | Tdk Corp | Capacitor and manufacturing method of the same |
| JP2008160040A (en) * | 2006-12-26 | 2008-07-10 | Tdk Corp | Manufacturing method of capacitor |
| JP2009194146A (en) * | 2008-02-14 | 2009-08-27 | Ngk Insulators Ltd | Piezoelectric/electrostrictive element and its manufacturing method |
| WO2013005468A1 (en) * | 2011-07-05 | 2013-01-10 | 株式会社村田製作所 | Dielectric thin film, dielectric thin film element, and thin film capacitor |
| JP5531163B2 (en) * | 2011-07-05 | 2014-06-25 | 株式会社村田製作所 | Dielectric thin film, dielectric thin film element, and thin film capacitor |
| US9324497B2 (en) | 2011-07-05 | 2016-04-26 | Murata Manufacturing Co., Ltd. | Dielectric thin film, dielectric thin film element and thin film capacitor |
| US9564270B2 (en) | 2013-12-27 | 2017-02-07 | Tdk Corporation | Thin film capacitor |
| US9620291B2 (en) | 2014-07-16 | 2017-04-11 | Tdk Corporation | Thin film capacitor |
| JP2016082032A (en) * | 2014-10-15 | 2016-05-16 | Tdk株式会社 | Thin film capacitor |
| US9818539B2 (en) | 2014-10-15 | 2017-11-14 | Tdk Corporation | Thin film capacitor with improved resistance to dielectric breakdown |
| US10014113B2 (en) | 2015-10-15 | 2018-07-03 | Tdk Corporation | Electronic device sheet having insulation patch member on dielectric layer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7138294B2 (en) | Circuit substrate device, method for producing the same, semiconductor device and method for producing the same | |
| KR100834515B1 (en) | Method for forming photoresist-laminated substrate, method for plating insulating substrate, method for surface treating metal layer of circuit board, and method for manufacturing multi layer ceramic condenser using metal nanoparticles aerosol | |
| CN100499053C (en) | Power semiconductor wiring technology for electric insulation material layer that follows the surface contours | |
| JP4868234B2 (en) | Capacitor manufacturing method | |
| JP2004311912A (en) | Circuit board module and its manufacturing method | |
| CN101658079A (en) | Multilayer printed wiring board and method for manufacturing the same | |
| JP2002185148A (en) | Multilayer wiring board, interlayer short circuit preventing method thereof multilayer wiring board, method of manufacturing the same, and electronic apparatus using the same | |
| US8327534B2 (en) | Method of fabricating printed circuit board assembly | |
| TW201106824A (en) | Printed wiring substrate and producing method thereof | |
| TW563142B (en) | Thin film capacitor, and electronic circuit component | |
| US6632343B1 (en) | Method and apparatus for electrolytic plating of surface metals | |
| TW200930169A (en) | Flexible film and display device comprising the same | |
| US5393406A (en) | Method of producing a thin film multilayer wiring board | |
| JP2009272437A (en) | Laminated structure, semiconductor device, laminated structure manufacturing method, and semiconductor device manufacturing method | |
| US7799370B2 (en) | Method of forming through hole and method of manufacturing electronic circuit | |
| EP4319512A1 (en) | Wiring board manufacturing method and wiring board | |
| CN100468670C (en) | Internal connection system for power semiconductors comprising large-area terminals | |
| KR20090048358A (en) | Wiring board, circuit board, and method for manufacturing thereof | |
| WO2006008736A1 (en) | Fabrication of electrical components and circuits by selective electrophoretic deposition (s-epd) and transfer | |
| JP5846594B1 (en) | Wiring formation method | |
| CN110739289B (en) | Substrate structure and manufacturing method thereof | |
| WO2002098193A1 (en) | A method for applying thick copper on substrates | |
| JP3562166B2 (en) | Method of forming printed circuit board having inspection electrode | |
| JP2003243799A (en) | Method of manufacturing flexible board | |
| JPH11102937A (en) | Double-side wiring tab tape |