JP2002184830A - Method of detecting defect in insulating film and device thereof - Google Patents
Method of detecting defect in insulating film and device thereofInfo
- Publication number
- JP2002184830A JP2002184830A JP2000381650A JP2000381650A JP2002184830A JP 2002184830 A JP2002184830 A JP 2002184830A JP 2000381650 A JP2000381650 A JP 2000381650A JP 2000381650 A JP2000381650 A JP 2000381650A JP 2002184830 A JP2002184830 A JP 2002184830A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- defect
- substrate
- film
- detecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、絶縁膜中の微小欠
陥を検出する技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for detecting minute defects in an insulating film.
【０００２】[0002]
【従来の技術】（１）ＬＳＩの高集積化に伴い、ゲート
絶縁膜やＤＲＡＭ、フラシュメモリのキャパシタ絶縁膜
の薄膜化が進んでいる。それに伴い、絶縁膜中の欠陥に
よる信頼性低下が問題となっている。2. Description of the Related Art (1) With the increasing integration of LSIs, gate insulating films and capacitor insulating films of DRAMs and flash memories have been reduced in thickness. Along with this, there has been a problem that reliability is reduced due to defects in the insulating film.
【０００３】絶縁膜欠陥評価は、一般的に金属（Ｍ）―
絶縁膜（Ｉ）―半導体（Ｓ）構造でキャパシタの電気特
性を測定する方法がある。この方法は、測定感度が高
く、最も信頼性が高い欠陥検出手法であるが、欠陥箇所
の特定が困難であった。[0003] Insulation film defect evaluation is generally performed using metal (M)-
There is a method of measuring the electrical characteristics of a capacitor with an insulating film (I) -semiconductor (S) structure. This method has a high measurement sensitivity and is the most reliable defect detection method, but it has been difficult to identify a defective portion.
【０００４】そこで絶縁膜の欠陥を顕在化する技術とし
て電気化学反応を用いた銅析出法（Ｃｕデコレーション
法）が提案されている（Ｗｅｒｎｅｒ Ｋｅｒｎ、 Ｒ
ＣＡＲｅｖｉｅｗ Ｖｏｌ．３４ ｐ６５５−６９０
１９７３）。メチルアルコールを溶媒として銅陽極を用
い、陰極である酸化膜を有するシリコン基板上に銅を電
解析出させる。リーク電流により、銅イオンが還元し、
析出するため、欠陥箇所のマーカーとなる。この方法
は、ゲート絶縁膜に発生するＣＯＰ（Ｃｒｙｓｔａｌ
Ｏｒｉｇｉｎａｔｅｄ Ｐａｒｔｉｃｌｅｓ）による欠
陥の検出に用いられている（応用物理 第６６巻７号、
Ｐ７２８−７３１（１９９７））。近年、ＦＩＢ（Ｆｏ
ｃｕｓｅｄ Ｉｏｎ Ｂｅａｍ）を用いてＣｕ析出箇所
の断面ＴＥＭ観察をする技術（特開平８−２６１９５７
号公報）や、レーザー散乱法と組み合わせた欠陥分布評
価技術（特開平１１−１９５６８５号公報）が提案さ
れ、さらに注目を集めている。Therefore, as a technique for revealing defects in an insulating film, a copper deposition method (Cu decoration method) using an electrochemical reaction has been proposed (Werner Kern, R.
CAReview Vol. 34 p655-690
1973). Using a copper anode with methyl alcohol as a solvent, copper is electrolytically deposited on a silicon substrate having an oxide film as a cathode. The copper ions are reduced by the leak current,
Since it is deposited, it serves as a marker for a defective portion. This method uses COP (Crystal) generated in the gate insulating film.
Used for defect detection by Originated Particles (Applied Physics Vol. 66, No. 7,
P728-731 (1997)). In recent years, FIB (Fo
Technology for performing cross-sectional TEM observation of a Cu deposition location using a used ion beam (Japanese Patent Laid-Open No. 8-261957).
And a defect distribution evaluation technique in combination with a laser scattering method (Japanese Unexamined Patent Application Publication No. 11-195885) have been proposed and attracted more attention.
【０００５】Ｃｕデコレーション法には、様々な課題が
あるが、改善方法が提案されてきた。[0005] The Cu decoration method has various problems, but an improvement method has been proposed.
【０００６】第１に、Ｃｕ析出の面内分布が悪い点であ
る。特に電解液にメチルアルコールを用いる場合、溶液
抵抗による電圧降下が大きく、表面電位を一定に保つの
が困難であり、析出現象がウエハ位置により異なってし
まう。これに対しては溶液抵抗の小さな銅の強酸塩を含
む電解液を用いた銅析出法が提案されている（特開昭５
２−１３２６８２号公報）。第２に銅析出の析出頻度が
小さく、銅が析出せず検出されない欠陥がみられる。電
着精度を上げ、析出後の消失を防止するため、Ａｕ等の
貴金属の電解液に用いた方法が提案されている（特開平
１１−２４８６０８号公報）。[0006] First, the in-plane distribution of Cu precipitation is poor. In particular, when methyl alcohol is used as the electrolytic solution, the voltage drop due to the solution resistance is large, it is difficult to keep the surface potential constant, and the deposition phenomenon varies depending on the wafer position. To cope with this, a copper deposition method using an electrolytic solution containing a copper strong acid salt having a small solution resistance has been proposed (Japanese Patent Laid-Open No.
2-132682). Second, there are defects in which the frequency of copper deposition is low and copper is not deposited and is not detected. In order to increase the electrodeposition accuracy and prevent the disappearance after deposition, a method using an electrolytic solution of a noble metal such as Au has been proposed (JP-A-11-248608).
【０００７】第３に、検出できる銅析出粒径が欠陥に比
べて大きく、欠陥位置を検出精度が悪い点である。そこ
で銅析出後、逆電圧を印加し、絶縁膜欠陥付近の銅を溶
出させ、さらに貴金属イオン水溶液中で貴金属を析出さ
せて、欠陥位置精度を０．１・ｍに向上させる方法が提
案されている（特開平１０−２７５８４０号公報）。Third, the detectable particle size of copper is larger than that of a defect, and the accuracy of detecting a defect position is poor. Therefore, after copper deposition, a method of applying a reverse voltage to elute copper in the vicinity of the insulating film defect, further precipitating a noble metal in a noble metal ion aqueous solution, and improving the defect position accuracy to 0.1 · m has been proposed. (JP-A-10-275840).
【０００８】[0008]
【発明が解決しようとする課題】これらの従来技術によ
り、金属析出による欠陥検出技術は改善されてきたが、
以下の課題が残っている。Although the prior art has improved the technique of detecting defects by metal deposition,
The following issues remain.
【０００９】（１）ＬＳＩの高集積化により、問題とな
る絶縁膜欠陥のリーク電流が低下し、ｎｍオーダーの位
置検出が要求されている。しかし、これらの手法では、
析出粒子の核形成の制御が困難であるため、析出粒の大
きさが不均一となり、一部大きな析出物が形成された
り、析出の起こらない欠陥箇所が出来てしまう。欠陥密
度が高い場合には、析出粒子が複数の欠陥にまたがって
個々に認識できない。さらにＤＲＡＭキャパシタ等の深
溝構造では、溝上部に大きな析出粒子が形成されて、溝
底での析出を阻害し、欠陥検出ができないという課題が
ある。従来技術にはない核発生を制御する技術が必要で
ある。さらに微小欠陥を検出するためには、析出させる
金属粒径をｎｍオーダーまで小さくする必要がある。従
来の方法では、成長速度が速すぎるため、時間制御が難
しく、微粒子を再現性良く形成することができない。成
長速度を遅くする方法としては、電流密度を下げること
で可能であるが、前述の核発生密度も減少してしまう。
電流密度を下げずに、成長速度を減少させる技術が必要
である。(1) With the increase in the degree of integration of LSIs, the leakage current of insulating film defects, which poses a problem, is reduced, and there is a demand for position detection on the order of nm. However, with these approaches,
Since it is difficult to control the nucleation of the precipitated particles, the size of the precipitated particles becomes non-uniform, and a partially large precipitate is formed or a defective portion where no precipitation occurs is generated. When the defect density is high, the precipitated particles cannot be individually recognized over a plurality of defects. Further, in a deep groove structure such as a DRAM capacitor, there is a problem that large precipitate particles are formed at the upper part of the groove, which hinders precipitation at the groove bottom and that defect detection cannot be performed. Techniques for controlling nucleation that are not available in the prior art are needed. Further, in order to detect minute defects, it is necessary to reduce the particle size of the deposited metal to the order of nm. In the conventional method, since the growth rate is too high, time control is difficult, and fine particles cannot be formed with good reproducibility. As a method of reducing the growth rate, it is possible to reduce the current density, but the above-described nucleation density also decreases.
There is a need for a technique that reduces the growth rate without reducing the current density.
【００１０】（２）また特開平１１−２４８６０８号公
報で提案されている貴金属の電解析出は、銅に比べ還元
電位が小さく、微小な電流で析出が可能であるが、硫酸
溶液中では不安定である。最も用いられている金の電解
液はシアン溶液であるが、有害であり作業上問題があ
る。安全で安定な金の電解液を用いる必要がある。(2) The electrolytic deposition of a noble metal proposed in Japanese Patent Application Laid-Open No. H11-248608 has a smaller reduction potential than copper and can be deposited with a small current, but is not possible in a sulfuric acid solution. It is stable. The most used gold electrolyte is cyanide, which is harmful and poses a problem in operation. It is necessary to use a safe and stable gold electrolyte.
【００１１】（３）Ｃｕデコレーション法では、特開平
８−２６１９５７号公報に記載されているように、銅析
出工程の際に照射される光量で銅析出量が大きく変化
し、遮蔽して光量を減らすことにより、銅析出を抑制し
ている。一方、特開平１１−１９５６８５号公報では光
量により銅析出量が大きく変化していない。２つの報告
で、光による影響が異なっており、光照射が金属析出を
不安定にするという問題がある。サンプル依存性を無く
し、同一条件で析出できる方法が必要である。(3) In the Cu decoration method, as described in Japanese Patent Application Laid-Open No. 8-261957, the amount of copper deposition changes greatly depending on the amount of light irradiated during the copper deposition step, and the amount of copper is shielded to reduce the amount of light. By reducing the amount, copper precipitation is suppressed. On the other hand, in Japanese Unexamined Patent Application Publication No. 11-195885, the amount of deposited copper does not change significantly with the amount of light. The effects of light differ between the two reports, and there is a problem that light irradiation makes metal deposition unstable. There is a need for a method that eliminates sample dependence and can precipitate under the same conditions.
【００１２】本発明は、このような課題を解決するため
のものであり、微小リーク電流により均一な金属微粒子
を析出させ、再現性良く欠陥を検出する方法を提供する
ことを目的とする。An object of the present invention is to solve such a problem, and an object of the present invention is to provide a method for depositing uniform metal fine particles by a minute leak current and detecting defects with good reproducibility.
【００１３】[0013]
【課題を解決するための手段】第１の発明は、表面を絶
縁膜で被覆した基板とアノード電極とを金属イオンを含
有する電解液中に設置し、基板と、アノード電極の間に
パルス電圧を印加し、絶縁膜表面で金属イオンが電気化
学反応により析出し、絶縁膜中の欠陥を検出することに
より、上記課題（１）を帰結する。特に該パルス電圧の
オン時間が１〜３０ｍｓ、パルスデューティ比５〜３
０、ピーク電流密度０．０１〜１０ｍＡ／ｃｍ２である
と良い。According to a first aspect of the present invention, a substrate whose surface is covered with an insulating film and an anode electrode are placed in an electrolytic solution containing metal ions, and a pulse voltage is applied between the substrate and the anode electrode. Is applied, metal ions are precipitated on the surface of the insulating film by an electrochemical reaction, and a defect in the insulating film is detected, which results in the above problem (1). In particular, the on time of the pulse voltage is 1 to 30 ms, and the pulse duty ratio is 5 to 3
0 and a peak current density of 0.01 to 10 mA / cm 2.
【００１４】第２の発明は、電解液として亜硫酸金塩を
含むことにより、上記課題（２）を解決する。特にＡｕ
＋濃度が０．０００１〜０．１ｍｏｌ／ｌで、ｐＨが６
〜１１で行うと良い。The second invention solves the above-mentioned problem (2) by including a gold sulfite as an electrolytic solution. Especially Au
+ Concentration of 0.0001-0.1 mol / l and pH of 6
It is good to carry out at ~ 11.
【００１５】第３の発明は、絶縁膜表面に半導体のバン
ドギャップ以上のエネルギーを持つ、１ｍＷ／ｃｍ２以
上の光を照射しながら、シリコン基板とアノード電極間
に電圧を印加することにより絶縁膜中の欠陥を検出する
ことにより、上記課題（３）を解決する。According to a third aspect of the present invention, a voltage is applied between a silicon substrate and an anode electrode while irradiating light of 1 mW / cm 2 or more having energy equal to or greater than the band gap of the semiconductor to the surface of the insulating film. The above-mentioned problem (3) is solved by detecting the defect (1).
【００１６】上記方法は、光源がシリコン基板直上に配
置され、かつ光源からの光がアノード電極により遮蔽さ
れ、絶縁膜表面に暗部を形成しないように、アノード電
極が開口率８０％以上のメッシュ形状で基板表面と平行
に設置されている、又は光源がシリコン基板直上に配置
され、かつアノード電極が、筒状で光源からの光を遮ら
ないように設置されている、又は光源が電解液容器外側
に配置し、かつ電解液容器の光透過率が８０％以上であ
り、絶縁膜表面での光量の均一性が８０％以上である装
置を用いることにより達成できる。In the above method, the light source is disposed directly above the silicon substrate, and the light from the light source is shielded by the anode electrode. Is installed in parallel with the substrate surface, or the light source is arranged directly above the silicon substrate, and the anode electrode is installed so as not to block light from the light source in a cylindrical shape, or the light source is outside the electrolyte container. And a device in which the light transmittance of the electrolyte container is 80% or more and the uniformity of the light amount on the surface of the insulating film is 80% or more.
【００１７】[0017]
【発明の実施の形態】（実施例１）以下本発明のパルス
電流を用いた絶縁膜欠陥検出の実施形態を図面を用いて
具体的に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Embodiments of the present invention for detecting an insulating film defect using a pulse current will be specifically described with reference to the drawings.
【００１８】図１は本実施例１の絶縁膜欠陥評価に用い
るパルス電解析出装置の概略図である。試料１０１を設
置する試料台１０２と、電解液容器１０３と、アノード
電極１０４、電源１０５からなる。試料台１０２に設置
したシリコン基板の試料１０１上に、直径５０ｍｍ、高
さ５０ｍｍの円柱状でガラス又はプラスチック製の電解
液容器１０３を置く。試料台１０２には導電性の金属板
を用い、試料１０１と電解液容器１０３の間にシリコン
ゴム１０６を挟み、例えばネジで電解液容器１０３を試
料１０１に押しつけて固定する。そこで電解液容器１０
３に亜硫酸金ナトリウムＮａ２Ａｕ（ＳＯ３）２（０．
００１〜０．１ｍｏｌ／ｌ）電解液１０７を入れ、さら
に例えばＰｔプレート等のアノード電極１０４を電解液
１０７に浸す。次に電源１０５をアノード電極１０４と
試料台１０２に接続する。電源１０５からパルス電圧を
印加し、試料１０１表面に電解液１０７から金属を析出
させる。図２に示すようにパルス電圧は、定常的なＤＣ
電圧と異なり、パルスオン時間に金属が析出し、パルス
オフ時間は休止する。ここでパルス電解条件について説
明する。パルスの特性を示すパラメータは、パルスオン
時間、パルスオフ時間とともに、オン時間の割合を示す
デューティー比、パルス電流密度、パルス平均電流密度
があり、以後説明に用いる。本実施例では、パルス電源
として定電圧パルス電源を用いているが、定電流パルス
電源を用いても良い。FIG. 1 is a schematic diagram of a pulse electrolytic deposition apparatus used for evaluating an insulating film defect according to the first embodiment. It comprises a sample stage 102 on which a sample 101 is placed, an electrolytic solution container 103, an anode electrode 104, and a power supply 105. A cylindrical glass or plastic electrolyte container 103 having a diameter of 50 mm and a height of 50 mm is placed on a silicon substrate sample 101 set on a sample stage 102. A conductive metal plate is used for the sample stage 102, and a silicone rubber 106 is sandwiched between the sample 101 and the electrolyte solution container 103, and the electrolyte solution container 103 is pressed against the sample 101 with, for example, screws to be fixed. Then, the electrolyte container 10
3 was added to sodium gold sulfite Na2Au (SO3) 2 (0.
(001 to 0.1 mol / l) The electrolytic solution 107 is added, and the anode electrode 104 such as a Pt plate is immersed in the electrolytic solution 107. Next, the power supply 105 is connected to the anode electrode 104 and the sample stage 102. A pulse voltage is applied from the power supply 105 to deposit metal from the electrolyte solution 107 on the surface of the sample 101. As shown in FIG. 2, the pulse voltage is a steady DC voltage.
Unlike voltage, metal deposits during the pulse-on time and pauses during the pulse-off time. Here, pulse electrolysis conditions will be described. Parameters indicating the characteristics of the pulse include a pulse ratio, a pulse current density, and a pulse average current density, which indicate the ratio of the ON time, in addition to the pulse ON time and the pulse OFF time. In this embodiment, a constant voltage pulse power supply is used as the pulse power supply, but a constant current pulse power supply may be used.
【００１９】また本実施例では、シリコン基板を用いた
場合について説明しているが、金属基板又は、導電膜付
の絶縁基板を用いても良い。但し、絶縁基板の場合に
は、基板表面側の導電膜に直接電流を流せば良い。In this embodiment, the case where a silicon substrate is used is described, but a metal substrate or an insulating substrate provided with a conductive film may be used. However, in the case of an insulating substrate, a current may be passed directly to the conductive film on the substrate surface side.
【００２０】パルス電流の効果を、５ｎｍの熱酸化膜に
用いた例で説明する。図３は亜硫酸金ナトリウム液のｐ
Ｈと析出金粒子の密度の関係を示している。粒密度はｐ
Ｈに強く依存し、６〜１１で高い。ｐＨ１１以上では、
析出金粒子の酸化膜への付着力が弱く、析出処理後の水
洗で流れてしまう。またｐＨ６未満では金析出が不均一
で析出密度が減少する。よって電解液のｐＨが６〜１１
にするのが重要である。The effect of the pulse current will be described using an example in which a 5 nm thermal oxide film is used. Figure 3 shows the p of sodium gold sulfite solution.
3 shows the relationship between H and the density of precipitated gold particles. The grain density is p
It depends strongly on H, and is high at 6-11. At pH 11 and above,
The adherence of the deposited gold particles to the oxide film is weak, and the gold particles flow by washing with water after the deposition treatment. On the other hand, when the pH is lower than 6, gold deposition is not uniform and the deposition density is reduced. Therefore, the pH of the electrolyte is 6 to 11
It is important to
【００２１】次に析出金粒子の密度とパルスパラメータ
の関係を図４、５に示す。Next, the relationship between the density of the deposited gold particles and the pulse parameters is shown in FIGS.
【００２２】図４は電圧オン時間と析出金粒子の密度の
関係を示している。オン時間が３０ｍｓ以下で急激に金
粒子密度が増加する。オン時間∞はＤＣ電圧を表してい
る。図５は電圧オフ時間と析出金粒子の密度の関係を示
している。オン時間が２０ｍｓ以上で急激に金粒子密度
が増加し、３０ｍｓ以上で飽和する。オフ時間０はＤＣ
電圧を表している。FIG. 4 shows the relationship between the voltage-on time and the density of the deposited gold particles. When the ON time is 30 ms or less, the density of gold particles rapidly increases. The on-time を represents a DC voltage. FIG. 5 shows the relationship between the voltage off time and the density of the deposited gold particles. The gold particle density rapidly increases when the on-time is 20 ms or more, and saturates at 30 ms or more. Off time 0 is DC
Indicates voltage.
【００２３】パルスオン時間が短い程、オフ時間が長い
程、析出密度が増加する。図６はオン時間２０ｍｓ、オ
フ時間１８０ｍｓ、処理時間１０ｓのパルス処理（パル
ス電流密度０．００１〜１０ｍＡ／ｃｍ２）と同じ電流
密度で１ｓＤＣ処理した酸化膜表面のＳＥＭ像を比較し
ている。ＤＣ処理（図６（ａ））では１μｍ以上の金粒
子と数１０ｎｍの金粒子が見られ、粒径が不均一であ
る。一方、パルス処理（図６（ｂ））では、粒径が１０
ｎｍと均一で高密度に形成されている。また１０ｎｍ程
度の微粒子を形成するのに、ＤＣ処理では１ｓと処理時
間が短すぎるが、パルス処理では、ディーティー比（本
実施例では１０）だけ処理時間が長くでき制御性が非常
に良い。ディーティー比を増やすことにより、さらに小
さな粒子の形成を制御可能も可能であり、パルス電圧が
微小欠陥検出に有利である。パルスオン時間は、３０ｍ
ｓ以上では、粒成長速度が速くなり粒径バラツキが生じ
やすい。また１ｍｓ以下では制御性が悪いため、１〜３
０ｍｓが良い。一方、パルスオフ時間は３０ｍｓ以上が
良いが、これはＡｕイオンの消費量と関係しているため
オン時間により変わる。The shorter the pulse-on time and the longer the off-time, the higher the deposition density. FIG. 6 compares SEM images of the oxide film surface subjected to 1sDC treatment at the same current density as the pulse treatment (pulse current density 0.001 to 10 mA / cm 2) with on time 20 ms, off time 180 ms, and treatment time 10 s. In the DC treatment (FIG. 6A), gold particles of 1 μm or more and gold particles of several tens of nm are observed, and the particle diameters are not uniform. On the other hand, in the pulse processing (FIG. 6B),
nm and are formed at a high density. In order to form fine particles of about 10 nm, the processing time is too short, 1 s in the DC processing, but the processing time is long in the pulse processing by the duty ratio (10 in this embodiment), and the controllability is very good. By increasing the duty ratio, the formation of even smaller particles can be controlled, and the pulse voltage is advantageous for detecting minute defects. Pulse on time is 30m
Above s, the grain growth rate is high and the grain size tends to vary. If the time is 1 ms or less, the controllability is poor.
0 ms is good. On the other hand, the pulse-off time is preferably 30 ms or more, but this depends on the consumption of Au ions and varies depending on the on-time.
【００２４】実用上からは、粒径１０ｎｍの粒子を形成
するのに１０〜６０秒で行うにはデューティー比が５〜
３０であると良い。From a practical point of view, to form particles having a particle size of 10 nm in 10 to 60 seconds, a duty ratio of 5 to 60 seconds is required.
It is good to be 30.
【００２５】次にパルス処理の効果について図７を用い
て説明する。厚さ５ｎｍの酸化膜は高密度（＞１Ｅ１５
／ｃｍ２）の欠陥を有しているが、ＤＣ処理（図７
（ａ））では、金粒子の核形成密度が低く、全ての欠陥
に析出せず、一部の金粒子が大きく成長している。一
方、パルス処理（図７（ｂ））では、全ての欠陥で金粒
子が析出しており、金粒子の成長も均一となる。図８は
パルス電圧印加時の絶縁膜表面における金イオン濃度の
時間変化を示している。ＤＣ電圧では、電圧印加前は金
イオンの表面濃度は溶液濃度と等しいが、電圧を印加
し、金が析出すると表面濃度は減少する。金粒子の核形
成頻度は金イオンの表面濃度に関係しており、表面濃度
が減少することにより核形成が起こらなくなる。一度形
成された金粒子の成長は、酸化膜上での新たな金粒子の
核形成に比べて起こりやすいため、核形成より粒成長が
支配的になる。さらに一度成長すると金粒子の表面積が
増加し、金成長が促進する。つまり金粒子の大きさが不
均一になる。Next, the effect of the pulse processing will be described with reference to FIG. The oxide film having a thickness of 5 nm has a high density (> 1E15).
/ Cm2), but DC treatment (FIG. 7)
In (a)), the nucleation density of the gold particles is low, the gold particles do not precipitate on all the defects, and some of the gold particles grow large. On the other hand, in the pulse processing (FIG. 7B), gold particles are precipitated at all the defects, and the growth of the gold particles becomes uniform. FIG. 8 shows a time change of the gold ion concentration on the surface of the insulating film when a pulse voltage is applied. With a DC voltage, the surface concentration of gold ions is equal to the solution concentration before the voltage is applied, but the surface concentration decreases when a voltage is applied and gold is deposited. The nucleation frequency of gold particles is related to the surface concentration of gold ions, and nucleation does not occur as the surface concentration decreases. The growth of the once formed gold particles is more likely to occur than the nucleation of new gold particles on the oxide film, so that the grain growth becomes dominant over the nucleation. Further, once grown, the surface area of the gold particles increases, which promotes gold growth. That is, the size of the gold particles becomes uneven.
【００２６】一方、パルス電圧を用いると、電圧オン時
間に金イオンの表面濃度は金析出により一度減少する
が、オフ時間に濃度が回復する。よって各パルス電圧印
加時に金粒子の核形成が起こる。またオン時間が短いた
め、核形成よりも粒成長が支配的になるのを抑制し、均
一な粒径の金粒子を形成できる。On the other hand, when a pulse voltage is used, the surface concentration of gold ions once decreases during gold-on time due to gold deposition, but recovers during off-time. Therefore, nucleation of gold particles occurs when each pulse voltage is applied. Further, since the on-time is short, it is possible to suppress that the grain growth becomes more dominant than the nucleation and to form gold particles having a uniform particle diameter.
【００２７】従来評価に用いられていたＣＯＰ起因の欠
陥密度は１０／ｃｍ２と低く、１欠陥当たりのリーク電
流が大きいため、ＤＣ電圧でもすべての欠陥を検出でき
ていたが、今後問題となってくるリーク電流の小さな欠
陥を検出する場合にはパルス電圧を用いる必要がある。The defect density due to COP used in the conventional evaluation is as low as 10 / cm 2, and the leakage current per defect is large, so that all defects can be detected even at DC voltage. In order to detect a defect having a small leak current, it is necessary to use a pulse voltage.
【００２８】以下本発明の絶縁膜欠陥検出の実施形態
を、ＤＲＡＭキャパシタを例に図９を用いて具体的に説
明する。Hereinafter, an embodiment of the present invention for detecting an insulating film defect will be specifically described with reference to FIG. 9 using a DRAM capacitor as an example.
【００２９】ｎ型半導体基板２０１上に層間絶縁膜２０
２を形成する。次に、層間絶縁膜２０２をドライエッチ
ング法で選択的に除去して接続孔を形成し、その後、接
続孔の内部に導電プラグ２０３を形成する。次に、導電
プラグ２０３を含む層間絶縁膜２０２上に窒化膜２０４
と１・ｍの層間絶縁膜２０５を形成する。次に、層間絶
縁膜２０５上にドライエッチング法で溝を形成する。溝
の側面に５０ｎｍのアモルファスシリコン膜からなる蓄
積電極膜２０６を形成する。この蓄積電極膜２０６は導
電プラグ２０３と電気的に接続されている。次に、レジ
ストをマスクとし、溝の側面以外の蓄積電極膜２０６を
ドライエッチングにより除去し、キャパシタセルを分離
する。さらにアモルファスシリコン膜からなる蓄積電極
膜２０６をＰＨ３雰囲気でアニールし、ポリシリコン膜
とする。次に蓄積電極膜２０６上に１０ｎｍ程度のＴａ
２Ｏ５膜からなる容量誘電体膜２０７をＣＶＤ法により
形成する。ＣＶＤ膜は結晶化しているが、不純物を多く
含んでいるため、６００〜８００℃の酸素雰囲気でアニ
ールする。本実施例ではＴａ２Ｏ５膜を用いているが、
容量誘電体膜２０７にＳｉ３Ｎ４やＢａ1-xＳｒxＴｉＯ
3、ＰｂＺｒ1-xＴｉxＯ3、ＳｒＢｉ２Ｔａ２Ｏ９膜等の
高誘電酸化物を用いてもよい。最後に、例えばＴｉＮ等
の上部電極を形成して、キャパシタが完成するが、本実
施例のサンプルは上部電極を形成せず、サンプル表面は
容量誘電体膜２０７で覆われている。次に絶縁膜欠陥評
価方法を説明する。容量誘電体膜２０７堆積後、サンプ
ルを電解析出装置に設置する。電解液には、Ａｕ２Ｎａ
（ＳＯ３）２（０．０００１〜０．１ｍｏｌ／ｌ）を用
い、電極にはＰｔプレートを用いた。電解析出はパルス
オン時間を２０ｍｓｅｃ、休止時間を１８０ｍｓｅｃに
設定し、３０秒間印加する。An interlayer insulating film 20 is formed on an n-type semiconductor substrate 201.
Form 2 Next, a connection hole is formed by selectively removing the interlayer insulating film 202 by a dry etching method, and thereafter, a conductive plug 203 is formed inside the connection hole. Next, a nitride film 204 is formed on the interlayer insulating film 202 including the conductive plug 203.
Then, an interlayer insulating film 205 of 1 · m is formed. Next, a groove is formed on the interlayer insulating film 205 by a dry etching method. A storage electrode film 206 made of a 50 nm amorphous silicon film is formed on the side surface of the groove. The storage electrode film 206 is electrically connected to the conductive plug 203. Next, using the resist as a mask, the storage electrode film 206 other than the side surface of the groove is removed by dry etching to separate the capacitor cell. Further, the storage electrode film 206 made of an amorphous silicon film is annealed in a PH3 atmosphere to form a polysilicon film. Next, about 10 nm of Ta is formed on the storage electrode film 206.
A capacitor dielectric film 207 made of a 2O5 film is formed by a CVD method. Although the CVD film is crystallized, it is annealed in an oxygen atmosphere at 600 to 800 ° C. because it contains many impurities. In this embodiment, a Ta2O5 film is used.
Si 3 N 4 or Ba 1-x Sr x TiO 2 is used for the capacitor dielectric film 207.
3, PbZr 1-x Ti x O 3, it may be used SrBi2Ta2O9 high dielectric oxide such as film. Finally, an upper electrode such as TiN is formed to complete the capacitor. However, the sample of the present embodiment does not have an upper electrode, and the surface of the sample is covered with the capacitor dielectric film 207. Next, an insulating film defect evaluation method will be described. After depositing the capacitor dielectric film 207, the sample is set in an electrolytic deposition apparatus. The electrolyte is Au2Na
(SO3) 2 (0.0001 to 0.1 mol / l) was used, and a Pt plate was used as an electrode. For the electrolytic deposition, the pulse-on time is set to 20 msec, the pause time is set to 180 msec, and the application is performed for 30 seconds.
【００３０】次に、サンプルを水洗し、断面ＳＥＭ観察
を行う。Next, the sample is washed with water and a cross-sectional SEM observation is performed.
【００３１】図１０に示すように金粒子は溝側面の底部
付近に直径１０ｎｍの金粒子が均一に析出する。溝の底
部でＴａ２Ｏ５膜の膜厚が薄くなり、リーク欠陥が形成
されていることがわかる。As shown in FIG. 10, gold particles having a diameter of 10 nm are uniformly deposited near the bottom of the groove side surface. It can be seen that the thickness of the Ta2O5 film becomes thinner at the bottom of the groove, and a leak defect is formed.
【００３２】本実施例では、Ａｕ粒子の観察のＳＥＭ観
察を用いているが、複雑な構造でＡｕ粒子が見にくい場
合には、反射電子像観察が有効である。またＡｕ粒子を
マーカーとして、ＦＩＢ加工による断面ＴＥＭ観察をし
ても良い。In this embodiment, the SEM observation of the observation of the Au particles is used. However, when the Au particles are difficult to see due to the complicated structure, the observation of the backscattered electron image is effective. Further, a cross-sectional TEM observation by FIB processing may be performed using Au particles as a marker.
【００３３】（実施例２）以下本発明の光照射を用いた
絶縁膜欠陥検出の実施形態を図面を用いて具体的に説明
する。(Embodiment 2) Embodiments of the present invention for detecting an insulating film defect using light irradiation will be described in detail with reference to the drawings.
【００３４】図１１は本実施例２の光照射を用いる電解
析出装置の概略図である。試料１０１を設置する試料台
１０２と、電解液容器１０３と、アノード電極１０４、
光源１０８、電源１０５からなる。実施例１と同様に、
電解液容器１０３に亜硫酸金ナトリウムＮａ２Ａｕ（Ｓ
Ｏ３）２（０．００１〜０．１ｍｏｌ／ｌ）電解液１０
７を入れ、さらにプレート電極としてＰｔメッシュ電極
１０４をこの電解液１０７に浸す。Ｐｔ電極には、光の
開口度が８０％以上のメッシュ形状で、十分に光を透過
できるものを用いる。次に電源１０５をアノード電極１
０４と試料台１０２に接続する。電源１０５から電圧を
印加し、試料１０１表面に電解液１０７から金属を析出
させる。この５０Ｗハロゲンランプ光源１０８を試料１
０１の１０ｃｍ上方に固定し、試料１０１の表面に光を
照射する。Ｐｔメッシュ電極１０４は試料１０１より約
３０ｍｍの位置に平行に設置してある。FIG. 11 is a schematic view of an electrolytic deposition apparatus using light irradiation according to the second embodiment. A sample stage 102 on which a sample 101 is placed, an electrolyte container 103, an anode electrode 104,
It comprises a light source 108 and a power supply 105. As in Example 1,
Gold sodium sulfite Na2Au (S
O3) 2 (0.001-0.1 mol / l) electrolyte 10
7, and a Pt mesh electrode 104 as a plate electrode is immersed in the electrolytic solution 107. As the Pt electrode, a mesh having a light aperture of 80% or more and capable of sufficiently transmitting light is used. Next, the power supply 105 is connected to the anode 1
04 and the sample table 102. A voltage is applied from the power supply 105 to deposit metal from the electrolyte solution 107 on the surface of the sample 101. This 50 W halogen lamp light source 108 was used for sample 1
The sample 101 is fixed 10 cm above, and the surface of the sample 101 is irradiated with light. The Pt mesh electrode 104 is installed in parallel at a position about 30 mm from the sample 101.
【００３５】従来技術の課題で説明した絶縁膜を流れる
電流と基板の関係を調べるため、ｐ型とｎ型シリコン基
板上の酸化膜の電流特性を比較した。図１２に示すよう
にｐ型基板上の酸化膜では、ｎ型基板上の酸化膜に比べ
て、電流が流れない。ｐ型基板で光を照射すると、電流
は増加し、ｎ型基板上と同程度になる。但し、ある電圧
以上では電流値が一定になり、飽和値は照射する光量に
依存していることがわかる。The current characteristics of the oxide films on the p-type and n-type silicon substrates were compared in order to investigate the relationship between the current flowing through the insulating film and the substrate described in the prior art. As shown in FIG. 12, no current flows in the oxide film on the p-type substrate as compared with the oxide film on the n-type substrate. When light is irradiated on the p-type substrate, the current increases, and becomes almost the same as on the n-type substrate. However, it can be seen that the current value becomes constant above a certain voltage, and the saturation value depends on the amount of light to be irradiated.
【００３６】Ｐ型基板上での酸化膜の抵抗は光照射によ
り変わるため、金析出の面内均一性を得るためには、試
料１０１表面の光量は１ｍＷ／ｃｍ２以上で面内均一性
は８０％以上である必要がある。Since the resistance of the oxide film on the P-type substrate changes with light irradiation, in order to obtain in-plane uniformity of gold deposition, the amount of light on the surface of the sample 101 is 1 mW / cm 2 or more and the in-plane uniformity is 80%. %.
【００３７】この現象はｎ型とｐ型基板上酸化膜の電気
伝導機構により説明できる。酸化膜中の電子伝導は直接
及び間接トンネルにより起こるが、トンネル現象はトン
ネル可能な電子密度とトンネル確率により決まる。ｎ基
板では室温では全てのドナー電子は励起され、トンネル
可能な伝導帯の電子密度が高いためトンネル電流が流れ
やすい。一方、ｐ基板では電流を溶液から基板に流す順
バイアスでは、ｐ基板の酸化膜近傍に空乏層が形成さ
れ、トンネル可能な電子密度が低い。しかし光照射によ
り荷電子帯の電子が伝導帯に励起され、擬フェルミ準位
が高くなり、ｎ型基板と同じ振る舞いをするようにな
る。つまり光照射によりｐ基板上の酸化膜に電流を流す
ことが可能となる。This phenomenon can be explained by the electric conduction mechanism of the oxide films on the n-type and p-type substrates. Electron conduction in the oxide film occurs by direct and indirect tunneling, and the tunneling phenomenon is determined by the electron density and tunnel probability that can be tunneled. In the n-substrate, at room temperature, all donor electrons are excited, and a tunnel current easily flows due to a high electron density of a tunneling conduction band. On the other hand, in the case of a forward bias in which a current flows from the solution to the substrate in the p-substrate, a depletion layer is formed near the oxide film of the p-substrate, and the electron density capable of tunneling is low. However, light irradiation excites electrons in the valence band to the conduction band, increasing the quasi-Fermi level, causing the same behavior as the n-type substrate. That is, it becomes possible to cause a current to flow through the oxide film on the p substrate by light irradiation.
【００３８】特に、ｐ型シリコンとｎ型シリコン上に同
時に酸化膜を形成するＣＭＯＳ評価に光照射技術は不可
欠である。ＣＭＯＳを評価する際、光照射をしないと抵
抗の低いｐＭＯＳ（ｎ基板上）にだけ金が析出し、抵抗
の高いｎＭＯＳ（ｐ基板上）には析出せず、欠陥検出が
できない。In particular, the light irradiation technique is indispensable for CMOS evaluation in which an oxide film is simultaneously formed on p-type silicon and n-type silicon. When a CMOS is evaluated, gold is deposited only on a pMOS having a low resistance (on an n-substrate) without light irradiation, and is not deposited on an nMOS having a high resistance (on a p-substrate), so that a defect cannot be detected.
【００３９】本発明の実施例をＣＭＯＳ用酸化膜の欠陥
検出に適用した例で説明する。An example in which the embodiment of the present invention is applied to defect detection of a CMOS oxide film will be described.
【００４０】図１３にＣＭＯＳ断面構造の概略を示す。
ｐ型基板３０１表面を酸化し、Ｓｉ３Ｎ４膜を形成す
る。次に、Ｓｉ３Ｎ４膜を一部除去し、Ｐを打ち込みｎ
型ウェル領域３０２を形成する。ｎ型ウェル領域３０２
表面を酸化した後、残りのＳｉ３Ｎ４膜を除去して、Ｂ
を打ち込みｐ型ウェル領域３０３を形成する。さらにア
ニールによりＰ、Ｂをそれぞれ拡散させる。FIG. 13 shows an outline of a CMOS sectional structure.
The surface of the p-type substrate 301 is oxidized to form a Si3N4 film. Next, the Si3N4 film is partially removed, and P is implanted.
A mold well region 302 is formed. n-type well region 302
After oxidizing the surface, the remaining Si3N4 film is removed and B
To form a p-type well region 303. Further, P and B are respectively diffused by annealing.
【００４１】次に、ＣＶＤ法によりＳｉ３Ｎ４膜を形成
し、部分的にエッチング除去し、酸化処理を施して、フ
ィールド酸化膜３０４を形成する。次に、Ｓｉ３Ｎ４膜
をマスクとし、基板１上に８５０℃程度のウエット酸化
処理を施してｐ型ウエル領域３０２、ｎ型ウェル領域３
０３の表面に７ｎｍ程度の酸化膜からなるゲート酸化膜
３０５、３０６を形成する。Next, a field oxide film 304 is formed by forming a Si3N4 film by the CVD method, partially removing the film by etching, and performing an oxidation process. Next, using the Si3N4 film as a mask, a wet oxidation process is performed on the substrate 1 at about 850 ° C. to form a p-type well region 302 and an n-type well region 3.
Gate oxide films 305 and 306 made of an oxide film of about 7 nm are formed on the surface of the substrate 03.
【００４２】次に、ゲート酸化膜３０５、３０６上にゲ
ート電極を形成する。ゲート電極は、７０ｎｍ程度の燐
が導入された多結晶シリコン膜をＣＶＤ法で形成し、そ
の上に、１５０ｎｍ程度の窒化シリコン膜からなるキャ
ップ絶縁膜をＣＶＤ法で形成した後、これらの膜をパタ
ーンニングすることにより形成する。多結晶シリコン
膜、キャップ絶縁膜をマスクとし、ｐ型ウエル領域３０
２とｎ型ウェル領域３０３にそれぞれＰ、Ｂを打ち込
む。Next, a gate electrode is formed on the gate oxide films 305 and 306. For the gate electrode, a polycrystalline silicon film into which phosphorus of about 70 nm is introduced is formed by a CVD method, and a cap insulating film made of a silicon nitride film of about 150 nm is formed thereon by a CVD method. It is formed by patterning. Using the polycrystalline silicon film and the cap insulating film as a mask, the p-type well region 30 is formed.
P and B are implanted into the 2 and n-type well regions 303, respectively.
【００４３】次に、ｐ型ウエル領域３０２とｎ型ウェル
領域３０３の主面上に５０〜１００ｎｍ程度の窒化シリ
コン膜をＣＶＤ法で形成し、その後、窒化シリコン膜に
ＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）
の異方性エッチングを施してゲート電極の側壁にサイド
ウォールスペーサ３０７を形成する。Next, the 50~100nm approximately silicon nitride film on the main surface of the p-type well region 302 and the n-type well region 303 formed by the CVD method, then, the silicon nitride film RIE (R eactive I on E tching)
Is performed to form a sidewall spacer 307 on the side wall of the gate electrode.
【００４４】次に、ゲート電極とサイドウォールスペー
サ３０７をマスクとし、ｐ型ウエル領域３０２とｎ型ウ
ェル領域３０３にそれぞれＰ、Ｂを打ち込む。次に、ゲ
ート酸化膜３０２、３０３上の多結晶シリコン膜のそれ
ぞれＰ、Ｂを打ち込む。多結晶シリコン膜中でＰ、Ｂが
活性化するため７００〜９００℃でアニール処理を施
す。この工程により、ＬＤＤ構造のＣＭＯＳが形成され
る。Next, P and B are implanted into the p-type well region 302 and the n-type well region 303, respectively, using the gate electrode and the sidewall spacer 307 as a mask. Next, P and B of the polycrystalline silicon film on the gate oxide films 302 and 303 are respectively implanted. Annealing is performed at 700 to 900 ° C. to activate P and B in the polycrystalline silicon film. Through this step, a CMOS having an LDD structure is formed.
【００４５】本発明の絶縁膜欠陥評価を行うため、ゲー
ト電極のパターンニング後、多結晶シリコン膜をＨＦと
過酸化水素水の混合溶液でエッチング除去する。In order to evaluate the defect of the insulating film of the present invention, after patterning the gate electrode, the polycrystalline silicon film is removed by etching with a mixed solution of HF and hydrogen peroxide.
【００４６】次に、試料を試料台に固定し、亜硫酸金ナ
トリウムＮａ２Ａｕ（ＳＯ３）２（０．００１〜０．１
ｍｏｌ／ｌ）電解液を用い、本発明の光照射を用いなが
ら電解析出処理を行う。試料を水洗し、乾燥した後、Ｓ
ＥＭ観察を行う。図１３に示すように金粒子３０８はｎ
型ウェル領域３０３のゲート酸化膜３０６上に見られ
る。アニールにより打ち込んだＢがポリシリコン膜の粒
界を拡散し、ゲート酸化膜３０６中を突き抜ける。この
際、ゲート酸化膜３０６中に欠陥が形成されている。一
方、Ｐを打ち込んだｐ型ウェル領域３０２上では、Ｐの
ゲート酸化膜３０５の突き抜けが起こりにくいため欠陥
が形成されていない。本発明により、ＣＭＯＳのゲート
絶縁特性劣化の場所と原因が明らかにできる。Next, the sample was fixed on a sample table, and sodium gold sulfite Na2Au (SO3) 2 (0.001 to 0.1
(mol / l) Electrolytic deposition treatment is performed using an electrolytic solution while using the light irradiation of the present invention. After washing the sample with water and drying,
EM observation is performed. As shown in FIG. 13, the gold particles 308
It can be seen on the gate oxide film 306 in the mold well region 303. B implanted by annealing diffuses through the grain boundaries of the polysilicon film and penetrates through the gate oxide film 306. At this time, a defect is formed in the gate oxide film 306. On the other hand, no defect is formed on the p-type well region 302 into which the P is implanted, because the P gate oxide film 305 hardly penetrates. According to the present invention, the location and the cause of the deterioration of the gate insulating characteristics of the CMOS can be clarified.
【００４７】従来の光を用いない場合には、ｎ型ウェル
領域３０３のゲート酸化膜３０６とｐ型ウェル領域３０
２のゲート酸化膜３０５で抵抗が異なるため、ゲート酸
化膜３０５には金析出が起こらない。そのためゲート絶
縁特性の差を検出することができない。本発明では、光
照射によりゲート絶縁膜３０５とゲート絶縁膜３０６の
抵抗を同じにできるため、欠陥を正確に評価できる。When the conventional light is not used, the gate oxide film 306 of the n-type well region 303 and the p-type well region 30
Since the resistance is different between the second gate oxide film 305 and the gate oxide film 305, gold deposition does not occur. Therefore, it is not possible to detect a difference in gate insulation characteristics. In the present invention, the resistance of the gate insulating film 305 and the resistance of the gate insulating film 306 can be made equal by light irradiation, so that defects can be accurately evaluated.
【００４８】本実施例では、光源を基板直上に設置し、
メッシュ状のアノード電極を用いているが、光源からの
光を遮り、絶縁膜表面での光量の均一性が８０％以上で
あれば良い。例えば図１４に示すように、アノード電極
を筒状にし、光源からの光が直接、絶縁膜表面に到達で
きる構造や、図１５に示すように透過率８０％以上の電
解液容器を用い、光源からの光を直接又はミラーで反射
させ容器の周囲から均一に光を照射する構造であっても
良い。In this embodiment, the light source is installed directly above the substrate,
Although a mesh-shaped anode electrode is used, it is sufficient that the light from the light source is blocked and the uniformity of the light amount on the insulating film surface is 80% or more. For example, as shown in FIG. 14, the anode electrode is formed in a cylindrical shape, and the light from the light source can directly reach the surface of the insulating film, or as shown in FIG. A structure may be employed in which light from the container is reflected directly or by a mirror to uniformly irradiate light from around the container.
【００４９】[0049]
【発明の効果】以上述べてきたように、本発明の、パル
ス電解析出法により、粒径１０ｎｍ以下の微小な析出粒
を均一に形成することができる。そして微小欠陥位置の
特定が可能となり、信頼性の高いＬＳＩが形成できる。As described above, by the pulse electrolytic deposition method of the present invention, fine precipitates having a particle size of 10 nm or less can be uniformly formed. Then, the position of the minute defect can be specified, and a highly reliable LSI can be formed.
【図１】本発明の一実施例となるパルス電源を用いた欠
陥評価装置を示す図。FIG. 1 is a diagram showing a defect evaluation apparatus using a pulse power supply according to an embodiment of the present invention.
【図２】本発明の欠陥検出方法に用いるパルス電流の波
形図。FIG. 2 is a waveform diagram of a pulse current used in the defect detection method of the present invention.
【図３】金粒子析出密度の亜硫酸金ナトリウム電解液の
ｐＨ依存性を示す図。FIG. 3 is a diagram showing the pH dependence of the gold particle deposition density of the gold sodium sulfite electrolyte.
【図４】金粒子析出密度のパルスオン時間依存性を示す
図。FIG. 4 is a diagram showing the pulse-on time dependency of the gold particle deposition density.
【図５】金粒子析出密度のパルスオフ時間依存性を示す
図。FIG. 5 is a diagram showing the pulse off time dependency of the gold particle deposition density.
【図６】電解析出処理をした酸化膜表面のＳＥＭ像を示
す図で、（ａ）はＤＣ処理、（ｂ）はパルス処理を示す
図。FIGS. 6A and 6B are SEM images of an oxide film surface subjected to an electrolytic deposition process, wherein FIG. 6A shows a DC process and FIG. 6B shows a pulse process.
【図７】酸化膜表面での金粒子析出のモデル図で、
（ａ）はＤＣ処理、（ｂ）はパルス処理を示す図。FIG. 7 is a model diagram of gold particle deposition on an oxide film surface;
(A) is a figure showing DC processing, (b) is a figure showing pulse processing.
【図８】パルス電圧印加時の金イオン表面濃度変化を示
す図。FIG. 8 is a diagram showing a change in gold ion surface concentration when a pulse voltage is applied.
【図９】本発明の一実施例に用いたＤＲＡＭキャパシタ
構造の断面図。FIG. 9 is a sectional view of a DRAM capacitor structure used in one embodiment of the present invention.
【図１０】電解析出処理をしたＤＲＡＭキャパシタの断
面ＳＥＭ像を示す図。FIG. 10 is a view showing a cross-sectional SEM image of a DRAM capacitor subjected to an electrolytic deposition process.
【図１１】本発明の一実施例となる光源とメシュ電極を
用いた欠陥評価装置を示す図。FIG. 11 is a diagram showing a defect evaluation apparatus using a light source and a mesh electrode according to an embodiment of the present invention.
【図１２】酸化膜を流れる電流の基板及び光照射依存性
を示す図。FIG. 12 is a graph showing dependence of a current flowing through an oxide film on a substrate and light irradiation.
【図１３】電解析出処理をしたＣＭＯＳ断面図。FIG. 13 is a cross-sectional view of a CMOS after an electrolytic deposition process.
【図１４】本発明の一実施例となる光源と筒状電極を用
いた欠陥評価装置を示す図。FIG. 14 is a view showing a defect evaluation apparatus using a light source and a cylindrical electrode according to one embodiment of the present invention.
【図１５】本発明の一実施例となる光源と透明容器を用
いた欠陥評価装置を示す図。FIG. 15 is a diagram showing a defect evaluation apparatus using a light source and a transparent container according to an embodiment of the present invention.
１０１…シリコン基板、１０２…試料台、１０３…容
器、１０４…アノード電極、１０５…電源、１０６…シ
リコンゴム、１０７…電解液、１０８…光源、２０１…
ｐ型半導体基板、２０２…酸化膜、２０３…導電プラ
グ、２０４…窒化膜、２０５…層間絶縁膜、２０６…蓄
積電極膜、２０７…容量誘電体膜、３０１…ｐ型シリコ
ン基板、３０２…ｐ型ウェル領域、３０３…ｎ型ウェル
領域、３０４…フィールド酸化膜、３０５、３０６…ゲ
ート酸化膜、３０７…サイドウォールスペーサ、３０８
…金粒子。DESCRIPTION OF SYMBOLS 101 ... Silicon substrate, 102 ... Sample stand, 103 ... Container, 104 ... Anode electrode, 105 ... Power supply, 106 ... Silicon rubber, 107 ... Electrolyte, 108 ... Light source, 201 ...
p-type semiconductor substrate, 202 oxide film, 203 conductive plug, 204 nitride film, 205 interlayer insulating film, 206 storage electrode film, 207 capacitance dielectric film, 301 p-type silicon substrate, 302 p-type Well region 303 n-type well region 304 field oxide film 305 306 gate oxide film 307 side wall spacer 308
... gold particles.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 古川 亮一 東京都青梅市新町六丁目16番地の３ 株式 会社日立製作所デバイス開発センタ内 (72)発明者 吉田 正義 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 (72)発明者 佐伯 智則 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 Ｆターム(参考） 2G060 AA09 AA19 AE01 AF04 AG03 AG11 DA02 DA14 HA03 HE01 KA16 4M106 AA01 AA12 BA04 BA12 CA27 DH04 DH24 DH31 DH60 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ryoichi Furukawa 3-16-1, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Masayoshi Yoshida 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 In the Hitachi, Ltd. Semiconductor Group (72) Inventor Tomonori Saeki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Hitachi, Ltd. Production Technology Research Laboratory F-term (reference) 2G060 AA09 AA19 AE01 AF04 AG03 AG11 AG02 DA02 DA14 HA03 HE01 KA16 4M106 AA01 AA12 BA04 BA12 CA27 DH04 DH24 DH31 DH60
Claims (9)
電性膜付きの基板と、アノード電極と、電解液を入れる
容器と、電源とからなり、電気化学反応のより該絶縁膜
表面に金属を析出させて絶縁膜中の欠陥を検出する方法
において、パルス電圧又は電流を用いることを特徴とす
る絶縁膜欠陥検出方法。1. A conductive substrate or a substrate with a conductive film having an insulating film on its surface, an anode electrode, a container for containing an electrolytic solution, and a power supply. A method for detecting defects in an insulating film by depositing the same, wherein a pulse voltage or a current is used.
いて、該パルスオン時間が１〜３０ｍｓ、パルスデュー
ティ比５〜３０、ピーク電流密度０．０１〜１０ｍＡ／
ｃｍ２であることを特徴とする絶縁膜欠陥検出方法。2. The method according to claim 1, wherein the pulse on time is 1 to 30 ms, the pulse duty ratio is 5 to 30, and the peak current density is 0.01 to 10 mA /.
cm2, a method for detecting an insulating film defect.
を析出させて絶縁膜中の欠陥を検出する方法において、
該電解液として亜硫酸金塩を含むことを特徴とする絶縁
膜欠陥検出方法。3. A method for detecting a defect in an insulating film by depositing a metal on the surface of the insulating film by an electrochemical reaction,
A method for detecting a defect in an insulating film, comprising a gold sulfite as the electrolytic solution.
において、該亜硫酸金塩を含む電解液のＡｕ＋濃度が
０．０００１〜０．１ｍｏｌ／ｌで、ｐＨが６〜１１で
ある電解液を用いることを特徴とする絶縁膜欠陥検出方
法。4. The gold-sulfite-containing electrolytic solution according to claim 3, wherein the gold-sulfite-containing electrolytic solution has an Au + concentration of 0.0001 to 0.1 mol / l and a pH of 6 to 11. A method for detecting an insulating film defect, comprising using an electrolytic solution.
該絶縁膜表面に電気化学反応により金属を析出させて絶
縁膜中の欠陥を検出する方法において、該絶縁膜表面に
該半導体のバンドギャップ以上のエネルギーを持つ光を
１ｍＷ／ｃｍ２以上の強度で照射しながら、該半導体基
板又は該半導体膜と該金属電極間に電圧を印加すること
を特徴とする絶縁膜欠陥検出方法。5. A method for detecting a defect in an insulating film by depositing a metal on an insulating film surface formed on a semiconductor substrate or a semiconductor film by an electrochemical reaction, wherein a band gap of the semiconductor is formed on the insulating film surface. A method for detecting an insulating film defect, comprising applying a voltage between the semiconductor substrate or the semiconductor film and the metal electrode while irradiating light having the above energy at an intensity of 1 mW / cm 2 or more.
いる装置において、表面に絶縁膜を有する導電性基板又
は導電膜付の基板と、導電性の試料台と、電解液を入れ
る容器と、アノード電極と電源からなり、該半導体基板
を該試料台上に設置し、該絶縁膜上に該電解液容器を固
定し、金属イオンを含む電解液を該絶縁膜表面に接触す
るように該電解溶液に注ぎ、かつ該電解溶液中に該アノ
ード電極を設置し、該導電性基板又は導電膜と該アノー
ド電極間にパルス電圧を印加し、該絶縁膜表面に金属を
析出させる絶縁膜欠陥検出装置。6. An apparatus for use in the method for detecting a defect of an insulating film according to claim 1, wherein the conductive substrate having an insulating film on the surface or the substrate having a conductive film, a conductive sample stage, and a container for containing an electrolytic solution are provided. Comprising an anode electrode and a power source, placing the semiconductor substrate on the sample stage, fixing the electrolytic solution container on the insulating film, and contacting the electrolytic solution containing metal ions with the insulating film surface. Pour into an electrolytic solution, place the anode electrode in the electrolytic solution, apply a pulse voltage between the conductive substrate or conductive film and the anode electrode, and detect an insulating film defect that deposits a metal on the surface of the insulating film. apparatus.
いる装置において、光源が表面に絶縁膜を有する半導体
基板又は半導体膜付の絶縁基板直上に配置され、かつ該
光源からの光が、該アノード電極による遮蔽で該絶縁膜
表面に暗部を形成しないように、該アノード電極が開口
率８０％以上のメッシュ形状で該基板表面と平行に設置
されていることを特徴とする絶縁膜欠陥検出装置。7. An apparatus used in the method for detecting an insulating film defect according to claim 5, wherein the light source is disposed directly on the semiconductor substrate having the insulating film on the surface or the insulating substrate with the semiconductor film, and the light from the light source is: Insulating film defect detection, characterized in that the anode electrode is installed in parallel with the substrate surface in a mesh shape with an aperture ratio of 80% or more so that a dark portion is not formed on the insulating film surface by shielding by the anode electrode. apparatus.
いる装置において、光源が表面に絶縁膜を有する半導体
基板又は半導体膜付の絶縁基板直上に配置され、かつ該
アノード電極が、筒状で該光源からの光を遮らないよう
に設置されていることを特徴とする絶縁膜欠陥検出装
置。8. An apparatus used in the method for detecting an insulating film defect according to claim 5, wherein the light source is disposed directly on the semiconductor substrate having the insulating film on the surface or on the insulating substrate with the semiconductor film, and the anode electrode has a cylindrical shape. Wherein the light from the light source is not blocked.
いる装置において、光源又は光源からの光を反射するミ
ラーが該電解液容器外側に配置し、かつ該電解液容器の
光透過率が８０％以上であり、該絶縁膜表面での光量の
均一性が８０％以上であることを特徴とする絶縁膜欠陥
検出装置。9. The apparatus used in the method for detecting an insulating film defect according to claim 5, wherein a light source or a mirror for reflecting light from the light source is disposed outside the electrolyte container, and the light transmittance of the electrolyte container is reduced. 80% or more, and the uniformity of the amount of light on the surface of the insulating film is 80% or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000381650A JP2002184830A (en) | 2000-12-11 | 2000-12-11 | Method of detecting defect in insulating film and device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000381650A JP2002184830A (en) | 2000-12-11 | 2000-12-11 | Method of detecting defect in insulating film and device thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002184830A true JP2002184830A (en) | 2002-06-28 |
Family
ID=18849612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000381650A Pending JP2002184830A (en) | 2000-12-11 | 2000-12-11 | Method of detecting defect in insulating film and device thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002184830A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006098362A (en) * | 2004-09-30 | 2006-04-13 | Kobe Steel Ltd | Fault detection method for insulating film |
| CN111074352A (en) * | 2019-12-19 | 2020-04-28 | 西安奕斯伟硅片技术有限公司 | Wafer processing method and apparatus |
-
2000
- 2000-12-11 JP JP2000381650A patent/JP2002184830A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006098362A (en) * | 2004-09-30 | 2006-04-13 | Kobe Steel Ltd | Fault detection method for insulating film |
| CN111074352A (en) * | 2019-12-19 | 2020-04-28 | 西安奕斯伟硅片技术有限公司 | Wafer processing method and apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100596189B1 (en) | Field emission-type electron source and manufacturing method thereof and display using the electron source | |
| JP3902883B2 (en) | Nanostructure and manufacturing method thereof | |
| JPH10158900A (en) | Electrode, electrolytic etching device using this electrode, electrolytic etching device and production of photovoltaic element | |
| Frese et al. | Electrochemical measurements of interface states at the GaAs/oxide interface | |
| JP2002184830A (en) | Method of detecting defect in insulating film and device thereof | |
| US5616233A (en) | Method for making a fluorinated silicon dioxide layer on silicon substrate by anodic oxidation at room temperature | |
| Ye et al. | Electrochemical investigation of the surface energy: Effect of the HF concentration on electroless silver deposition onto p-Si (1 1 1) | |
| De Mierry et al. | Defects Induced in p‐Type Silicon by Photocathodic Charging of Hydrogen | |
| CN107293581B (en) | Thin film transistor and manufacturing method and application method thereof | |
| CN112002753B (en) | Gate unit and preparation method thereof, preparation method of array substrate and display mechanism | |
| WO2006001156A1 (en) | Method for evaluating soi wafer | |
| US4726885A (en) | Selenidization passivation | |
| Goryachev et al. | Electrolytic fabrication of porous silicon with the use of internal current source | |
| Gruszecki et al. | Preparation of thin films of polycrystalline CdSe for solar energy conversion: II. Experimental | |
| Muñoz et al. | Kinetics of oxide growth and oxygen evolution on p-Si in neutral aqueous electrolytes | |
| JP2005324325A (en) | Nanostructure, electron emitting device, and method of producing carbon nanotube device | |
| JP2004140129A (en) | Method and apparatus for detecting fault of insulating film | |
| JPH10270516A (en) | Semiconductor-wafer evaluation and its device | |
| JP4135309B2 (en) | Manufacturing method of field emission electron source | |
| JP2697674B2 (en) | Manufacturing method of photoconductive infrared detecting element | |
| JP2012060066A (en) | SEMICONDUCTOR DEVICE HAVING AlGaN OXIDE FILM AND MANUFACTURING METHOD OF THE SAME | |
| JPH05152271A (en) | Method of treating surface to be etched of semiconductor or semi-insulating body, integrated circuit obtained through said method and anode oxidizing device for carrying out said method | |
| JP3430165B2 (en) | Method for manufacturing electron-emitting device | |
| US6352939B1 (en) | Method for improving the electrical properties of a gate oxide | |
| JP3687520B2 (en) | Field emission electron source and manufacturing method thereof |