JP2002164463A - Wiring board and electronic device using the same - Google Patents
Wiring board and electronic device using the sameInfo
- Publication number
- JP2002164463A JP2002164463A JP2000362225A JP2000362225A JP2002164463A JP 2002164463 A JP2002164463 A JP 2002164463A JP 2000362225 A JP2000362225 A JP 2000362225A JP 2000362225 A JP2000362225 A JP 2000362225A JP 2002164463 A JP2002164463 A JP 2002164463A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plating layer
- nickel
- nickel plating
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子等の電
子部品を搭載するために用いられる配線基板およびこの
配線基板上に半導体素子等の電子部品を搭載して成る電
子装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for mounting electronic parts such as semiconductor elements, and an electronic device comprising electronic parts such as semiconductor elements mounted on the wiring board.
【０００２】[0002]
【従来の技術】従来、半導体素子等の電子部品を搭載す
るために用いられる配線基板は、例えばガラス−エポキ
シ板等から成る絶縁板やエポキシ樹脂等から成る絶縁層
を複数層積層して成る絶縁基体の内部および表面に銅箔
等から成る配線導体を設けて成る。この配線基板におい
ては、絶縁基体表面の配線導体の一部が半導体素子等の
電子部品の電極を接続するための電子部品接続用パッド
や外部電気回路基板に接続される外部接続用パッドとし
て供され、これらの電子部品接続用パッドや外部接続用
パッドには電子部品や外部電気回路基板との接合を容易
なものとするために例えば鉛−錫共晶合金等の錫を含有
する半田が予め接合される場合がある。2. Description of the Related Art Conventionally, a wiring board used for mounting an electronic component such as a semiconductor element has an insulating plate formed by laminating a plurality of insulating layers made of, for example, a glass-epoxy plate or an epoxy resin. A wiring conductor made of copper foil or the like is provided inside and on the surface of the base. In this wiring board, a part of the wiring conductor on the surface of the insulating base is used as an electronic component connection pad for connecting an electrode of an electronic component such as a semiconductor element or an external connection pad connected to an external electric circuit board. In order to facilitate bonding with the electronic components and the external electric circuit board, for example, a solder containing tin such as a lead-tin eutectic alloy is pre-bonded to these electronic component connection pads and external connection pads. May be done.
【０００３】なお、このような配線基板において電子部
品接続用パッドや外部接続用パッドに半田を接合するに
は、配線導体の露出表面に厚みが0.5〜10μｍ程度のニ
ッケルめっき層および厚みが0.01〜0.8μｍ程度の金め
っき層を順次被着させておくとともに、その上に半田を
溶融させて付着させる方法が採用される。このとき、金
めっき層は溶融した半田内に拡散吸収されて消滅し、ま
たニッケルめっき層と半田との間には厚みの不均一なニ
ッケル−錫合金層が形成される。In order to bond the solder to electronic component connection pads and external connection pads on such a wiring board, a nickel plating layer having a thickness of about 0.5 to 10 μm and a thickness of 0.01 to 10 μm are formed on the exposed surface of the wiring conductor. A method is adopted in which a gold plating layer of about 0.8 μm is sequentially deposited, and solder is melted and deposited thereon. At this time, the gold plating layer is diffused and absorbed in the molten solder and disappears, and a nickel-tin alloy layer having an uneven thickness is formed between the nickel plating layer and the solder.
【０００４】そして、この配線基板は、電子部品接続用
パッドに電子部品の電極を半田を介して接続して電子部
品を搭載することにより電子装置となり、この電子装置
は外部接続用パッドを外部電気回路基板の配線導体に半
田を介して接続することにより外部電気回路基板に実装
される。The wiring board is an electronic device by connecting the electrodes of the electronic component to the electronic component connection pads via solder and mounting the electronic component. The electronic device uses the external connection pads for the external electrical connection. It is mounted on an external electric circuit board by connecting to a wiring conductor of the circuit board via solder.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、この従
来の配線基板によると、これに半導体素子等の電子部品
を搭載して電子装置となした後、これを外部電気回路基
板に実装して半導体素子等の電子部品を長期間にわたり
作動させると、半導体素子等の電子部品が作動時に発生
する熱等に起因する熱応力が半田と電子部品接続用パッ
ドや外部接続用パッドとの間に繰返し印加されることに
よりニッケルめっき層と半田との間で剥離が生じ、その
ため、搭載する電子部品を外部電気回路に長期間にわた
り正常に接続することができないという問題点を有して
いた。However, according to the conventional wiring board, an electronic device such as a semiconductor element is mounted on the wiring board to form an electronic device, which is then mounted on an external electric circuit board. When an electronic component such as a semiconductor device is operated for a long period of time, thermal stress caused by heat generated when the electronic component such as a semiconductor device is operated is repeatedly applied between the solder and the electronic component connection pad or the external connection pad. This causes peeling between the nickel plating layer and the solder, so that the mounted electronic component cannot be normally connected to an external electric circuit for a long period of time.
【０００６】そこで、本発明者は、鋭意研究の結果、ニ
ッケルめっき層と半田との間にニッケル−錫合金層が実
質的に殆ど形成されていないニッケル−錫合金の非形成
部が特にニッケルめっき層表面の結晶粒界に沿って数多
く存在し、このようなニッケル−錫合金の非形成部から
ニッケルめっき層と半田との剥離が発生しやすいという
ことを見出し、本発明を完成するに至った。Accordingly, the present inventor has conducted intensive studies, and as a result, the nickel-tin alloy non-formed portion where substantially no nickel-tin alloy layer is formed between the nickel plating layer and the solder is particularly nickel plated. It has been found that there are many along the crystal grain boundaries on the layer surface, and that the nickel-plated layer and the solder are easily peeled off from the non-formed portion of such a nickel-tin alloy, and the present invention has been completed. .
【０００７】本発明は、かかる上述の問題点に鑑み完成
されたものであり、その目的は、ニッケルめっき層と半
田との間で剥離が発生することがなく、搭載する電子部
品を外部電気回路に長期間にわたり、正常に接続するこ
とが可能な配線基板および電子装置を提供することにあ
る。The present invention has been completed in view of the above-mentioned problems, and an object of the present invention is to prevent the peeling between the nickel plating layer and the solder from occurring and to mount the mounted electronic component on an external electric circuit. Another object of the present invention is to provide a wiring board and an electronic device that can be connected normally for a long period of time.
【０００８】[0008]
【課題を解決するための手段】本発明の配線基板は、絶
縁基体に形成した配線導体の表面に被着させたニッケル
めっき層上に錫を含有する半田を接合させて成る配線基
板であって、ニッケルめっき層と半田との間の90％以上
の面積において厚みが0.05〜0.5μｍのニッケル−錫合
金層が形成されていることを特徴とするものである。A wiring board according to the present invention is a wiring board formed by joining a solder containing tin on a nickel plating layer adhered to the surface of a wiring conductor formed on an insulating base. A nickel-tin alloy layer having a thickness of 0.05 to 0.5 μm is formed in an area of 90% or more between the nickel plating layer and the solder.
【０００９】また、本発明の電子装置は、絶縁基体に形
成した配線導体の表面に被着させたニッケルめっき層上
に錫を含有する半田を接合させて成る配線基板に電子部
品を搭載して成る電子装置であって、ニッケルめっき層
と半田との間の90％以上の面積において厚みが0.05〜0.
5μｍのニッケル−錫合金層が形成されていることを特
徴とするものである。Further, the electronic device of the present invention is provided by mounting an electronic component on a wiring board formed by joining a solder containing tin on a nickel plating layer adhered to a surface of a wiring conductor formed on an insulating base. An electronic device comprising: a nickel plating layer and a solder having a thickness of 0.05 to 0.
A nickel-tin alloy layer having a thickness of 5 μm is formed.
【００１０】本発明の配線基板によれば、ニッケルめっ
き層と半田との間の90％以上の面積において厚みが0.05
〜0.5μｍのニッケル−錫合金層が形成されていること
から、これに電子部品を搭載した後、外部電気回路基板
に実装して電子部品を長期間にわたり作動させたとして
も、ニッケルめっき層と半田との間に剥離が発生するよ
うなことはない。According to the wiring board of the present invention, the thickness is 0.05% in the area of 90% or more between the nickel plating layer and the solder.
Since the nickel-tin alloy layer of ~ 0.5 μm is formed, after mounting electronic components on this, even if the electronic components are mounted on an external electric circuit board and operated for a long time, the nickel plating layer and There is no separation between the solder and the solder.
【００１１】また、本発明の電子装置によれば、ニッケ
ルめっき層と半田との間の90％以上の面積において厚み
が0.05〜0.5μｍのニッケル−錫合金層が形成されてい
ることから、これを外部電気回路基板に実装して電子部
品を長期間にわたり作動させたとしても、ニッケルめっ
き層と半田との間に剥離が発生するようなことはない。According to the electronic device of the present invention, a nickel-tin alloy layer having a thickness of 0.05 to 0.5 μm is formed in an area of 90% or more between the nickel plating layer and the solder. Even if the electronic component is operated for a long period of time by mounting the electronic component on an external electric circuit board, peeling does not occur between the nickel plating layer and the solder.
【００１２】[0012]
【発明の実施の形態】つぎに、本発明を添付の図面に基
づき詳細に説明する。図１は、本発明を半導体素子を搭
載するための配線基板およびこれに半導体素子を搭載し
た電子装置に適用した場合の実施の形態の一例を示す断
面図であり、１は絶縁基体、２は配線導体である。この
絶縁基体１と配線導体２とで本発明の配線基板が構成さ
れ、これに半導体素子３を搭載することにより本発明の
電子装置が形成される。Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment in which the present invention is applied to a wiring board for mounting a semiconductor element and an electronic device having the semiconductor element mounted on the wiring board. It is a wiring conductor. The insulating substrate 1 and the wiring conductor 2 constitute the wiring board of the present invention, and the semiconductor device 3 is mounted thereon to form the electronic device of the present invention.
【００１３】絶縁基体１は、例えばガラス繊維を縦横に
織り込んだガラス織物にエポキシ樹脂やビスマレイミド
トリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状
の芯体１ａの上下面にエポキシ樹脂やビスマレイミドト
リアジン樹脂等の熱硬化性樹脂から成る絶縁層１ｂをそ
れぞれ複数層ずつ積層して成り、その上面から下面にか
けては銅箔から成る複数の配線導体２が形成されてい
る。The insulating base 1 is made of a glass fabric in which glass fibers are woven vertically and horizontally, and is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. A plurality of insulating layers 1b each made of a thermosetting resin such as a bismaleimide triazine resin are laminated, and a plurality of wiring conductors 2 made of copper foil are formed from the upper surface to the lower surface.
【００１４】絶縁基体１を構成する芯体１ａは、厚みが
0.3〜1.5ｍｍ程度であり、その上面から下面にかけて直
径が0.2〜1.0ｍｍ程度の複数の貫通孔４を有している。
そして、その上下面および各貫通孔４の内壁には配線導
体２の一部が被着されており、上下面の配線導体２が貫
通孔４を介して電気的に接続されている。The core 1a constituting the insulating base 1 has a thickness of
It has a plurality of through holes 4 having a diameter of about 0.2 to 1.0 mm from the upper surface to the lower surface of about 0.3 to 1.5 mm.
A part of the wiring conductor 2 is attached to the upper and lower surfaces and the inner wall of each through hole 4, and the upper and lower wiring conductors 2 are electrically connected through the through hole 4.
【００１５】このような芯体１ａは、ガラス織物に未硬
化の熱硬化性樹脂を含浸させたシートを熱硬化させた
後、これに上面から下面にかけてドリル加工を施すこと
により製作される。なお、芯体１ａ上下面の配線導体２
は、芯体１ａ用のシートの上下全面に厚みが５〜50μｍ
程度の銅箔を貼着しておくとともにこの銅箔をシートの
硬化後にエッチング加工することにより所定のパターン
に形成される。また、貫通孔４内壁の配線導体２は、芯
体１ａに貫通孔４を設けた後に、この貫通孔４内壁に無
電解めっき法および電解めっき法により厚みが５〜50μ
ｍ程度の銅箔を析出させることにより形成される。Such a core 1a is manufactured by heat-curing a sheet of glass fabric impregnated with an uncured thermosetting resin, and then drilling the sheet from the upper surface to the lower surface. The wiring conductors 2 on the upper and lower surfaces of the core 1a
Has a thickness of 5 to 50 μm on the entire upper and lower surfaces of the sheet for the core 1a.
A predetermined degree of copper foil is adhered, and the copper foil is formed into a predetermined pattern by etching after curing of the sheet. The wiring conductor 2 on the inner wall of the through-hole 4 has a thickness of 5 to 50 μm after the through-hole 4 is formed in the core body 1 a by an electroless plating method and an electrolytic plating method.
It is formed by depositing about m of copper foil.
【００１６】さらに、芯体１ａは、その貫通孔４の内部
にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱
硬化性樹脂から成る樹脂柱５が充填されている。樹脂柱
５は、貫通孔４を塞ぐことにより貫通孔４の直上および
直下に絶縁層１ｂを形成可能とするためのものであり、
未硬化のペースト状の熱硬化性樹脂を貫通孔４内にスク
リーン印刷法により充填し、これを熱硬化させた後、そ
の上下面を略平坦に研磨することにより形成される。そ
して、この樹脂柱５を含む芯体１ａの上下面に絶縁層１
ｂが積層されている。Further, in the core 1a, a resin column 5 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is filled in the through hole 4. The resin pillar 5 is for closing the through-hole 4 so that the insulating layer 1b can be formed directly above and directly below the through-hole 4.
An uncured paste-like thermosetting resin is filled in the through-hole 4 by a screen printing method, thermally cured, and then, the upper and lower surfaces thereof are polished to be substantially flat. The insulating layer 1 is formed on the upper and lower surfaces of the core body 1a including the resin column 5.
b is laminated.
【００１７】芯体１ａの上下面に積層された絶縁層１ｂ
は、それぞれの厚みが20〜60μｍ程度であり、各層の上
面から下面にかけて直径が30〜100μｍ程度の複数の貫
通孔６を有している。これらの絶縁層１ｂは、配線導体
２を高密度に配線するための絶縁間隔を提供するための
ものであり、最表層を除く絶縁層１ｂにはその表面およ
び貫通孔６内に配線導体２の一部が被着されている。そ
して、上層の配線導体２と下層の配線導体２とを貫通孔
６を介して電気的に接続することにより高密度配線を立
体的に形成可能としている。このような絶縁層１ｂは、
厚みが20〜60μｍ程度の未硬化の熱硬化性樹脂のフィル
ムを芯体１ａ上下面に貼着し、これを熱硬化させるとと
もにレーザー加工により貫通孔６を穿孔し、さらにその
上に同様にして次の絶縁層１ｂを順次積み重ねることに
よって形成される。なお、各絶縁層１ｂ表面および貫通
孔６内に被着された配線導体２は、各絶縁層１ｂを形成
する毎に各絶縁層１ｂの表面および貫通孔６内に５〜50
μｍ程度の厚みの銅箔を公知のセミアディティブ法やフ
ルアディティブ法等のパターン形成法により所定のパタ
ーンに被着させることによって形成される。Insulating layer 1b laminated on upper and lower surfaces of core 1a
Has a plurality of through holes 6 each having a thickness of about 20 to 60 μm and a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. These insulating layers 1b are provided to provide an insulating interval for wiring the wiring conductors 2 at a high density, and the insulating layers 1b except for the outermost layer are provided on the surface and in the through holes 6 of the wiring conductors 2. Some have been deposited. By electrically connecting the upper layer wiring conductor 2 and the lower layer wiring conductor 2 through the through-hole 6, high-density wiring can be formed three-dimensionally. Such an insulating layer 1b is
A film of an uncured thermosetting resin having a thickness of about 20 to 60 μm is attached to the upper and lower surfaces of the core body 1a, and the thermosetting resin is thermally cured, and a through hole 6 is formed by laser processing. It is formed by sequentially stacking the next insulating layers 1b. The wiring conductor 2 attached to the surface of each insulating layer 1b and the inside of the through-hole 6 is formed on the surface of each insulating layer 1b and the inside of the through-hole 6 every time the insulating layer 1b is formed.
It is formed by applying a copper foil having a thickness of about μm to a predetermined pattern by a known pattern forming method such as a semi-additive method or a full-additive method.
【００１８】絶縁基体１の上面から下面にかけて形成さ
れた配線導体２は、半導体素子３の各電極を外部電気回
路基板に接続するための導電路として機能し、絶縁基体
１の上面に露出している部位が半導体素子３の各電極に
鉛−錫共晶合金から成る半田７を介して接続される電子
部品接続用パッド２ａを、絶縁基体１の下面に露出した
部位が外部電気回路基板に鉛−錫共晶合金から成る半田
８を介して接続される外部接続用パッド２ｂを形成して
いる。The wiring conductor 2 formed from the upper surface to the lower surface of the insulating base 1 functions as a conductive path for connecting each electrode of the semiconductor element 3 to an external electric circuit board, and is exposed on the upper surface of the insulating base 1. The exposed portion on the lower surface of the insulating base 1 is connected to the external electric circuit board by connecting the electronic component connecting pad 2a connected to each electrode of the semiconductor element 3 to the respective electrodes of the semiconductor element 3 via solder 7 made of a lead-tin eutectic alloy. Forming external connection pads 2b connected via a solder 8 made of a tin eutectic alloy.
【００１９】そして、この配線基板においては、電子部
品接続用パッド２ａに半導体素子３の各電極を半田７を
介して接続して半導体素子３を搭載することによって電
子装置となり、この電子装置における外部接続用パッド
２ｂを外部電気回路基板の配線導体に半田８を介して接
続することにより本発明の電子装置が外部電気回路基板
に実装されることとなる。In this wiring board, the electrodes of the semiconductor element 3 are connected to the electronic component connection pads 2a via the solder 7, and the semiconductor element 3 is mounted on the wiring board to form an electronic device. By connecting the connection pads 2b to the wiring conductors of the external electric circuit board via the solder 8, the electronic device of the present invention is mounted on the external electric circuit board.
【００２０】さらに、本発明の配線基板および電子装置
においては、半田７は半導体素子３を搭載する前に電子
部品接続用パッド２ａに予め接合されており、半田８は
外部電気回路基板に実装する前に外部接続用パッド２ｂ
に予め接合されている。それにより、電子部品接続用パ
ット２ａと半導体素子３の電極との接続および外部接続
用パッド２ｂと外部電気回路基板の配線導体との接続の
作業性が極めて良好なものとなっている。Further, in the wiring board and the electronic device of the present invention, the solder 7 is previously bonded to the electronic component connection pad 2a before mounting the semiconductor element 3, and the solder 8 is mounted on an external electric circuit board. Before the external connection pad 2b
Previously joined. Thereby, workability of connection between the electronic component connection pad 2a and the electrode of the semiconductor element 3 and connection between the external connection pad 2b and the wiring conductor of the external electric circuit board is extremely good.
【００２１】なお、電子部品接続用パッド２ａおよび外
部接続用パッド２ｂの表面には、図２に要部拡大断面図
で示すように、厚みが0.5〜10μｍ程度のニッケルめっ
き層９が被着されており、その上に厚みが0.05〜５μｍ
程度のニッケル−錫合金層10を介して半田７・８が接合
されている。A nickel plating layer 9 having a thickness of about 0.5 to 10 .mu.m is applied to the surfaces of the electronic component connection pads 2a and the external connection pads 2b, as shown in FIG. With a thickness of 0.05 to 5 μm
Solder 7.8 is joined via a nickel-tin alloy layer 10 of a certain degree.
【００２２】このように電子部品接続用パッド２ａおよ
び外部接続用パッド２ｂに半田７・８を接合させるに
は、配線導体２の露出表面に例えばリンを４〜12重量％
程度含有する無電解ニッケルめっき層９を0.5〜10μｍ
の厚みに被着させるとともに、このニッケルめっき層９
上に厚みが0.01〜0.8μｍの無電解金めっき層を被着さ
せておき、その上に半田を溶融させて付着させる方法が
採用される。このとき、ニッケルめっき層９上の無電解
金めっき層は半田中に拡散吸収されて消滅し、また、ニ
ッケルめっき層９中のニッケルと半田７・８中の錫とが
反応してニッケルめっき層９と半田７・８との間にニッ
ケル−錫の合金層10が形成される。In order to bond the solder 7.8 to the electronic component connection pad 2a and the external connection pad 2b in this way, for example, phosphorus is added to the exposed surface of the wiring conductor 2 by 4 to 12% by weight.
0.5 to 10 μm of electroless nickel plating layer 9 containing
And the nickel plating layer 9
A method is adopted in which an electroless gold plating layer having a thickness of 0.01 to 0.8 μm is applied thereon, and solder is melted and attached thereon. At this time, the electroless gold plating layer on the nickel plating layer 9 is diffused and absorbed in the solder and disappears, and nickel in the nickel plating layer 9 reacts with tin in the solders 7.8 to form the nickel plating layer. A nickel-tin alloy layer 10 is formed between the solder 9 and the solders 7 and 8.
【００２３】この場合、無電解ニッケルめっき層９用の
無電解めっき液としては、硫酸ニッケル40ｇ／ｌ，クエ
ン酸ナトリウム24ｇ／ｌ，酢酸ナトリウム14ｇ／ｌ，次
亜リン酸ナトリウム20ｇ／ｌ，塩化アンモニウム５ｇ／
ｌから成り、温度が50〜90℃の無電解ニッケルめっき液
を用いればよく、無電解金めっき層用の無電解金めっき
液としては、シアン化金カリウム5.0ｇ／ｌ，クエン酸
カリウム50.0ｇ／ｌ，エチレンジアミンテトラアセティ
クアシッド5.0ｇ／ｌから成り、温度が50〜90℃の無電
解金めっき液を用いればよい。In this case, the electroless plating solution for the electroless nickel plating layer 9 includes nickel sulfate 40 g / l, sodium citrate 24 g / l, sodium acetate 14 g / l, sodium hypophosphite 20 g / l, chloride Ammonium 5g /
and an electroless nickel plating solution having a temperature of 50 to 90 ° C. may be used. As the electroless gold plating solution for the electroless gold plating layer, potassium cyanide 5.0 g / l and potassium citrate 50.0 g / L, 5.0 g / l of ethylenediaminetetraacetate and a temperature of 50 to 90 ° C may be used.
【００２４】なお、ニッケルめっき層９は、その厚みが
0.5μｍ未満では、電子部品接続用パッド２ａおよび外
部接続用パッド２ｂを良好に被覆することができずに、
配線導体２の表面に酸化や変色をきたして半田７・８と
の接合が弱いものとなる傾向にあり、他方、10μｍを超
えると、ニッケルめっき層９の内部応力によりニッケル
めっき層９にクラックや剥がれが発生してしまいやす
い。したがって、ニッケルめっき層９の厚みは0.5〜10
μｍの範囲が好ましい。The nickel plating layer 9 has a thickness of
When the thickness is less than 0.5 μm, the electronic component connection pad 2a and the external connection pad 2b cannot be covered well,
The surface of the wiring conductor 2 tends to be oxidized or discolored and the bonding with the solders 7.8 tends to be weak. On the other hand, if it exceeds 10 μm, the nickel plating layer 9 has cracks due to the internal stress of the nickel plating layer 9. Peeling is likely to occur. Therefore, the thickness of the nickel plating layer 9 is 0.5 to 10
The range of μm is preferred.
【００２５】また、ニッケルめっき層９中のリンの含有
量が４重量％未満であると、ニッケルめっきの析出速度
が遅くなり、所定の厚みのニッケルめっき層９を得るた
めに長時間を要するので配線基板の生産性が極めて悪く
なり、他方、12重量％を超えると、ニッケルめっき層９
上に被着させる金めっき層との反応性が悪くなり、ニッ
ケルめっき層９を金めっき層で良好に被覆することが困
難となる傾向にある。したがって、ニッケルめっき層９
中のリンの含有量は、４〜12重量％の範囲が好ましい。On the other hand, if the content of phosphorus in the nickel plating layer 9 is less than 4% by weight, the deposition rate of nickel plating becomes slow, and it takes a long time to obtain the nickel plating layer 9 having a predetermined thickness. When the productivity of the wiring board becomes extremely poor, on the other hand, when it exceeds 12% by weight, the nickel plating layer 9
The reactivity with the gold plating layer to be adhered thereon becomes poor, and it tends to be difficult to cover the nickel plating layer 9 with the gold plating layer satisfactorily. Therefore, the nickel plating layer 9
The content of phosphorus therein is preferably in the range of 4 to 12% by weight.
【００２６】さらに、ニッケルめっき層９は、その表面
の結晶粒界に沿って形成される溝の深さを0.2μｍ以下
としておくことが好ましい。ニッケルめっき層９表面の
結晶粒界に沿って形成される溝の深さが0.2μｍを超え
ると、ニッケルめっき層９上に無電解金めっき層を被着
させる際に、この粒界に沿った部位でニッケルめっき層
９中のニッケルが局所的に多量に溶出して腐食が発生し
やすい。そのような腐食が発生すると、電子部品接続用
パッド２ａおよび外部接続用パッド２ｂに半田７・８を
接合させた際に、この部位でのニッケルめっき層９と半
田７・８との反応性が阻害されてニッケル−錫合金層10
が実質的に殆ど形成されないニッケル−錫合金の非形成
部が広い面積で形成されてこのニッケル−錫合金の非形
成部から剥離が発生しやすくなり、その結果、ニッケル
めっき層９と半田７・８との接合強度が劣ったものとな
る。なお、ニッケルめっき層９表面の結晶粒界に沿って
形成される溝の深さを0.2μｍ以下とするには、たとえ
ばニッケルめっき液中に非イオン性の界面活性剤を数ｐ
ｐｍ添加し、析出するニッケルめっき層９とめっき液と
の界面張力を小さなものとした状態でめっきをすること
により、溝の深さを0.2μｍ以下とすることができる。Further, it is preferable that the depth of the groove formed along the crystal grain boundary on the surface of the nickel plating layer 9 be 0.2 μm or less. When the depth of the groove formed along the crystal grain boundary on the surface of the nickel plating layer 9 exceeds 0.2 μm, when the electroless gold plating layer is deposited on the nickel plating layer 9, Nickel in the nickel plating layer 9 is locally eluted in a large amount at portions, and corrosion is likely to occur. When such corrosion occurs, when the solders 7.8 are joined to the electronic component connection pads 2a and the external connection pads 2b, the reactivity between the nickel plating layer 9 and the solders 7.8 at these portions is reduced. Inhibited nickel-tin alloy layer 10
The nickel-tin alloy non-formed portion where substantially no nickel is formed is formed in a large area, and the nickel-tin alloy non-formed portion is easily peeled off. As a result, the nickel plating layer 9 and the solder 7. 8 is inferior in bonding strength. In order to reduce the depth of the groove formed along the crystal grain boundary on the surface of the nickel plating layer 9 to 0.2 μm or less, for example, a non-ionic surfactant is added to the nickel plating solution by several p.
By adding pm and performing plating with the interfacial tension between the nickel plating layer 9 to be deposited and the plating solution reduced, the depth of the groove can be reduced to 0.2 μm or less.
【００２７】また、ニッケルめっき層９と半田７・８と
の間に形成されたニッケル−錫の合金層10は、その厚み
を0.05〜５μｍ程度としている。そして、ニッケルめっ
き層９と半田７・８との間の90％以上の面積に形成され
ており、そのことが重要である。ニッケルめっき層９と
半田７・８との間の90％以上の面積に厚みが0.05〜５μ
ｍのニッケル−錫合金層10が形成されていることから、
半導体素子３を搭載した後、これを外部電気回路基板に
実装して半導体素子３を長期間にわたり作動させたとし
ても、半導体素子３が作動時に発生する熱等による応力
によってニッケルめっき層９と半田７・８との間で剥離
が発生するようなことはない。The thickness of the nickel-tin alloy layer 10 formed between the nickel plating layer 9 and the solders 7.8 is about 0.05 to 5 μm. And it is formed in the area of 90% or more between the nickel plating layer 9 and the solders 7, 8, which is important. The thickness of the nickel plating layer 9 and the solder 7.8 is 0.05 to 5 μm in the area of 90% or more.
m nickel-tin alloy layer 10 is formed,
Even after the semiconductor element 3 is mounted and mounted on an external electric circuit board and the semiconductor element 3 is operated for a long period of time, even if the semiconductor element 3 is operated for a long time, stress generated by heat or the like generated when the semiconductor element 3 is operated causes the nickel plating layer 9 and the solder to be soldered. There is no occurrence of separation between 7.8 and 7.8.
【００２８】なお、ニッケルめっき層９と半田７・８と
の間の90％以上の面積に形成されるニッケル−錫合金層
10の厚みが0.05μｍ未満では、ニッケルめっき層９とニ
ッケル−錫合金層10との密着が悪く、両者の間から剥離
が生じることがあり、他方、５μｍを超えると、強度的
に脆くて弱いニッケル−錫合金層10の厚みが厚いため、
ニッケル−錫合金層10から剥離が生じることがある。し
たがって、ニッケルめっき層９と半田７・８との間の90
％以上の面積に形成されるニッケル−錫合金層10の厚み
は0.05〜５μｍの範囲に特定される。The nickel-tin alloy layer formed in an area of 90% or more between the nickel plating layer 9 and the solder 7.8
If the thickness of the layer 10 is less than 0.05 μm, the adhesion between the nickel plating layer 9 and the nickel-tin alloy layer 10 is poor, and peeling may occur between the two. On the other hand, if it exceeds 5 μm, the layer is brittle and weak in strength. Because the thickness of the nickel-tin alloy layer 10 is large,
Peeling may occur from the nickel-tin alloy layer 10. Therefore, the distance between the nickel plating layer 9 and the solders 7.8 is 90%.
%, The thickness of the nickel-tin alloy layer 10 formed in the area of 0.05% to 5 μm is specified.
【００２９】さらに、ニッケルめっき層９と半田７・８
との間に形成される厚みが0.05〜５μｍのニッケル−錫
合金層10の形成面積がニッケルめっき層９と半田７・８
との間の面積の90％未満であると、ニッケルめっき層９
と半田７・８との間に厚みが0.05〜５μｍのニッケル−
錫合金層が形成されていない領域からニッケルめっき層
９と半田７・８との間に剥離が発生しやすいものとな
る。したがって、ニッケルめっき層９と半田７・８との
間に形成される厚みが0.05〜５μｍのニッケル−錫合金
層10の形成面積はニッケルめっき層９と半田７・８との
間の面積の90％以上に特定される。Further, the nickel plating layer 9 and the solder 7.8
The nickel-tin alloy layer 10 having a thickness of 0.05 to 5 μm formed between the nickel plating layer 9 and the solder 7.8
If less than 90% of the area between the nickel plating layer 9
Nickel having a thickness of 0.05 to 5 μm between the solder and the solder 7.8
Peeling is likely to occur between the nickel plating layer 9 and the solder 7.8 from the region where the tin alloy layer is not formed. Therefore, the formation area of the nickel-tin alloy layer 10 having a thickness of 0.05 to 5 μm formed between the nickel plating layer 9 and the solders 7.8 is 90% of the area between the nickel plating layer 9 and the solders 7.8. % Or more.
【００３０】このように、ニッケルめっき層９と半田７
・８との間の90％以上の面積に厚みが0.05〜５μｍのニ
ッケル−錫合金層10を形成するには、上述のようにニッ
ケルめっき層９表面の結晶粒界に沿って形成される溝の
深さを0.2μｍ以下とする等してニッケルめっき層９の
結晶粒界に沿った腐食の発生をなくすとともに、このニ
ッケルめっき層９上に半田を溶融させる時間および温度
を適宜調整すればよい。As described above, the nickel plating layer 9 and the solder 7
In order to form the nickel-tin alloy layer 10 having a thickness of 0.05 to 5 μm in an area of 90% or more between 8 and 8, the grooves formed along the crystal grain boundaries on the surface of the nickel plating layer 9 as described above. In this case, the depth of the surface of the nickel plating layer 9 is set to 0.2 μm or less to prevent corrosion along the crystal grain boundaries of the nickel plating layer 9, and the time and temperature for melting the solder on the nickel plating layer 9 may be appropriately adjusted. .
【００３１】かくして、本発明の配線基板および電子装
置によれば、搭載する電子部品を外部電気回路に長期間
にわたり正常に接続することができる。Thus, according to the wiring board and the electronic device of the present invention, the mounted electronic components can be normally connected to the external electric circuit for a long time.
【００３２】なお、本発明は、上述の実施の形態の一例
に限定されるものではなく、本発明の要旨を逸脱しない
範囲であれば種々の変更は可能であり、例えば上述の実
施の形態の一例では、絶縁基体１はガラス織物に熱硬化
性樹脂を含浸させた材料および熱硬化性樹脂から形成さ
れていたが、絶縁基体１は、セラミックス材料等の他の
絶縁材料から形成されていてもよく、また、配線導体２
としては、タングステンやモリブデン・銅・銀等の金属
粉末のメタライズ導体等の他の導電材料を使用すること
ができる。Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. In one example, the insulating substrate 1 is formed of a material obtained by impregnating a glass fabric with a thermosetting resin and a thermosetting resin. However, the insulating substrate 1 may be formed of another insulating material such as a ceramic material. Well, wiring conductor 2
For example, other conductive materials such as metallized conductors of metal powders such as tungsten, molybdenum, copper, and silver can be used.
【００３３】[0033]
【発明の効果】本発明の配線基板および電子装置によれ
ば、ニッケルめっき層と半田との間の90％以上の面積に
おいて厚みが0.05〜５μｍのニッケル−錫合金層が形成
されていることから、これを外部電気回路基板に実装し
て電子部品を長期間にわたり作動させたとしても、ニッ
ケルめっき層と半田との間に剥離が発生するようなこと
はなく、したがって、搭載する電子部品を長期間にわた
り正常に接続することが可能である。According to the wiring board and the electronic device of the present invention, a nickel-tin alloy layer having a thickness of 0.05 to 5 μm is formed in an area of 90% or more between the nickel plating layer and the solder. However, even if this is mounted on an external electric circuit board and the electronic component is operated for a long period of time, there is no occurrence of peeling between the nickel plating layer and the solder. It is possible to connect normally over a period.
【図１】本発明の配線基板および電子装置の実施形態の
一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a wiring board and an electronic device of the present invention.
【図２】図１に示す配線基板および電子装置の要部拡大
断面図である。FIG. 2 is an enlarged sectional view of a main part of the wiring board and the electronic device shown in FIG. 1;
１・・・・・絶縁基体 ２・・・・・配線導体 ３・・・・・電子部品としての半導体素子 ７，８・・・半田 ９・・・・・ニッケルめっき層 10・・・・・ニッケル−錫合金層 1 Insulating substrate 2 Wiring conductor 3 Semiconductor element 7 as electronic component 7, 8 Solder 9 Nickel plating layer 10 Nickel-tin alloy layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/34 ５０１ Ｈ０１Ｌ 23/14 Ｒ Ｆターム(参考） 4E351 AA03 BB01 BB23 BB24 BB29 BB33 BB35 DD12 DD19 DD24 GG15 5E319 AA03 AB05 AC02 AC17 BB07 GG20 5E343 AA02 AA12 BB09 BB15 BB34 BB44 BB54 BB65 BB71 DD32 GG18 5F044 KK13 KK16 LL01 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/34 501 H01L 23/14 RF term (Reference) 4E351 AA03 BB01 BB23 BB24 BB29 BB33 BB35 DD12 DD19 DD24 GG15 5E319 AA03 AB05 AC02 AC17 BB07 GG20 5E343 AA02 AA12 BB09 BB15 BB34 BB44 BB54 BB65 BB71 DD32 GG18 5F044 KK13 KK16 LL01
Claims (2)
着させたニッケルめっき層上に錫を含有する半田を接合
させて成る配線基板であって、前記ニッケルめっき層と
半田との間の９０％以上の面積において厚みが０．０５
〜５μｍのニッケル−錫合金層が形成されていることを
特徴とする配線基板。1. A wiring board comprising a tin-containing solder bonded on a nickel plating layer adhered to a surface of a wiring conductor formed on an insulating base, wherein a solder between the nickel plating layer and the solder is provided. The thickness is 0.05 in the area of 90% or more.
A wiring substrate, wherein a nickel-tin alloy layer having a thickness of about 5 μm is formed.
載して成ることを特徴とする電子装置。2. An electronic device comprising an electronic component mounted on the wiring board according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000362225A JP4614528B2 (en) | 2000-11-29 | 2000-11-29 | Wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000362225A JP4614528B2 (en) | 2000-11-29 | 2000-11-29 | Wiring board manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| JP2002164463A true JP2002164463A (en) | 2002-06-07 |
| JP4614528B2 JP4614528B2 (en) | 2011-01-19 |
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| WO2011102498A2 (en) * | 2010-02-22 | 2011-08-25 | 株式会社小松製作所 | Thermoelectric generation module |
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|---|---|---|---|---|
| JPH11307565A (en) * | 1998-04-24 | 1999-11-05 | Mitsubishi Electric Corp | Electrode for semiconductor device, its manufacture, and the semiconductor device |
| JP2001060760A (en) * | 1999-06-18 | 2001-03-06 | Mitsubishi Electric Corp | Circuit electrode and formation process thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011102498A2 (en) * | 2010-02-22 | 2011-08-25 | 株式会社小松製作所 | Thermoelectric generation module |
| JP2011171668A (en) * | 2010-02-22 | 2011-09-01 | Komatsu Ltd | Thermoelectric power generation module |
| WO2011102498A3 (en) * | 2010-02-22 | 2011-10-20 | 株式会社小松製作所 | Thermoelectric generation module |
| US9559281B2 (en) | 2010-02-22 | 2017-01-31 | Komatsu Ltd. | Thermoelectric power module |
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