JP2002050735A - Three-dimensional laminated semiconductor device - Google Patents
Three-dimensional laminated semiconductor deviceInfo
- Publication number
- JP2002050735A JP2002050735A JP2000231214A JP2000231214A JP2002050735A JP 2002050735 A JP2002050735 A JP 2002050735A JP 2000231214 A JP2000231214 A JP 2000231214A JP 2000231214 A JP2000231214 A JP 2000231214A JP 2002050735 A JP2002050735 A JP 2002050735A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- semiconductor
- semiconductor device
- electrode
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、表裏面に貫通する
電極を有する例えばＬＳＩ（大規模集積回路）を、厚み
方向に積層してなる３次元積層半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional stacked semiconductor device in which, for example, an LSI (Large Scale Integrated Circuit) having electrodes penetrating on the front and back surfaces is stacked in the thickness direction.
【０００２】[0002]
【従来の技術】従来、３次元積層半導体装置としては、
図３に示すようなものがある。この３次元積層半導体装
置は、表裏面に貫通する貫通電極５１Ａ，５１Ｂ，５１
Ｃ・・・を有する第１乃至第３半導体チップ５１，５
２，５３を、厚み方向に積層して形成されている。上記
貫通電極５１Ａ，５１Ｂ，５１Ｃ・・・は、半導体チッ
プ５１，５２，５３の表裏面に対して直交するように、
かつ上記半導体チップ５１，５２，５３に関して、図３
において互いに同じ横方向位置に形成されている。そし
て、第１乃至第３半導体チップ５１，５２，５３の同じ
横方向位置にある貫通電極５１Ａ，５２Ａ，５３Ａ；５
１Ｂ，５２Ｂ，５３Ｂ；５１Ｃ，５２Ｃ，５３Ｃを接続
して、第１乃至第３半導体チップ５１，５２，５３を互
いに電気的に接続している。2. Description of the Related Art Conventionally, as a three-dimensional stacked semiconductor device,
There is one as shown in FIG. The three-dimensional stacked semiconductor device has through electrodes 51A, 51B, 51 penetrating on the front and back surfaces.
The first to third semiconductor chips 51 and 5 having C ...
2, 53 are laminated in the thickness direction. The through electrodes 51A, 51B, 51C... Are orthogonal to the front and back surfaces of the semiconductor chips 51, 52, 53, respectively.
In addition, regarding the semiconductor chips 51, 52 and 53, FIG.
Are formed at the same lateral position. Then, the through electrodes 51A, 52A, 53A at the same lateral position of the first to third semiconductor chips 51, 52, 53;
1B, 52B, 53B; 51C, 52C, 53C are connected, and the first to third semiconductor chips 51, 52, 53 are electrically connected to each other.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来の３次元積層半導体装置は、上記貫通電極５１Ａ，５
１Ｂ，５１Ｃ・・・は、半導体チップ５１，５２，５３
の表裏面に対して直交するように、かつ半導体チップ５
１，５２，５３において互いに同じ横方向位置に形成さ
れているので、貫通電極５１Ａ，５１Ｂ，５１Ｃのいず
れの貫通電極も第３半導体チップ５３に接続しているか
ら、例えばコントロール信号などを１つの半導体チップ
５１，５２，５３のみに直接印加できないという問題が
あった。However, the above-described conventional three-dimensional stacked semiconductor device has the above-described through-electrodes 51A and 51A.
1B, 51C... Are semiconductor chips 51, 52, 53
And the semiconductor chip 5
Since the through electrodes 51A, 51B, and 51C are connected to the third semiconductor chip 53 because the through electrodes 51, 52, and 53 are formed at the same horizontal position, the control signal is transmitted to one of the first semiconductor chip 53, for example. There is a problem that the voltage cannot be directly applied only to the semiconductor chips 51, 52, and 53.
【０００４】そこで、積層された半導体チップのうちの
１つの半導体チップのみに信号を印加するために、図４
に示すような３次元積層半導体装置が提案されている。
この３次元積層半導体装置は、第１の半導体チップ５５
に３個の貫通電極５５Ａ，５５Ｂ，５５Ｃを設け、第２
半導体チップ５６に２個の貫通電極５６Ａ，５６Ｂを設
け、第３半導体チップ５７に１個の貫通電極５７Ａを設
けている。そして、貫通電極５５Ｃを介して第１半導体
チップ５５に信号を印加して、貫通電極５５Ｂと、貫通
電極５６Ｂとを介して第２半導体チップ５６に信号を印
加して、貫通電極５５Ａと、貫通電極５６Ａと、貫通電
極５７Ａとを介して第３半導体チップ５７に信号を印加
するようにしている。In order to apply a signal to only one of the stacked semiconductor chips, FIG.
The following three-dimensional stacked semiconductor devices have been proposed.
This three-dimensional stacked semiconductor device includes a first semiconductor chip 55
Are provided with three through electrodes 55A, 55B, and 55C,
The semiconductor chip 56 is provided with two through electrodes 56A and 56B, and the third semiconductor chip 57 is provided with one through electrode 57A. Then, a signal is applied to the first semiconductor chip 55 via the through electrode 55C, and a signal is applied to the second semiconductor chip 56 via the through electrode 55B and the through electrode 56B. A signal is applied to the third semiconductor chip 57 via the electrode 56A and the through electrode 57A.
【０００５】しかしながら、上記３次元積層半導体装置
は、互いに異なる数の貫通電極を有して貫通電極構造が
異なる半導体チップ５５，５６，５７を夫々作る必要が
あるので、生産コストが大幅に上昇するという問題があ
る。However, in the three-dimensional stacked semiconductor device, it is necessary to manufacture semiconductor chips 55, 56, and 57 having different numbers of through electrodes and different through electrode structures, respectively, so that the production cost is significantly increased. There is a problem.
【０００６】そこで、図５に示すように、互いに同じ貫
通電極構造を有する半導体チップ６１，６２，６３を用
いて、積層された第１乃至第３半導体チップ６１，６
２，６３のうちの１つの半導体チップ６１，６２，６３
のみに信号を印加するようにした３次元積層半導体装置
がある。この３次元積層半導体装置は、第１半導体チッ
プ６１に配線６１ｅを設け、第２半導体チップ６２に配
線６２ｅを設け、第３半導体チップ６３に配線６３ｅを
設けて、上記配線６１ｅ,６２ｅ,６３ｅによって、各々
の半導体チップのみに信号を印加するようにしている。Therefore, as shown in FIG. 5, the first to third semiconductor chips 61, 6 stacked using semiconductor chips 61, 62, 63 having the same through electrode structure as one another.
One of semiconductor chips 61, 62, 63
There is a three-dimensional stacked semiconductor device in which a signal is applied only to the three-dimensional stacked semiconductor device. In this three-dimensional stacked semiconductor device, a wiring 61e is provided on a first semiconductor chip 61, a wiring 62e is provided on a second semiconductor chip 62, a wiring 63e is provided on a third semiconductor chip 63, and the wirings 61e, 62e, 63e are used. The signal is applied only to each semiconductor chip.
【０００７】しかしながら、上記３次元積層半導体装置
は、第１乃至第３半導体チップ６１，６２，６３に、互
いに異なる配線６１ｅ，６２ｅ，６３ｅを施すために、
互いに異なるパターニング工程が必要になるので、第１
乃至第３半導体チップ６１，６２，６３を製造するため
の工程が煩雑になると同時に、生産歩留りが低下して生
産コストが上昇するという問題がある。However, in the three-dimensional stacked semiconductor device, different wirings 61e, 62e, 63e are provided to the first to third semiconductor chips 61, 62, 63, respectively.
Since different patterning steps are required, the first
In addition, there is a problem that a process for manufacturing the third semiconductor chips 61, 62, and 63 becomes complicated, and that a production yield decreases and a production cost increases.
【０００８】そこで、本発明の目的は、互いに同じ位置
に貫通電極を有して同一の電極構造を有するにも拘わら
ず、積層されて３次元積層半導体装置を形成した場合に
半導体装置毎に信号を印加でき、しかも構造が簡単で安
価な半導体装置と、それを用いた３次元積層半導体装置
を提供することにある。Therefore, an object of the present invention is to provide a three-dimensional stacked semiconductor device in which, despite having through electrodes at the same positions and having the same electrode structure, a three-dimensional stacked semiconductor device is formed, It is an object of the present invention to provide an inexpensive semiconductor device that can apply a voltage and that has a simple structure and a three-dimensional stacked semiconductor device using the same.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体装置は、表裏面に貫通する貫通電極
を有する半導体装置において、少なくとも１つの上記貫
通電極は、上記表裏面に対して斜めに交差する斜め貫通
電極であることを特徴としている。In order to achieve the above object, a semiconductor device according to the present invention has a through electrode penetrating on the front and back surfaces. It is characterized in that it is an oblique through electrode that obliquely intersects.
【００１０】本発明の半導体装置によれば、上記斜め貫
通電極が半導体装置の表裏面に対して斜めに交差してい
るので、この斜め貫通電極は、表面と裏面とで異なる位
置の例えば端子などを接続する。したがって、この半導
体装置は、従来のように別個に引き回し用の配線を設け
ることなく、半導体装置の表面と裏面とで異なる位置の
例えば端子などが接続される。According to the semiconductor device of the present invention, since the oblique through electrodes obliquely intersect with the front and back surfaces of the semiconductor device, the oblique through electrodes have different positions on the front surface and the rear surface, such as terminals. Connect. Therefore, in this semiconductor device, for example, terminals and the like at different positions on the front surface and the back surface of the semiconductor device are connected without separately providing wiring for routing as in the related art.
【００１１】１実施形態の半導体装置は、上記表裏面に
対して直交する垂直貫通電極を有することを特徴として
いる。The semiconductor device of one embodiment is characterized in that it has a vertical through electrode perpendicular to the front and back surfaces.
【００１２】１実施形態の半導体装置によれば、半導体
装置の表裏面に対して斜めに交差する斜め貫通電極を有
すると共に、半導体装置の表裏面に対して直交する垂直
貫通電極も有するので、上記斜め貫通電極と垂直貫通電
極とが、上記半導体装置の表面と裏面とにおいて、同じ
位置と異なる位置の例えば端子などを接続する。したが
って、この半導体装置は、上記斜め貫通電極と垂直貫通
電極の配置位置および配置個数を変えることによって、
半導体装置の表面と裏面との間で所定の接続パターンが
得られる。According to the semiconductor device of one embodiment, the semiconductor device has oblique through electrodes obliquely intersecting the front and back surfaces of the semiconductor device and also has vertical through electrodes orthogonal to the front and back surfaces of the semiconductor device. The oblique penetrating electrode and the vertical penetrating electrode connect, for example, terminals at the same position and different positions on the front and back surfaces of the semiconductor device. Therefore, in this semiconductor device, by changing the arrangement position and the number of the oblique through electrodes and the vertical through electrodes,
A predetermined connection pattern is obtained between the front surface and the back surface of the semiconductor device.
【００１３】本発明の3次元積層半導体装置は、上記半
導体装置を２個以上積層して、少なくとも上記斜め貫通
電極によって上記半導体装置を互いに電気的に接続した
ことを特徴としている。A three-dimensional stacked semiconductor device according to the present invention is characterized in that two or more of the above-mentioned semiconductor devices are stacked, and the above-mentioned semiconductor devices are electrically connected to each other at least by the above-mentioned oblique through electrodes.
【００１４】本発明の3次元積層半導体装置によれば、
上記斜め貫通電極が上記２個以上積層された半導体装置
の異なる位置を接続する。したがって、同じ位置に斜め
貫通電極または垂直貫通電極を有して同じ電極構造を有
する半導体装置を２個以上積層しても、上記斜め貫通電
極は、積層された２個以上の半導体装置の全てを接続し
ないで、積層された２個以上の半導体装置のうちの所定
の半導体装置のみを接続する。その結果、異なる電極構
造の半導体装置を用いたり、半導体装置にさらに配線を
施すことなく、所定の半導体装置のみに信号を印加でき
る３次元積層半導体装置が得られる。According to the three-dimensional stacked semiconductor device of the present invention,
The oblique through electrodes connect different positions of the semiconductor device in which two or more of the oblique through electrodes are stacked. Therefore, even if two or more semiconductor devices having the same electrode structure with diagonal through electrodes or vertical penetrating electrodes at the same position are stacked, the diagonal through electrodes can be used to form all of the two or more stacked semiconductor devices. Without connection, only a predetermined semiconductor device of the two or more stacked semiconductor devices is connected. As a result, a three-dimensional stacked semiconductor device in which signals can be applied only to a predetermined semiconductor device without using a semiconductor device having a different electrode structure or providing additional wiring to the semiconductor device can be obtained.
【００１５】本発明の３次元積層半導体装置は、上記半
導体装置を２個以上積層して、上記斜め貫通電極および
垂直貫通電極によって、上記半導体装置を互いに電気的
に接続したことを特徴としている。A three-dimensional stacked semiconductor device according to the present invention is characterized in that two or more of the above-mentioned semiconductor devices are stacked, and the above-mentioned semiconductor devices are electrically connected to each other by the oblique through electrodes and the vertical through electrodes.
【００１６】本発明の３次元積層半導体装置によれば、
上記斜め貫通電極および垂直貫通電極によって、斜め貫
通電極および垂直貫通電極を有する２個以上積層された
半導体装置の間を接続する。したがって、垂直貫通電極
が上記２個以上積層された半導体装置の全てを接続する
一方、斜め貫通電極が上記２個以上積層された半導体装
置のうちのいずれかのみを接続する。その結果、同一の
電極構造を有する半導体装置を積層するにも拘らず、全
ての半導体装置に信号を印加する一方、所定の半導体装
置のみにも信号を印加できる３次元積層半導体装置が得
られる。According to the three-dimensional stacked semiconductor device of the present invention,
The oblique through electrode and the vertical through electrode connect between two or more stacked semiconductor devices having the oblique through electrode and the vertical through electrode. Therefore, the vertical through electrodes connect all of the semiconductor devices in which the two or more are stacked, while the oblique through electrodes connect only one of the semiconductor devices in which the two or more are stacked. As a result, a three-dimensional stacked semiconductor device is obtained in which signals can be applied to all the semiconductor devices while signals can be applied to only predetermined semiconductor devices, despite the fact that semiconductor devices having the same electrode structure are stacked.
【００１７】[0017]
【発明の実施の形態】以下、本発明を図示の実施の形態
により詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments.
【００１８】図１は、本発明の一実施形態に係る半導体
装置としての半導体チップを示す断面図である。この半
導体チップ１は、表面２にＡｕ（金）からなる突起電極
４ａ，４ｂ，４ｃ，４ｄ，４ｅ・・・を備え、裏面３に
Ａｕからなる突起電極５ａ，５ｂ，５ｃ，５ｄ，５ｅ・
・・を備える。FIG. 1 is a sectional view showing a semiconductor chip as a semiconductor device according to one embodiment of the present invention. The semiconductor chip 1 has projecting electrodes 4a, 4b, 4c, 4d, 4e... Made of Au (gold) on the front surface 2 and projecting electrodes 5a, 5b, 5c, 5d, 5e.
・ ・
【００１９】上記表面２の突起電極４ｂ，４ｃ，４ｄ
と、裏面３の突起電極５ａ，５ｂ，５ｃは、上記表面２
および裏面３に対して斜めに交差するＣｕ（銅）からな
る斜め貫通電極７Ａ，７Ｂ，７Ｃによって電気的に接続
されている。より詳しくは、表面２の突起電極４ｂと裏
面３の突起電極５ａとが斜め貫通電極７Ａによって、表
面２の突起電極４ｃと裏面３の突起電極５ｂとが斜め貫
通電極７Ｂによって、表面２の突起電極４ｄと裏面３の
突起電極５ｃとが斜め貫通電極７Ｃによって接続されて
いる。すなわち、上記斜め貫通電極７Ａ，７Ｂ，７Ｃ
は、半導体チップ１の表裏面２，３において、電極を１
ピッチだけシフトして接続している。The protruding electrodes 4b, 4c, 4d on the surface 2
And the protruding electrodes 5a, 5b, 5c on the back surface 3
And are electrically connected by oblique through electrodes 7A, 7B, 7C made of Cu (copper) obliquely intersecting the back surface 3. More specifically, the protruding electrode 4b on the front surface 2 and the protruding electrode 5a on the back surface 3 are formed by the oblique penetrating electrode 7A, and the protruding electrode 4c on the front surface 2 and the protruding electrode 5b on the back surface 3 are formed by the oblique penetrating electrode 7B. The electrode 4d and the protruding electrode 5c on the back surface 3 are connected by an oblique through electrode 7C. That is, the oblique through electrodes 7A, 7B, 7C
Indicates that the electrodes are connected to the front and back surfaces 2 and 3 of the semiconductor chip 1 by one.
The connection is shifted by the pitch.
【００２０】一方、半導体チップ１の表面２の突起電極
４ｅと、裏面３の突起電極５ｅは、半導体チップ１の表
裏面２，３に対して直交する垂直貫通電極８によって電
気的に接続されている。上記斜め貫通電極７Ａ，７Ｂ，
７Ｃと垂直貫通電極８は、周面が絶縁性半導体酸化皮膜
で覆われている。On the other hand, the protruding electrode 4e on the front surface 2 of the semiconductor chip 1 and the protruding electrode 5e on the back surface 3 are electrically connected by a vertical through electrode 8 orthogonal to the front and back surfaces 2, 3 of the semiconductor chip 1. I have. The oblique through electrodes 7A, 7B,
The peripheral surfaces of 7C and the vertical through electrode 8 are covered with an insulating semiconductor oxide film.
【００２１】上記半導体チップ１は、以下のようにして
製造する。The semiconductor chip 1 is manufactured as follows.
【００２２】まず、５０μｍの厚みを有する半導体部１
ａの表面２側から、この表面２の法線に対して２１．８
度の角度をなして、炭酸ガスレーザーもしくはＹＡＧレ
ーザーによって小径スポットのレーザ光を照射する。そ
うして、半導体部１ａの表裏面２，３に対して斜めに交
差する直径１０μｍの貫通穴を形成する。上記２１．８
度の傾きによって、上記貫通穴の表面２側端と裏面３側
端との間に、図１において横方向に２０μｍのずれを生
じさせる。その後、上記貫通穴の内面に熱酸化膜を形成
し、その内側にＣｕめっきを施して斜め貫通電極７Ａ，
７Ｂ，７Ｃを形成する。そして、上記半導体部１ａの表
面２に、Ａｕめっきによって突起電極４ａ，４ｂ，４
ｃ，４ｄを２０μｍの間隔をおいて形成する。また、上
記半導体部１ａの裏面３に、上記表面２の突起電極４
ａ，４ｂ，４ｃ，４ｄの直下に、突起電極５ａ，５ｂ，
５ｃ，５ｄを形成する。ここにおいて、上記表面２の突
起電極４ｂ，４ｃ，４ｄと、裏面３の突起電極５ａ，５
ｂ，５ｃとが、上記斜め貫通電極７Ａ，７Ｂ，７Ｃによ
って各々接続されるようにする。First, a semiconductor unit 1 having a thickness of 50 μm
a from the surface 2 side with respect to the normal to this surface 2
At a certain angle, a laser beam of a small diameter spot is irradiated by a carbon dioxide gas laser or a YAG laser. As a result, a through-hole having a diameter of 10 μm that obliquely intersects the front and back surfaces 2 and 3 of the semiconductor portion 1a is formed. 21.8 above
Due to the degree of inclination, a shift of 20 μm occurs in the lateral direction in FIG. 1 between the end on the front surface 2 side and the end on the back surface 3 of the through hole. Thereafter, a thermal oxide film is formed on the inner surface of the through hole, and Cu plating is applied to the inside thereof to form oblique through electrodes 7A,
7B and 7C are formed. Then, the projecting electrodes 4a, 4b, 4 are formed on the surface 2 of the semiconductor portion 1a by Au plating.
c and 4d are formed at intervals of 20 μm. Also, on the back surface 3 of the semiconductor portion 1a, the projecting electrode 4 on the front surface 2 is provided.
a, 4b, 4c, and 4d, projecting electrodes 5a, 5b,
5c and 5d are formed. Here, the projecting electrodes 4b, 4c, 4d on the front surface 2 and the projecting electrodes 5a, 5
b and 5c are connected by the oblique through electrodes 7A, 7B and 7C, respectively.
【００２３】さらに、上記半導体部分１ａの表面２側か
ら、上記表面２に対して直角をなして小径スポットのレ
ーザ光を照射して、半導体部分１ａの表裏面２，３に対
して直交する直径１０μｍの貫通穴を形成する。この貫
通穴の内面に熱酸化膜を形成し、その内側にＣｕめっき
を施して、垂直貫通電極８を形成する。上記半導体部分
１ａの表面２および裏面３の上記垂直貫通電極８の両端
部に、Ａｕめっきによって夫々突起電極４ｅ，５ｅを形
成する。Further, a laser beam of a small-diameter spot is irradiated from the front surface 2 side of the semiconductor portion 1a at right angles to the front surface 2 so as to have a diameter perpendicular to the front and back surfaces 2 and 3 of the semiconductor portion 1a. A 10 μm through hole is formed. A thermal oxide film is formed on the inner surface of the through-hole, and Cu plating is applied to the inside thereof to form the vertical through-electrode 8. Protruding electrodes 4e and 5e are formed by Au plating on both ends of the vertical through electrode 8 on the front surface 2 and the rear surface 3 of the semiconductor portion 1a, respectively.
【００２４】図２は、本発明の実施形態における３次元
積層半導体装置を示す断面図であり、上記半導体チップ
１と同一の構造を有する半導体チップ１０，２０，３０
を厚み方向に積層して形成されている。FIG. 2 is a sectional view showing a three-dimensional stacked semiconductor device according to an embodiment of the present invention, and semiconductor chips 10, 20, and 30 having the same structure as the semiconductor chip 1 described above.
Are laminated in the thickness direction.
【００２５】この３次元積層半導体装置は、第１半導体
チップ１０と第２半導体チップ２０との間において、第
１半導体チップ１０の表面１２に形成された突起電極１
４ａ，１４ｂ，１４ｃ，１４ｄと、第２半導体チップ２
０の表面２３に形成された突起電極２５ａ，２５ｂ，２
５ｃ，２５ｄとを、Ａｕ−Ａｕの固相拡散接合によって
各々接合している。また、第２半導体チップ２０の表面
２２に形成された突起電極２４ａ，２４ｂ，２４ｃ，２
４ｄと、第３半導体チップ３０の裏面３３に形成された
突起電極３５ａ，３５ｂ，３５ｃ，３５ｄとを、Ａｕ−
Ａｕの固相拡散接合によって各々接合している。また、
第１半導体チップ１０の表面１２の突起電極１４ｅ，１
４ｅ・・・と第２半導体チップ２０の裏面２３の突起電
極２５ｅ，２５ｅ・・・と、かつ、第２半導体チップ２
０の表面２２の突起電極２４ｅ，１４ｅ・・・と第３半
導体チップ３０の裏面３３の突起電極３５ｅ，５３ｅ・
・・とを、Ａｕ−Ａｕの固相拡散接合によって各々接合
している。ここにおいて、Ａｕ−Ａｕの固相拡散接合の
他に、単に圧接した状態で接着剤を硬化させて導通を得
る方法や、異方性導電接着剤を用いて接合してもよく、
常温接合を用いてもよい。In this three-dimensional stacked semiconductor device, the projection electrode 1 formed on the surface 12 of the first semiconductor chip 10 is provided between the first semiconductor chip 10 and the second semiconductor chip 20.
4a, 14b, 14c, 14d and the second semiconductor chip 2
Projecting electrodes 25a, 25b, 2 formed on the surface 23
5c and 25d are respectively bonded by solid-phase diffusion bonding of Au-Au. Further, the protruding electrodes 24a, 24b, 24c, 2 formed on the surface 22 of the second semiconductor chip 20
4d and the projecting electrodes 35a, 35b, 35c, 35d formed on the back surface 33 of the third semiconductor chip 30 are connected to Au-
They are joined by solid-state diffusion bonding of Au. Also,
The projecting electrodes 14e, 1 on the surface 12 of the first semiconductor chip 10
4e... And the protruding electrodes 25e on the back surface 23 of the second semiconductor chip 20 and the second semiconductor chip 2
. And the protruding electrodes 35e, 53e on the back surface 33 of the third semiconductor chip 30.
Are joined by Au-Au solid phase diffusion bonding. Here, in addition to the solid-phase diffusion bonding of Au-Au, a method of hardening the adhesive in a state of being simply pressed to obtain conduction, or a bonding using an anisotropic conductive adhesive,
Room temperature bonding may be used.
【００２６】この３次元積層半導体装置は、第１半導体
チップ１０の裏面１３の突起電極１５ａ，１５ｂ，１５
ｃが、斜め貫通電極１７Ａ，１７Ｂ，１７Ｃ・・・を介
して、互いに異なる半導体チップ１０，２０，３０に夫
々接続している。すなわち、上記突起電極１５ｃが、斜
め貫通電極１７Ｃを介して、第１半導体チップ１０の表
面１２の突起電極１４ｄに接続している。上記突起電極
３５ｂは、斜め貫通電極１７Ｂと斜め貫通電極２７Ｃと
を介して、半第２導体チップ２０の表面２２の突起電極
２４ｄに接続している。さらに、斜め貫通電極１７Ａと
斜め貫通電極２７Ｂと斜め貫通電極３７Ｃとを介して、
上記突起電極１５ａが、第３半導体チップ３０の表面３
２の突起電極３４ｄに接続している。This three-dimensional stacked semiconductor device is provided with the protruding electrodes 15a, 15b, 15 on the back surface 13 of the first semiconductor chip 10.
are connected to different semiconductor chips 10, 20, 30 via diagonal through electrodes 17A, 17B, 17C,..., respectively. That is, the protruding electrode 15c is connected to the protruding electrode 14d on the surface 12 of the first semiconductor chip 10 via the oblique through electrode 17C. The protruding electrode 35b is connected to the protruding electrode 24d on the surface 22 of the semi-second conductor chip 20 via the oblique through electrode 17B and the oblique through electrode 27C. Furthermore, via the oblique through electrode 17A, the oblique through electrode 27B, and the oblique through electrode 37C,
The protruding electrode 15a is disposed on the surface 3 of the third semiconductor chip 30.
The second projection electrode 34d is connected to the second projection electrode 34d.
【００２７】上記第１半導体チップ１０の突起電極１４
ｄには第１半導体チップ１０のセレクト信号線を、第2
半導体チップ２０の突起電極２４ｄには第２半導体チッ
プ２０のセレクト信号線を、第3半導体チップ３０の突
起電極３４ｄには第３半導体チップ３０のセレクト信号
線を連結している。The protruding electrode 14 of the first semiconductor chip 10
d denotes the select signal line of the first semiconductor chip 10 and the second
The select signal line of the second semiconductor chip 20 is connected to the projecting electrode 24 d of the semiconductor chip 20, and the select signal line of the third semiconductor chip 30 is connected to the projecting electrode 34 d of the third semiconductor chip 30.
【００２８】上記構成の３次元積層半導体装置におい
て、上記第１半導体チップ１０の裏面１３の突起端子１
５ａ，１５ｂ，１５ｃに、（１，０，０）の論理信号を
印加する。そうすると、上記突起端子１５ａに接続され
た第３半導体チップ３０のみに信号が印加されて、第３
半導体チップ３０に形成された回路が能動状態になる。
また、（０，１，０）および、（０，０，１）の各論理
信号に対しては、夫々第２半導体チップ２０および、第
１半導体チップ１０の各々に形成された回路が夫々排他
的に能動状態になる。In the three-dimensional stacked semiconductor device having the above structure, the protrusion terminals 1 on the back surface 13 of the first semiconductor chip 10 are formed.
A logic signal of (1, 0, 0) is applied to 5a, 15b, 15c. Then, a signal is applied only to the third semiconductor chip 30 connected to the protruding terminal 15a, and the third
The circuit formed on the semiconductor chip 30 becomes active.
Further, for the logic signals (0, 1, 0) and (0, 0, 1), the circuits formed on each of the second semiconductor chip 20 and the first semiconductor chip 10 are exclusive. Becomes active state.
【００２９】一方、第１半導体チップ１０の表面１３の
突起端子１５ｅ，１５ｅ・・・に信号を印加すると、第
１乃至第３半導体チップ１０，２０，３０の全てに信号
が印加される。On the other hand, when a signal is applied to the protruding terminals 15e, 15e... On the surface 13 of the first semiconductor chip 10, the signal is applied to all of the first to third semiconductor chips 10, 20, 30.
【００３０】このように、上記３次元積層半導体装置
は、図４に示した従来の３次元積層半導体装置における
ような互いに異なる貫通電極構造を有する半導体チップ
５５，５６，５７を積層することなく、同一の貫通電極
構造を有する半導体チップ１０，２０，３０を積層し
て、この半導体チップ１０，２０，３０に個別に信号を
印加できるので、３次元積層半導体装置の生産コストを
大幅に削減することができる。As described above, the three-dimensional stacked semiconductor device does not have to stack the semiconductor chips 55, 56, 57 having different through-electrode structures as in the conventional three-dimensional stacked semiconductor device shown in FIG. Since the semiconductor chips 10, 20, and 30 having the same through-electrode structure can be stacked and signals can be individually applied to the semiconductor chips 10, 20, and 30, the production cost of the three-dimensional stacked semiconductor device can be significantly reduced. Can be.
【００３１】また、図５に示した従来の３次元積層半導
体装置におけるように、半導体チップ６１，６２，６３
に、互いに異なるパターンの引き回し用配線６１ｅ，６
２ｅ，６３ｅを形成する必要がないため、従来よりも工
程を簡素化できて、生産歩留りを向上できると共に生産
効率を向上でき、その結果、３次元積層半導体装置の生
産コストを低減できる。As in the conventional three-dimensional stacked semiconductor device shown in FIG. 5, the semiconductor chips 61, 62, 63
In addition, routing wirings 61e, 6
Since there is no need to form the 2e and 63e, the process can be simplified as compared with the conventional case, the production yield can be improved, and the production efficiency can be improved. As a result, the production cost of the three-dimensional stacked semiconductor device can be reduced.
【００３２】上記実施形態の３次元積層半導体装置は、
斜め貫通電極１７Ａ，１７Ｂ，１７Ｃ・・・を図２にお
いて右側に３個づつ設けたが、斜め貫通電極を配置する
位置はどこでもよく、また、斜め貫通電極と垂直貫通電
極とを交互に配置してもよい。また、斜め貫通電極およ
び垂直貫通電極の個数は何個でもよく、全てが斜め貫通
電極であってもよい。全ての貫通電極が斜め貫通電極の
場合、同一の電極構造を有する半導体装置を積層したに
も拘らず、積層された半導体装置に個別に信号を印加で
きる3次元積層半導体装置が得られる。The three-dimensional stacked semiconductor device of the above embodiment is
Two oblique through electrodes 17A, 17B, 17C,... Are provided on the right side in FIG. 2, but the oblique penetrating electrodes may be arranged at any position, and oblique penetrating electrodes and vertical penetrating electrodes are alternately arranged. You may. Also, the number of oblique through electrodes and vertical through electrodes may be any number, and all may be oblique through electrodes. When all the penetrating electrodes are oblique penetrating electrodes, a three-dimensional stacked semiconductor device capable of individually applying a signal to the stacked semiconductor devices is obtained despite the stacked semiconductor devices having the same electrode structure.
【００３３】上記実施形態の３次元積層半導体装置は、
半導体チップ１０，２０，３０を３個積層したが、積層
する半導体装置チップは２個以上の何個でもよい。The three-dimensional stacked semiconductor device of the above embodiment is
Although three semiconductor chips 10, 20, and 30 are stacked, the number of stacked semiconductor device chips may be two or more.
【００３４】[0034]
【発明の効果】以上より明らかなように、本発明の半導
体装置によれば、少なくとも１つの貫通電極が、半導体
装置の表裏面に対して斜めに交差する斜め貫通電極であ
るので、従来におけるような引き回し用の配線を設ける
ことなく、上記斜め貫通電極によって、半導体装置の表
面と裏面とで異なる位置の例えば端子などを接続でき
る。As is clear from the above, according to the semiconductor device of the present invention, at least one through electrode is an oblique through electrode obliquely intersecting the front and back surfaces of the semiconductor device. The diagonal through electrode allows connection of, for example, terminals at different positions on the front surface and the back surface of the semiconductor device without providing an appropriate wiring for wiring.
【００３５】１実施形態の半導体装置によれば、上記表
裏面に対して直交する垂直貫通電極を有するので、上記
斜め貫通電極と垂直貫通電極とが上記半導体装置の表面
と裏面の同じ位置と異なる位置を接続するから、上記斜
め貫通電極と垂直貫通電極の配置位置および配置個数を
変えることによって、半導体装置の表面と裏面との間で
所定の接続パターンを得ることができる。According to the semiconductor device of one embodiment, since the vertical through electrodes perpendicular to the front and back surfaces are provided, the oblique through electrodes and the vertical through electrodes are different from the same position on the front surface and the back surface of the semiconductor device. Since the positions are connected, a predetermined connection pattern can be obtained between the front surface and the back surface of the semiconductor device by changing the arrangement position and the number of the oblique through electrodes and the vertical through electrodes.
【００３６】本発明の3次元積層半導体装置は、上記半
導体装置を２個以上積層して、少なくとも上記斜め貫通
電極によって上記半導体装置を互いに電気的に接続した
ので、同じ電極構造を有する半導体装置を２個以上積層
しても、上記斜め貫通電極が２個以上の半導体装置のう
ちの所定の半導体装置を接続するから、異なる電極構造
の半導体装置を用いたり、半導体装置にさらに配線を施
すことなく、積層された２個以上の半導体装置のうちの
所定の半導体装置のみに信号を印加できる３次元積層半
導体装置を得ることができる。In the three-dimensional stacked semiconductor device of the present invention, two or more of the semiconductor devices are stacked and the semiconductor devices are electrically connected to each other at least by the oblique through-electrodes. Even when two or more semiconductor devices are stacked, the oblique through electrode connects a predetermined semiconductor device of the two or more semiconductor devices, so that a semiconductor device having a different electrode structure is not used, and further wiring is not applied to the semiconductor device. Thus, a three-dimensional stacked semiconductor device capable of applying a signal to only a predetermined semiconductor device among two or more stacked semiconductor devices can be obtained.
【００３７】本発明の３次元積層半導体装置は、上記半
導体装置を２個以上積層して、上記斜め貫通電極および
垂直貫通電極によって、上記半導体装置を互いに電気的
に接続したので、同一の電極構造を有する半導体装置を
積層するにも拘らず、全ての半導体装置に信号を印加す
る一方、所定の半導体装置のみにも信号を印加できる３
次元積層半導体装置を得ることができる。In the three-dimensional stacked semiconductor device of the present invention, two or more of the above-mentioned semiconductor devices are stacked, and the above-mentioned semiconductor devices are electrically connected to each other by the above-mentioned oblique through electrodes and vertical through electrodes. Although signals are applied to all the semiconductor devices despite the fact that the semiconductor devices having
A three-dimensional stacked semiconductor device can be obtained.
【図１】 この発明の実施形態の半導体装置を示す断面
図である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】 図１に示した半導体装置を３個積層して形成
した３次元積層半導体装置を示す断面図である。FIG. 2 is a cross-sectional view illustrating a three-dimensional stacked semiconductor device formed by stacking three semiconductor devices illustrated in FIG. 1;
【図３】 従来の同一の電極構造を有する半導体装置を
積層して形成した３次元積層半導体装置を示す断面図で
ある。FIG. 3 is a cross-sectional view showing a conventional three-dimensional stacked semiconductor device formed by stacking semiconductor devices having the same electrode structure.
【図４】 従来の互いに異なる電極構造を有する半導体
装置を積層して形成した３次元積層半導体装置を示す断
面図である。FIG. 4 is a cross-sectional view illustrating a conventional three-dimensional stacked semiconductor device formed by stacking semiconductor devices having different electrode structures.
【図５】 従来の、同一の電極構造を有する半導体装置
を積層すると共に、互いに異なる配線を施した３次元積
層半導体装置を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional three-dimensional stacked semiconductor device in which semiconductor devices having the same electrode structure are stacked and different wirings are provided.
１０ 第１半導体チップ １２ 第１半導体チップの表面 １３ 第１半導体チップの裏面 １４ａ，１４ｂ，１４ｃ，１４ｄ，１４ｅ 第１半導体
チップの表面の突起電極 １５ａ，１５ｂ，１５ｃ，１５ｄ，１５ｅ 第１半導体
チップの裏面の突起電極 １７Ａ，１７Ｂ，１７Ｃ 第１半導体チップの斜め貫通
電極 １８ 第１半導体チップの垂直貫通電極 ２０ 第２半導体チップ ２４ａ，２４ｂ，２４ｃ，２４ｄ，２４ｅ 第２半導体
チップの表面の突起電極 ２５ａ，２５ｂ，２５ｃ，２５ｄ，２５ｅ 第２半導体
チップの裏面の突起電極 ２７Ａ，２７Ｂ，２７Ｃ 第２半導体チップの斜め貫通
電極 ２８ 第２半導体チップの垂直貫通電極 ３０ 第３半導体チップ ３４ａ，３４ｂ，３４ｃ，３４ｄ，３４ｅ 第３半導体
チップの表面の突起電極 ３５ａ，３５ｂ，３５ｃ，３５ｄ，３５ｅ 第３半導体
チップの裏面の突起電極 ３７Ａ，３７Ｂ，３７Ｃ 第３半導体チップの斜め貫通
電極 ３８ 第３半導体チップの垂直貫通電極Reference Signs List 10 first semiconductor chip 12 front surface of first semiconductor chip 13 back surface of first semiconductor chip 14a, 14b, 14c, 14d, 14e projecting electrode 15a, 15b, 15c, 15d, 15e on front surface of first semiconductor chip Projecting electrodes 17A, 17B, 17C on the back surface of the first semiconductor chip 18 Oblique penetrating electrodes of the first semiconductor chip 18 Vertical penetrating electrodes of the first semiconductor chip 20 Second semiconductor chips 24a, 24b, 24c, 24d, 24e Projecting electrodes on the front surface of the second semiconductor chip 25a, 25b, 25c, 25d, 25e Projecting electrodes 27A, 27B, 27C on the back surface of the second semiconductor chip Diagonal through electrodes of the second semiconductor chip 28 Vertical through electrodes of the second semiconductor chip 30 Third semiconductor chips 34a, 34b, 34c , 34d, 34e Projecting electrodes 35a, 35b on the surface of the third semiconductor chip , 35c, 35d, 35e Projecting electrodes 37A, 37B, 37C on the back surface of the third semiconductor chip Oblique penetrating electrodes of the third semiconductor chip 38 Vertical penetrating electrodes of the third semiconductor chip
Claims (4)
体装置において、 少なくとも１つの上記貫通電極は、上記表裏面に対して
斜めに交差する斜め貫通電極であることを特徴とする半
導体装置。1. A semiconductor device having a penetrating electrode penetrating on the front and back surfaces, wherein at least one of the penetrating electrodes is an oblique penetrating electrode obliquely intersecting the front and back surfaces.
を特徴とする半導体装置。2. The semiconductor device according to claim 1, further comprising a vertical through electrode perpendicular to the front and back surfaces.
２個以上積層して、少なくとも上記斜め貫通電極によっ
て上記半導体装置を互いに電気的に接続したことを特徴
とする３次元積層半導体装置。3. A three-dimensional stacked semiconductor device, wherein two or more semiconductor devices according to claim 1 or 2 are stacked, and the semiconductor devices are electrically connected to each other at least by the oblique through electrodes.
積層して、上記斜め貫通電極および垂直貫通電極によっ
て、上記半導体装置を互いに電気的に接続したことを特
徴とする３次元積層半導体装置。4. A three-dimensional laminated semiconductor, wherein two or more semiconductor devices according to claim 2 are stacked, and the semiconductor devices are electrically connected to each other by the oblique through electrodes and the vertical through electrodes. apparatus.
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| JP2000231214A JP3723725B2 (en) | 2000-07-31 | 2000-07-31 | Semiconductor device and three-dimensional stacked semiconductor device |
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| JP2006040261A (en) * | 2004-06-25 | 2006-02-09 | Matsushita Electric Ind Co Ltd | Slave device, master device and laminated device |
| US7064443B2 (en) | 2003-03-27 | 2006-06-20 | Seiko Epson Corporation | Semiconductor device having a plurality of stacked semiconductor chips with positions of chip-selecting terminals being different from each other |
| JP2007103521A (en) * | 2005-09-30 | 2007-04-19 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| US7346051B2 (en) | 2004-06-25 | 2008-03-18 | Matsushita Electric Industrial Co., Ltd. | Slave device, master device and stacked device |
| CN100433326C (en) * | 2004-06-25 | 2008-11-12 | 松下电器产业株式会社 | Slave device, master device and stacked device |
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