JP2002010488A - Control method for turning on power supply - Google Patents
Control method for turning on power supplyInfo
- Publication number
- JP2002010488A JP2002010488A JP2000216634A JP2000216634A JP2002010488A JP 2002010488 A JP2002010488 A JP 2002010488A JP 2000216634 A JP2000216634 A JP 2000216634A JP 2000216634 A JP2000216634 A JP 2000216634A JP 2002010488 A JP2002010488 A JP 2002010488A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power
- power supplies
- turned
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Direct Current Feeding And Distribution (AREA)
- Dc-Dc Converters (AREA)
- Power Conversion In General (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の電源を使用
して内部回路を供給する電源投入制御方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on control method for supplying an internal circuit using a plurality of power supplies.
【０００２】[0002]
【従来の技術】例えば、従来技術として、複数の電源か
らの投入電力により内部の素子を動作させ、共通の負荷
に電力を供給するように構成されたものがある。このよ
うな共通の負荷に電力供給する電源投入制御回路にあっ
ては、電源側の都合等により、投入される複数の電源の
順序が様々であり、各電源からの投入順序が不確定にな
る場合がある。2. Description of the Related Art For example, there is a prior art in which internal elements are operated by power supplied from a plurality of power supplies to supply power to a common load. In such a power-on control circuit for supplying power to a common load, the order of a plurality of power supplies to be supplied is various due to the convenience of the power supply side, and the power-on order from each power supply is uncertain. There are cases.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
電源投入制御回路は、複数の電源の投入順序が不確定と
なると、場合によっては内部回路に設けられている素子
が定格以上の電圧や電流を発生し、素子破壊を起こす問
題があった。However, in the conventional power-on control circuit, if the power-on sequence of a plurality of power sources becomes indeterminate, the elements provided in the internal circuit may generate a voltage or current exceeding the rated value in some cases. And there is a problem of causing element destruction.
【０００４】本発明は、上記従来技術の問題点に鑑み、
複数の電源の投入順序に拘わることなく、素子破壊が起
こるのを確実に防止することができる電源投入制御方法
を提供するのを目的とする。The present invention has been made in view of the above-mentioned problems of the prior art,
It is an object of the present invention to provide a power-on control method capable of reliably preventing element destruction without regard to the order of turning on a plurality of power supplies.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に本発明においては、以下の手段を採用した。本発明で
は、複数の電源により回路内部に電力供給する電源投入
制御方法において、複数の電源の各々が全て入力された
時点で、回路内部に対し同時に電力を供給することを特
徴とする。Means for Solving the Problems To solve the above problems, the present invention employs the following means. According to the present invention, in a power-on control method for supplying power to the inside of a circuit by a plurality of power supplies, power is simultaneously supplied to the inside of the circuit when all of the plurality of power supplies are input.
【０００６】このように、複数の電源の各々が全て入力
された時点で、回路内部に対し同時に電力を供給するよ
うに構成したので、電源の投入時、各電源の投入順序が
不確定であっても、回路内部に対し同時に電力を供給す
ることにより、回路内部に突入電流が流れるのを防止す
ることができ、回路素子が破壊されるのを確実に回避す
ることができ、それだけ電源投入制御回路としての安定
性を得ることができると共に、突入電流に対する信頼性
を上げることができる。As described above, since the power is simultaneously supplied to the inside of the circuit when all of the plurality of power supplies are inputted, the power-on sequence of each power supply is uncertain at the time of power-on. Even by supplying power to the inside of the circuit at the same time, it is possible to prevent the inrush current from flowing into the inside of the circuit and to surely prevent the destruction of the circuit elements. The stability as a circuit can be obtained, and the reliability against inrush current can be increased.
【０００７】[0007]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。図１は本発明方法を実施するため
の電源投入制御回路の一実施形態を示している。本発明
方法を実施するための電源投入制御回路の一実施形態に
おいては、複数の電源ａ〜ｃがそれぞれ投入されたか否
かを電源監視回路１〜３によって監視し、電源ａ〜ｃの
全てが投入されると、論理回路４が閉成し、平滑回路５
を介しスイッチング素子（ＭＯＳ−ＦＥＴ）６〜８が同
時にオンし、回路内部の素子に所定の電力を供給するよ
うにしている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a power-on control circuit for carrying out the method of the present invention. In one embodiment of the power-on control circuit for implementing the method of the present invention, whether or not a plurality of power supplies a to c are respectively turned on is monitored by power supply monitoring circuits 1 to 3, and all of the power supplies a to c are monitored. When turned on, the logic circuit 4 is closed and the smoothing circuit 5 is closed.
, The switching elements (MOS-FETs) 6 to 8 are simultaneously turned on to supply predetermined power to the elements inside the circuit.
【０００８】電源監視回路１〜３は、互いにシリーズ接
続されてあって、各電源ａ〜ｃと論理回路４としてのＡ
ＮＤゲートとの間に直列接続され、各電源ａ〜ｃのそれ
ぞれが正常に入力されたか否かをチェックし、各電源ａ
〜ｃが全て正常に入力された場合のみ、ＡＮＤゲートに
出力する。The power supply monitoring circuits 1 to 3 are connected in series with each other, and each of the power supplies a to c and A as the logic circuit 4 are connected.
It is connected in series with the ND gate to check whether each of the power supplies a to c has been normally input.
Only when all of .about.c have been input normally, output to the AND gate.
【０００９】論理回路４としてのＡＮＤゲートは、電源
監視回路１〜３のそれぞれから出力された時点で出力
し、平滑回路５に並列接続されたスイッチング素子とし
てのＭＯＳ−ＦＥＴ６〜８をそれぞれ同時にオンさせる
ようになっている。その場合、ＭＯＳ−ＦＥＴ６〜８の
オンに際しては、平滑回路により各ＭＯＳ−ＦＥＴ６〜
８が予め設定された時間で徐々にオンし、回路内部に突
入電流が印加されるのを防止するようにしている。The AND gate as the logic circuit 4 outputs at the time when it is output from each of the power supply monitoring circuits 1 to 3, and simultaneously turns on the MOS-FETs 6 to 8 as switching elements connected in parallel to the smoothing circuit 5. It is made to let. In this case, when the MOS-FETs 6 to 8 are turned on, each of the MOS-FETs 6 to 8 is turned on by a smoothing circuit.
8 is turned on gradually for a preset time to prevent the inrush current from being applied to the inside of the circuit.
【００１０】上記の如き構成の電源投入制御回路は、各
電源ａ〜ｃの全てが正常に入力されるまでの間、電源監
視回路１〜３が出力されないことから論理回路４が閉
じ、ＭＯＳ−ＦＥＴ６〜８が閉じた状態にある。In the power-on control circuit having the above configuration, the logic circuit 4 is closed because the power supply monitoring circuits 1 to 3 are not output until all of the power supplies a to c are normally input. The FETs 6 to 8 are in a closed state.
【００１１】そして、各電源ａ〜ｃに電力が入力される
と、電源監視回路１〜３は複数の電源ａ〜ｃが投入され
た否かをチェックし、全て投入された場合のみ論理回路
４が開き、平滑回路５を介しＭＯＳ−ＦＥＴ６〜８を同
時にオンさせるので、電源の投入時、各電源ａ〜ｃの投
入順序が不確定であっても、回路内部の素子に突入電流
が流れるのを防止することができ、回路内部の素子が破
壊されるのを確実に回避することができる。しかも、Ｍ
ＯＳ−ＦＥＴ６〜８が平滑回路５により徐々にオンする
ので、回路内部の素子の破壊防止をいっそう的確なもの
とすることができる。When power is input to each of the power supplies a to c, the power supply monitoring circuits 1 to 3 check whether or not a plurality of power supplies a to c are turned on. Open, and simultaneously turn on the MOS-FETs 6 to 8 via the smoothing circuit 5. Therefore, when the power is turned on, an inrush current flows through the elements inside the circuit even if the order of turning on the power supplies a to c is uncertain. Can be prevented, and destruction of elements inside the circuit can be reliably avoided. And M
Since the OS-FETs 6 to 8 are gradually turned on by the smoothing circuit 5, the destruction of elements in the circuit can be more accurately prevented.
【００１２】従って、電源ａ〜ｃの投入時、ＭＯＳ−Ｆ
ＥＴ６〜８を同時にオンさせることにより、回路内部の
素子が破壊されるのを確実に回避できるので、それだけ
電源投入制御回路としての安定性を得ることができると
共に、突入電流に対する信頼性を上げることができる効
果がある。なお本実施形態では、ＭＯＳ−ＦＥＴ６〜８
を用いた例を示したが、これと代わりにスイッチング素
子で代用することもできる。Therefore, when the power supplies a to c are turned on, the MOS-F
By simultaneously turning on ET6 to ET8, it is possible to reliably avoid destruction of elements inside the circuit, so that it is possible to obtain stability as a power-on control circuit and to increase reliability against inrush current. There is an effect that can be. In this embodiment, the MOS-FETs 6 to 8
Although an example using is described, a switching element can be used instead.
【００１３】[0013]
【発明の効果】以上述べたように、本発明によれば、複
数の電源の各々が全て入力された場合にのみ回路内部に
同時に電力供給するように構成したので、複数の電源の
各々が不確定に投入されることがあっても、回路内の素
子が破壊されるのを回避し、突入電流を防止することが
でき、それだけ突入電流に対する信頼性を高めることが
できる効果がある。As described above, according to the present invention, power is simultaneously supplied to the inside of the circuit only when all of the plurality of power supplies are input, so that each of the plurality of power supplies is inoperable. Even if it is turned on for confirmation, it is possible to prevent the elements in the circuit from being destroyed, to prevent an inrush current, and to increase the reliability against the inrush current.
【図１】 本発明方法を実施するための電源投入制御回
路の一実施形態を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of a power-on control circuit for implementing a method of the present invention.
【符号の説明】 ａ〜ｃ…電源 １〜３…電源監視回路 ４…論理回路 ６〜８…スイッチング素子としてのＭＯＳ−ＦＥＴ[Description of Signs] a to c: Power supply 1-3: Power supply monitoring circuit 4: Logic circuit 6 to 8: MOS-FET as switching element
Claims (1)
る電源投入制御方法において、複数の電源の各々が全て
入力された時点で、回路内部に対し同時に電力を供給す
ることを特徴とする電源投入制御方法。1. A power-on control method for supplying power to the inside of a circuit by a plurality of power supplies, wherein power is simultaneously supplied to the inside of the circuit when all of the plurality of power supplies are input. Control method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000216634A JP2002010488A (en) | 2000-06-14 | 2000-06-14 | Control method for turning on power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000216634A JP2002010488A (en) | 2000-06-14 | 2000-06-14 | Control method for turning on power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002010488A true JP2002010488A (en) | 2002-01-11 |
Family
ID=18711870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000216634A Pending JP2002010488A (en) | 2000-06-14 | 2000-06-14 | Control method for turning on power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002010488A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8278992B2 (en) | 2009-10-26 | 2012-10-02 | Samsung Electronics Co., Ltd. | Circuit and method for generating internal voltage, and semiconductor device having the circuit |
-
2000
- 2000-06-14 JP JP2000216634A patent/JP2002010488A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8278992B2 (en) | 2009-10-26 | 2012-10-02 | Samsung Electronics Co., Ltd. | Circuit and method for generating internal voltage, and semiconductor device having the circuit |
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