JP2001504998A - Ldd構造をもつmosトランジスタを有する半導体素子の製造方法 - Google Patents
Ldd構造をもつmosトランジスタを有する半導体素子の製造方法Info
- Publication number
- JP2001504998A JP2001504998A JP52943498A JP52943498A JP2001504998A JP 2001504998 A JP2001504998 A JP 2001504998A JP 52943498 A JP52943498 A JP 52943498A JP 52943498 A JP52943498 A JP 52943498A JP 2001504998 A JP2001504998 A JP 2001504998A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate electrode
- semiconductor material
- manufacturing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000002019 doping agent Substances 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 22
- 239000012212 insulator Substances 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims 1
- 230000004913 activation Effects 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 11
- 229910006990 Si1-xGex Inorganic materials 0.000 description 10
- 229910007020 Si1−xGex Inorganic materials 0.000 description 10
- 108091006146 Channels Proteins 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 241000238558 Eucarida Species 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 241000282376 Panthera tigris Species 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/923—Diffusion through a layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. ゲートの誘電体とゲート電極をシリコン基板の表面に形成し、前記ゲート電 極に隣接する前記表面を露出させ、半導体物質の層を、前記ゲート電極と前記 半導体物質の層とをマスクとして前記ゲート電極に隣接している前記表面のエ ッジで前記シリコン基板内に形成し、イオンを注入し、そして、前記注入され たイオンの活性化と前記半導体物質の層からのドーパント原子の拡散とによっ てソースゾーンとドレインゾーンが形成されるように熱処理を行う、MOSトラ ンジスタを有する半導体素子の製造方法において、Si1-xGex(0.1<x<0.6)か らなる半導体物質層を、前記ゲート電極に直近で隣接する前記エッジ上に設け 、前記熱処理の後その層を選択的にエッチ除去することを特徴とする半導体素 子の製造方法。 2. Si1-xGex(0.1<X<0.6)からなる前記半導体物質層を非単結晶の形態で設ける ことを特徴とする請求項1に記載の半導体素子の製造方法。 3. 前記半導体物質の層をエッチ除去した後に、側壁絶縁体を前記ゲート電極の 前記側壁と前記ゲート電極に隣接する前記表面の前記エッジに設けることを特 徴とする請求項1または2に記載の半導体素子の製造方法。 4. 前記半導体物質の層を設ける前に、前記ゲート電極上と前記ゲート電極に燐 接する前記表面の上に厚さ2-10nmの酸化物層が形成される熱酸化を行うことを 特徴とする請求項1、2または3の何れかに記載の半導体素子の製造方法。 5. 前記ゲート電極に隣接する前記表面を露出させた後に、前記ゲート誘電体の 厚みよりも小である厚さまで熱酸化により前記酸化物層を設けることを特徴と する請求項4に記載の半導体素子の製造方法。 6. 半導体物質層の前記層を設ける前に、前記ゲート電極に隣接する前記表面が 露出されるまで、前記酸化物層に異方性エッチング処理を行うことを特徴とす る請求項4または5に記載の半導体素子の製造方法。 7. 前記半導体物質の層を前記ゲート電極に直近で隣接する位置に有る前記表面 の前記エッジに形成するまで、この層にドーパント原子を供給しないことを 特徴とする前項何れかの請求項に記載の半導体素子の製造方法。 8. 前記ソースコンタクトゾーンと前記ドレインコンタクトゾーンを形成するた めに前記表面にイオンを注入する間に、イオンを同時に前記ゲート電極に直近 で隣接する前記エッジで前記半導体物質の層に注入することを特徴とする請求 項7に記載の半導体素子の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97201562.2 | 1997-05-23 | ||
EP97201562 | 1997-05-23 | ||
PCT/IB1998/000633 WO1998053491A2 (en) | 1997-05-23 | 1998-04-27 | Manufacture of a semiconductor device with a mos transistor having an ldd structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001504998A true JP2001504998A (ja) | 2001-04-10 |
JP3827734B2 JP3827734B2 (ja) | 2006-09-27 |
Family
ID=8228357
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52943498A Expired - Fee Related JP3827734B2 (ja) | 1997-05-23 | 1998-04-27 | Ldd構造をもつmosトランジスタを有する半導体素子の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6255183B1 (ja) |
EP (1) | EP0939974B1 (ja) |
JP (1) | JP3827734B2 (ja) |
DE (1) | DE69836124T2 (ja) |
WO (1) | WO1998053491A2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6506653B1 (en) * | 2000-03-13 | 2003-01-14 | International Business Machines Corporation | Method using disposable and permanent films for diffusion and implant doping |
KR100386674B1 (ko) | 2000-11-27 | 2003-06-02 | 이진구 | 파이형 구조의 게이트를 갖는 트랜지스터 및 그의 제조 방법 |
ATE544176T1 (de) | 2001-07-18 | 2012-02-15 | Infineon Technologies Ag | Selektives basisätzen |
US7344934B2 (en) * | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
US7928577B2 (en) * | 2008-07-16 | 2011-04-19 | Micron Technology, Inc. | Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the same |
US8741704B2 (en) | 2012-03-08 | 2014-06-03 | International Business Machines Corporation | Metal oxide semiconductor (MOS) device with locally thickened gate oxide |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5238859A (en) * | 1988-04-26 | 1993-08-24 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
US5306655A (en) * | 1990-07-24 | 1994-04-26 | Matsushita Electric Industrial Co., Ltd. | Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions |
JP2994128B2 (ja) * | 1991-03-04 | 1999-12-27 | シャープ株式会社 | 半導体装置の製造方法 |
US5212110A (en) * | 1992-05-26 | 1993-05-18 | Motorola, Inc. | Method for forming isolation regions in a semiconductor device |
US5391508A (en) | 1992-12-21 | 1995-02-21 | Sharp Kabushiki Kaisha | Method of forming semiconductor transistor devices |
US5281552A (en) * | 1993-02-23 | 1994-01-25 | At&T Bell Laboratories | MOS fabrication process, including deposition of a boron-doped diffusion source layer |
US5571744A (en) * | 1993-08-27 | 1996-11-05 | National Semiconductor Corporation | Defect free CMOS process |
US5654212A (en) * | 1995-06-30 | 1997-08-05 | Winbond Electronics Corp. | Method for making a variable length LDD spacer structure |
US5637514A (en) * | 1995-10-18 | 1997-06-10 | Micron Technology, Inc. | Method of forming a field effect transistor |
US5710054A (en) * | 1996-08-26 | 1998-01-20 | Advanced Micro Devices, Inc. | Method of forming a shallow junction by diffusion from a silicon-based spacer |
TW302539B (en) * | 1996-08-26 | 1997-04-11 | Lin Horng Hyh | Manufacturing method of deep submicron PMOS device shallow junction |
US6087239A (en) * | 1996-11-22 | 2000-07-11 | Micron Technology, Inc. | Disposable spacer and method of forming and using same |
US5874343A (en) * | 1996-12-06 | 1999-02-23 | Advanced Micro Devices, Inc. | CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof |
-
1998
- 1998-04-22 US US09/064,207 patent/US6255183B1/en not_active Expired - Lifetime
- 1998-04-27 DE DE69836124T patent/DE69836124T2/de not_active Expired - Fee Related
- 1998-04-27 EP EP98913989A patent/EP0939974B1/en not_active Expired - Lifetime
- 1998-04-27 JP JP52943498A patent/JP3827734B2/ja not_active Expired - Fee Related
- 1998-04-27 WO PCT/IB1998/000633 patent/WO1998053491A2/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
WO1998053491A3 (en) | 1999-02-25 |
EP0939974B1 (en) | 2006-10-11 |
DE69836124T2 (de) | 2007-08-23 |
JP3827734B2 (ja) | 2006-09-27 |
US6255183B1 (en) | 2001-07-03 |
WO1998053491A2 (en) | 1998-11-26 |
DE69836124D1 (de) | 2006-11-23 |
EP0939974A2 (en) | 1999-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5437112B2 (ja) | 金属酸化物半導体デバイスのゲート電極を形成する方法及び金属酸化物半導体デバイスを形成する方法 | |
KR100199527B1 (ko) | 약하게 도핑된 드레인(ldd)형의 cmos장치제조방법 | |
JPH11111982A (ja) | 半導体素子の製造方法 | |
KR100396692B1 (ko) | 반도체 소자의 제조방법 | |
US6258646B1 (en) | CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof | |
EP0459398B1 (en) | Manufacturing method of a channel in MOS semiconductor devices | |
JP2001156059A (ja) | 絶縁膜の形成方法および半導体装置の製造方法 | |
US6245603B1 (en) | Manufacturing method for semiconductor device | |
JP2001504998A (ja) | Ldd構造をもつmosトランジスタを有する半導体素子の製造方法 | |
US6069046A (en) | Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment | |
JP2733082B2 (ja) | Mos装置の製法 | |
JP2001196469A (ja) | 半導体装置の製造方法 | |
KR100617068B1 (ko) | 반도체 소자의 제조방법 | |
KR100940996B1 (ko) | 반도체 소자의 실리사이드층 형성 방법 | |
KR100628253B1 (ko) | 반도체 소자의 자기 정렬 실리사이드 형성방법 | |
KR100705233B1 (ko) | 반도체 소자의 제조 방법 | |
KR100481381B1 (ko) | 반도체 소자 제조 방법 | |
KR100491419B1 (ko) | 반도체 소자의 제조 방법 | |
JPH10223887A (ja) | 半導体装置の製造方法 | |
KR101079873B1 (ko) | 반도체 소자의 형성 방법 | |
KR100333647B1 (ko) | 반도체소자의자기정렬실리사이드막을이용한전계효과트랜지스터제조방법 | |
KR100995332B1 (ko) | 반도체 소자의 제조 방법 | |
KR101016337B1 (ko) | 반도체 소자의 제조 방법 | |
KR101004808B1 (ko) | 반도체 소자의 실리사이드 형성 방법 | |
KR100382552B1 (ko) | 반도체 소자의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050324 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050426 |
|
A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20050722 |
|
A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20051024 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051108 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060207 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20060328 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060606 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060705 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090714 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100714 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110714 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110714 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120714 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |