JP2001332860A - Multi-layered wiring board, semiconductor device, electronic device, and their manufacturing method - Google Patents
Multi-layered wiring board, semiconductor device, electronic device, and their manufacturing methodInfo
- Publication number
- JP2001332860A JP2001332860A JP2000152701A JP2000152701A JP2001332860A JP 2001332860 A JP2001332860 A JP 2001332860A JP 2000152701 A JP2000152701 A JP 2000152701A JP 2000152701 A JP2000152701 A JP 2000152701A JP 2001332860 A JP2001332860 A JP 2001332860A
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- wiring board
- insulating base
- wiring
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＴＣＰテープ、ま
たはガラエポに多層配線を形成した配線基板及びそれに
半導体チップを搭載した半導体装置及びそれを用いた電
子装置及びそれらの製造方法に適用して有効な技術に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is effective when applied to a wiring board having a multilayer wiring formed on a TCP tape or glass epoxy, a semiconductor device having a semiconductor chip mounted thereon, an electronic device using the same, and a method of manufacturing the same. Technology.
【０００２】[0002]
【従来の技術】図１０は、従来の多層配線基板及びそれ
に半導体チップを搭載した半導体装置の構成を説明する
ための断面図である。2. Description of the Related Art FIG. 10 is a cross-sectional view for explaining the structure of a conventional multilayer wiring board and a semiconductor device having a semiconductor chip mounted thereon.
【０００３】従来の半導体装置は、図１０に示すよう
に、上下面に配線パターンを持つ全２層（上下面各１
層）の配線パターン３０を形成した配線基板（ここで
は、ＴＡＢテープ）２０ａに半導体チップ１を搭載した
ものである。半導体チップ１の外部電極２と配線パター
ン３０の上面の配線パターン３０とは、例えば、金錫接
合で接続される。２層の配線パターン３０は、それぞれ
ビアホール７０内に形成された銅めっきで接続される。
また、配線基板２０ａの絶縁基材としてはポリイミドを
用い、配線パターンには銅箔を用いる。As shown in FIG. 10, a conventional semiconductor device has a total of two layers (one for each upper and lower surface) having wiring patterns on the upper and lower surfaces.
The semiconductor chip 1 is mounted on a wiring board (here, a TAB tape) 20a on which a wiring pattern 30 of a layer is formed. The external electrodes 2 of the semiconductor chip 1 and the wiring pattern 30 on the upper surface of the wiring pattern 30 are connected by, for example, gold-tin bonding. The two-layer wiring patterns 30 are connected by copper plating formed in the via holes 70, respectively.
In addition, polyimide is used as an insulating base material of the wiring board 20a, and copper foil is used as a wiring pattern.
【０００４】そして、電子装置のマザーボード搭載用の
外部端子としての役目を持つＢＧＡボール３５を配線パ
ターン３０上に形成する。なお、このＢＧＡボール３５
には、例えば、３７Ｐｂ−６３Ｓｎの共晶組成の半田ボ
ール０．３mmφを用いる。[0004] Then, BGA balls 35 serving as external terminals for mounting the motherboard of the electronic device are formed on the wiring pattern 30. The BGA ball 35
For example, a 0.3 mmφ solder ball having a eutectic composition of 37Pb-63Sn is used.
【０００５】次に、従来の半導体装置１０ａの製造方法
について説明する。まず、配線基板の製造方法について
説明する。Next, a method of manufacturing the conventional semiconductor device 10a will be described. First, a method for manufacturing a wiring board will be described.
【０００６】図１１及び図１２は、従来の半導体装置１
０ａに用いる配線基板２０ａの製造方法を説明するため
の断面図である。FIGS. 11 and 12 show a conventional semiconductor device 1.
FIG. 10 is a cross-sectional view for describing a method of manufacturing wiring substrate 20a used for Oa.
【０００７】従来の配線基板２０ａの製造方法は、ま
ず、図１１（ａ）に示すように、約２５μｍ〜１２５μ
ｍの厚さのポリイミドフィルム４０の両面（上下面）に
８μｍ〜１８μｍの厚さ、９９．９９９９重量％の純度
のＯＦＣ（Oxygen Free Copper、酸素濃度が０．３ＰＰ
Ｍ以下）銅箔５０を形成する。これはＯＦＣ銅箔５０の
表面にポリイミドワニスを連続ロールコートしてから焼
き付けることによって製造する。A conventional method of manufacturing a wiring board 20a firstly employs a method of manufacturing a wiring board 20a of about 25 μm to 125 μm as shown in FIG.
8 μm to 18 μm thick, 99.9999 wt% pure OFC (Oxygen Free Copper, oxygen concentration 0.3 PP) on both sides (upper and lower surfaces) of the polyimide film 40 having a thickness of m.
M or less) A copper foil 50 is formed. This is manufactured by continuous roll coating of the polyimide varnish on the surface of the OFC copper foil 50 and then baking.
【０００８】次に、図１１（ｂ）に示すように、そのポ
リイミドフィルム４０の片面に対してホトレジスト６０
を形成し、露光現像してビアホール形成箇所をエッチン
グする。Next, as shown in FIG. 11B, a photoresist 60 is applied to one side of the polyimide film 40.
Is formed, and is exposed and developed to etch the via hole formation portion.
【０００９】次に、図１１（ｃ）に示すように、ホトレ
ジスト６０を基にエッチングして例えば、０．２mmφの
ビアホール（穴）７０を上面の銅箔５０に開ける。Next, as shown in FIG. 11C, a via hole (hole) 70 of, for example, 0.2 mmφ is formed in the copper foil 50 on the upper surface by etching based on the photoresist 60.
【００１０】次に、図１１（ｄ）に示すように、ホトレ
ジスト６０を取り除く。Next, as shown in FIG. 11D, the photoresist 60 is removed.
【００１１】次に、図１１（ｅ）に示すように、炭酸ガ
スレーザにより、０．２mmφのビアホール（穴）７０を
ポリイミドフィルム４０に開け、下面の銅箔５０の裏面
を露出させ、レーザ加工によって生じた残漬を取り除
く。Next, as shown in FIG. 11 (e), a 0.2 mmφ via hole (hole) 70 is opened in the polyimide film 40 with a carbon dioxide gas laser to expose the lower surface of the copper foil 50 on the lower surface. Remove the resulting pickles.
【００１２】次に、図１２（ｆ）に示すように、ポリイ
ミドフィルム４０のビアホール７０の側面にパラジウム
触媒８０を塗布し、上下面の銅箔５０を電極に電気めっ
きを行い、図１２（ｇ）に示すように、上面の銅箔５０
表面部及びビアホール７０側面部に銅めっき９０層を形
成する。Next, as shown in FIG. 12 (f), a palladium catalyst 80 is applied to the side surfaces of the via holes 70 of the polyimide film 40, and the copper foils 50 on the upper and lower surfaces are subjected to electroplating using the electrodes to form the electrodes shown in FIG. As shown in FIG.
A copper plating 90 layer is formed on the surface and the side surface of the via hole 70.
【００１３】次に、図１２（ｈ）示すように、両面の銅
箔５０をエッチングして、上下面に配線パターン３０を
形成する。Next, as shown in FIG. 12 (h), the copper foils 50 on both sides are etched to form wiring patterns 30 on the upper and lower surfaces.
【００１４】次に、図１２（ｉ）に示すように、下面の
配線パターン３０上に３７Ｐｂ−Ｓｎの共晶組成の半田
ボール０．３mmφ（ＢＧＡボール）３５を形成し、上面
の配線パターン３０上に半導体チップ１を搭載し、それ
ぞれの接続部分をレジン１００で封止することによって
製造する。なお、配線基板２０ａへの半導体チップ１搭
載は、例えば、金錫接続で行う。Next, as shown in FIG. 12 (i), a solder ball 0.3 mmφ (BGA ball) 35 having a eutectic composition of 37Pb—Sn is formed on the lower wiring pattern 30, and the upper wiring pattern 30 is formed. It is manufactured by mounting the semiconductor chip 1 thereon and sealing each connection portion with the resin 100. The mounting of the semiconductor chip 1 on the wiring board 20a is performed by, for example, gold-tin connection.
【００１５】[0015]
【発明が解決しようとする課題】上述した従来の配線基
板２０ａ及び半導体装置１０ａは以下に示すような問題
点がある。The above-described conventional wiring board 20a and semiconductor device 10a have the following problems.
【００１６】従来の半導体装置１０ａにおける配線基板
２０ａは、ビアホール７０内に銅めっき層９０を形成す
る際に、上面配線パターン３０上の半導体チップ１が搭
載される部分にも銅めっき層９０が形成されるため、配
線パターン３０上の平坦性が失われてしまう。In the conventional wiring board 20a of the semiconductor device 10a, when the copper plating layer 90 is formed in the via hole 70, the copper plating layer 90 is also formed on the portion of the upper wiring pattern 30 where the semiconductor chip 1 is mounted. Therefore, the flatness on the wiring pattern 30 is lost.
【００１７】このために、配線基板２０ａにおける配線
パターン３０上への部品搭載（ここでは、半導体チップ
１搭載）において、接続不良を生じるという問題点があ
った。For this reason, there is a problem that a connection failure occurs when components are mounted on the wiring pattern 30 on the wiring substrate 20a (here, the semiconductor chip 1 is mounted).
【００１８】また、銅めっき層９０は、配線基板２０ａ
のビアホール７０内の側面に密着形成され、上下面の配
線パターン３０の導通が取れる範囲内で極薄く（約７μ
ｍ厚）形成される。The copper plating layer 90 is formed on the wiring board 20a.
Is formed in close contact with the side surface in the via hole 70, and is extremely thin (approximately
m thickness).
【００１９】このため、温度サイクル試験において、配
線基板２０ａの絶縁基材（ポリイミドフィルム）４０の
熱膨張係数と、銅めっき層９０の銅の熱膨張係数との違
いから発生する熱応力によって銅めっき層９０が切断さ
れてしまうという問題点があった。特に、絶縁基材がガ
ラスエポキシのように熱膨張係数が余りにも違う場合
は、より切断されやすい。Therefore, in the temperature cycle test, the copper plating is performed by the thermal stress generated from the difference between the thermal expansion coefficient of the insulating base material (polyimide film) 40 of the wiring board 20a and the thermal expansion coefficient of the copper of the copper plating layer 90. There is a problem that the layer 90 is cut. In particular, when the insulating base material has a significantly different coefficient of thermal expansion such as glass epoxy, the insulating substrate is more easily cut.
【００２０】本発明は、上記問題点を解決するために成
されたものであり、多層配線された配線基板において、
搭載する部品の接続不良の防止、及び熱応力により生じ
るめっき層の切断の防止を行うことが可能な技術を提供
することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in a wiring board having a multilayer wiring structure.
It is an object of the present invention to provide a technique capable of preventing a connection failure of a mounted component and preventing a plating layer from being cut off due to thermal stress.
【００２１】[0021]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【００２２】（１）導電性材料で形成された複数層の配
線パターンが絶縁基材内外に配設され、前記絶縁基材内
に形成したビアホールを金属めっきで埋め込んだ埋め込
み型金属めっきでそれら複数層の配線パターン間を互い
に接続した、電子部品を搭載する多層配線基板であっ
て、前記埋め込み型金属めっきは、互いに接続する前記
複数の配線パターン間で接続支持され、前記ビアホール
内の絶縁基材とは接合（接着）しない。(1) Plural layers of wiring patterns formed of a conductive material are disposed inside and outside an insulating base material, and the plurality of wiring patterns are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. A multilayer wiring board, on which electronic components are mounted, in which wiring patterns of layers are connected to each other, wherein the embedded metal plating is connected and supported between the plurality of wiring patterns connected to each other, and an insulating base material in the via hole. Does not join (adhere).
【００２３】（２）（１）の多層配線基板において、前
記埋め込み型金属めっきの形状は、円柱、またはｎ（ｎ
は３以上の整数）角柱である。(2) In the multilayer wiring board of (1), the shape of the buried metal plating is a column or n (n
Is an integer of 3 or more) prism.
【００２４】（３）（１）の多層配線基板において、前
記埋め込み型金属めっきの形状は、外形表面積を大きく
する加工をした円柱、またはｎ（ｎは３以上の整数）角
柱である。(3) In the multilayer wiring board of (1), the shape of the buried metal plating is a column processed to increase the external surface area or an n (n is an integer of 3 or more) prism.
【００２５】（４）（１）の多層配線基板において、前
記埋め込み型金属めっきを、信号線の配線パターンと接
続される信号線用埋め込み型金属めっきと、グランド線
の配線パターンと接続され、前記信号線用埋め込み型金
属めっきを取り囲むように形成されたグランド線用埋め
込み型金属めっきと、から構成する。(4) In the multilayer wiring board according to (1), the embedded metal plating is connected to the embedded metal plating for a signal line connected to a wiring pattern of a signal line and the wiring pattern of a ground line. Embedded metal plating for ground lines formed so as to surround the embedded metal plating for signal lines.
【００２６】（５）導電性材料で形成された複数層の配
線パターンが絶縁基材内外に配設され、前記絶縁基材内
に形成したビアホールを金属めっきで埋め込んだ埋め込
み型金属めっきでそれら複数層の配線パターン間を互い
に接続した多層配線基板に半導体チップを搭載して樹脂
封止した半導体装置であって、前記埋め込み型金属めっ
きは、互いに接続する前記複数の配線パターン間で接続
支持され、前記ビアホール内の絶縁基材とは接合（接
着）しない。(5) A plurality of wiring patterns formed of a conductive material are disposed inside and outside the insulating base material, and the plurality of wiring patterns are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. A semiconductor device in which a semiconductor chip is mounted on a multi-layer wiring board in which layers of wiring patterns are connected to each other and sealed with a resin, wherein the embedded metal plating is connected and supported between the plurality of wiring patterns connected to each other, It does not bond (adhere) to the insulating base material in the via hole.
【００２７】（６）導電性材料で形成された複数層の配
線パターンが絶縁基材内外に配設され、前記絶縁基材内
に形成したビアホールを金属めっきで埋め込んだ埋め込
み型金属めっきでそれら複数層の配線パターン間を互い
に接続した多層配線基板と半導体チップとを接続して樹
脂封止した半導体装置と、前記半導体装置を搭載する配
線基板とを有する電子装置であって、前記埋め込み型金
属めっきは、互いに接続する前記複数の配線パターン間
で接続支持され、前記ビアホール内の絶縁基材とは接合
（接着）しない。(6) A plurality of wiring patterns formed of a conductive material are provided inside and outside the insulating base material, and the plurality of wiring patterns are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. An electronic device comprising: a semiconductor device in which a semiconductor chip is connected to a multi-layer wiring board in which wiring patterns of layers are connected to each other and a semiconductor chip is sealed with a resin; and a wiring board on which the semiconductor device is mounted; Are connected and supported between the plurality of wiring patterns connected to each other, and do not bond (adhere) to the insulating base material in the via hole.
【００２８】（７）導電性材料で形成された複数層の配
線パターンが絶縁基材内外に配設され、前記絶縁基材内
に形成したビアホールを金属めっきで埋め込んだ埋め込
み型金属めっきでそれら複数層の配線パターン間を互い
に接続した多層配線基板に、電子部品を搭載した電子装
置であって、前記埋め込み型金属めっきは、互いに接続
する前記複数の配線パターン間で接続支持され、前記ビ
アホール内の絶縁基材とは接合（接着）しない。(7) Plural layers of wiring patterns formed of a conductive material are disposed inside and outside the insulating base material, and the plurality of wiring patterns are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. An electronic device in which electronic components are mounted on a multilayer wiring board in which wiring patterns of layers are connected to each other, wherein the embedded metal plating is connected and supported between the plurality of wiring patterns connected to each other, and the inside of the via hole is provided. Does not bond (adhere) to the insulating substrate.
【００２９】（８）導電性材料で形成された複数層の配
線パターンが絶縁基材内外に配設され、前記配線パター
ン上に電子部品を搭載する多層配線基板の製造方法であ
って、絶縁基材の片面に導電性材料箔を形成し、その導
電性材料箔上にめっきレジストを形成し、前記導電性材
料箔の形成面と反対面に接着剤層を形成したものを用意
し、前記めっきレジスト、導電性材料箔、前記絶縁基
材、及び接着剤にビアホール（貫通穴）の形成加工を行
い、加工された前記絶縁基材の接着剤層側に新たな導電
性材料箔を形成し、上下面の導電性材料箔を電極に、上
下面の導電性材料箔とが互いに接合するまで金属の電気
めっきを行ってビアホール内に埋め込み型金属めっきを
形成し、前記めっきレジストを剥離し、上下面の導電性
材料箔に対してホトレジストを形成し、エッチングを行
って配線パターンを形成し、２層の配線基板を形成し、
その２層の配線基板を複数個形成し、それら複数個の２
層の配線基板を互いに貼り合わせていくことによって複
数層の配線パターンを有する多層配線基板を製造する。(8) A method for manufacturing a multilayer wiring board in which a plurality of wiring patterns formed of a conductive material are provided inside and outside an insulating base material and electronic components are mounted on the wiring patterns. A conductive material foil is formed on one side of the material, a plating resist is formed on the conductive material foil, and an adhesive layer is formed on the surface opposite to the surface on which the conductive material foil is formed. A via hole (through hole) is formed on the resist, the conductive material foil, the insulating base material, and the adhesive, and a new conductive material foil is formed on the adhesive layer side of the processed insulating base material, The conductive material foils on the upper and lower surfaces are used as electrodes, and metal is electroplated until the conductive material foils on the upper and lower surfaces are bonded to each other to form embedded metal plating in the via holes, and the plating resist is peeled off. Photo on the conductive material foil on the bottom Forming a resist, by etching to form a wiring pattern, to form a wiring board of the two layers,
A plurality of the two-layer wiring boards are formed, and
A multilayer wiring board having a wiring pattern of a plurality of layers is manufactured by bonding the wiring boards of the layers to each other.
【００３０】（９）導電性材料で形成された複数層の配
線パターンが絶縁基材内外に配設され、前記配線パター
ン上に電子部品を搭載する多層配線基板の製造方法であ
って、絶縁基材の上下面に導電性材料箔を形成したもの
を用意し、前記絶縁基材の上面の導電性材料箔及びビア
ホールを形成するための穴を形成し、下面の導電性材料
箔の裏面に達する深さを有するビアホールを前記絶縁基
材内に形成し、前記下面の導電性材料箔を電極に、上下
面の導電性材料箔とが互いに接合するまで金属の電気め
っきを行ってビアホール内に埋め込み型金属めっきを形
成し、上下面の導電性材料箔に対してホトレジストを形
成し、エッチングを行って配線パターンを形成し、２層
の配線基板を形成し、その２層の配線基板を複数個形成
し、それら複数個の２層の配線基板を互いに貼り合わせ
ていくことによって複数層の配線パターンを有する多層
配線基板を製造する。(9) A method of manufacturing a multilayer wiring board in which a plurality of wiring patterns formed of a conductive material are disposed inside and outside an insulating base material and electronic components are mounted on the wiring patterns. Prepare a conductive material foil formed on the upper and lower surfaces of the material, form a hole for forming a conductive material foil on the upper surface of the insulating base material and a via hole, and reach the back surface of the conductive material foil on the lower surface. A via hole having a depth is formed in the insulating base material, and the conductive material foil on the lower surface is used as an electrode, and electroplating of metal is performed until the conductive material foils on the upper and lower surfaces are bonded to each other, and embedded in the via hole. Mold metal plating is formed, a photoresist is formed on the upper and lower conductive material foils, etching is performed to form a wiring pattern, a two-layer wiring board is formed, and a plurality of the two-layer wiring boards are formed. Forming them Producing multilayer wiring board having a wiring pattern of a plurality of layers by a wiring substrate of two layers will laminated to each other.
【００３１】（１０）導電性材料で形成された複数層の
配線パターンが絶縁基材内外に配設された多層配線基板
上に半導体チップを搭載した半導体装置の製造方法であ
って、絶縁基材の片面に導電性材料箔を形成し、その導
電性材料箔上にめっきレジストを形成し、前記導電性材
料箔の形成面と反対面に接着剤層を形成したものを用意
し、前記めっきレジスト、導電性材料箔、前記絶縁基
材、及び接着剤にビアホール（貫通穴）の形成加工を行
い、加工された前記絶縁基材の接着剤層側に新たな導電
性材料箔を形成し、上下面の導電性材料箔を電極に、上
下面の導電性材料箔とが互いに接合するまで金属の電気
めっきを行ってビアホール内に埋め込み型金属めっきを
形成し、前記めっきレジストを剥離し、上下面の導電性
材料箔に対してホトレジストを形成し、エッチングを行
って配線パターンを形成し、２層の配線基板を形成し、
その２層の配線基板を複数個形成し、それら複数個の２
層の配線基板を互いに貼り合わせていくことによって複
数層の配線パターンを有する多層配線基板を形成し、前
記多層配線基板の表層の配線パターン上に半導体チップ
を接続し、前記多層配線基板の一部及び前記半導体チッ
プとの接続部分を樹脂封止して半導体装置を製造する。(10) A method of manufacturing a semiconductor device in which a semiconductor chip is mounted on a multilayer wiring board on which a plurality of wiring patterns formed of a conductive material are disposed inside and outside an insulating base material. A conductive material foil is formed on one surface of the conductive material foil, a plating resist is formed on the conductive material foil, and an adhesive layer is formed on a surface opposite to the surface on which the conductive material foil is formed. Forming a via hole (through hole) in the conductive material foil, the insulating base material, and the adhesive; forming a new conductive material foil on the processed adhesive base material on the adhesive layer side; The conductive material foil on the lower surface is used as an electrode, and metal plating is performed until the conductive material foils on the upper and lower surfaces are bonded to each other to form an embedded metal plating in the via hole, and the plating resist is peeled off. Of conductive material foil Forming a resist, by etching to form a wiring pattern, to form a wiring board of the two layers,
A plurality of the two-layer wiring boards are formed, and
Forming a multilayer wiring board having a wiring pattern of a plurality of layers by bonding the wiring boards of the layers together, connecting a semiconductor chip on a wiring pattern of a surface layer of the multilayer wiring board, and forming a part of the multilayer wiring board; Then, a semiconductor device is manufactured by sealing a connection portion with the semiconductor chip with a resin.
【００３２】（１１）導電性材料で形成された複数層の
配線パターンが絶縁基材内外に配設された多層配線基板
上に半導体チップを搭載した半導体装置の製造方法であ
って、絶縁基材の上下面に導電性材料箔を形成したもの
を用意し、前記絶縁基材の上面の導電性材料箔及びビア
ホールを形成するための穴を形成し、下面の導電性材料
箔の裏面に達する深さを有するビアホールを前記絶縁基
材内に形成し、前記下面の導電性材料箔を電極に、上下
面の導電性材料箔とが互いに接合するまで金属の電気め
っきを行ってビアホール内に埋め込み型金属めっきを形
成し、上下面の導電性材料箔に対してホトレジストを形
成し、エッチングを行って配線パターンを形成し、２層
の配線基板を形成し、その２層の配線基板を複数個形成
し、それら複数個の２層の配線基板を互いに貼り合わせ
ていくことによって複数層の配線パターンを有する多層
配線基板を形成し、前記多層配線基板の表層の配線パタ
ーン上に半導体チップを接続し、前記多層配線基板の一
部及び前記半導体チップとの接続部分を樹脂封止して半
導体装置を製造する。(11) A method of manufacturing a semiconductor device in which a semiconductor chip is mounted on a multilayer wiring board in which a plurality of wiring patterns formed of a conductive material are disposed inside and outside an insulating base material. Prepare a conductive material foil formed on the upper and lower surfaces, form a conductive material foil on the upper surface of the insulating base and a hole for forming a via hole, and reach the lower surface of the conductive material foil on the lower surface. Forming a via hole having a thickness in the insulating base material, performing electroplating of a metal until the conductive material foil on the lower surface is used as an electrode, and the conductive material foil on the upper and lower surfaces are bonded to each other, and embedded in the via hole. Metal plating is formed, photoresist is formed on the upper and lower conductive material foils, etching is performed to form a wiring pattern, a two-layer wiring board is formed, and a plurality of the two-layer wiring boards are formed. And several of them A multi-layered wiring board having a multi-layered wiring pattern is formed by bonding two-layered wiring boards to each other, and a semiconductor chip is connected to a wiring pattern on a surface layer of the multi-layered wiring board. The semiconductor device is manufactured by sealing the portion and the connection portion with the semiconductor chip with resin.
【００３３】これによって、半導体チップを搭載する多
層配線基板の配線パターン上にめっき層が形成されない
ため、配線パターン上の平坦性が確保できるので、半導
体チップ等の部品搭載における接続不良を防止できる。As a result, since a plating layer is not formed on the wiring pattern of the multilayer wiring board on which the semiconductor chip is mounted, flatness on the wiring pattern can be ensured, so that a connection failure in mounting a component such as a semiconductor chip can be prevented.
【００３４】また、埋め込み型金属めっきは、上下面に
形成される配線パターン同士で互いに接続されて支持し
ており、ビアホール内の絶縁基材とは一切接合（接着）
されない。このため、温度サイクル試験において、熱膨
張係数の違いによる熱応力を絶縁基材から受けないの
で、めっき層の切断を防止することが可能となる。The buried metal plating is connected to and supported by wiring patterns formed on the upper and lower surfaces, and is completely bonded (adhered) to the insulating base material in the via hole.
Not done. For this reason, in the temperature cycle test, thermal stress due to a difference in thermal expansion coefficient is not received from the insulating base material, so that the plating layer can be prevented from being cut.
【００３５】[0035]
【発明の実施の形態】本発明の実施の形態を図面を用い
て詳細に説明する。Embodiments of the present invention will be described in detail with reference to the drawings.
【００３６】図１は、本発明の一実施形態にかかる多層
配線基板を有する半導体装置の構成を説明するための図
であり、斜め上方から見た立体図である。図２は、図１
に示すＡ−Ａ線で切った断面図である。本実施形態では
多層配線基板として２層の配線パターンを有する配線基
板とそれを用いた半導体装置を取り挙げる。FIG. 1 is a view for explaining the configuration of a semiconductor device having a multilayer wiring board according to one embodiment of the present invention, and is a three-dimensional view as viewed from obliquely above. FIG. 2 shows FIG.
FIG. 3 is a sectional view taken along line AA shown in FIG. In the present embodiment, a wiring board having a two-layer wiring pattern and a semiconductor device using the same will be described as a multilayer wiring board.
【００３７】図１に示すように、本実施形態の半導体装
置１０は、ボリイミド、液晶ポリマ等のベースフィルム
４０の上下面に各１層の導電性材料箔（例えば、銅箔
等）の配線パターン３０が形成された２層の配線基板２
０に半導体チップ１を搭載した構成をとる。この２層の
配線パターン３０は、それぞれビアホール７０内を埋め
込むようにめっき形成された埋め込み型金属（例えば、
銅）めっき１１０で接続される。As shown in FIG. 1, the semiconductor device 10 of the present embodiment has a wiring pattern of one layer of conductive material foil (for example, copper foil or the like) on the upper and lower surfaces of a base film 40 such as polyimide or liquid crystal polymer. Two-layer wiring board 2 on which 30 is formed
0 has a configuration in which a semiconductor chip 1 is mounted. The two-layered wiring pattern 30 is formed of a buried metal (for example,
(Copper) plating 110 for connection.
【００３８】半導体チップ１の素子形成面には電極パッ
ドが所定ピッチで配列され、その電極パッド上に接続の
ためのバンプ（突起）が外部電極として形成されてい
る。この半導体チップ１の外部電極としては、例えば、
Ｔｉ，Ｃｒ，Ｃｕ，Ｎｉのスパッタ膜を順次形成し、そ
の後、金の電気めっきを行った金バンプ２を用いる。Electrode pads are arranged at a predetermined pitch on the element forming surface of the semiconductor chip 1, and bumps (projections) for connection are formed as external electrodes on the electrode pads. As an external electrode of the semiconductor chip 1, for example,
A gold bump 2 formed by sequentially forming a sputtered film of Ti, Cr, Cu, and Ni and then electroplating gold is used.
【００３９】そして、この配線基板２０への半導体チッ
プ１の実装は、図２に示すように、配線基板２０上の配
線パターン３０の接続部分に錫を被覆し、外部電極に形
成された金バンプ２の金との拡散反応によって金錫合金
（共晶接合）を形成する金錫接続で行われる。Then, as shown in FIG. 2, the semiconductor chip 1 is mounted on the wiring board 20 by coating a connection portion of the wiring pattern 30 on the wiring board 20 with tin and forming a gold bump formed on an external electrode. 2 is formed by gold-tin connection forming a gold-tin alloy (eutectic junction) by a diffusion reaction with gold.
【００４０】次に、本実施形態の配線基板２０及び半導
体装置１０の製造方法について図面を用いて詳細に説明
する。なお、本実施形態では、２通りの配線基板２０の
製造方法を説明する。Next, a method for manufacturing the wiring board 20 and the semiconductor device 10 of the present embodiment will be described in detail with reference to the drawings. In the present embodiment, two methods of manufacturing the wiring board 20 will be described.
【００４１】まず、本実施形態の配線基板２０の第１の
製造方法について説明する。First, a first method for manufacturing the wiring board 20 of the present embodiment will be described.
【００４２】図３は、本実施形態の配線基板２０の第１
の製造方法を説明するための図である。FIG. 3 shows a first example of the wiring board 20 of the present embodiment.
FIG. 7 is a diagram for explaining the manufacturing method of the first embodiment.
【００４３】本実施形態の配線基板２０の第１の製造方
法は、まず、図３（ａ）に示すように、絶縁基材である
ポリイミド等のベースフィルム４０の片面に導電性材料
箔（銅箔）５０を貼り付け、その銅箔５０上にめっきレ
ジスト６５を貼り付け、その反対面に接着剤５５を塗布
または貼り付けたものを用意する。このベースフィルム
４０の寸法は、例えば、幅３５〜３００mm、長さ１０〜
１００ｍ、厚さ２５μｍ〜１２５μｍである。また、銅
箔５０は、例えば、ベースフィルム４０と同等の幅，長
さを有し、厚さ２５μｍ〜１２５μｍである。また、絶
縁基材として液晶ポリマを用いても構わない。In the first method of manufacturing the wiring board 20 of the present embodiment, first, as shown in FIG. 3A, a conductive material foil (copper) is coated on one surface of a base film 40 such as polyimide which is an insulating base material. A foil 50 is adhered, a plating resist 65 is adhered on the copper foil 50, and an adhesive 55 is applied or adhered on the opposite surface. The dimensions of the base film 40 are, for example, 35 to 300 mm in width and 10 to 10 in length.
100 m and a thickness of 25 μm to 125 μm. The copper foil 50 has, for example, the same width and length as the base film 40, and has a thickness of 25 μm to 125 μm. Further, a liquid crystal polymer may be used as the insulating base material.
【００４４】次に、図３（ｂ）に示すように、そのベー
スフィルム４０に埋め込み型銅めっき１１０を形成する
ためのビアホール７０の穴形成加工を行う。なお、図示
しないが、パッケージ外形穴（最終的にパッケージ外形
加工するために一部分を予め切り抜いておくもの）の形
成も同時に行う。Next, as shown in FIG. 3B, a hole forming process of a via hole 70 for forming an embedded copper plating 110 in the base film 40 is performed. Although not shown, a package outer hole (one part of which is cut out in advance for final package outer shape processing) is also formed at the same time.
【００４５】その後、図３（ｃ）に示すように、その加
工されたベースフィルム４０の接着剤５５の形成側に、
ベースフィルム４０と同一の幅，長さの新たな銅箔５０
を貼り合せる。Thereafter, as shown in FIG. 3 (c), the processed base film 40 is placed on the side where the adhesive 55 is formed.
A new copper foil 50 having the same width and length as the base film 40
And stick them together.
【００４６】そして、図３（ｄ）に示すように、上下面
の銅箔５０を電極に電気めっきを行い、ビアホール７０
内に埋め込み型銅めっき１１０を形成する。この埋め込
み型銅めっき１１０の形成の電気めっきは、下面と上面
の銅箔５０とが互いに接合するまで行われる。すなわ
ち、この埋め込み型銅めっき１１０により、ベースフィ
ルム４０の下面の銅箔５０の裏面と上面の銅箔５０の切
り出し側面部分とが電気的に接続される。Then, as shown in FIG. 3D, the copper foils 50 on the upper and lower surfaces are electroplated on the electrodes, and the via holes 70 are formed.
A buried copper plating 110 is formed therein. The electroplating for forming the embedded copper plating 110 is performed until the copper foil 50 on the lower surface and the upper surface is bonded to each other. That is, the embedded copper plating 110 electrically connects the back surface of the copper foil 50 on the lower surface of the base film 40 and the cut-out side surface portion of the copper foil 50 on the upper surface.
【００４７】次に、図３（ｅ）に示すように、めっきレ
ジスト６５を剥離する。これにより、上面の銅箔５０上
には銅めっきが形成されないことになる。Next, as shown in FIG. 3E, the plating resist 65 is peeled off. As a result, no copper plating is formed on the copper foil 50 on the upper surface.
【００４８】最後に、図３（ｆ）に示すように、上下面
の銅箔５０に対してホトレジストを形成し、エッチング
を行い、配線パターン３０を形成する。なお、半導体チ
ップと金錫接合する場合は、少なくともその半導体チッ
プの外部電極との接続を行う接続部分に錫めっきを施
す。Finally, as shown in FIG. 3 (f), a photoresist is formed on the upper and lower copper foils 50, and etching is performed to form a wiring pattern 30. When gold-tin bonding is performed on a semiconductor chip, tin plating is applied to at least a connection portion of the semiconductor chip for connection with an external electrode.
【００４９】これにより、本実施形態の配線基板２０を
製造する。Thus, the wiring board 20 of the present embodiment is manufactured.
【００５０】次に、本実施形態の配線基板２０の第２の
製造方法について説明する。Next, a second method of manufacturing the wiring board 20 of the present embodiment will be described.
【００５１】図４は、本実施形態の配線基板２０の第２
の製造方法を説明するための図である。FIG. 4 shows a second example of the wiring board 20 of this embodiment.
FIG. 7 is a diagram for explaining the manufacturing method of the first embodiment.
【００５２】本実施形態の配線基板２０の第２の製造方
法は、まず、図４（ａ）に示すように、絶縁基材である
ポリイミド等のベースフィルム４０の両面に導電性材料
箔（銅箔）５０を貼り付けたものを用意する。このベー
スフィルム４０及び銅箔５０の寸法は、第１の製造方法
と同様である。In the second method of manufacturing the wiring board 20 of the present embodiment, first, as shown in FIG. 4A, a conductive material foil (copper) is formed on both sides of a base film 40 such as polyimide which is an insulating base material. A foil (foil) 50 is prepared. The dimensions of the base film 40 and the copper foil 50 are the same as in the first manufacturing method.
【００５３】次に、図４（ｂ）に示すように、炭酸ガス
レーザ等で、ベースフィルム４０の上面の銅箔５０にビ
アホール７０を形成するための穴７５を形成する。Next, as shown in FIG. 4B, holes 75 for forming via holes 70 are formed in the copper foil 50 on the upper surface of the base film 40 by using a carbon dioxide laser or the like.
【００５４】次に、図４（ｃ）に示すように、そのベー
スフィルム４０に埋め込み型銅めっき１１０を形成する
ためのビアホール７０の穴形成加工を炭酸ガスレーザ等
により行う。このビアホール７０はベースフィルム４０
の下面の銅箔５０の裏面に達する深さである。なお、第
１の製造方法と同様に図示しないが、パッケージ外形穴
の形成も同時に行う。Next, as shown in FIG. 4C, a hole forming process of the via hole 70 for forming the embedded copper plating 110 in the base film 40 is performed by a carbon dioxide gas laser or the like. This via hole 70 is used for the base film 40.
Is the depth that reaches the rear surface of the copper foil 50 on the lower surface of FIG. Although not shown like the first manufacturing method, the package outer hole is also formed at the same time.
【００５５】そして、図４（ｄ）に示すように、下面の
銅箔５０のみを電極に電気めっきを行い、ビアホール７
０内に埋め込み型銅めっき１１０を形成する。この埋め
込み型銅めっき１１０の形成の電気めっきは、上面の銅
箔５０の高さまで達して接合されるまで行われ、上面の
銅箔５０上には銅めっきが形成されないようにする。こ
の埋め込み型銅めっき１１０により、ベースフィルム４
０の下面の銅箔５０の裏面と上面の銅箔５０の切り出し
側面部分とが電気的に接続される。Then, as shown in FIG. 4D, only the copper foil 50 on the lower surface is subjected to electroplating on the electrode to form a via hole 7.
A buried type copper plating 110 is formed in 0. The electroplating for forming the embedded copper plating 110 is performed until the copper foil 50 on the upper surface is joined to the upper surface of the copper foil 50, so that no copper plating is formed on the copper foil 50 on the upper surface. With this embedded copper plating 110, the base film 4
0, the back surface of the copper foil 50 on the lower surface and the cut-out side surface portion of the copper foil 50 on the upper surface are electrically connected.
【００５６】最後に、図４（ｅ）に示すように、上下面
の銅箔５０に対してホトレジストを形成し、エッチング
を行い、配線パターン３０を形成する。なお、半導体チ
ップと金錫接合する場合は、同様に、その半導体チップ
の外部電極との接続を行う接続部分に錫めっきを施す。Finally, as shown in FIG. 4E, a photoresist is formed on the upper and lower copper foils 50, and etching is performed to form a wiring pattern 30. In the case of gold-tin bonding with a semiconductor chip, similarly, tin plating is applied to a connection portion of the semiconductor chip for connection with an external electrode.
【００５７】これにより、本実施形態の配線基板２０を
製造する。この第２の製造方法では、めっきレジスト６
５を用いずに、第１の製造方法で製造した同一の配線基
板２０を製造できる。Thus, the wiring board 20 of the present embodiment is manufactured. In the second manufacturing method, the plating resist 6
5, the same wiring board 20 manufactured by the first manufacturing method can be manufactured.
【００５８】次に、上述した第１または第２の製造方法
で製造した配線基板２０に対して半導体チップを搭載す
る場合について説明する。図５は、本実施形態の配線基
板２０に半導体チップ１を搭載してパッケージングする
製造方法について説明するための図である。Next, a case where a semiconductor chip is mounted on the wiring board 20 manufactured by the above-described first or second manufacturing method will be described. FIG. 5 is a diagram for explaining a manufacturing method for mounting and packaging the semiconductor chip 1 on the wiring board 20 of the present embodiment.
【００５９】図５（ａ）に示すように、まず、半導体チ
ップ１の外部電極に金バンプ２を形成し、その金バンプ
と本実施形態の配線基板２０の配線パターン３０との位
置合わせを行い、配線パターン３０の錫めっきと、半導
体チップ１の金バンプ２との金錫接合を行い、図５
（ｂ）に示すように、それらの接続付近及び半導体チッ
プ１の外周部分と配線基板２０の一部をレジン１００で
封止する。As shown in FIG. 5A, first, gold bumps 2 are formed on the external electrodes of the semiconductor chip 1, and the gold bumps are aligned with the wiring patterns 30 of the wiring board 20 of the present embodiment. Then, tin plating of the wiring pattern 30 and gold-tin bonding with the gold bump 2 of the semiconductor chip 1 are performed, and FIG.
As shown in (b), the vicinity of the connection, the outer peripheral portion of the semiconductor chip 1 and a part of the wiring board 20 are sealed with a resin 100.
【００６０】これによって、本実施形態の半導体装置１
０を製造する。As a result, the semiconductor device 1 of the present embodiment
0 is produced.
【００６１】このように、本実施形態の配線基板２０及
び半導体装置１０では、半導体チップを搭載する配線パ
ターン上にめっき層が形成されないため、配線パターン
上の平坦性が確保できるので、半導体チップ等の部品搭
載における接続不良を防止できる。As described above, in the wiring board 20 and the semiconductor device 10 of the present embodiment, since the plating layer is not formed on the wiring pattern on which the semiconductor chip is mounted, the flatness on the wiring pattern can be ensured. Connection failure in component mounting can be prevented.
【００６２】また、本実施形態の埋め込み型銅めっき１
１０は、上下面に形成される配線パターン３０同士で互
いに接続されて支持しており、ビアホール７０内のポリ
イミド等のベールフィルム４０とは一切接合（接着）さ
れない。このように、埋め込み型銅めっき層１１０は同
一の材料（特に、熱膨張係数が同一）である銅の配線パ
ターン３０によって支えられているため、温度サイクル
試験において、熱膨張係数の違いによる熱応力をベース
フィルム４０から受けないので、めっき層の切断を防止
することが可能となる。なお、埋め込み型金属めっきは
本実施形態のように銅めっきと限定されるものではな
い。配線パターン３０の熱膨張係数と差がなく、導電性
が高いものであれば他の金属めっきでも構わない。The embedded copper plating 1 of the present embodiment
Numerals 10 are connected and supported by wiring patterns 30 formed on the upper and lower surfaces, and are not bonded (adhered) to the veil film 40 such as polyimide in the via hole 70 at all. As described above, since the embedded copper plating layer 110 is supported by the copper wiring pattern 30 made of the same material (especially, the same thermal expansion coefficient), in the temperature cycle test, the thermal stress due to the difference in the thermal expansion coefficient is increased. From the base film 40, it is possible to prevent the plating layer from being cut. The embedded metal plating is not limited to copper plating as in the present embodiment. Other metal plating may be used as long as there is no difference from the coefficient of thermal expansion of the wiring pattern 30 and the wiring pattern 30 has high conductivity.
【００６３】次に、上述した埋め込み型銅めっき１１０
について図面を用いて詳細に説明する。Next, the above-described embedded copper plating 110
Will be described in detail with reference to the drawings.
【００６４】本実施形態の埋め込み型銅めっき１１０
は、図６（ａ）に示すように、一般に円柱の形状のもの
が考えられるが、本発明はこれに限定されずに、炭酸ガ
スレーザ等による自由な形状の穴開け加工を利用するこ
とによって、例えば、図６（ｂ）に示すように四角柱に
形成したり、図６（ｃ）に示すように、三角柱に形成し
ても構わない。The embedded copper plating 110 of the present embodiment
As shown in FIG. 6 (a), generally, a cylindrical shape can be considered. However, the present invention is not limited to this. By using a free-form drilling process using a carbon dioxide laser or the like, For example, it may be formed in a square pole as shown in FIG. 6B, or may be formed in a triangular pole as shown in FIG. 6C.
【００６５】特に、近年では半導体装置の小型化に伴い
配線基板の配線も細かくなってきており、基板内に十分
なスペースがとれないのが現状である。このため、多層
配線の導通をとる埋め込み型銅めっきを空いているスペ
ースの形状に合わせ、形状を変えていくことにより、導
通ビア確保のための余分なスペースをとらなくても済
み、配線基板を小型化できる。なお、この埋め込み型銅
めっきの形状は、上述形状に限定されるものではなく、
他の角柱、例えば、ｎ（ｎは３以上の整数）角柱であっ
ても構わない。In particular, in recent years, with the miniaturization of the semiconductor device, the wiring of the wiring board has become finer, and at present, a sufficient space cannot be taken in the board. Therefore, by changing the shape of the buried copper plating that takes the conduction of the multilayer wiring into the shape of the vacant space and changing the shape, it is not necessary to take extra space to secure conduction vias, and Can be downsized. The shape of the embedded copper plating is not limited to the above-described shape,
Other prisms, for example, n (n is an integer of 3 or more) prisms may be used.
【００６６】また、配線基板の小型化に伴い、配線幅が
減少して配線の抵抗値が上昇する傾向にある。このよう
な場合は、埋め込み型銅めっき１１０の形状を表面積が
より大きく取れるように加工するよい。例えば、図６
（ｂ）に示す四角柱の埋め込み型銅めっき１１０を、図
７（ｂ）に示すように、より表面積が多く取れる十字型
の角柱形状にして多層配線の抵抗値を高くしないように
することも可能である。Further, as the size of the wiring board is reduced, the wiring width tends to decrease and the resistance value of the wiring tends to increase. In such a case, the shape of the embedded copper plating 110 may be processed so that a larger surface area can be obtained. For example, FIG.
As shown in FIG. 7B, the square pillar embedded copper plating 110 shown in FIG. 7B may be formed in a cross-shaped prism shape having a larger surface area so as not to increase the resistance value of the multilayer wiring. It is possible.
【００６７】また、配線基板の小型化に伴い、導通ビア
の間隔も狭まってきており、特に高速動作する半導体装
置では、導通ビア間のクロストークも問題になって来て
いる。従来では、この導通ビア間のクロストークの対策
がなかったが、例えば、図７（ａ）に示すように、円柱
形状の埋め込み型銅めっきを信号線用の埋め込み型銅め
っき１１０ａとし、それを一部が欠けた円筒形状（欠け
た部分には信号線用の導通ビアと接続される配線パター
ン３０が形成される）のグランド線用の埋め込み型銅め
っき（導通ビア）で囲むように形成したグランド線用埋
め込み型銅めっき１１０ｂを設けることにより、導通ビ
ア間のクロストークをも対策することができる。なお、
この場合はグランド線用埋め込み型銅めっき１１０ｂの
円筒状の一部欠け部分を隣の信号線用埋め込み型銅めっ
き１１０ａが剥き出しになっている位置に設けないよう
にすることにより、よりクロストークを抑止する効果が
ある。これによって高速動作する半導体装置にも適応可
能になる。Further, as the size of the wiring board is reduced, the spacing between the conductive vias is becoming narrower. In particular, in a semiconductor device operating at a high speed, crosstalk between the conductive vias is becoming a problem. Conventionally, there has been no countermeasure for the crosstalk between the conductive vias. For example, as shown in FIG. 7A, a columnar embedded copper plating is used as an embedded copper plating 110a for a signal line. It was formed so as to be surrounded by a buried copper plating (conductive via) for a ground line in a cylindrical shape with a part missing (a wiring pattern 30 connected to a conductive via for a signal line is formed in the missing part). By providing the embedded copper plating 110b for the ground line, it is possible to prevent crosstalk between the conductive vias. In addition,
In this case, the crosstalk can be further reduced by preventing the cylindrical part of the embedded copper plating 110b for the ground line from being provided at a position where the embedded copper plating 110a for the adjacent signal line is exposed. It has a deterrent effect. This makes it applicable to a semiconductor device operating at high speed.
【００６８】さらに、炭酸ガスレーザ等による自由な形
状の穴開け加工を利用することによって、図８に示すよ
うに、本実施形態のビアホール７０内の埋め込み型銅め
っき１１０を配線パターン３０の代替として配線形状に
形成し、導通ビアによる配線（以下、導通ビア配線と記
す）を行ってもよい。図８（ａ）に示す例は直線を用い
た配線、図８（ｂ）に示す例は曲線を用いた配線をそれ
ぞれ示す。これらも炭酸ガスレーザ等による自由な形状
の穴開け加工を利用することによって、これら形状に限
定されずに様々な形状にすることが可能である。As shown in FIG. 8, the buried copper plating 110 in the via hole 70 according to the present embodiment is replaced with the wiring pattern 30 by using a free-form drilling process using a carbon dioxide laser or the like. The wiring may be formed in a shape, and wiring using conductive vias (hereinafter, referred to as conductive via wiring) may be performed. The example shown in FIG. 8A shows wiring using a straight line, and the example shown in FIG. 8B shows wiring using a curve. These can also be formed in various shapes without being limited to these shapes by using a free-form boring process using a carbon dioxide laser or the like.
【００６９】この本実施形態の埋め込み型銅めっき１１
０を用いた導通ビア配線は、絶縁基材（例えば、ポリイ
ミドフィルム）内にめっき形成されるため、配線基板２
０の配線パターン３０より厚さ（ポリイミドフィルムと
ほぼ同じ厚さ）があるため、配線に同一の抵抗値を持た
せると仮定すると、配線の厚さが薄い配線パターン３０
の配線幅よりも細く形成することができる。The embedded copper plating 11 of the present embodiment
0 is formed on the insulating base material (for example, a polyimide film) by plating.
Since the thickness of the wiring pattern 30 is smaller than that of the wiring pattern 30 (substantially the same thickness as the polyimide film), it is assumed that the wiring has the same resistance value.
Can be formed to be narrower than the wiring width.
【００７０】したがって、この本実施形態の埋め込み型
銅めっき１１０を用いた導通ビア配線を積極的に用いる
ことで配線基板２０の小型化を図ることができる。Therefore, the size of the wiring board 20 can be reduced by positively using the conductive via wiring using the embedded copper plating 110 of this embodiment.
【００７１】次に、上述した埋め込み型銅めっき１１０
を用いた配線基板２０を有する半導体装置１０を電子装
置に搭載した例について説明する。Next, the above-described embedded copper plating 110
An example in which the semiconductor device 10 having the wiring substrate 20 using a semiconductor device is mounted on an electronic device will be described.
【００７２】図９は、埋め込み型銅めっき１１０を用い
た配線基板２０を有する半導体装置１０を搭載した電子
装置（ここでは、メモリモジュール）を示した図であ
り、図９（ａ）は上から見た平面図、図９（ｂ）は図９
（ａ）に示すＸ−Ｘ線で切った断面図である。FIG. 9 is a view showing an electronic device (here, a memory module) on which the semiconductor device 10 having the wiring board 20 using the embedded copper plating 110 is mounted, and FIG. FIG. 9B is a plan view of FIG.
It is sectional drawing cut | disconnected by XX shown to (a).
【００７３】図９（ａ）、図９（ｂ）において、２００
はメモリモジュール、２１０はマザーボード、２２０は
配線をそれぞれ示す。In FIGS. 9A and 9B, 200
Denotes a memory module, 210 denotes a motherboard, and 220 denotes wiring.
【００７４】上述した本実施形態の半導体装置は、高速
動作を行う場合に適しており、その半導体装置をこのメ
モリモジュール２００に搭載することによって、高速動
作を行う電子装置を提供することができる。The above-described semiconductor device of the present embodiment is suitable for performing high-speed operation. By mounting the semiconductor device on the memory module 200, an electronic device that performs high-speed operation can be provided.
【００７５】また、メモリモジュール２００のマザーボ
ード（例えば、ガラエポ基板）が多層配線を有する場合
には、その多層配線を接続する導通ビアとして埋め込み
型銅めっき１１０を用いて行うことにより、上述した本
実施形態の配線基板２０と同様に、搭載する部品の接続
不良の防止、及び熱応力により生じるめっき層の切断の
防止を行うことが可能になり、より高速に動作させるこ
とも可能である。When the mother board (eg, glass epoxy substrate) of the memory module 200 has a multilayer wiring, the embedded copper plating 110 is used as a conductive via for connecting the multilayer wiring, thereby implementing the above-described embodiment. As in the case of the wiring board 20 of the embodiment, it is possible to prevent poor connection of components to be mounted and to prevent cutting of the plating layer caused by thermal stress, and it is possible to operate at higher speed.
【００７６】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.
【００７７】[0077]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００７８】半導体チップを搭載する多層配線基板の配
線パターン上にはめっき層が形成されないため、配線パ
ターン上の平坦性が確保できるので、半導体チップ等の
部品搭載における接続不良を防止できる。Since no plating layer is formed on the wiring pattern of the multilayer wiring board on which the semiconductor chip is mounted, flatness on the wiring pattern can be ensured, so that a connection failure in mounting a component such as a semiconductor chip can be prevented.
【００７９】また、埋め込み型金属めっきは、上下面に
形成される配線パターン同士で互いに接続されて支持し
ており、ビアホール内の絶縁基材とは一切接合（接着）
されない。このため、温度サイクル試験において、熱膨
張係数の違いによる熱応力を絶縁基材から受けないの
で、めっき層の切断を防止することが可能となる。The embedded metal plating is connected and supported by wiring patterns formed on the upper and lower surfaces, and is completely bonded (adhered) to the insulating base material in the via hole.
Not done. For this reason, in the temperature cycle test, thermal stress due to a difference in thermal expansion coefficient is not received from the insulating base material, so that the plating layer can be prevented from being cut.
【図１】本発明の実施形態にかかる半導体装置の構成を
説明するための立体図である。FIG. 1 is a three-dimensional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.
【図２】図１に示すＡ−Ａ線で切った断面図である。FIG. 2 is a cross-sectional view taken along the line AA shown in FIG.
【図３】本実施形態の配線基板の第１の製造方法を説明
するための図である。FIG. 3 is a diagram illustrating a first method of manufacturing the wiring board according to the embodiment;
【図４】本実施形態の配線基板の第２の製造方法を説明
するための図である。FIG. 4 is a diagram illustrating a second method of manufacturing the wiring board according to the embodiment;
【図５】本実施例１の半導体装置の製造方法を説明する
ための断面図である。FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
【図６】本実施例の埋め込み型銅めっきの構成例を説明
するための図である。FIG. 6 is a diagram for explaining a configuration example of embedded copper plating according to the present embodiment.
【図７】本実施例の埋め込み型銅めっきの構成例を説明
するための図である。FIG. 7 is a diagram illustrating a configuration example of embedded copper plating according to the present embodiment.
【図８】本実施例の埋め込み型銅めっきの構成例を説明
するための図である。FIG. 8 is a diagram illustrating a configuration example of embedded copper plating according to the present embodiment.
【図９】本実施例のメモリモジュールの構成を説明する
ための図である。FIG. 9 is a diagram illustrating a configuration of a memory module according to the present embodiment.
【図１０】従来の半導体装置の構成を説明するための断
面図である。FIG. 10 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
【図１１】従来の半導体装置の製造方法を説明するため
の図である。FIG. 11 is a view for explaining a conventional method for manufacturing a semiconductor device.
【図１２】従来の半導体装置の製造方法を説明するため
の図である。FIG. 12 is a view illustrating a conventional method of manufacturing a semiconductor device.
１ 半導体チップ ２ 金バンプ １０ 半導体装置 ２０ 配線基板 ３０ 配線パターン ４０ ポリイミド（ベースフィルム） ５０ 銅箔 ５５ 接着剤 ６０ フォトレジスト ６５ めっきレジスト ７０ ビアホール ８０ Ｐｄ触媒 ９０ 銅めっき層 １００ レジン １１０ 埋め込み型銅めっき １１０ａ 信号線用埋め込み型銅めっき １１０ｂ グランド線埋め込み型銅めっき ２００ メモリモジュール ２１０ 配線基板 ２２０ 配線 Reference Signs List 1 semiconductor chip 2 gold bump 10 semiconductor device 20 wiring substrate 30 wiring pattern 40 polyimide (base film) 50 copper foil 55 adhesive 60 photoresist 65 plating resist 70 via hole 80 Pd catalyst 90 copper plating layer 100 resin 110 embedded copper plating 110a Embedded copper plating for signal line 110b Embedded copper plating for ground line 200 Memory module 210 Wiring board 220 Wiring
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/04 Ｈ０５Ｋ 3/40 Ｋ 25/18 Ｈ０１Ｌ 23/12 Ｌ Ｈ０５Ｋ 1/11 25/04 Ｚ 3/40 Ｆターム(参考） 5E317 AA24 BB01 BB11 CC25 CC33 CC53 CD15 CD18 CD25 GG05 5E346 AA05 AA15 AA22 AA29 AA32 AA43 AA51 BB01 BB02 BB04 BB06 BB15 BB16 CC10 CC32 CC54 CC55 DD02 DD12 DD32 EE01 EE06 EE13 FF07 FF14 GG15 GG17 GG18 GG22 GG23 GG28 HH04 HH11 5F044 KK02 KK08 KK10 KK18 LL04 QQ03 QQ04 QQ05 RR18 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 25/04 H05K 3/40 K 25/18 H01L 23/12 L H05K 1/11 25/04 Z 3 / 40 F-term (reference) 5E317 AA24 BB01 BB11 CC25 CC33 CC53 CD15 CD18 CD25 GG05 5E346 AA05 AA15 AA22 AA29 AA32 AA43 AA51 BB01 BB02 BB04 BB06 BB15 BB16 CC10 CC32 CC54 CC55 DD02 DD12 DD32 EE13 GG17 GG01 GG23 HH11 5F044 KK02 KK08 KK10 KK18 LL04 QQ03 QQ04 QQ05 RR18
Claims (11)
ーンが絶縁基材内外に配設され、前記絶縁基材内に形成
したビアホールを金属めっきで埋め込んだ埋め込み型金
属めっきでそれら複数層の配線パターン間を互いに接続
した、電子部品を搭載する多層配線基板であって、 前記埋め込み型金属めっきは、互いに接続する前記複数
の配線パターン間で接続支持され、前記ビアホール内の
絶縁基材とは接合（接着）されないことを特徴とする多
層配線基板。A plurality of wiring patterns formed of a conductive material are disposed inside and outside an insulating base material, and the plurality of wiring patterns are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. A multilayer wiring board on which electronic components are mounted, wherein the embedded metal plating is connected and supported between the plurality of wiring patterns connected to each other, and an insulating base material in the via hole. Is a multilayer wiring board that is not bonded (adhered).
て、 前記埋め込み型金属めっきの形状は、円柱、またはｎ
（ｎは３以上の整数）角柱であることを特徴とする多層
配線基板。2. The multilayer wiring board according to claim 1, wherein the buried metal plating has a shape of a column or n.
(N is an integer of 3 or more) A multilayer wiring board characterized by being a prism.
て、 前記埋め込み型金属めっきの形状は、外形表面積を大き
くする加工をした円柱、またはｎ（ｎは３以上の整数）
角柱であることを特徴とする多層配線基板。3. The multilayer wiring board according to claim 1, wherein the buried metal plating has a shape of a column processed to increase the outer surface area or n (n is an integer of 3 or more).
A multilayer wiring board characterized by being a prism.
て、 前記埋め込み型金属めっきは、信号線の配線パターンと
接続される信号線用埋め込み型金属めっきと、 グランド線の配線パターンと接続され、前記信号線用埋
め込み型金属めっきを取り囲むように形成されたグラン
ド線用埋め込み型金属めっきと、から構成されることを
特徴とする多層配線基板。4. The multilayer wiring board according to claim 1, wherein the embedded metal plating is connected to a signal line embedded metal plating connected to a signal line wiring pattern and a ground line wiring pattern. And a buried metal plating for a ground line formed so as to surround the buried metal plating for a signal line.
ーンが絶縁基材内外に配設され、前記絶縁基材内に形成
したビアホールを金属めっきで埋め込んだ埋め込み型金
属めっきでそれら複数層の配線パターン間を互いに接続
した多層配線基板に半導体チップを搭載して樹脂封止し
た半導体装置であって、 前記埋め込み型金属めっきは、互いに接続する前記複数
の配線パターン間で接続支持され、前記ビアホール内の
絶縁基材とは接合（接着）されないことを特徴とする半
導体装置。5. A plurality of wiring patterns formed of a conductive material are disposed inside and outside an insulating base material, and the plurality of wiring patterns are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. A semiconductor device mounted on a multi-layer wiring board in which the wiring patterns are connected to each other and sealed with a resin, wherein the embedded metal plating is connected and supported between the plurality of wiring patterns connected to each other; A semiconductor device which is not bonded (bonded) to an insulating base material in a via hole.
ーンが絶縁基材内外に配設され、前記絶縁基材内に形成
したビアホールを金属めっきで埋め込んだ埋め込み型金
属めっきでそれら複数層の配線パターン間を互いに接続
した多層配線基板と半導体チップとを接続して樹脂封止
した半導体装置と、前記半導体装置を搭載する配線基板
とを有する電子装置であって、 前記埋め込み型金属めっきは、互いに接続する前記複数
の配線パターン間で接続支持され、前記ビアホール内の
絶縁基材とは接合（接着）されないことを特徴とする電
子装置。6. A plurality of wiring patterns formed of a conductive material are provided inside and outside an insulating base material, and the plurality of layers are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. An electronic device comprising: a semiconductor device in which a multilayer wiring board and a semiconductor chip in which the wiring patterns are connected to each other are connected and a semiconductor chip is sealed with a resin; and a wiring board on which the semiconductor device is mounted, wherein the embedded metal plating is An electronic device, wherein the electronic device is connected and supported between the plurality of wiring patterns connected to each other, and is not joined (adhered) to an insulating base material in the via hole.
ーンが絶縁基材内外に配設され、前記絶縁基材内に形成
したビアホールを金属めっきで埋め込んだ埋め込み型金
属めっきでそれら複数層の配線パターン間を互いに接続
した多層配線基板に、電子部品を搭載した電子装置であ
って、 前記埋め込み型金属めっきは、互いに接続する前記複数
の配線パターン間で接続支持され、前記ビアホール内の
絶縁基材とは接合（接着）されないことを特徴とする電
子装置。7. A plurality of wiring patterns formed of a conductive material are provided inside and outside an insulating base material, and the plurality of layers are formed by burying metal plating in which via holes formed in the insulating base material are buried by metal plating. An electronic device in which an electronic component is mounted on a multilayer wiring board in which the wiring patterns are connected to each other, wherein the embedded metal plating is connected and supported between the plurality of wiring patterns connected to each other, and an insulation in the via hole is provided. An electronic device, which is not bonded (adhered) to a substrate.
ーンが絶縁基材内外に配設され、前記配線パターン上に
電子部品を搭載する多層配線基板の製造方法であって、 絶縁基材の片面に導電性材料箔を形成し、その導電性材
料箔上にめっきレジストを形成し、前記導電性材料箔の
形成面と反対面に接着剤層を形成したものを用意し、前
記めっきレジスト、導電性材料箔、前記絶縁基材、及び
接着剤にビアホール（貫通穴）の形成加工を行い、加工
された前記絶縁基材の接着剤層側に新たな導電性材料箔
を形成し、上下面の導電性材料箔を電極に、上下面の導
電性材料箔とが互いに接合するまで金属の電気めっきを
行ってビアホール内に埋め込み型金属めっきを形成し、
前記めっきレジストを剥離し、上下面の導電性材料箔に
対してホトレジストを形成し、エッチングを行って配線
パターンを形成し、２層の配線基板を形成し、その２層
の配線基板を複数個形成し、それら複数個の２層の配線
基板を互いに貼り合わせていくことによって複数層の配
線パターンを有する多層配線基板を製造することを特徴
とする多層配線基板の製造方法。8. A method for manufacturing a multilayer wiring board in which a plurality of wiring patterns formed of a conductive material are disposed inside and outside an insulating base material and electronic components are mounted on the wiring patterns. A conductive material foil is formed on one surface of the conductive material foil, a plating resist is formed on the conductive material foil, and an adhesive layer is formed on a surface opposite to the surface on which the conductive material foil is formed. Forming a via hole (through hole) in the conductive material foil, the insulating base material, and the adhesive; forming a new conductive material foil on the processed adhesive base material on the adhesive layer side; The conductive material foil on the lower surface is used as an electrode, and metal plating is performed until the conductive material foils on the upper and lower surfaces are joined to each other to form an embedded metal plating in the via hole.
The plating resist is peeled off, a photoresist is formed on the conductive material foil on the upper and lower surfaces, a wiring pattern is formed by etching, a two-layer wiring board is formed, and a plurality of the two-layer wiring boards are formed. Forming a multi-layered wiring board having a multi-layered wiring pattern by bonding the two-layered wiring boards to each other.
ーンが絶縁基材内外に配設され、前記配線パターン上に
電子部品を搭載する多層配線基板の製造方法であって、 絶縁基材の上下面に導電性材料箔を形成したものを用意
し、前記絶縁基材の上面の導電性材料箔及びビアホール
を形成するための穴を形成し、下面の導電性材料箔の裏
面に達する深さを有するビアホールを前記絶縁基材内に
形成し、前記下面の導電性材料箔を電極に、上下面の導
電性材料箔とが互いに接合するまで金属の電気めっきを
行ってビアホール内に埋め込み型金属めっきを形成し、
上下面の導電性材料箔に対してホトレジストを形成し、
エッチングを行って配線パターンを形成し、２層の配線
基板を形成し、その２層の配線基板を複数個形成し、そ
れら複数個の２層の配線基板を互いに貼り合わせていく
ことによって複数層の配線パターンを有する多層配線基
板を製造することを特徴とする多層配線基板の製造方
法。9. A method for manufacturing a multilayer wiring board in which a plurality of wiring patterns formed of a conductive material are provided inside and outside an insulating base material and electronic components are mounted on the wiring patterns. Prepare a conductive material foil formed on the upper and lower surfaces, form a conductive material foil on the upper surface of the insulating base and a hole for forming a via hole, and reach the lower surface of the conductive material foil on the lower surface. Forming a via hole having a thickness in the insulating base material, performing electroplating of a metal until the conductive material foil on the lower surface is used as an electrode, and the conductive material foil on the upper and lower surfaces are bonded to each other, and embedded in the via hole. Forming metal plating,
Form photoresist on conductive material foil on upper and lower surface,
A wiring pattern is formed by etching, a two-layer wiring board is formed, a plurality of the two-layer wiring boards are formed, and the plurality of the two-layer wiring boards are bonded to each other to form a plurality of layers. A method for manufacturing a multilayer wiring board, comprising manufacturing a multilayer wiring board having the above wiring pattern.
ターンが絶縁基材内外に配設された多層配線基板上に半
導体チップを搭載した半導体装置の製造方法であって、 絶縁基材の片面に導電性材料箔を形成し、その導電性材
料箔上にめっきレジストを形成し、前記導電性材料箔の
形成面と反対面に接着剤層を形成したものを用意し、前
記めっきレジスト、導電性材料箔、前記絶縁基材、及び
接着剤にビアホール（貫通穴）の形成加工を行い、加工
された前記絶縁基材の接着剤層側に新たな導電性材料箔
を形成し、上下面の導電性材料箔を電極に、上下面の導
電性材料箔とが互いに接合するまで金属の電気めっきを
行ってビアホール内に埋め込み型金属めっきを形成し、
前記めっきレジストを剥離し、上下面の導電性材料箔に
対してホトレジストを形成し、エッチングを行って配線
パターンを形成し、２層の配線基板を形成し、その２層
の配線基板を複数個形成し、それら複数個の２層の配線
基板を互いに貼り合わせていくことによって複数層の配
線パターンを有する多層配線基板を形成し、前記多層配
線基板の表層の配線パターン上に半導体チップを接続
し、前記多層配線基板の一部及び前記半導体チップとの
接続部分を樹脂封止して半導体装置を製造することを特
徴とする半導体装置の製造方法。10. A method for manufacturing a semiconductor device in which a semiconductor chip is mounted on a multilayer wiring board having a plurality of wiring patterns formed of a conductive material disposed inside and outside an insulating base material. Forming a conductive material foil on one side, forming a plating resist on the conductive material foil, preparing an adhesive layer on the surface opposite to the surface on which the conductive material foil is formed, preparing the plating resist, A via hole (through hole) is formed in the conductive material foil, the insulating base material, and the adhesive, and a new conductive material foil is formed on the processed adhesive base material on the adhesive layer side. With the conductive material foil of the electrode as an electrode, perform metal electroplating until the conductive material foils on the upper and lower surfaces are bonded to each other to form an embedded metal plating in the via hole,
The plating resist is peeled off, a photoresist is formed on the conductive material foil on the upper and lower surfaces, a wiring pattern is formed by etching, a two-layer wiring board is formed, and a plurality of the two-layer wiring boards are formed. Forming a multi-layered wiring board having a multi-layered wiring pattern by laminating the plurality of two-layered wiring boards to each other, and connecting a semiconductor chip onto the surface wiring pattern of the multi-layered wiring board. And manufacturing a semiconductor device by sealing a portion of the multilayer wiring board and a portion connected to the semiconductor chip with a resin.
ターンが絶縁基材内外に配設された多層配線基板上に半
導体チップを搭載した半導体装置の製造方法であって、 絶縁基材の上下面に導電性材料箔を形成したものを用意
し、前記絶縁基材の上面の導電性材料箔及びビアホール
を形成するための穴を形成し、下面の導電性材料箔の裏
面に達する深さを有するビアホールを前記絶縁基材内に
形成し、前記下面の導電性材料箔を電極に、上下面の導
電性材料箔とが互いに接合するまで金属の電気めっきを
行ってビアホール内に埋め込み型金属めっきを形成し、
上下面の導電性材料箔に対してホトレジストを形成し、
エッチングを行って配線パターンを形成し、２層の配線
基板を形成し、その２層の配線基板を複数個形成し、そ
れら複数個の２層の配線基板を互いに貼り合わせていく
ことによって複数層の配線パターンを有する多層配線基
板を形成し、前記多層配線基板の表層の配線パターン上
に半導体チップを接続し、前記多層配線基板の一部及び
前記半導体チップとの接続部分を樹脂封止して半導体装
置を製造することを特徴とする半導体装置の製造方法。11. A method of manufacturing a semiconductor device in which a semiconductor chip is mounted on a multilayer wiring board having a plurality of wiring patterns formed of a conductive material disposed inside and outside an insulating base material. Prepare a conductive material foil formed on the upper and lower surfaces, form a hole for forming a conductive material foil and via holes on the upper surface of the insulating base material, the depth reaching the back surface of the conductive material foil on the lower surface Forming a via hole in the insulating base having the conductive material foil on the lower surface as an electrode, performing electroplating of the metal until the conductive material foils on the upper and lower surfaces are bonded to each other, and embedding the metal in the via hole. Forming plating,
Form photoresist on conductive material foil on upper and lower surface,
A wiring pattern is formed by etching, a two-layer wiring board is formed, a plurality of the two-layer wiring boards are formed, and the plurality of the two-layer wiring boards are bonded to each other to form a plurality of layers. Forming a multilayer wiring board having a wiring pattern, connecting a semiconductor chip on the surface wiring pattern of the multilayer wiring board, and sealing a portion of the multilayer wiring board and a connection portion with the semiconductor chip by resin sealing A method for manufacturing a semiconductor device, comprising manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000152701A JP2001332860A (en) | 2000-05-18 | 2000-05-18 | Multi-layered wiring board, semiconductor device, electronic device, and their manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000152701A JP2001332860A (en) | 2000-05-18 | 2000-05-18 | Multi-layered wiring board, semiconductor device, electronic device, and their manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001332860A true JP2001332860A (en) | 2001-11-30 |
Family
ID=18658089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000152701A Withdrawn JP2001332860A (en) | 2000-05-18 | 2000-05-18 | Multi-layered wiring board, semiconductor device, electronic device, and their manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001332860A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008177554A (en) * | 2006-12-21 | 2008-07-31 | Ngk Spark Plug Co Ltd | Multilayer wiring board, and power supply structure to be embedded in multilayer wiring board |
| JP2013131777A (en) * | 2009-04-02 | 2013-07-04 | Murata Mfg Co Ltd | Circuit board |
| CN103906371A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| CN103906372A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| US11876012B2 (en) | 2017-08-31 | 2024-01-16 | Haesung Ds Co., Ltd. | Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same |
-
2000
- 2000-05-18 JP JP2000152701A patent/JP2001332860A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008177554A (en) * | 2006-12-21 | 2008-07-31 | Ngk Spark Plug Co Ltd | Multilayer wiring board, and power supply structure to be embedded in multilayer wiring board |
| JP2013131777A (en) * | 2009-04-02 | 2013-07-04 | Murata Mfg Co Ltd | Circuit board |
| CN103906371A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| CN103906372A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| US11876012B2 (en) | 2017-08-31 | 2024-01-16 | Haesung Ds Co., Ltd. | Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same |
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