JP2001267708A - Printed wiring board and its manufacturing method - Google Patents
Printed wiring board and its manufacturing methodInfo
- Publication number
- JP2001267708A JP2001267708A JP2000074787A JP2000074787A JP2001267708A JP 2001267708 A JP2001267708 A JP 2001267708A JP 2000074787 A JP2000074787 A JP 2000074787A JP 2000074787 A JP2000074787 A JP 2000074787A JP 2001267708 A JP2001267708 A JP 2001267708A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- wiring board
- printed wiring
- layer
- electrode pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はプリント配線板とそ
の製造方法に関し、特に半導体装置のチップサイズパッ
ケージ（以下、ＣＳＰ：Chip Size Packageという）の
実装に適した電極パッド構造を有するプリント配線板と
その製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a method of manufacturing the same, and more particularly to a printed wiring board having an electrode pad structure suitable for mounting a chip size package (CSP) of a semiconductor device. The present invention relates to the manufacturing method.
【０００２】[0002]
【従来の技術】電子機器の小型・軽量・薄型化や高速・
高機能化の進展に伴い、表面実装技術の高度化が要求さ
れている。2. Description of the Related Art Smaller, lighter and thinner electronic devices and high speed
With the advancement of functions, sophistication of surface mounting technology is required.
【０００３】半導体パッケージの主流はＱＦＰ(Quad Fl
at Package)に代表されるリード付きの周辺実装タイプ
からＢＧＡ（Ball Grid Array）等の面実装タイプに移
行しつつあり、最近では携帯情報端末機器を中心にＢＧ
Ａよりさらに狭ピッチであるＣＳＰの実用化が急速に進
みつつある。The mainstream of semiconductor packages is QFP (Quad Fl
At Package) is moving from a peripheral mounting type with leads to a surface mounting type such as a BGA (Ball Grid Array).
Practical application of CSPs having a narrower pitch than A is progressing rapidly.
【０００４】ＢＧＡ型パケージのプリント配線板への実
装構造の例が特開平８―３４０１６４号公報等に開示さ
れている。この技術のように、ＢＧＡ型パッケージはは
んだボールにより、プリント配線板にリジットに接合す
る構造となっている。そのためにこれら部品を実装した
プリント配線板を温度サイクル試験等の信頼性試験を行
うと、部品とプリント配線板との材料特性の違いから、
接合したはんだボールに応力がかかる。ＱＦＰなどのリ
ード付き部品であれば、この応力はリード部にかかるこ
とになり、リードが曲がることにより応力が緩和され、
接続信頼性上特に問題になることはない。ＣＳＰやＢＧ
Ａの場合は、はんだボールに直接応力がかかることにな
るが、この応力を緩和する部分がないために部品の種類
によってはプリント配線板とのはんだ接続部にクラック
が入り接続信頼性が低下する。特に、ＣＳＰははんだボ
ールのピッチが狭く、接合面積も小さいため、接続信頼
性が問題となりやすい。今後さらに、多ピン化に伴い、
より狭ピッチ化してくると、接続信頼性問題はより深刻
となる。An example of a mounting structure of a BGA type package on a printed wiring board is disclosed in Japanese Patent Application Laid-Open No. 8-340164. As in this technique, the BGA type package has a structure in which it is rigidly joined to a printed wiring board by solder balls. Therefore, when a reliability test such as a temperature cycle test is performed on a printed wiring board on which these components are mounted, the difference in material properties between the components and the printed wiring board indicates that
Stress is applied to the joined solder balls. In the case of a leaded component such as QFP, this stress is applied to the lead portion, and the stress is relaxed by bending the lead,
There is no particular problem in connection reliability. CSP and BG
In the case of A, stress is directly applied to the solder ball. However, since there is no portion to relieve this stress, cracks occur in the solder connection portion with the printed wiring board depending on the type of component, and the connection reliability decreases. . In particular, since the CSP has a narrow pitch of solder balls and a small bonding area, connection reliability tends to be a problem. In the future, as the number of pins increases,
As the pitch becomes narrower, the connection reliability problem becomes more serious.
【０００５】従来、ＣＳＰを用いる場合は、プリント配
線板の電極パッドの径及びソルダーレジスト構造を最適
化することにより信頼性を向上させていたが、それでも
不十分な場合は、さらに、部品実装後、アンダーフィル
を部品とプリント配線板の間に充填し、硬化させること
により接合強度の補強を行っている。また、半導体パッ
ケージ側でも構造的な工夫をこらし、四隅に補強パッド
を設けたり、パッケージ内部で応力緩和手段を設ける技
術が提案されている。Conventionally, when the CSP is used, the reliability has been improved by optimizing the diameter of the electrode pad of the printed wiring board and the solder resist structure. In addition, the underfill is filled between the component and the printed wiring board and hardened to reinforce the bonding strength. In addition, a technique has been proposed in which a structural device is also devised on the semiconductor package side, and reinforcing pads are provided at four corners, or stress relaxation means is provided inside the package.
【０００６】[0006]
【発明が解決しようとする課題】しかし、前者のアンダ
ーフィルを用いる従来方法では、部品実装工程におい
て、新たに工程が追加されるなどによる工程数の増加や
これに伴うコストの増加などの問題が発生している。However, in the former method using the underfill, there are problems such as an increase in the number of steps due to a new step in the component mounting step and an increase in cost associated therewith. It has occurred.
【０００７】後者の半導体パッケージ側での改良におい
ては、パッケージの構造が複雑になり、パッケージのコ
スト上昇の問題となっている。[0007] In the latter improvement on the semiconductor package side, the structure of the package becomes complicated, which causes a problem of an increase in package cost.
【０００８】本発明の目的は、以上の問題点を解決した
電極パッド構造を有するプリント配線板とその製造方法
を提供するものである。An object of the present invention is to provide a printed wiring board having an electrode pad structure which solves the above problems, and a method of manufacturing the same.
【０００９】[0009]
【課題を解決するための手段】本発明のプリント配線板
の第１の構成は、絶縁基板上に半導体装置をはんだで面
実装するための電極パッドを有するプリント配線板にお
いて、前記電極パッドが前記絶縁基板上に形成された平
面形状の第１導電層と該第１導電層上に突起状に形成さ
れた第２導電層から構成されることを特徴とする。According to a first aspect of the present invention, there is provided a printed wiring board having an electrode pad for surface mounting a semiconductor device on an insulating substrate by soldering. It is characterized by comprising a first conductive layer having a planar shape formed on an insulating substrate and a second conductive layer formed in a protruding shape on the first conductive layer.
【００１０】前記突起状の第２導電層がめっき層または
導電性樹脂層から構成され前記めっき層としては銅めっ
き層から構成され、また、前記導電性樹脂層としては、
銅または銀を含む熱硬化性樹脂から構成することができ
る。The projecting second conductive layer is formed of a plating layer or a conductive resin layer, the plating layer is formed of a copper plating layer, and the conductive resin layer is formed of a copper plating layer.
It can be composed of a thermosetting resin containing copper or silver.
【００１１】上記の本発明のプリント配線板の構成にお
いて、前記第２導電層の表面をニッケル薄膜またはニッ
ケルと金の２層薄膜で被覆することにより、はんだ付け
における電極パッドのはんだ喰われを低減できる効果が
ある。In the structure of the printed wiring board of the present invention described above, the surface of the second conductive layer is coated with a nickel thin film or a two-layer thin film of nickel and gold, thereby reducing the solder erosion of the electrode pads during soldering. There is an effect that can be done.
【００１２】本発明のプリント配線板の製造方法の第１
の構成は、絶縁基板上に第１導電層を形成する工程と、
前記第１導電層全面にめっきレジストを被覆した後、前
記絶縁基板の電極パッド形成位置の前記めっきレジスト
の所定の箇所に前記第１導電層表面に達し、前記電極パ
ッドよりも小さな断面積の開口を形成する工程と、前記
開口に第２導電層をめっきにより堆積した後、前記めっ
きレジストを剥離する工程と、フォトリソグラフィ技術
により少なくとも前記第２導電層が前記第１導電層上に
残るように、前記第１導電層をパターニングし、前記第
２導電層を上層に前記第１導電層を下層とする電極パッ
ドを形成する工程とを含むことを特徴とする。A first method of manufacturing a printed wiring board according to the present invention.
Forming a first conductive layer on an insulating substrate;
After covering the entire surface of the first conductive layer with a plating resist, the opening reaches the surface of the first conductive layer at a predetermined position of the plating resist at a position where the electrode pad is formed on the insulating substrate, and has an opening having a smaller cross-sectional area than the electrode pad. Forming a second conductive layer in the opening by plating, and then removing the plating resist, so that at least the second conductive layer remains on the first conductive layer by a photolithography technique. Patterning the first conductive layer to form an electrode pad having the second conductive layer as an upper layer and the first conductive layer as a lower layer.
【００１３】また、本発明のプリント配線板の製造方法
の第２の構成は、絶縁基板上に第１導電層を形成する工
程と、前記第１導電層をフォトリソグラフィ技術により
パターニングし、所定のパッドと配線パターンを形成す
る工程と、前記パッド上に導電性樹脂インクからなる第
２導電層を突起状に印刷形成した後、前記導電性樹脂を
熱硬化し、前記パッドと該パッド上に突起状に形成され
た第２導電層から構成された電極パッドを形成する工程
とを含むことを特徴とする。In a second aspect of the method for manufacturing a printed wiring board according to the present invention, a step of forming a first conductive layer on an insulating substrate and a step of patterning the first conductive layer by a photolithography technique, A step of forming a pad and a wiring pattern, and after forming a second conductive layer made of a conductive resin ink on the pad by printing in a projection shape, the conductive resin is thermally cured to form the pad and the projection on the pad. Forming an electrode pad composed of a second conductive layer formed in a shape.
【００１４】本発明では、上記の構成のように半導体装
置をはんだボールで面実装するためのプリント配線板の
電極パッドを第１導電層とその上に突起状に形成した第
２導電層で構成することにより、電極パッドのはんだ接
合面積が増加し、ＣＳＰ等の微細ピッチ端子を有する半
導体装置とプリント配線板との接続信頼性が向上する。According to the present invention, as described above, an electrode pad of a printed wiring board for surface mounting a semiconductor device with solder balls is constituted by a first conductive layer and a second conductive layer formed thereon in a projecting shape. By doing so, the solder bonding area of the electrode pad increases, and the connection reliability between the semiconductor device having fine pitch terminals such as CSP and the printed wiring board improves.
【００１５】[0015]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
【００１６】図１は本発明の実施の形態のプリント配線
板を説明するための基板要部の断面図である。図１のよ
うに本実施の形態のプリント配線板は絶縁基板１の表面
に形成された第１導電層２とその上に形成された該第１
導電層の表面領域内に形成された突起状の第２導電層４
ら構成されたＣＳＰ接続用の電極パッド５を有してい
る。電極パッド５間にはソルダーレジスト７が形成され
ており、電極パッド５間のはんだ付け時のブリッジを防
止する。FIG. 1 is a sectional view of a main part of a substrate for explaining a printed wiring board according to an embodiment of the present invention. As shown in FIG. 1, the printed wiring board of the present embodiment has a first conductive layer 2 formed on the surface of an insulating substrate 1 and the first conductive layer 2 formed thereon.
Protruding second conductive layer 4 formed in the surface region of the conductive layer
CSP connection electrode pad 5 composed of A solder resist 7 is formed between the electrode pads 5 to prevent a bridge between the electrode pads 5 at the time of soldering.
【００１７】第２導電層４の突起形状は、角柱状または
円柱状であり、直角柱や直角円柱でも角錐台や円錐台で
もよい。The projection of the second conductive layer 4 is in the shape of a prism or a cylinder, and may be a right prism, a right cylinder, a truncated pyramid or a truncated cone.
【００１８】第１導電層２は銅箔またはそれを銅めっき
で厚付けしたものであり、第２導電層４の材質は銅めっ
き層または銅または銀を含む導電性樹脂層から構成され
ている。なお、導電性樹脂の樹脂としては熱硬化性エポ
キシ樹脂が使用される。第２導電層４の表面ははんだボ
ールが溶融した際のはんだで喰われを低減するために、
ニッケル薄膜またはニッケルおよび金の２層薄膜を電気
めっきまたは無電解めっきで被覆することもできる。な
お、第１導電層２の平面形状は、自由に設計され、例え
ば、矩形、多角形あるいは円形等の形状が使用される。The first conductive layer 2 is a copper foil or a copper foil which is thickened by copper plating. The material of the second conductive layer 4 is a copper plating layer or a conductive resin layer containing copper or silver. . Note that a thermosetting epoxy resin is used as the conductive resin. The surface of the second conductive layer 4 reduces the erosion of the solder when the solder ball is melted.
A nickel thin film or a two-layer thin film of nickel and gold can be coated by electroplating or electroless plating. Note that the planar shape of the first conductive layer 2 is freely designed, and for example, a rectangular, polygonal, or circular shape is used.
【００１９】次に上記の本実施の形態のプリント配線板
の第１の製造方法について図面を参照して説明する。本
製造方法では、図１の電極パッドの突起形状の第２導電
層を銅めっきで形成する。図２および図３は本発明のプ
リント配線板の第１の製造方法の工程順を説明するため
の基板要部の断面図である。なお、図３は図２（ｄ）の
工程に続く工程を説明する基板要部の断面図である。Next, a first method of manufacturing the printed wiring board according to the present embodiment will be described with reference to the drawings. In this manufacturing method, the protruding second conductive layer of the electrode pad of FIG. 1 is formed by copper plating. FIGS. 2 and 3 are cross-sectional views of a main part of a substrate for explaining a process sequence of a first method for manufacturing a printed wiring board according to the present invention. FIG. 3 is a cross-sectional view of a main part of the substrate for explaining a step that follows the step of FIG.
【００２０】まず、図２（ａ）のように、絶縁基板１の
表面に厚さ１８μｍの銅箔２ａを貼った銅張り積層板１
００を用意する。銅張り積層板は内層基板の表面に絶縁
樹脂を介して銅箔を積層した基板を使用してもよい。First, as shown in FIG. 2A, a copper-clad laminate 1 having a copper foil 2a having a thickness of 18 μm adhered to the surface of an insulating substrate 1
Prepare 00. As the copper-clad laminate, a substrate in which a copper foil is laminated on the surface of an inner substrate via an insulating resin may be used.
【００２１】次に、図２（ｂ）のように、銅張り積層板
１００に貫通孔８を孔明けした後、図２（ｃ）のよう
に、銅張り積層基板の貫通孔８を含む全面に厚さ約２０
μｍの第１の銅めっき層２ｂを形成する。符号２は銅箔
２ａおよび第１の銅めっき層２ｂから構成された第１導
電層を示す。第１の銅めっき層２ｂは電気銅めっき法ま
たは無電解銅めっき法で形成できる。Next, as shown in FIG. 2B, a through hole 8 is formed in the copper-clad laminate 100, and then, as shown in FIG. 2C, the entire surface including the through-hole 8 of the copper-clad laminate. About 20
A first copper plating layer 2b of μm is formed. Reference numeral 2 denotes a first conductive layer composed of a copper foil 2a and a first copper plating layer 2b. The first copper plating layer 2b can be formed by an electrolytic copper plating method or an electroless copper plating method.
【００２２】次に、図２（ｄ）のように、第１の銅めっ
き層２ｂ上の突起形状パターン形成する箇所に２５０〜
３００μｍ径の開口１０を有する厚さ約２０μｍのめっ
きレジスト９をパターニングした後、開口部１０に厚さ
１０〜２０μｍの第２の銅めっき層からなる第２導電層
４を形成する。その後、めっきレジスト９を剥離する
（図３（ａ））。Next, as shown in FIG. 2D, 250-250 parts are formed on the first copper plating layer 2b where the projection pattern is to be formed.
After patterning a plating resist 9 having a thickness of about 20 μm and having an opening 10 having a diameter of 300 μm, a second conductive layer 4 made of a second copper plating layer having a thickness of 10 to 20 μm is formed in the opening 10. Thereafter, the plating resist 9 is peeled off (FIG. 3A).
【００２３】次に、図３（ｂ）のように、基板の貫通孔
８表面、第２導電層４の表面を含む電極パッド形成表面
および配線パターン形成表面にエッチングレジスト１１
をパターニングする。Next, as shown in FIG. 3B, an etching resist 11 is formed on the surface of the through hole 8 of the substrate, the surface of the electrode pad including the surface of the second conductive layer 4 and the surface of the wiring pattern.
Is patterned.
【００２４】次いで、図３（ｃ）のように、エッチング
してスルーホール３、電極パッド５および配線パターン
６を形成した後、エッチングレジスト１１を剥離する。
なお、０．８ｍｍピッチＣＳＰ実装用の場合、電極パッ
ド５の径は、３５０〜４００μｍに形成される。Next, as shown in FIG. 3C, after the etching to form the through holes 3, the electrode pads 5 and the wiring patterns 6, the etching resist 11 is removed.
In addition, in the case of 0.8 mm pitch CSP mounting, the diameter of the electrode pad 5 is formed to be 350 to 400 μm.
【００２５】次いで、電極パッド５間および配線パター
ン６間等にソルダーレジスト形成して本発明のプリント
配線板２００が完成する。Next, a solder resist is formed between the electrode pads 5 and between the wiring patterns 6 to complete the printed wiring board 200 of the present invention.
【００２６】次に上記の本実施の形態のプリント配線板
の第２の製造方法について図面を参照して説明する。本
製造方法では、図１の電極パッドの突起形状の第２導電
層を導電性樹脂層で形成する。Next, a second method for manufacturing a printed wiring board according to the present embodiment will be described with reference to the drawings. In the present manufacturing method, the second conductive layer having the protrusion shape of the electrode pad in FIG. 1 is formed of a conductive resin layer.
【００２７】図４は本発明のプリント配線板の第２の製
造方法の工程順を説明するための基板要部の断面図であ
る。FIG. 4 is a cross-sectional view of a main part of a substrate for explaining a process sequence of a second method for manufacturing a printed wiring board according to the present invention.
【００２８】まず、図４（ａ）のように、絶縁基板１の
表面に厚さ１８μｍの銅箔２ａを貼った銅張り積層板１
００を用意する。銅張り積層板は内層基板の表面に絶縁
樹脂を介して銅箔を積層した基板を使用してもよい。First, as shown in FIG. 4A, a copper-clad laminate 1 having a copper foil 2a having a thickness of 18 μm adhered to the surface of an insulating substrate 1
Prepare 00. As the copper-clad laminate, a substrate in which a copper foil is laminated on the surface of an inner substrate via an insulating resin may be used.
【００２９】次に、図４（ｂ）のように、銅張り積層板
１００に貫通孔８を孔明けした後、銅張り積層基板の貫
通孔８を含む全面に厚さ約２０μｍの第１の銅めっき層
２ｂを形成する。その後、基板のスルーホール形成表
面、電極パッド形成表面および配線パターン形成表面に
エッチングレジスト１１を形成する（図４（ｃ））。Next, as shown in FIG. 4B, after a through hole 8 is formed in the copper-clad laminate 100, a first layer of about 20 μm in thickness is formed on the entire surface including the through-hole 8 of the copper-clad laminate. The copper plating layer 2b is formed. Thereafter, an etching resist 11 is formed on the through-hole forming surface, the electrode pad forming surface, and the wiring pattern forming surface of the substrate (FIG. 4C).
【００３０】次に、エッチングしてスルーホール３、配
線パターン６および電極パッドの第１導電層２をパター
ニングしてエッチングレジスト１１を剥離した後、配線
パターン間、電極パッドの第１導電層２間等にソルダー
レジスト７を形成する。Next, after etching to pattern the through-hole 3, the wiring pattern 6 and the first conductive layer 2 of the electrode pad and to peel off the etching resist 11, between the wiring pattern and the first conductive layer 2 of the electrode pad. Then, a solder resist 7 is formed.
【００３１】次いで、電極パッドの第１導電層２上にス
クリーン印刷で銅または銀を含む導電性樹脂インクを印
刷した後、熱硬化して第２導電層４を形成して電極パッ
ド５を有するプリント配線板２００が完成する（図４
（ｄ））。Next, a conductive resin ink containing copper or silver is printed on the first conductive layer 2 of the electrode pad by screen printing, and then thermally cured to form the second conductive layer 4 to have the electrode pad 5. The printed wiring board 200 is completed (FIG. 4)
(D)).
【００３２】次に、本発明の実施の形態のプリント配線
板の動作について図面を参照して説明する。図５は本発
明のプリント配線板にＣＳＰを実装した場合の要部の断
面図である。Next, the operation of the printed wiring board according to the embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a sectional view of a main part when a CSP is mounted on the printed wiring board of the present invention.
【００３３】ＣＳＰ３００はプリント配線板２００への
実装面に端子１２を有し、この端子が本発明のプリント
配線板２００の電極パッド５とはんだボールが溶融して
形成されたはんだ２０を介して電気的に接続されてい
る。The CSP 300 has terminals 12 on the surface to be mounted on the printed wiring board 200, and these terminals are electrically connected to the electrode pads 5 of the printed wiring board 200 of the present invention and the solder 20 formed by melting solder balls. Connected.
【００３４】このＣＳＰ３００を実装したプリント配線
板２００を高温雰囲気に暴露すると、ＣＳＰ３００とプ
リント配線板２００の構成する材料特性の違いから応力
がはんだ２０の接合部にかかる。ＣＳＰ３００内部のシ
リコンチップは熱膨張係数が３〜５ｐｐｍと小さく、熱
により延びにくい。ところが、プリント配線板２００の
熱膨張係数は１５ｐｐｍと、シリコンチップと比較して
大きく、熱により延やすい。この熱膨張係数の違いによ
り、ＣＳＰ３００を実装したプリント配線板２００に熱
が加わると、プリント配線板２００の延びが拘束されて
プリント配線板２００が反る。この反りはＣＳＰ３００
とプリント基板２００を接合しているはんだ接続部の熱
疲労寿命に大きく影響する。When the printed wiring board 200 on which the CSP 300 is mounted is exposed to a high-temperature atmosphere, stress is applied to the joint of the solder 20 due to the difference in the material characteristics of the CSP 300 and the printed wiring board 200. The silicon chip inside the CSP 300 has a small coefficient of thermal expansion of 3 to 5 ppm, and is not easily expanded by heat. However, the thermal expansion coefficient of the printed wiring board 200 is 15 ppm, which is larger than that of a silicon chip, and is easily spread by heat. Due to this difference in the coefficient of thermal expansion, when heat is applied to the printed wiring board 200 on which the CSP 300 is mounted, the extension of the printed wiring board 200 is restricted, and the printed wiring board 200 warps. This warp is CSP300
Greatly affects the thermal fatigue life of the solder connection part joining the printed circuit board 200 and the printed circuit board 200.
【００３５】ＣＳＰ３００のピッチが狭くなり、ピン数
が多くなるとプリント配線板２００の配線引き回しの難
易度があがり、配線本数を増やすためにプリント配線板
２００のパッド径を小さくする必要が出てくる。この場
合、プリント配線板２００側での破断が発生しやすくな
り、寿命が短くなる。When the pitch of the CSP 300 is reduced and the number of pins is increased, it becomes difficult to route the wiring of the printed wiring board 200, and it is necessary to reduce the pad diameter of the printed wiring board 200 in order to increase the number of wirings. In this case, breakage easily occurs on the printed wiring board 200 side, and the life is shortened.
【００３６】本発明のプリント配線板２００では電極パ
ッド５に突起状の第２導電層４を有しているために、は
んだ２０との接続面積が増えるために、はんだ２０中に
クラックが発生した場合でもこの突起状の第２導電層４
によりその進行を防止することが出来る。Since the printed wiring board 200 of the present invention has the protruding second conductive layer 4 on the electrode pad 5, a crack is generated in the solder 20 because the connection area with the solder 20 increases. Even in this case, the projecting second conductive layer 4
This can prevent the progress.
【００３７】[0037]
【発明の効果】以上説明したように、本発明では、プリ
ント配線板のＣＳＰを実装する電極パッドを突起状の構
造とすることで、アンダーフィルなどの補強を行うこと
なく、ＣＳＰとプリント配線板の電極パッドのはんだ接
続部との接合強度をあげることができ、ＣＳＰ接続信頼
性を向上できる効果がある。As described above, according to the present invention, the CSP and the printed wiring board can be formed without reinforcing the underfill or the like by forming the electrode pads for mounting the CSP of the printed wiring board in a projecting structure. This has the effect of increasing the bonding strength between the electrode pad and the solder connection part and improving the CSP connection reliability.
【図１】本発明の実施の形態のプリント配線板を説明す
るための基板要部の断面図である。FIG. 1 is a cross-sectional view of a main part of a substrate for describing a printed wiring board according to an embodiment of the present invention.
【図２】本発明のプリント配線板の第１の製造方法の工
程順を説明するための基板要部の断面図である。FIG. 2 is a cross-sectional view of a main part of a substrate for describing a process order of a first method for manufacturing a printed wiring board according to the present invention.
【図３】図２（ｄ）の工程に続く工程を説明する基板要
部の断面図である。FIG. 3 is a cross-sectional view of a relevant part of the substrate, illustrating a step that follows the step of FIG. 2D.
【図４】本発明のプリント配線板の第２の製造方法の工
程順を説明するための基板要部の断面図である。FIG. 4 is a cross-sectional view of a main part of a substrate for describing a process order of a second method for manufacturing a printed wiring board according to the present invention.
【図５】本発明のプリント配線板にＣＳＰを実装した場
合の要部の断面図である。FIG. 5 is a sectional view of a main part when a CSP is mounted on the printed wiring board of the present invention.
１ 絶縁基板 ２ 第１導電層 ２ａ 銅箔 ２ｂ 第１の銅めっき層 ３ スルーホール ４ 第２導電層 ５ 電極パッド ６ 配線パターン ７ ソルダーレジスト ８ 貫通孔 ９ めっきレジスト １０ 開口 １１ エッチングレジスト １２ 端子 ２０ はんだ １００ 銅張り積層板 ２００ プリント配線板 ３００ ＣＳＰ REFERENCE SIGNS LIST 1 Insulating substrate 2 First conductive layer 2a Copper foil 2b First copper plating layer 3 Through hole 4 Second conductive layer 5 Electrode pad 6 Wiring pattern 7 Solder resist 8 Through hole 9 Plating resist 10 Opening 11 Etching resist 12 Terminal 20 Solder 100 Copper-clad laminate 200 Printed wiring board 300 CSP
Claims (9)
装するための電極パッドを有するプリント配線板におい
て、前記電極パッドが前記絶縁基板上に形成された平面
形状の第１導電層と該第１導電層上に突起状に形成され
た第２導電層から構成されることを特徴とするプリント
配線板。1. A printed wiring board having an electrode pad for surface mounting a semiconductor device on an insulating substrate by soldering, wherein the electrode pad is formed on the insulating substrate and has a planar first conductive layer; A printed wiring board comprising a second conductive layer formed in a protruding shape on one conductive layer.
は導電性樹脂層から構成されることを特徴とする請求項
１記載のプリント配線板。2. The printed wiring board according to claim 1, wherein the protruding second conductive layer is formed of a plating layer or a conductive resin layer.
２記載のプリント配線板。3. The printed wiring board according to claim 2, wherein said plating layer is a copper plating layer.
硬化性樹脂から構成されることを特徴とする請求項２記
載のプリント配線板。4. The printed wiring board according to claim 2, wherein the conductive resin layer is made of a thermosetting resin containing copper or silver.
たはニッケルと金の２層薄膜で被覆されていることを特
徴とする請求項１記載のプリント配線板。5. The printed wiring board according to claim 1, wherein the surface of the second conductive layer is coated with a nickel thin film or a two-layer thin film of nickel and gold.
柱状である請求項１記載のプリント配線板。6. The printed wiring board according to claim 1, wherein the shape of the second conductive layer is a prism or a column.
と、前記第１導電層全面にめっきレジストを被覆した
後、前記絶縁基板の電極パッド形成位置の前記めっきレ
ジストの所定の箇所に前記第１導電層表面に達し、前記
電極パッドよりも小さな断面積の開口を形成する工程
と、前記開口に第２導電層をめっきにより堆積した後、
前記めっきレジストを剥離する工程と、フォトリソグラ
フィ技術により少なくとも前記第２導電層が前記第１導
電層上に残るように、前記第１導電層をパターニング
し、前記第２導電層を上層に前記第１導電層を下層とす
る電極パッドを形成する工程とを含むことを特徴とする
プリント配線板の製造方法。7. A step of forming a first conductive layer on an insulating substrate, and after coating a plating resist on the entire surface of the first conductive layer, forming a plating resist on a predetermined portion of the plating resist at a position where an electrode pad is formed on the insulating substrate. Forming an opening reaching the first conductive layer surface and having a smaller cross-sectional area than the electrode pad; and depositing a second conductive layer in the opening by plating.
Removing the plating resist, and patterning the first conductive layer so that at least the second conductive layer remains on the first conductive layer by a photolithography technique; Forming an electrode pad having one conductive layer as a lower layer.
と、前記第１導電層をフォトリソグラフィ技術によりパ
ターニングし、所定のパッドと配線パターンを形成する
工程と、前記パッド上に導電性樹脂インクからなる第２
導電層を突起状に印刷形成した後、前記導電性樹脂を熱
硬化し、前記パッドと該パッド上に突起状に形成された
第２導電層から構成された電極パッドを形成する工程と
を含むことを特徴とするプリント配線板の製造方法。8. A step of forming a first conductive layer on an insulating substrate, a step of patterning the first conductive layer by photolithography to form a predetermined pad and a wiring pattern, and a step of forming a conductive layer on the pad. Second made of resin ink
Forming a conductive layer by printing in a projecting manner, and then thermally curing the conductive resin to form an electrode pad composed of the pad and a second conductive layer formed in a projecting manner on the pad. A method for manufacturing a printed wiring board, comprising:
の製造方法において、前記電極パッドを形成した後、さ
らに電極パッド表面にニッケル薄膜またはニッケルと金
の２層薄膜が被覆される工程を有するプリント配線板の
製造方法。9. The method for manufacturing a printed wiring board according to claim 7, further comprising, after forming the electrode pad, a step of coating the surface of the electrode pad with a nickel thin film or a two-layer thin film of nickel and gold. Manufacturing method of printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000074787A JP2001267708A (en) | 2000-03-16 | 2000-03-16 | Printed wiring board and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000074787A JP2001267708A (en) | 2000-03-16 | 2000-03-16 | Printed wiring board and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001267708A true JP2001267708A (en) | 2001-09-28 |
Family
ID=18592775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000074787A Withdrawn JP2001267708A (en) | 2000-03-16 | 2000-03-16 | Printed wiring board and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001267708A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100632545B1 (en) | 2004-12-20 | 2006-10-09 | 삼성전기주식회사 | Method of manufacturing a ball grid array substrate having a ball pad shape for improved reliability |
-
2000
- 2000-03-16 JP JP2000074787A patent/JP2001267708A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100632545B1 (en) | 2004-12-20 | 2006-10-09 | 삼성전기주식회사 | Method of manufacturing a ball grid array substrate having a ball pad shape for improved reliability |
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