JP2001257351A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2001257351A JP2001257351A JP2000065911A JP2000065911A JP2001257351A JP 2001257351 A JP2001257351 A JP 2001257351A JP 2000065911 A JP2000065911 A JP 2000065911A JP 2000065911 A JP2000065911 A JP 2000065911A JP 2001257351 A JP2001257351 A JP 2001257351A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- semiconductor layer
- insulating layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は格子歪を有する半導
体層にチャネル領域を形成した半導体装置及びその製造
方法に関する。The present invention relates to a semiconductor device in which a channel region is formed in a semiconductor layer having lattice distortion, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】Ｓｉを材料とする半導体素子、とりわけ
ＭＯＳＦＥＴの性能は、大規模集積回路（ＬＳＩ）の進
歩と共にこれまで年々向上してきたが、近年、リソグラ
フィ技術の微細化対応への限界、Ｓｉの理論的なキャリ
ア移動度の飽和などの問題が指摘され、更なる高性能化
は、困難になってきている。2. Description of the Related Art The performance of semiconductor devices made of Si, particularly MOSFETs, has been improving year by year with the progress of large-scale integrated circuits (LSIs). Problems such as saturation of the theoretical carrier mobility have been pointed out, and further improvement in performance has become difficult.
【０００３】現在、Ｓｉの電子移動度を向上させＭＯＳ
ＦＥＴを高性能化する方法の一つとして、Ｓｉ層に格子
歪を形成する技術が注目されている。一般に半導体層に
格子歪を形成すると、そのバンド構造が変化し、チャネ
ル中のキャリアの散乱が抑制されるため電子移動度の向
上が期待できる。At present, the electron mobility of Si has been improved and MOS
As one of the methods for improving the performance of an FET, a technique of forming a lattice strain in a Si layer has attracted attention. In general, when lattice strain is formed in a semiconductor layer, the band structure is changed, and scattering of carriers in a channel is suppressed, so that an improvement in electron mobility can be expected.
【０００４】具体的には、Ｓｉ基板上にＳｉよりも格子
定数の大きな材料からなる混晶層、例えばＧｅを２０％
含むＳｉＧｅ混晶層（以下、単にＳｉＧｅ層という）
を、格子歪が緩和されるように厚く（数μｍ）形成し、
このＳｉＧｅ層上に薄いＳｉ層（数ｎｍ）を形成する
と、ＳｉＧｅとＳｉの格子定数差による格子歪の内在す
るＳｉ層（以下、歪Ｓｉ層と称する。）が形成される。Specifically, a mixed crystal layer made of a material having a larger lattice constant than Si, for example, Ge
Containing SiGe mixed crystal layer (hereinafter simply referred to as SiGe layer)
Is formed thick (several μm) so that lattice distortion is reduced,
When a thin Si layer (several nm) is formed on this SiGe layer, an Si layer (hereinafter, referred to as a strained Si layer) having a lattice strain due to a difference in lattice constant between SiGe and Si is formed.
【０００５】この歪Ｓｉ層をＭＯＳＦＥＴのチャネルに
用いると、格子歪のないＳｉ層をチャネルに用いた場合
の約１．７６倍と大幅な電子移動度の向上を達成できる
ことが報告されている（Ｊ．Ｗｅｌｓｅｒ， Ｊ．Ｌ．
Ｈｏｙｌ，Ｓ．Ｔａｇｋａｇｉ， ａｎｄ Ｊ．Ｆ．Ｇ
ｉｂｂｏｎｓ，ＩＥＤＭ ９４−３７３）。It has been reported that when this strained Si layer is used for the channel of a MOSFET, a significant improvement in electron mobility can be achieved, about 1.76 times that when a Si layer without lattice distortion is used for the channel ( J. Welser, J.L.
Hoyl, S .; Tagkagi, and J.M. F. G
ibbons, IEDM 94-373).
【０００６】一方、Ｓｉの電子移動度を向上させる別の
方法として、ＭＯＳＦＥＴのチャネル長をより短くする
方法があるが、チャネル長が短くなると浮遊容量の影響
が大きくなるため、期待通りに電子移動度を向上するこ
とが困難になる。この浮遊容量の問題を解決するため、
絶縁膜上のＳｉ層にチャネル層等を設けるＳＯＩ（Ｓｉ
ｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）構造が注目さ
れている。On the other hand, as another method for improving the electron mobility of Si, there is a method of further shortening the channel length of the MOSFET. It becomes difficult to improve the degree. To solve this stray capacitance problem,
SOI (Si) in which a channel layer or the like is provided on the Si layer on the insulating film
(Licon on Insulator) structure.
【０００７】この構造では素子の作られるＳｉ層が絶縁
膜によりアイソレーションされるので、浮遊容量の低減
や素子分離が容易となり、さらなる低消費電力化、高集
積化が実現すると期待されている。In this structure, since the Si layer on which the element is formed is isolated by the insulating film, it is expected that stray capacitance can be reduced and the element can be easily separated, and further lower power consumption and higher integration can be realized.
【０００８】[0008]
【発明が解決しようとする課題】そこで、電子移動度の
向上を期待できる歪Ｓｉ層を、浮遊容量の低減や素子分
離が容易となるＳＯＩ構造に適用するため次のような試
みが行われた。Therefore, the following attempts have been made to apply a strained Si layer, which is expected to improve electron mobility, to an SOI structure in which stray capacitance is reduced and element isolation is facilitated. .
【０００９】Ｓｉ基板に酸素をイオン注入した後、高温
アニールを施して埋め込み酸化層を形成するＳＩＭＯＸ
（Ｓｉｌｉｃｏｎ Ｉｍｐｌａｎｔｅｄ Ｏｘｙｇｅ
ｎ）工程を用いてＳＯＩ基板を準備し、このＳＯＩ基板
表面にＳｉより格子定数の大きいＳｉＧｅ層をＳＯＩ基
板表面のＳｉ層よりも十分厚く形成する。SIMOX for forming a buried oxide layer by performing high-temperature annealing after oxygen ions are implanted into a Si substrate
(Silicon Implanted Oxyge
An SOI substrate is prepared by using the step n), and a SiGe layer having a larger lattice constant than Si is formed on the surface of the SOI substrate sufficiently thicker than the Si layer on the surface of the SOI substrate.
【００１０】この後、アニールを施して、Ｓｉ層を塑性
変形させ転位を導入することにより、ＳｉＧｅ層からＳ
ｉ層にかかる引っ張り応力を緩和し、同時にＳｉＧｅ層
の格子歪を緩和する。そして、格子歪の緩和されたＳｉ
Ｇｅ層上に薄膜のＳｉ層を形成すると、引っ張り歪を有
する歪Ｓｉ層が形成される。After that, annealing is performed to plastically deform the Si layer to introduce dislocations, so that the SiGe layer
The tensile stress applied to the i-layer is reduced, and at the same time, the lattice strain of the SiGe layer is reduced. Then, Si with lattice strain relaxed
When a thin Si layer is formed on the Ge layer, a strained Si layer having tensile strain is formed.
【００１１】上述の方法では、ＳＯＩ基板表面のＳｉ層
の塑性変形によって、そのＳｉ層中に貫通転位やミスフ
ィット転位などの転位が発生するが、その転位がその後
の熱履歴によって１個／１０μｍ２程度の密度でＳｉＧ
ｅ層の表面にも伝播し、歪Ｓｉ層の結晶性を劣化させる
ことが分かった。この歪Ｓｉ層の結晶性劣化はその上に
作製される半導体素子の特性を大きく劣化させる可能性
があり、半導体素子が微細化されるほど顕著になると予
想される。In the above-described method, dislocations such as threading dislocations and misfit dislocations are generated in the Si layer by the plastic deformation of the Si layer on the surface of the SOI substrate. SiG with moderate density
It has been found that it also propagates to the surface of the e layer and deteriorates the crystallinity of the strained Si layer. This deterioration in the crystallinity of the strained Si layer may significantly degrade the characteristics of the semiconductor element manufactured thereon, and is expected to become more significant as the semiconductor element is miniaturized.
【００１２】従って、歪Ｓｉ層の結晶性劣化させるよう
な転位のＳｉＧｅ表面への伝播を抑えるためには、これ
までのところＳｉＧｅ層を数μｍ以上の厚さで厚く形成
しなければならない。Therefore, in order to suppress the dislocation from propagating to the SiGe surface which causes the crystallinity of the strained Si layer to deteriorate, the SiGe layer has to be formed to a thickness of several μm or more so far.
【００１３】しかしながら、浮遊容量の影響を抑えるＳ
ＯＩ構造の効果を十分に発揮するためには、ＳｉＯ２層
からチャネル層である歪Ｓｉ層までの厚みを極力抑える
ことが必要であり、歪Ｓｉ層の結晶性とＳＯＩ構造の効
果とを両立させることができない。However, S which suppresses the influence of stray capacitance
In order to sufficiently exert the effect of the OI structure, it is necessary to minimize the thickness from the SiO 2 layer to the strained Si layer as the channel layer, and to achieve both the crystallinity of the strained Si layer and the effect of the SOI structure. Can not do.
【００１４】また、最近の開発動向を見るに、メモリ、
ＣＰＵなどの単一または特定機能のみのデバイスでは商
品付加価値が低く、高速論理素子と記憶保持用メモリを
同一基板上に有するような混載デバイス、或いはシステ
ムＬＳＩ等と呼ばれものが注目されているが、この様な
混載型の半導体装置を製造する場合、高速演算を行う半
導体素子には、高速動作が可能な歪Ｓｉ層利用の半導体
素子が有効である一方で、記憶保持用メモリに利用され
る半導体素子、例えばＤＲＡＭを構成するＭＯＳＦＥＴ
に要求される重要な素子特性は信頼性であって、歪Ｓｉ
層中の欠陥は無視出来ない。Looking at recent development trends, memory,
A device such as a CPU having only a single function or a specific function has a low value added to a product, and a device called a hybrid device or a system LSI having a high-speed logic element and a memory for storing data on the same substrate has attracted attention. However, when manufacturing such a hybrid type semiconductor device, a semiconductor element utilizing a strained Si layer capable of high-speed operation is effective as a semiconductor element performing high-speed operation, while a semiconductor element utilizing storage strain is used for a memory element. Semiconductor device, for example, a MOSFET constituting a DRAM
An important element characteristic required for the device is reliability,
Defects in the layer cannot be ignored.
【００１５】本発明は、かかる事情に鑑みて成されたも
のであって、浮遊容量の小さな所望のＳＯＩ構造に、上
述の結晶性劣化の問題を抑えた歪み半導体層を組み込ん
だ半導体装置及びその製造方法を提供することを目的と
する。The present invention has been made in view of the above circumstances, and provides a semiconductor device in which a desired SOI structure having a small stray capacitance is incorporated with a strained semiconductor layer that suppresses the above-described problem of crystallinity deterioration. It is intended to provide a manufacturing method.
【００１６】[0016]
【課題を解決するための手段】Ｓｉ基板表面から酸素を
イオン注入する際、イオン注入条件とその後のアニール
条件を制御すると、イオン注入の濃度ピークとダメージ
・ピークの各位置に、二層の埋め込み酸化層を形成可能
であることが判っている（Ａ．Ｏｇｕｒａ，Ａｐｐｌ．
Ｐｈｙｓ． Ｌｅｔｔ． ｖｏｌ．７４， ｎｏ．１
５， Ｐ２１８８， １９９９）が、本発明では、半導
体層、例えばＳｉ層表面に、組成の異なる半導体層、例
えばＳｉＧｅ層を積層するように成長した半導体基板
に、酸素をイオン注入し、濃度ピークとダメージピーク
の各位置に、二層の埋め込み酸化層を形成した。When oxygen is ion-implanted from the surface of the Si substrate, the ion implantation conditions and the subsequent annealing conditions are controlled, so that two layers are buried at each position of the ion implantation concentration peak and the damage peak. It has been found that an oxide layer can be formed (A. Ogura, Appl.
Phys. Lett. vol. 74, no. 1
According to the present invention, oxygen ions are implanted into a semiconductor substrate grown such that a semiconductor layer having a different composition, for example, a SiGe layer is stacked on the surface of a semiconductor layer, for example, a Si layer, and a concentration peak is obtained. At each position of the damage peak, two buried oxide layers were formed.
【００１７】その結果、例えばＳｉＧｅ層、酸化層、Ｓ
ｉ層、酸化層、Ｓｉ層の順に二層の異なる組成を持つＳ
ＯＩ構造が形成できることを見出した。しかも、この二
層の異なる組成を持つＳＯＩ構造では、従来の技術の欄
で説明したような、Ｓｉ層の塑性変形による転位導入工
程がないため、ＳｉＧｅ層の格子歪を緩和させるための
高温アニールで、貫通転位等が歪半導体層に影響するこ
とがない。As a result, for example, a SiGe layer, an oxide layer,
S having two different compositions in the order of i-layer, oxide layer and Si layer
It has been found that an OI structure can be formed. Moreover, in the SOI structure having the two layers having different compositions, there is no dislocation introduction step due to the plastic deformation of the Si layer as described in the section of the prior art, so that the high-temperature annealing for relaxing the lattice distortion of the SiGe layer is performed. Thus, threading dislocations and the like do not affect the strained semiconductor layer.
【００１８】上記目的を達成するために、請求項１に係
る発明は、一主面を有する半導体基板と、この半導体基
板の内部に前記一主面とは略平行に離間して形成された
第１絶縁層と、この第１絶縁層上に位置させられた第１
半導体層と、この第１半導体層上に選択的に形成された
第２絶縁層と、前記第１半導体層とは異なる組成で前記
第２絶縁層上に位置させられた第２半導体層と、前記第
１半導体層とは異なる組成で前記第１半導体層上に積層
して形成された第３半導体層とを備え、前記第２半導体
層がチャネル領域として使用された電界効果トランジス
タ及び第３半導体層がチャネル領域として使用された電
界効果トランジスタとにより集積回路が構成されている
ことを特徴とする半導体装置を提供する。In order to achieve the above object, the invention according to claim 1 is directed to a semiconductor substrate having one main surface and a semiconductor substrate formed inside the semiconductor substrate so as to be substantially parallel to and separated from the one main surface. 1 insulating layer and a first insulating layer located on the first insulating layer.
A semiconductor layer, a second insulating layer selectively formed on the first semiconductor layer, a second semiconductor layer positioned on the second insulating layer with a composition different from that of the first semiconductor layer, A third semiconductor layer having a composition different from that of the first semiconductor layer and stacked on the first semiconductor layer, wherein the second semiconductor layer is used as a channel region; There is provided a semiconductor device in which an integrated circuit is formed by a field effect transistor whose layer is used as a channel region.
【００１９】また、請求項２に係る発明は、一主面を有
する半導体基板と、この半導体基板の内部に前記一主面
とは略平行に離間して形成された第１絶縁層と、この第
１絶縁層上に位置させられた第１半導体層と、この第１
半導体層上に選択的に形成された第２絶縁層と、前記第
１半導体層とは異なる組成で前記第２絶縁層上に位置さ
せられた第２半導体層と、この第２半導体層とは異なる
組成で前記第２半導体層上に積層形成された第４半導体
層とを備え、前記第１半導体層がチャネル領域として使
用された電界効果トランジスタ及び第４半導体層がチャ
ネル領域として使用された電界効果トランジスタとによ
り集積回路が構成されていることを特徴とする半導体装
置を提供する。According to a second aspect of the present invention, there is provided a semiconductor substrate having one main surface, a first insulating layer formed inside the semiconductor substrate so as to be substantially parallel to and separated from the one main surface, A first semiconductor layer located on the first insulating layer;
A second insulating layer selectively formed on the semiconductor layer, a second semiconductor layer located on the second insulating layer with a composition different from that of the first semiconductor layer, and the second semiconductor layer A fourth semiconductor layer having a different composition and stacked on the second semiconductor layer, wherein the first semiconductor layer is used as a channel region and the fourth semiconductor layer is used as a channel region. There is provided a semiconductor device in which an integrated circuit is constituted by an effect transistor.
【００２０】また、請求項３に係る発明は、一主面を有
する半導体基板と、この半導体基板の内部に前記一主面
とは略平行に離間して形成された第１絶縁層と、この第
１絶縁層上に位置させられた第１半導体層と、この第１
半導体層上に選択的に形成された第２絶縁層と、前記第
１半導体層とは異なる組成で前記第２絶縁層上に位置さ
せられた第２半導体層と、前記第１半導体層とは異なる
組成で前記第１半導体層上に積層して形成された第３半
導体層と、前記第２半導体層とは異なる組成で前記第２
半導体層上に積層形成された第４半導体層とを備え、前
記第３半導体層がチャネル領域として使用された電界効
果トランジスタ及び第４半導体層がチャネル領域として
使用された電界効果トランジスタとにより集積回路が構
成されていることを特徴とする半導体装置を提供する。According to a third aspect of the present invention, there is provided a semiconductor substrate having one main surface, a first insulating layer formed inside the semiconductor substrate so as to be substantially parallel to and separated from the one main surface, A first semiconductor layer located on the first insulating layer;
A second insulating layer selectively formed on the semiconductor layer, a second semiconductor layer located on the second insulating layer with a composition different from that of the first semiconductor layer, and the first semiconductor layer The third semiconductor layer formed by being stacked on the first semiconductor layer with a different composition, and the second semiconductor layer having a different composition from the second semiconductor layer.
A fourth semiconductor layer laminated on a semiconductor layer, wherein the third semiconductor layer is used as a channel region and a field effect transistor and the fourth semiconductor layer is used as a channel region. Are provided, and a semiconductor device is provided.
【００２１】また、請求項４に係る発明は、請求項１又
は請求項３に係る半導体装置の前記第３半導体層が、前
記第１半導体層とは異なる格子定数を有し、圧縮歪みを
有することを特徴とする半導体装置を提供する。According to a fourth aspect of the present invention, in the semiconductor device according to the first or third aspect, the third semiconductor layer has a different lattice constant from the first semiconductor layer and has a compressive strain. A semiconductor device is provided.
【００２２】また、請求項５に係る発明は、請求項２又
は請求項３に係る半導体装置の前記第４半導体層が、前
記第２半導体層とは異なる格子定数を有し、引っ張り歪
みを有することを特徴とする半導体装置を提供する。According to a fifth aspect of the present invention, in the semiconductor device according to the second or third aspect, the fourth semiconductor layer has a lattice constant different from that of the second semiconductor layer and has a tensile strain. A semiconductor device is provided.
【００２３】また、請求項６に係る発明は、請求項１乃
至請求項５に係る半導体装置の前記第１半導体層がＳｉ
単結晶層であり、且つ前記第２半導体層がＳｉＧｅ混晶
層であることを特徴とする半導体装置を提供する。According to a sixth aspect of the present invention, in the semiconductor device according to the first to fifth aspects, the first semiconductor layer is made of Si.
A semiconductor device is provided, wherein the semiconductor device is a single crystal layer, and the second semiconductor layer is a SiGe mixed crystal layer.
【００２４】また、請求項７に係る発明は、請求項１乃
至請求項５に係る半導体装置の前記第１半導体層がＳ
ｉ、Ｂ、Ａｓ、Ｐ、Ｃ、Ｇｅ、Ｇａ、Ｉｎ、Ａｌ、Ｚ
ｎ、Ｓｅから選ばれた少なくとも一つの材料で構成され
る結晶または混晶層であることを特徴とする半導体装置
を提供する。According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the first semiconductor layer is formed of S
i, B, As, P, C, Ge, Ga, In, Al, Z
A semiconductor device is provided which is a crystal or mixed crystal layer formed of at least one material selected from n and Se.
【００２５】また、請求項８に係る発明は、請求項１乃
至請求項５に係る半導体装置の前記半導体基板が、Ｇａ
Ａｓ、ＺｎＳｅ、ＳｉＣ、Ｇｅ、ＳｉＧｅ、サファイ
ア、有機ガラス、無機ガラス、プラスティックから選ば
れた少なくとも一つの材料で構成される基板と積層され
ていることを特徴とする半導体装置を提供する。According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the semiconductor substrate is formed of Ga.
A semiconductor device is provided, which is stacked with a substrate made of at least one material selected from the group consisting of As, ZnSe, SiC, Ge, SiGe, sapphire, organic glass, inorganic glass, and plastic.
【００２６】また、請求項９に係る発明は、請求項１乃
至請求項５に係る半導体装置の前記第２絶縁層と前記第
２半導体層のとが、ウェハーの張り合わせ技術により一
体化されていることを特徴とする半導体装置を提供す
る。According to a ninth aspect of the present invention, in the semiconductor device according to the first to fifth aspects, the second insulating layer and the second semiconductor layer are integrated by a wafer bonding technique. A semiconductor device is provided.
【００２７】また、請求項１０に係る発明は、請求項１
乃至請求項６に係る半導体装置の前記第１半導体層の厚
さが１００ｎｍ以下であることを特徴とする半導体装置
を提供する。The invention according to claim 10 is the first invention.
7. A semiconductor device according to claim 6, wherein the thickness of the first semiconductor layer is 100 nm or less.
【００２８】また、請求項１１に係る発明は、半導体基
板の一主面に、その半導体基板と異なる組成の第１半導
体層を形成する工程と、イオン注入による損傷ピークと
濃度ピークが前記半導体基板内部において異なる深さと
なる条件で、前記半導体基板内部に前記一主面側から酸
素をイオン注入する工程と、前記半導体基板を加熱し、
前記半導体基板内部に注入された酸素と半導体基板構成
材料との酸化物を形成することにより、前記半導体基板
内部のより深い位置に第１絶縁層を、その第１絶縁層よ
りも浅い位置に第２絶縁層を互いに離間させて形成する
工程とを具備することを特徴とする半導体装置の製造方
法を提供する。The invention according to claim 11 is a step of forming a first semiconductor layer having a composition different from that of the semiconductor substrate on one main surface of the semiconductor substrate, and the step of reducing a damage peak and a concentration peak caused by ion implantation. Under a condition of different depths inside, a step of ion-implanting oxygen into the semiconductor substrate from the one main surface side, and heating the semiconductor substrate,
The first insulating layer is formed at a deeper position inside the semiconductor substrate, and the first insulating layer is formed at a position shallower than the first insulating layer by forming an oxide of the oxygen and the constituent material of the semiconductor substrate that are injected into the semiconductor substrate. Forming the two insulating layers separately from each other.
【００２９】また、請求項１２に係る発明は、請求項１
１に係る半導体装置の製造方法に更に、前記第１絶縁層
上の半導体基板の一部に、前記半導体基板とは異なる組
成の第２半導体層を、前記半導体基板の一部に積層して
形成する工程を備えることを特徴とする半導体装置の製
造方法を提供する。The invention according to claim 12 is based on claim 1.
Further, in the method of manufacturing a semiconductor device according to the first aspect, a second semiconductor layer having a composition different from that of the semiconductor substrate is formed on a part of the semiconductor substrate on the first insulating layer by laminating the semiconductor substrate on a part of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising the steps of:
【００３０】また、請求項１３に係る発明は、請求項１
１に係る半導体装置の製造方法に更に、前記第１半導体
層とは異なる組成の第３半導体層を前記第１半導体層上
に積層して形成する工程を備えることを特徴とする半導
体装置の製造方法を提供する。[0030] The invention according to claim 13 is based on claim 1.
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a third semiconductor layer having a composition different from that of the first semiconductor layer by laminating the third semiconductor layer on the first semiconductor layer. Provide a way.
【００３１】[0031]
【作用】本発明によれば、Ｓｉ層の塑性変形による転位
導入工程がなく、ＳｉＧｅ層の格子歪を緩和させるため
の高温アニールで、貫通転位等が歪半導体層に影響する
ことがないため、格子歪が緩和された状態で、互いに絶
縁された、組成の異なる二層の半導体層、例えばＳｉＧ
ｅ層とＳｉ層を結晶性良く且つ薄く、また同時に得るこ
とが可能になり、素子特性の劣化等の問題も解消され
る。According to the present invention, since there is no dislocation introduction step due to plastic deformation of the Si layer and high-temperature annealing for relaxing lattice strain of the SiGe layer, threading dislocations and the like do not affect the strained semiconductor layer. In a state where the lattice strain is relaxed, two semiconductor layers having different compositions and insulated from each other, for example, SiG
The e layer and the Si layer can be obtained simultaneously with good crystallinity and thinness, and problems such as deterioration of device characteristics can be solved.
【００３２】[0032]
【発明の実施の形態】以下、図面を参照しながら、本発
明の実施例を説明する。 （実施例１）図１は、本発明の半導体装置の一部を示す
断面図である。図１の半導体装置は、Ｓｉ基板１の一主
面側からその内部にイオン注入された酸素を、濃度ピー
クとダメージ・ピークの近傍において、夫々、基板構成
材料であるＳｉと反応させ、ＳｉＯ２の絶縁層３及び絶
縁層４を形成し、ＳｉＧｅ層６及びＳｉ層５を絶縁層４
により電気的に分離した二層のＳＯＩ構造を利用して構
成されている。Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a sectional view showing a part of a semiconductor device of the present invention. In the semiconductor device of FIG. 1, oxygen ion-implanted from one main surface side of the Si substrate 1 to the inside thereof reacts with Si, which is a substrate constituent material, in the vicinity of a concentration peak and a damage peak, respectively. An insulating layer 3 and an insulating layer 4 are formed, and the SiGe layer 6 and the Si layer 5 are
It is configured using a two-layer SOI structure which is electrically separated from the SOI structure.
【００３３】イオン注入後の高温アニール処理により格
子歪の緩和されたＳｉＧｅ層（以下、緩和ＳｉＧｅ層と
称する。）６及びＳｉ層５は、ＳＯＩ構造にける寄生容
量の低減効果を十分に発揮させるため、非常に薄く形成
されており、夫々の厚さはＳｉ層５、緩和ＳｉＧｅ層６
共に、１０ｎｍ〜２００ｎｍの範囲に制御されている。The SiGe layer (hereinafter, referred to as a relaxed SiGe layer) 6 whose lattice distortion has been relaxed by the high-temperature annealing treatment after the ion implantation and the Si layer 5 sufficiently exhibit the effect of reducing the parasitic capacitance in the SOI structure. Therefore, they are formed to be very thin, and their thicknesses are the Si layer 5 and the relaxed SiGe layer 6 respectively.
Both are controlled in the range of 10 nm to 200 nm.
【００３４】また、緩和ＳｉＧｅ層６上には比較的に高
速な動作を要求される半導体素子を作りこむため、引っ
張り歪を有するＳｉ層（以下、歪Ｓｉ層と称する。）７
がＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓ
ｉｔｉｏｎ）や、ＭＢＥ（Ｍｏｌｅｃｕｌａｒ Ｂｅａ
ｍ Ｅｐｉｔａｘｙ）等で形成されている。この歪Ｓｉ
層７には、この層を利用して作り込まれるＭＯＳＦＥＴ
のチャンネル領域の導電型を決定するため、Ｐ型ウェル
領域８及びＮ型ウェル領域９がＢ，Ａｓ，Ｐ等の不純物
を導入して形成されている。On the relaxed SiGe layer 6, a Si layer having a tensile strain (hereinafter, referred to as a strained Si layer) 7 is formed in order to fabricate a semiconductor element required to operate at a relatively high speed.
Is CVD (Chemical Vapor Depos)
ition), MBE (Molecular BEA)
m Epitaxy). This strain Si
Layer 7 has a MOSFET built using this layer
In order to determine the conductivity type of the channel region, a P-type well region 8 and an N-type well region 9 are formed by introducing impurities such as B, As, and P.
【００３５】更に、Ｐ型ウェル領域８には、選択的にＰ
等のＮ型不純物が導入され、ＭＯＳＦＥＴのソース領域
１２及びドレイン領域１３が形成されている。それ等、
ソース領域１２及びドレイン領域１３間のチャンネル領
域上にはゲート機能を付与するためゲート絶縁層１６及
びゲート電極１７が積層されている。Further, the P-type well region 8 is selectively
The source region 12 and the drain region 13 of the MOSFET are formed by introducing N-type impurities such as. Etc.
A gate insulating layer 16 and a gate electrode 17 are stacked on the channel region between the source region 12 and the drain region 13 to provide a gate function.
【００３６】同様に、Ｎ型ウェル領域９には、選択的に
Ｂ等のＰ型不純物が導入され、ＭＯＳＦＥＴのソース領
域１４及びドレイン領域１５が形成されている。それ
等、ソース領域１４及びドレイン領域１５間のチャネル
領域上にはゲート機能を付与するためゲート絶縁層１８
及びゲート電極１９が積層されている。Similarly, a P-type impurity such as B is selectively introduced into the N-type well region 9 to form a source region 14 and a drain region 15 of the MOSFET. On the channel region between the source region 14 and the drain region 15, a gate insulating layer 18 for providing a gate function is provided.
And a gate electrode 19 are stacked.
【００３７】ゲート絶縁層１６としては、熱酸化膜、Ｔ
ＥＯＳ、ＣＶＤ膜等を用いることができる。また、ゲー
ト電極１７に、減圧ＣＶＤ法により形成された多結晶Ｓ
ｉ層を用いれば、ＲＩＥ（反応性イオンエッチング）に
より、ゲート電極形状は容易にパターニングできる。As the gate insulating layer 16, a thermal oxide film, T
EOS, a CVD film, or the like can be used. Also, a polycrystalline S formed by a low pressure CVD method is formed on the gate electrode 17.
If an i layer is used, the shape of the gate electrode can be easily patterned by RIE (reactive ion etching).
【００３８】図１で示されている範囲では、緩和ＳｉＧ
ｅ層６上に構成された半導体素子は、Ｐチャンネル型Ｍ
ＯＳＦＥＴ及びＮチャンネル型ＭＯＳＦＥＴの夫々一素
子分であるが、実際のデバイスを構成するには、Ｐチャ
ンネル型ＭＯＳＦＥＴ及びＮチャンネル型ＭＯＳＦＥＴ
共に多数を作り込む必要がある。In the range shown in FIG. 1, the relaxed SiG
The semiconductor element formed on the e-layer 6 is a P-channel type M
OSFETs and N-channel MOSFETs each correspond to one element. However, to construct an actual device, a P-channel MOSFET and an N-channel MOSFET are used.
It is necessary to build many together.
【００３９】また、歪Ｓｉ層７を利用して作り込まれる
ＭＯＳＦＥＴは、格子歪の無いＳｉ層を利用して作られ
る半導体素子に比較し、高速な動作が期待できるので、
回路的にはＣＭＯＳ構成でロジックＩＣ部として構成さ
れるのに適している。Since a MOSFET fabricated using the strained Si layer 7 can be expected to operate at a higher speed than a semiconductor device fabricated using a Si layer having no lattice distortion,
The circuit is suitable to be configured as a logic IC unit with a CMOS configuration.
【００４０】一方、絶縁層３上のＳｉ層５は、ＣＤＥ
（ケミカル・ドライ・エッチング）や、ＲＩＥなどのド
ライ・エッチング処理により絶縁層４及び緩和ＳｉＧｅ
層６が選択的に除去された露出表面を有しており、この
表面から比較的信頼性の高い動作を要求される半導体素
子が作り込まれている。On the other hand, the Si layer 5 on the insulating layer 3
(Chemical dry etching) or dry etching such as RIE to form the insulating layer 4 and relaxed SiGe.
Layer 6 has an exposed surface that is selectively removed, from which a semiconductor device that requires relatively reliable operation has been fabricated.
【００４１】絶縁層４及び緩和ＳｉＧｅ層６が除去され
たＳｉ層５の表面からは、Ｂ，Ａｓ，Ｐ等の不純物が導
入され、この層を利用して作り込まれるＭＯＳＦＥＴの
チャネル領域の導電型を決定するため、Ｐ型ウェル領域
１０及びＮ型ウェル領域１１が形成されている。Impurities such as B, As, and P are introduced from the surface of the Si layer 5 from which the insulating layer 4 and the relaxed SiGe layer 6 are removed, and the conductivity of the channel region of the MOSFET formed by using this layer is introduced. In order to determine the type, a P-type well region 10 and an N-type well region 11 are formed.
【００４２】更に、Ｐ型ウェル領域１０には、選択的に
Ｐ等のＮ型不純物が導入され、ＭＯＳＦＥＴのソース領
域２０及びドレイン領域２１が形成されている。それ
等、ソース領域２０及びドレイン領域２１間のチャンネ
ル領域上にはゲート機能を付与するためゲート絶縁層２
４及びゲート電極２５が積層されている。Further, an N-type impurity such as P is selectively introduced into the P-type well region 10 to form a source region 20 and a drain region 21 of the MOSFET. The gate insulating layer 2 is provided on the channel region between the source region 20 and the drain region 21 to provide a gate function.
4 and the gate electrode 25 are stacked.
【００４３】ゲート絶縁層２４としては、熱酸化膜、Ｔ
ＥＯＳ、ＣＶＤ膜等を用いることができる。また、ゲー
ト電極２５に、減圧ＣＶＤ法により形成された多結晶Ｓ
ｉ層を用いれば、ＲＩＥ（反応性イオンエッチング）に
より、ゲート電極形状は容易にパターニングできる。As the gate insulating layer 24, a thermal oxide film, T
EOS, a CVD film, or the like can be used. Also, a polycrystalline S formed by a low pressure CVD method is formed on the gate electrode 25.
If an i layer is used, the shape of the gate electrode can be easily patterned by RIE (reactive ion etching).
【００４４】同様にＮ型ウェル領域１１には、選択的に
Ｂ等のＰ型不純物が導入され、ＭＯＳＦＥＴのソース領
域２２及びドレイン領域２３が形成されている。それ
等、ソース領域２２及びドレイン領域２３間のチャネル
領域上にはゲート機能を付与するためゲート絶縁層２６
及びゲート電極２７が積層されている。Similarly, a P-type impurity such as B is selectively introduced into the N-type well region 11 to form a source region 22 and a drain region 23 of the MOSFET. On the channel region between the source region 22 and the drain region 23, a gate insulating layer 26 for imparting a gate function is provided.
And a gate electrode 27 are stacked.
【００４５】図１で示されている範囲では、上部に絶縁
層４及び緩和ＳｉＧｅ層６が存在しない部分のＳｉ層５
を利用した半導体素子は、Ｐチャンネル型ＭＯＳＦＥＴ
及びＮチャンネル型ＭＯＳＦＥＴの夫々一素子分である
が、実際のデバイスを構成するには、Ｐチャンネル型Ｍ
ＯＳＦＥＴ及びＮチャンネル型ＭＯＳＦＥＴ共に多数を
作り込む必要がある。In the range shown in FIG. 1, the upper portion of the Si layer 5 where the insulating layer 4 and the relaxed SiGe layer 6 do not exist is provided.
Is a P-channel MOSFET
And an N-channel MOSFET, one element each. However, to construct an actual device, a P-channel M
It is necessary to build many OSFETs and N-channel MOSFETs.
【００４６】また、Ｓｉ層５は、結晶欠陥及び格子歪が
共に極力減少させて製造されるＳｉ基板１と同等の状態
にあるため、信頼性及び安定性のある動作が期待できる
ので、回路的にはＤＲＡＭ等のメモリ部として構成され
るのに適している。Since the Si layer 5 is in the same state as the Si substrate 1 manufactured with the crystal defects and the lattice strain both reduced as much as possible, a reliable and stable operation can be expected. Is suitable for being configured as a memory unit such as a DRAM.
【００４７】尚、ソース領域１２，１４，２０，２２及
びドレイン領域１３，１５，２１，２３には、電極２
８，２９，３０，３１，３２，３３が、絶縁層３４及び
３５に選択的に設けられた開口を介してオーミックに接
続されている。The source regions 12, 14, 20, 22 and the drain regions 13, 15, 21, 23 are provided with electrodes 2
8, 29, 30, 31, 32, and 33 are ohmically connected through openings selectively provided in the insulating layers and.
【００４８】図１の実施例によれば、引っ張り歪が存在
するＳｉ層を用いたＭＯＳＦＥＴと結晶欠陥及び格子歪
が共に少ないＳｉ層を用いたＭＯＳＦＥＴとを同じ基板
上のＳＯＩ構造上に形成できるので、両Ｓｉ層の特性を
十分引き出し半導体装置の高速・高性能化を図ることが
できる。According to the embodiment shown in FIG. 1, a MOSFET using an Si layer having tensile strain and a MOSFET using an Si layer having less crystal defects and less lattice strain can be formed on the SOI structure on the same substrate. Therefore, the characteristics of both Si layers can be sufficiently extracted to achieve high speed and high performance of the semiconductor device.
【００４９】この実施例では、歪Ｓｉ層７中にソース領
域１２，１３及びドレイン領域１４，１５を形成した
が、歪Ｓｉ層７をゲート絶縁層１６，１８直下のみ選択
的に形成してチャンネル領域とし、そのチャンネル領域
に隣接させて緩和ＳｉＧｅ層６中にソース領域１２，１
３及びドレイン領域１４，１５を形成しても良い。In this embodiment, the source regions 12, 13 and the drain regions 14, 15 are formed in the strained Si layer 7. However, the strained Si layer 7 is selectively formed only immediately below the gate insulating layers 16, 18 to form a channel. Source regions 12, 1 in the relaxed SiGe layer 6 adjacent to the channel region.
3 and the drain regions 14 and 15 may be formed.
【００５０】図２乃び図３は、本発明に係る半導体装置
の製造方法の一部の工程を示す部分断面図である。図２
乃び図３により二層のＳＯＩ構造を得るための製造方法
を詳述する。FIGS. 2 and 3 are partial sectional views showing some steps of a method of manufacturing a semiconductor device according to the present invention. FIG.
The manufacturing method for obtaining a two-layer SOI structure will be described in detail with reference to FIG.
【００５１】まず、図２に示すように、Ｓｉ基板１上に
格子歪を有するＳｉＧｅ層（以下、歪ＳｉＧｅ層と称す
る。）２が１００ｎｍ程度の厚さで形成されたウェハを
用意する。この歪ＳｉＧｅ層２は、４０〜３００ｎｍの
範囲の膜厚が好ましく、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖ
ａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）、ＭＢＥ（Ｍｏｌｅ
ｃｕｌａｒ Ｂｅａｍ Ｅｐｉｔａｘｙ）等により形成
される。First, as shown in FIG. 2, a wafer is prepared in which a SiGe layer 2 having lattice strain (hereinafter, referred to as a strained SiGe layer) 2 having a thickness of about 100 nm is formed on a Si substrate 1. The strained SiGe layer 2 preferably has a thickness in the range of 40 to 300 nm, and is formed by CVD (Chemical V).
apor Deposition), MBE (Mole
Circular Beam Epitaxy) or the like.
【００５２】例えばＣＶＤで形成する場合は、Ｓｉの原
料ガスとＧｅの原料ガスを、５５０℃に加熱したＳｉ基
板１上に導入してＳｉＧｅ層を堆積する。Ｇｅ濃度は２
％以上５０％以下の範囲で選択して良いが、素子特性の
向上の観点から１０％〜４０％程度が望ましく、２０％
〜３０％の範囲が最適である。For example, in the case of forming by CVD, a source gas of Si and a source gas of Ge are introduced onto the Si substrate 1 heated to 550 ° C. to deposit a SiGe layer. Ge concentration is 2
% To 50%, but may be selected from the range of about 10% to 40% from the viewpoint of improvement of device characteristics, and 20% to 50%.
The range of ３０30% is optimal.
【００５３】次に、所望の加速電圧及び、ドーズ量で、
Ｓｉ基板１中に酸素をイオン注入する。酸素のイオン注
入条件は、注入エネルギー１８０ＫｅＶ、注入量４Ｅ１
７ｃｍ−２、基板温度６００℃とした。Next, at a desired acceleration voltage and a desired dose,
Oxygen is ion-implanted into the Si substrate 1. The oxygen ion implantation conditions are as follows: implantation energy 180 KeV, implantation amount 4E1.
7 cm-2 and a substrate temperature of 600C.
【００５４】この段階では、歪ＳｉＧｅ層２とＳｉ基板
１の界面からＳｉ基板１側へ１０ｎｍ〜２μｍの範囲
で、好ましくは５００ｎｍ〜６００ｎｍの位置に酸素の
濃度ピークが、その濃度ピークよりも歪ＳｉＧｅ層２側
に２００ｎｍ〜３００ｎｍ寄った位置にダメージ・ピー
クが存在するが、いわゆる酸化層は形成されていない。At this stage, the oxygen concentration peak at a position within a range of 10 nm to 2 μm, preferably 500 nm to 600 nm from the interface between the strained SiGe layer 2 and the Si substrate 1 to the Si substrate 1 is more strained than the concentration peak. Although a damage peak exists at a position closer to the SiGe layer 2 by 200 nm to 300 nm, a so-called oxide layer is not formed.
【００５５】このイオン注入の後、高温アニールを施す
ことによって、図３に示すように、濃度ピーク近傍に絶
縁層３が、ダメージ・ピーク近傍に絶縁層４が形成さ
れ、二層のＳＯＩ構造、即ち、格子歪の緩和された１０
ｎｍ〜２００ｎｍのＳｉＧｅ層（以下、緩和ＳｉＧｅ層
と称する。）６、１０ｎｍ〜５００ｎｍのＳｉＯ２層
（絶縁層４）、１０ｎｍ〜２００ｎｍのＳｉ層５、１０
ｎｍ〜５００ｎｍのＳｉＯ２層（絶縁層３）、及びＳｉ
基板１の積層構造が形成される。After this ion implantation, high-temperature annealing is performed to form an insulating layer 3 near the concentration peak and an insulating layer 4 near the damage peak, as shown in FIG. In other words, 10 in which the lattice strain was relaxed
6 nm to 200 nm (hereinafter referred to as relaxed SiGe layer) 6, 10 nm to 500 nm SiO 2 layer (insulating layer 4), 10 nm to 200 nm Si layer 5, 10
nm to 500 nm SiO2 layer (insulating layer 3) and Si
A laminated structure of the substrate 1 is formed.
【００５６】この高温アニールは、真空中でも、Ａｒ、
水素、Ｈｅ、窒素などの不活性ガスのいずれか１種類の
雰囲気中、或いはそれ等の不活性ガスの混合雰囲気中で
も良く、更には、上記不活性ガスに酸素ガスを加えた混
合ガス雰囲気中であっても良い。アニール温度は、絶縁
層３及び４が図３の如く形成される温度であることが必
要で、ＳｉＯ２層により形成する場合は、１０００℃〜
１４００℃の間であることが望ましいが、１２７０〜１
３７０℃が最適である。This high-temperature anneal is performed in a vacuum, even if Ar,
In an atmosphere of any one of inert gases such as hydrogen, He, and nitrogen, or in a mixed atmosphere of such inert gases, and further in a mixed gas atmosphere obtained by adding oxygen gas to the above inert gas. There may be. The annealing temperature is required to be a temperature at which the insulating layers 3 and 4 are formed as shown in FIG. 3.
It is desirable to be between 1400 ° C.,
370 ° C. is optimal.
【００５７】また、この高温アニールにより、図２の歪
ＳｉＧｅ層２の格子歪は緩和され、格子歪が緩和された
状態のＳｉＧｅ混晶層、即ち緩和ＳｉＧｅ層６が形成さ
れる。Also, by this high-temperature annealing, the lattice strain of the strained SiGe layer 2 in FIG. 2 is relaxed, and a SiGe mixed crystal layer in which the lattice strain is relaxed, that is, the relaxed SiGe layer 6 is formed.
【００５８】尚、高温アニール直後は、最上層のＳｉＧ
ｅ層６表面にも酸化層が形成されているが、この酸化層
はその後のＷｅｔ処理により取り除かれるので、図３で
はその酸化層の除去後の構造を示した。Immediately after the high-temperature annealing, the uppermost layer of SiG
An oxide layer is also formed on the surface of the e-layer 6, but since this oxide layer is removed by a subsequent Wet process, FIG. 3 shows the structure after the removal of the oxide layer.
【００５９】また、上述の高温アニール工程で、絶縁層
３及び絶縁層４の形成に要するアニール時間が長い場合
には、ＳｉＧｅ層２中のＧｅが、Ｓｉ層５に１％以上も
拡散することがある。これを避け、且つ図３と同様のＳ
ｉ基板１、絶縁層３、Ｓｉ層５、絶縁層４、及び緩和Ｓ
ｉＧｅ層６の積層構造を得たい場合には、次の様な工程
により製造することが好ましい。If the annealing time required for forming the insulating layers 3 and 4 is long in the above-described high-temperature annealing step, Ge in the SiGe layer 2 may diffuse by 1% or more into the Si layer 5. There is. This is avoided, and S similar to FIG.
i-substrate 1, insulating layer 3, Si layer 5, insulating layer 4, and relaxed S
When it is desired to obtain a laminated structure of the iGe layer 6, it is preferable to manufacture the iGe layer 6 by the following steps.
【００６０】即ち、ＳＩＭＯＸ工程を用いて一層のＳＯ
Ｉ基板を準備し、そのＳＯＩ基板表面のＳｉ層に予め酸
化膜を形成して、ＳｉＧｅ層を有する基板とウェハの張
り合せ技術により接合する。ウェハの張り合せ技術によ
れば、比較的低温での接合が可能なため、Ｇｅの拡散を
抑制することができ、元々のＳｉＧｅ層中のＧｅ濃度を
大きく変えることなく図３に示される積層構造を得るこ
とができる。 （実施例２）図４は、本発明の第２の実施例に係る半導
体装置を示す断面図である。That is, one layer of SOX is formed by using the SIMOX process.
An I substrate is prepared, an oxide film is previously formed on a Si layer on the surface of the SOI substrate, and the substrate having the SiGe layer is bonded to a wafer by a bonding technique. According to the wafer bonding technique, bonding at a relatively low temperature is possible, so that the diffusion of Ge can be suppressed, and the stacked structure shown in FIG. 3 can be obtained without largely changing the Ge concentration in the original SiGe layer. Can be obtained. (Embodiment 2) FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【００６１】尚、図１の実施例における半導体装置と対
応する部分には同一符号を付し、その詳細な説明は省略
する。The parts corresponding to those of the semiconductor device in the embodiment of FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
【００６２】この実施例では、Ｓｉ層５の上に更に圧縮
歪を有するＳｉＧｅ層１００（以下、圧縮歪ＳｉＧｅ層
と称する。）を形成し、この層をチャネル層として利用
するゲート構造を、ゲート絶縁層１０１及びゲート電極
１０２を形成して構成したものである。ソース領域２２
及びドレイン領域２３は、チャンネル層である圧縮歪Ｓ
ｉＧｅ層１００に隣接するよう形成されている。In this embodiment, an SiGe layer 100 having a compressive strain (hereinafter referred to as a compressively strained SiGe layer) is further formed on the Si layer 5, and a gate structure using this layer as a channel layer is referred to as a gate structure. It is formed by forming an insulating layer 101 and a gate electrode 102. Source area 22
And the drain region 23 has a compressive strain S which is a channel layer.
It is formed so as to be adjacent to the iGe layer 100.
【００６３】このような構成にすることで、一層目のＳ
ＯＩ構造上にも高速動作を必要とする半導体素子が形成
可能となる。また、この形態で一層目のＳＯＩ構造上に
高速動作を必要とする半導体素子を形成する場合は、歪
Ｓｉ層７の形成を省略して緩和ＳｉＧｅ層６により信頼
性及び安定性の要求されるメモリ素子等を形成しても良
い。 （実施例３）図５は、本発明の第３の実施例に係る半導
体装置を示す断面図である。With such a configuration, the first S
A semiconductor element requiring high-speed operation can also be formed on the OI structure. In the case where a semiconductor element requiring high-speed operation is formed on the first SOI structure in this mode, the formation of the strained Si layer 7 is omitted, and the relaxed SiGe layer 6 requires reliability and stability. A memory element or the like may be formed. (Embodiment 3) FIG. 5 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【００６４】尚、図１の実施例における半導体装置と対
応する部分には同一符号を付し、その詳細な説明は省略
する。The parts corresponding to those of the semiconductor device in the embodiment of FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
【００６５】この実施例では、絶縁層３より上に形成さ
れている二層のＳＯＩ構造が、緩和ＳｉＧｅ層２００及
び緩和ＳｉＧｅ層２０１で形成されている。緩和ＳｉＧ
ｅ層２０１上には引っ張り歪みを有する歪Ｓｉ層７が形
成され、この層がチャネル層として利用できるように、
ゲート絶縁層１６とゲート電極１７が形成されているこ
と等は第１の実施例と同様である。In this embodiment, the two-layer SOI structure formed above the insulating layer 3 is formed by the relaxed SiGe layer 200 and the relaxed SiGe layer 201. Relaxed SiG
A strained Si layer 7 having a tensile strain is formed on the e layer 201, and this layer can be used as a channel layer.
The formation of the gate insulating layer 16 and the gate electrode 17 is the same as in the first embodiment.
【００６６】上述の構成を得るためには、図２により説
明した製造方法における歪ＳｉＧｅ層２の厚さを、酸素
イオン注入の際のダメージ・ピーク及び濃度ピークの深
さが共にＳｉ基板１との界面を上回らないように設定す
ればよい。 （実施例４）図６は、本発明の半導体装置に用いる図１
乃至図３で説明された基板とは別の基板を示す断面図で
ある。In order to obtain the above configuration, the thickness of the strained SiGe layer 2 in the manufacturing method described with reference to FIG. May be set so as not to exceed the interface. (Embodiment 4) FIG. 6 is a cross-sectional view of FIG.
FIG. 4 is a cross-sectional view illustrating a substrate different from the substrate described in FIGS.
【００６７】尚、図１の実施例における半導体装置と対
応する部分には同一符号を付し、その詳細な説明は省略
する。Parts corresponding to those of the semiconductor device in the embodiment of FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
【００６８】図６では、図３の絶縁層４上の緩和ＳｉＧ
ｅ層６とＳｉ層５の上下が逆になった構造を示してい
る。即ち、Ｓｉ層７、ＳｉＯ２層（絶縁層４）、緩和Ｓ
ｉＧｅ層６、ＳｉＯ２層（絶縁層３）、Ｓｉ基板１の順
に積層された二層のＳＯＩ構造が示されている。このよ
うな二層のＳＯＩ構造を得るには、図２で用意したウェ
ハの歪ＳｉＧｅ層２の表面に、更にＳｉ層を上述のＭＢ
Ｅ及びＣＶＤ等の手法で連続成長させたウェハを用いる
ことが必要である。In FIG. 6, the relaxed SiG on the insulating layer 4 of FIG.
The structure in which the e layer 6 and the Si layer 5 are upside down is shown. That is, the Si layer 7, the SiO2 layer (insulating layer 4), the relaxed S
2 shows a two-layer SOI structure in which an iGe layer 6, a SiO2 layer (insulating layer 3), and a Si substrate 1 are stacked in this order. To obtain such a two-layer SOI structure, a Si layer is further added to the surface of the strained SiGe layer 2 of the wafer prepared in FIG.
It is necessary to use a wafer continuously grown by a technique such as E and CVD.
【００６９】また、その後のイオン注入工程では、高温
アニール後に緩和ＳｉＧｅ層６に接した絶縁層４が形成
されるように、歪ＳｉＧｅ層２上のＳｉ層中の適切な位
置にダメージ・ピークを形成するよう制御する必要があ
る。しかしながら、その他のイオン注入時の濃度ピーク
の位置や、高温アニール等の処理については、上記図１
の実施例で説明したものと同様に行えば良い。In the subsequent ion implantation step, a damage peak is formed at an appropriate position in the Si layer on the strained SiGe layer 2 so that the insulating layer 4 in contact with the relaxed SiGe layer 6 is formed after the high-temperature annealing. It needs to be controlled to form. However, regarding the position of the concentration peak at the time of ion implantation and the processing such as high-temperature annealing, FIG.
What is necessary is just to carry out similarly to what was demonstrated in the Example of this.
【００７０】この図６に示される二層のＳＯＩ構造を用
いる場合には、絶縁層３及び絶縁層４の間にある緩和Ｓ
ｉＧｅ層６の一部を選択的に露出させ、その表面に歪Ｓ
ｉ層を積層して高速動作素子を形成すればよく、一方高
信頼性素子はＳｉ層７を利用して作り込めば良い。When the two-layer SOI structure shown in FIG. 6 is used, the relaxed S between insulating layer 3 and insulating layer 4 is used.
A part of the iGe layer 6 is selectively exposed, and a strain S
A high-speed operation element may be formed by laminating i-layers, while a highly reliable element may be formed using the Si layer 7.
【００７１】[0071]
【発明の効果】以上、本発明によれば、ＳＯＩ構造の効
果を損なわずに、元素、組成の異なる連続した二層のＳ
ＯＩ構造が提供できるため、例えば、歪Ｓｉ系の高速論
理演算素子と、高信頼性が要求されるＤＲＡＭ等の素子
とを同一基板上の任意の位置に作り分けることが可能で
ある。従って、従来よりも、素子特性の劣化を抑え、低
消費電力化、高集積化が可能となり、半導体素子の高性
能化が実現できる。As described above, according to the present invention, two consecutive layers of S and S having different elements and compositions can be used without impairing the effect of the SOI structure.
Since an OI structure can be provided, for example, a strained Si-based high-speed logical operation element and an element such as a DRAM requiring high reliability can be separately formed at an arbitrary position on the same substrate. Therefore, deterioration of device characteristics is suppressed, power consumption is reduced, and integration is increased, and higher performance of the semiconductor device can be realized.
【図１】本発明の第１の実施例に半導体基板の部分断面
図。FIG. 1 is a partial cross-sectional view of a semiconductor substrate according to a first embodiment of the present invention.
【図２】本発明の半導体装置の製造方法の工程を示す部
分断面図。FIG. 2 is a partial cross-sectional view showing steps of a method for manufacturing a semiconductor device of the present invention.
【図３】本発明の半導体装置の製造方法の工程を示す部
分断面図。FIG. 3 is a partial cross-sectional view showing steps of a method for manufacturing a semiconductor device according to the present invention.
【図４】本発明の第２の実施例に係る半導体装置の部分
断面図。FIG. 4 is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
【図５】本発明の第３の実施例に係る半導体装置の部分
断面図。FIG. 5 is a partial sectional view of a semiconductor device according to a third embodiment of the present invention.
【図６】本発明の半導体装置に使用される基板の部分断
面図。FIG. 6 is a partial cross-sectional view of a substrate used in the semiconductor device of the present invention.
１・・・Ｓｉ基板 ２・・・歪ＳｉＧｅ層 ３，４，３４，３５・・・絶縁層 ４・・・絶縁層 ５・・・緩和Ｓｉ層 ６・・・緩和ＳｉＧｅ層 ７・・・歪Ｓｉ層 ８，１０・・・Ｐ型ウェル領域 ９，１１・・・Ｎ型ウェル領域 １２，１４，２０，２２・・・ソース領域 １３，１５，２１，２３・・・ドレイン領域 １６，１８，２４，２６・・・ゲート絶縁層 １７，１９，２５，２７・・・ゲート電極層 ２８〜３３・・・電極 DESCRIPTION OF SYMBOLS 1 ... Si board | substrate 2 ... Strained SiGe layer 3,4,34,35 ... Insulating layer 4 ... Insulating layer 5 ... Relaxed Si layer 6 ... Relaxed SiGe layer 7 ... Strain Si layer 8, 10, P-type well region 9, 11, N-type well region 12, 14, 20, 22 ... source region 13, 15, 21, 23 ... drain region 16, 18, 24, 26: gate insulating layer 17, 19, 25, 27: gate electrode layer 28 to 33: electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 水野 智久 神奈川県横浜市磯子区新杉田町８番地 株 式会社東芝横浜事業所内 (72)発明者 畠山 哲夫 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 (72)発明者 杉山 直治 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 (72)発明者 高木 信一 神奈川県横浜市磯子区新杉田町８番地 株 式会社東芝横浜事業所内 Ｆターム(参考） 5F110 AA04 AA09 BB04 BB06 CC02 DD01 DD02 DD04 DD05 DD13 EE09 EE45 FF02 FF23 FF29 GG01 GG02 GG12 GG19 GG25 GG32 GG42 GG44 NN78 QQ17 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tomohisa Mizuno 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Works Co., Ltd. In the Toshiba R & D Center (72) Inventor Naoji Sugiyama 1 in Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture 8F Town Toshiba Yokohama Office F Term (Reference) 5F110 AA04 AA09 BB04 BB06 CC02 DD01 DD02 DD04 DD05 DD13 EE09 EE45 FF02 FF23 FF29 GG01 GG02 GG12 GG19 GG25 GG32 GG42 GG44 NN78 QQ17
Claims (13)
て形成された第１絶縁層と、 この第１絶縁層上に位置させられた第１半導体層と、 この第１半導体層上に選択的に形成された第２絶縁層
と、 前記第１半導体層とは異なる組成で前記第２絶縁層上に
位置させられた第２半導体層と、 前記第１半導体層とは異なる組成で前記第１半導体層上
に積層して形成された第３半導体層とを備え、 前記第２半導体層がチャネル領域として使用された電界
効果トランジスタ及び第３半導体層がチャネル領域とし
て使用された電界効果トランジスタとにより集積回路が
構成されていることを特徴とする半導体装置。A semiconductor substrate having one main surface; a first insulating layer formed inside the semiconductor substrate so as to be substantially parallel to and separated from the one main surface; and a first insulating layer positioned on the first insulating layer. A first semiconductor layer, a second insulating layer selectively formed on the first semiconductor layer, and a second insulating layer positioned on the second insulating layer with a composition different from that of the first semiconductor layer. A field effect transistor comprising: a semiconductor layer; and a third semiconductor layer formed by stacking on the first semiconductor layer with a composition different from that of the first semiconductor layer, wherein the second semiconductor layer is used as a channel region. And a field effect transistor in which the third semiconductor layer is used as a channel region to form an integrated circuit.
て形成された第１絶縁層と、 この第１絶縁層上に位置させられた第１半導体層と、こ
の第１半導体層上に選択的に形成された第２絶縁層と、 前記第１半導体層とは異なる組成で前記第２絶縁層上に
位置させられた第２半導体層と、 この第２半導体層とは異なる組成で前記第２半導体層上
に積層形成された第４半導体層とを備え、 前記第１半導体層がチャネル領域として使用された電界
効果トランジスタ及び第４半導体層がチャネル領域とし
て使用された電界効果トランジスタとにより集積回路が
構成されていることを特徴とする半導体装置。2. A semiconductor substrate having one main surface; a first insulating layer formed inside the semiconductor substrate so as to be substantially parallel to and separated from the one main surface; The first semiconductor layer, a second insulating layer selectively formed on the first semiconductor layer, and a second insulating layer positioned on the second insulating layer with a composition different from that of the first semiconductor layer. A field effect transistor, comprising: a semiconductor layer; and a fourth semiconductor layer laminated on the second semiconductor layer with a composition different from that of the second semiconductor layer, wherein the first semiconductor layer is used as a channel region. 4. A semiconductor device, wherein an integrated circuit is formed by four field effect transistors in which a semiconductor layer is used as a channel region.
て形成された第１絶縁層と、 この第１絶縁層上に位置させられた第１半導体層と、 この第１半導体層上に選択的に形成された第２絶縁層
と、 前記第１半導体層とは異なる組成で前記第２絶縁層上に
位置させられた第２半導体層と、 前記第１半導体層とは異なる組成で前記第１半導体層上
に積層して形成された第３半導体層と、 前記第２半導体層とは異なる組成で前記第２半導体層上
に積層形成された第４半導体層とを備え、 前記第３半導体層がチャネル領域として使用された電界
効果トランジスタ及び第４半導体層がチャネル領域とし
て使用された電界効果トランジスタとにより集積回路が
構成されていることを特徴とする半導体装置。3. A semiconductor substrate having one main surface; a first insulating layer formed inside the semiconductor substrate so as to be substantially parallel to and separated from the one main surface; A first semiconductor layer, a second insulating layer selectively formed on the first semiconductor layer, and a second insulating layer positioned on the second insulating layer with a composition different from that of the first semiconductor layer. A semiconductor layer; a third semiconductor layer formed by being stacked on the first semiconductor layer with a composition different from the first semiconductor layer; and a third semiconductor layer having a composition different from the second semiconductor layer on the second semiconductor layer. A fourth semiconductor layer formed in a stacked manner, wherein an integrated circuit is formed by a field effect transistor in which the third semiconductor layer is used as a channel region and a field effect transistor in which the fourth semiconductor layer is used as a channel region A semiconductor device.
は異なる格子定数を有し、圧縮歪みを有することを特徴
とする請求項１又は請求項３記載の半導体装置。4. The semiconductor device according to claim 1, wherein the third semiconductor layer has a lattice constant different from that of the first semiconductor layer and has a compressive strain.
は異なる格子定数を有し、引っ張り歪みを有することを
特徴とする請求項２又は請求項３記載の半導体装置。5. The semiconductor device according to claim 2, wherein the fourth semiconductor layer has a lattice constant different from that of the second semiconductor layer and has a tensile strain.
前記第２半導体層はＳｉＧｅ混晶層であることを特徴と
する請求項１乃至請求項５記載の半導体装置。6. The first semiconductor layer is a single-crystal Si layer,
The semiconductor device according to claim 1, wherein the second semiconductor layer is a SiGe mixed crystal layer.
Ｃ、Ｇｅ、Ｇａ、Ｉｎ、Ａｌ、Ｚｎ、Ｓｅから選ばれた
少なくとも一つの材料で構成される結晶または混晶層で
あることを特徴とする請求項１乃至請求項５記載の半導
体装置。7. The semiconductor device according to claim 1, wherein the first semiconductor layer comprises Si, B, As, P,
6. The semiconductor device according to claim 1, wherein the semiconductor device is a crystal or mixed crystal layer made of at least one material selected from C, Ge, Ga, In, Al, Zn, and Se.
ＳｉＣ、Ｇｅ、ＳｉＧｅ、サファイア、有機ガラス、無
機ガラス、プラスチックから選ばれた少なくとも一つの
材料で構成される基板と積層されていることを特徴とす
る請求項１乃至請求項５記載の半導体装置。8. The semiconductor substrate according to claim 1, wherein said semiconductor substrate is GaAs, ZnSe,
6. The semiconductor device according to claim 1, wherein the semiconductor device is laminated on a substrate made of at least one material selected from SiC, Ge, SiGe, sapphire, organic glass, inorganic glass, and plastic.
は、ウェハーの張り合わせ技術により一体化されている
ことを特徴とする請求項１乃至請求項５記載の半導体装
置。9. The semiconductor device according to claim 1, wherein said second insulating layer and said second semiconductor layer are integrated by a wafer bonding technique.
下であることを特徴とする請求項１乃至請求項６記載の
半導体装置。10. The semiconductor device according to claim 1, wherein said first semiconductor layer has a thickness of 100 nm or less.
と異なる組成の第１半導体層を形成する工程と、 イオン注入によるダメージ・ピークと濃度ピークが前記
半導体基板内部において異なる深さとなる条件で、前記
半導体基板内部に前記一主面側から酸素をイオン注入す
る工程と、前記半導体基板を加熱し、前記半導体基板内
部に注入された酸素と半導体基板構成材料との酸化物を
形成することにより、前記半導体基板内部のより深い位
置に第１絶縁層を、その第１絶縁層よりも浅い位置に第
２絶縁層を互いに離間させて形成する工程とを具備する
ことを特徴とする半導体装置の製造方法。11. A step of forming a first semiconductor layer having a composition different from that of the semiconductor substrate on one principal surface of the semiconductor substrate, and a condition that damage peaks and concentration peaks due to ion implantation have different depths inside the semiconductor substrate. A step of ion-implanting oxygen into the semiconductor substrate from the one main surface side, and heating the semiconductor substrate to form an oxide of the oxygen implanted inside the semiconductor substrate and a semiconductor substrate constituent material. Forming a first insulating layer at a deeper position inside the semiconductor substrate and forming a second insulating layer at a position shallower than the first insulating layer by separating them from each other. Manufacturing method.
に、前記半導体基板とは異なる組成の第２半導体層を、
前記半導体基板の一部に積層して形成する工程を更に備
えることを特徴とする請求項１１記載の半導体装置の製
造方法。12. A second semiconductor layer having a composition different from that of the semiconductor substrate on a part of the semiconductor substrate on the first insulating layer.
The method of manufacturing a semiconductor device according to claim 11, further comprising a step of laminating the semiconductor device on a part of the semiconductor substrate.
半導体層を前記第１半導体層上に積層して形成する工程
を更に備えることを特徴とする請求項１１または請求項
１２記載の半導体装置の製造方法。13. A third semiconductor having a composition different from that of the first semiconductor layer.
The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a semiconductor layer by laminating the semiconductor layer on the first semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000065911A JP3512701B2 (en) | 2000-03-10 | 2000-03-10 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000065911A JP3512701B2 (en) | 2000-03-10 | 2000-03-10 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001257351A true JP2001257351A (en) | 2001-09-21 |
| JP3512701B2 JP3512701B2 (en) | 2004-03-31 |
Family
ID=18585359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000065911A Expired - Fee Related JP3512701B2 (en) | 2000-03-10 | 2000-03-10 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3512701B2 (en) |
Cited By (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849883B2 (en) | 2002-09-02 | 2005-02-01 | Oki Electric Industry Co., Ltd. | Strained SOI MOSFET device and method of fabricating same |
| WO2005013375A1 (en) * | 2003-08-05 | 2005-02-10 | Fujitsu Limited | Semiconductor device and its manufacturing method |
| JP2005286341A (en) * | 2004-03-30 | 2005-10-13 | Samsung Electronics Co Ltd | Low-noise and high-performance lsi element, layout, and its manufacturing method |
| WO2005112097A1 (en) * | 2004-05-13 | 2005-11-24 | Fujitsu Limited | Semiconductor device and method for fabricating the same, semiconductor substrate and method for producing the same |
| JP2006032785A (en) * | 2004-07-20 | 2006-02-02 | Sumco Corp | Method for manufacturing soi substrate and soi substrate |
| JP2006041516A (en) * | 2004-07-23 | 2006-02-09 | Internatl Business Mach Corp <Ibm> | Patterned strained semiconductor substrate and device |
| JP2006049673A (en) * | 2004-08-06 | 2006-02-16 | Seiko Epson Corp | Semiconductor substrate, manufacturing method thereof, semiconductor device, and manufacturing method thereof |
| JP2006513567A (en) * | 2003-01-08 | 2006-04-20 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor structure and manufacturing method thereof (high performance embedded DRAM technology using strained silicon) |
| JP2007027194A (en) * | 2005-07-12 | 2007-02-01 | Renesas Technology Corp | Semiconductor device |
| JP2008505488A (en) * | 2004-06-30 | 2008-02-21 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Technology for forming substrates having crystalline semiconductor regions with different characteristics |
| JP2008521229A (en) * | 2004-11-18 | 2008-06-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | SOI substrate material and method of forming Si-containing SOI and lower substrate having different orientations |
| JP2009177306A (en) * | 2008-01-22 | 2009-08-06 | Hitachi Ltd | Magnetic logic element |
| JP4751825B2 (en) * | 2004-05-13 | 2011-08-17 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof, semiconductor substrate and manufacturing method thereof |
| US8216951B2 (en) | 2006-09-27 | 2012-07-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
| US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
| US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
| US8344242B2 (en) | 2007-09-07 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-junction solar cells |
| JP2013016789A (en) * | 2011-06-10 | 2013-01-24 | Sumitomo Chemical Co Ltd | Semiconductor device, semiconductor substrate, semiconductor substrate manufacturing method and semiconductor device manufacturing method |
| US8384196B2 (en) | 2008-09-19 | 2013-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
| US8502263B2 (en) | 2006-10-19 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-emitter-based devices with lattice-mismatched semiconductor structures |
| US8624103B2 (en) | 2007-04-09 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
| US8629446B2 (en) | 2009-04-02 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
| US8765510B2 (en) | 2009-01-09 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
| US8822248B2 (en) | 2008-06-03 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial growth of crystalline material |
| US8847279B2 (en) | 2006-09-07 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
| US8878243B2 (en) | 2006-03-24 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
| US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
| US9859381B2 (en) | 2005-05-17 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US9984872B2 (en) | 2008-09-19 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication and structures of crystalline material |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170036966A (en) | 2015-09-24 | 2017-04-04 | 삼성전자주식회사 | Method of fabricating semiconductor device |
-
2000
- 2000-03-10 JP JP2000065911A patent/JP3512701B2/en not_active Expired - Fee Related
Cited By (83)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849883B2 (en) | 2002-09-02 | 2005-02-01 | Oki Electric Industry Co., Ltd. | Strained SOI MOSFET device and method of fabricating same |
| JP2006513567A (en) * | 2003-01-08 | 2006-04-20 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor structure and manufacturing method thereof (high performance embedded DRAM technology using strained silicon) |
| WO2005013375A1 (en) * | 2003-08-05 | 2005-02-10 | Fujitsu Limited | Semiconductor device and its manufacturing method |
| US7449379B2 (en) | 2003-08-05 | 2008-11-11 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
| US9425182B2 (en) | 2004-03-30 | 2016-08-23 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device |
| US8816440B2 (en) | 2004-03-30 | 2014-08-26 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device |
| JP2005286341A (en) * | 2004-03-30 | 2005-10-13 | Samsung Electronics Co Ltd | Low-noise and high-performance lsi element, layout, and its manufacturing method |
| US9899386B2 (en) | 2004-03-30 | 2018-02-20 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device |
| US9093306B2 (en) | 2004-03-30 | 2015-07-28 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device |
| WO2005112129A1 (en) * | 2004-05-13 | 2005-11-24 | Fujitsu Limited | Semiconductor device and process for fabricating same, and process for producing semiconductor substrate |
| WO2005112097A1 (en) * | 2004-05-13 | 2005-11-24 | Fujitsu Limited | Semiconductor device and method for fabricating the same, semiconductor substrate and method for producing the same |
| US7910415B2 (en) | 2004-05-13 | 2011-03-22 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the same, and semiconductor substrate and method of manufacturing the same |
| JP4751825B2 (en) * | 2004-05-13 | 2011-08-17 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof, semiconductor substrate and manufacturing method thereof |
| JP2008505488A (en) * | 2004-06-30 | 2008-02-21 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Technology for forming substrates having crystalline semiconductor regions with different characteristics |
| JP2006032785A (en) * | 2004-07-20 | 2006-02-02 | Sumco Corp | Method for manufacturing soi substrate and soi substrate |
| US9053970B2 (en) | 2004-07-23 | 2015-06-09 | International Business Machines Corporation | Patterned strained semiconductor substrate and device |
| JP2006041516A (en) * | 2004-07-23 | 2006-02-09 | Internatl Business Mach Corp <Ibm> | Patterned strained semiconductor substrate and device |
| US9515140B2 (en) | 2004-07-23 | 2016-12-06 | Globalfoundries Inc. | Patterned strained semiconductor substrate and device |
| JP2006049673A (en) * | 2004-08-06 | 2006-02-16 | Seiko Epson Corp | Semiconductor substrate, manufacturing method thereof, semiconductor device, and manufacturing method thereof |
| JP4706204B2 (en) * | 2004-08-06 | 2011-06-22 | セイコーエプソン株式会社 | Semiconductor substrate manufacturing method and semiconductor device manufacturing method |
| JP2008521229A (en) * | 2004-11-18 | 2008-06-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | SOI substrate material and method of forming Si-containing SOI and lower substrate having different orientations |
| US9431243B2 (en) | 2005-05-17 | 2016-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US10522629B2 (en) | 2005-05-17 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8987028B2 (en) | 2005-05-17 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US9859381B2 (en) | 2005-05-17 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US9219112B2 (en) | 2005-05-17 | 2015-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8519436B2 (en) | 2005-05-17 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US11251272B2 (en) | 2005-05-17 | 2022-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8796734B2 (en) | 2005-05-17 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| US8629477B2 (en) | 2005-05-17 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
| JP2007027194A (en) * | 2005-07-12 | 2007-02-01 | Renesas Technology Corp | Semiconductor device |
| US8878243B2 (en) | 2006-03-24 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| US10074536B2 (en) | 2006-03-24 | 2018-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
| US9818819B2 (en) | 2006-09-07 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
| US8847279B2 (en) | 2006-09-07 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
| US9318325B2 (en) | 2006-09-07 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
| US8629047B2 (en) | 2006-09-27 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
| US9559712B2 (en) | 2006-09-27 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
| US8860160B2 (en) | 2006-09-27 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
| US9105522B2 (en) | 2006-09-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
| US8216951B2 (en) | 2006-09-27 | 2012-07-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
| US8502263B2 (en) | 2006-10-19 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-emitter-based devices with lattice-mismatched semiconductor structures |
| US10468551B2 (en) | 2006-10-19 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-emitter-based devices with lattice-mismatched semiconductor structures |
| US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
| US9449868B2 (en) | 2007-04-09 | 2016-09-20 | Taiwan Semiconductor Manufacutring Company, Ltd. | Methods of forming semiconductor diodes by aspect ratio trapping with coalesced films |
| US10680126B2 (en) | 2007-04-09 | 2020-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
| US9040331B2 (en) | 2007-04-09 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US9853176B2 (en) | 2007-04-09 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
| US9853118B2 (en) | 2007-04-09 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US9231073B2 (en) | 2007-04-09 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US9543472B2 (en) | 2007-04-09 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US8624103B2 (en) | 2007-04-09 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
| US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
| US9780190B2 (en) | 2007-06-15 | 2017-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
| US8344242B2 (en) | 2007-09-07 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-junction solar cells |
| US10002981B2 (en) | 2007-09-07 | 2018-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-junction solar cells |
| JP2009177306A (en) * | 2008-01-22 | 2009-08-06 | Hitachi Ltd | Magnetic logic element |
| US9365949B2 (en) | 2008-06-03 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial growth of crystalline material |
| US8822248B2 (en) | 2008-06-03 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial growth of crystalline material |
| US10961639B2 (en) | 2008-06-03 | 2021-03-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial growth of crystalline material |
| US9356103B2 (en) | 2008-07-01 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US8629045B2 (en) | 2008-07-01 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US8994070B2 (en) | 2008-07-01 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US9640395B2 (en) | 2008-07-01 | 2017-05-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
| US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
| US9607846B2 (en) | 2008-07-15 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
| US9287128B2 (en) | 2008-07-15 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
| US9934967B2 (en) | 2008-09-19 | 2018-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation of devices by epitaxial layer overgrowth |
| US8384196B2 (en) | 2008-09-19 | 2013-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
| US9984872B2 (en) | 2008-09-19 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication and structures of crystalline material |
| US8809106B2 (en) | 2008-09-24 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for semiconductor sensor structures with reduced dislocation defect densities |
| US9105549B2 (en) | 2008-09-24 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
| US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
| US9455299B2 (en) | 2008-09-24 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for semiconductor sensor structures with reduced dislocation defect densities |
| US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
| US9029908B2 (en) | 2009-01-09 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
| US8765510B2 (en) | 2009-01-09 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
| US9576951B2 (en) | 2009-04-02 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
| US9299562B2 (en) | 2009-04-02 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
| US8629446B2 (en) | 2009-04-02 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
| JP2013016789A (en) * | 2011-06-10 | 2013-01-24 | Sumitomo Chemical Co Ltd | Semiconductor device, semiconductor substrate, semiconductor substrate manufacturing method and semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3512701B2 (en) | 2004-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001257351A (en) | Semiconductor device and its manufacturing method | |
| US6709909B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP3376211B2 (en) | Semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device | |
| JP4678877B2 (en) | Silicon devices on Si: C-OI and SGOI and manufacturing methods | |
| CN100378918C (en) | Insulating layer coating substrate for strain semiconductor and its making process | |
| US8319285B2 (en) | Silicon-on-insulator chip having multiple crystal orientations | |
| US6717213B2 (en) | Creation of high mobility channels in thin-body SOI devices | |
| US7528056B2 (en) | Low-cost strained SOI substrate for high-performance CMOS technology | |
| US7498229B1 (en) | Transistor and in-situ fabrication process | |
| US20020008289A1 (en) | Mosfet with strained channel layer | |
| US7018882B2 (en) | Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon | |
| JP2009105427A (en) | Method of manufacturing semiconductor substrate | |
| US20060006412A1 (en) | Semiconductor substrate, method of manufacturing the same and semiconductor device | |
| JP2002237590A (en) | Mos field effect transistor | |
| JPH09219524A (en) | Semiconductor device and its manufacture | |
| WO2005122272A1 (en) | Mis field-effect transistor having strained silicon channel layer | |
| TW200539425A (en) | Integrated circuit with strained and non-strained transistors, and method of forming thereof | |
| JP2000031491A (en) | Semiconductor device, its manufacture, semiconductor substrate and its manufacture | |
| JP2001284558A (en) | Laminated wafer, producing method therefor and semiconductor device | |
| US20070166960A1 (en) | Method for forming a strained si-channel in a mosfet structure | |
| JPH1092947A (en) | Semiconductor device and manufacture thereof | |
| JP4296726B2 (en) | Manufacturing method of semiconductor substrate and manufacturing method of field effect transistor | |
| JPH11163343A (en) | Semiconductor device and its manufacture | |
| JP4322706B2 (en) | Manufacturing method of semiconductor device | |
| JP2004055943A (en) | Semiconductor device and manufacturing method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20040106 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20040107 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080116 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090116 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100116 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110116 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120116 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130116 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |