JP2001253800A - Thin sapphire substrate - Google Patents
Thin sapphire substrateInfo
- Publication number
- JP2001253800A JP2001253800A JP2000069422A JP2000069422A JP2001253800A JP 2001253800 A JP2001253800 A JP 2001253800A JP 2000069422 A JP2000069422 A JP 2000069422A JP 2000069422 A JP2000069422 A JP 2000069422A JP 2001253800 A JP2001253800 A JP 2001253800A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- sapphire substrate
- thickness
- semiconductor
- growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は単結晶サファイヤ基
板に関し、特に、半導体をエピタキシャル成長させる際
に用いる基板材料としての薄板円盤状のサファイヤ基板
に関する。The present invention relates to a single-crystal sapphire substrate, and more particularly to a thin disk-shaped sapphire substrate used as a substrate material for epitaxially growing a semiconductor.
【０００２】[0002]
【従来の技術】従来、半導体をエピタキシャル成長させ
る基板材料としては様々なものが案出されている。例え
ば、サファイヤ（Ａl２Ｏ３）、スピネル、ニオブ酸リ
チウム、ガリウム酸ネオジウム、シリコン（Ｓi）、６
Ｈ−ＳiＣ、ＺnＯ、ＧaＡs等が挙げられる。このうち、
青色発光素材として近年特に注目されているＧaＮに代
表されるIII族窒化物半導体や窒化ガリウム系化合物半
導体等（以降においてＧaＮ等と称することとする）を
結晶成長させる基板として、もっとも広く用いられてい
る基板材料は、前記の単結晶サファイヤ基板である。2. Description of the Related Art Conventionally, various materials have been proposed as a substrate material for epitaxially growing a semiconductor. For example, sapphire (Al 2 O 3 ), spinel, lithium niobate, neodymium gallate, silicon (Si), 6
H-SiC, ZnO, GaAs and the like can be mentioned. this house,
It is most widely used as a substrate for crystal growth of a group III nitride semiconductor represented by GaN, a gallium nitride-based compound semiconductor, or the like (hereinafter referred to as GaN or the like) represented by GaN, which has recently attracted particular attention as a blue light emitting material. The substrate material used is the single crystal sapphire substrate described above.
【０００３】これは、ＧaＮ等の格子定数とサファイヤ
の格子定数が比較的近似しているため、ＧaＮ等をサフ
ァイヤ基板上でエピタキシャル成長させやすく、かつ、
格子定数が近似している成長可能な各種基板の中ではも
っとも価格が安いためである。[0003] This is because the lattice constant of GaN or the like is relatively close to the lattice constant of sapphire, and therefore, GaN or the like can be easily epitaxially grown on a sapphire substrate.
This is because the price is the lowest among various types of substrates that can be grown and have similar lattice constants.
【０００４】図９及び図１０は、従来の結晶成長工程で
のサファイヤ基板形状の一例を示す図であり、同図９は
平面図を、同図１０は図９におけるＢ−Ｂ断面の概略を
示している。使用されるサファイヤ基板10は、通常、直
径が２インチ（5.08［cm］）もしくは３インチ（7.62
［cm］）の円盤形状であり、これは半導体を積層させた
後の処理、例えばエッチング、ボンディングなどで使用
する次工程の加工機器でのクランプ等において、常に高
精度が要求されるためで、基板の大きさや形状に関する
事実上の標準仕様が決まっているからである。FIGS. 9 and 10 are views showing an example of the shape of a sapphire substrate in a conventional crystal growth step. FIG. 9 is a plan view, and FIG. Is shown. The sapphire substrate 10 used is typically 2 inches (5.08 cm) in diameter or 3 inches (7.62 cm).
[Cm]), because high precision is always required in the processing after lamination of semiconductors, for example, clamping in processing equipment in the next process used for etching, bonding, etc. This is because the actual standard specifications regarding the size and shape of the substrate are determined.
【０００５】また、図１０の側断面模式図に示すよう
に、サファイヤ基板10は少なからず中心凹球面状に湾曲
している。このサファイヤ基板10は、厚さＨ１が300
［μm］〜500［μm］であるのに対して、その湾曲の度
合い、すなわち、中心部の図に示す凹み深さＤ１は平均
5［μm］〜10［μm］程度である場合が多い。従来の一
般的な成形加工の技術水準では、厚さＨ１は300［μm］
が限界とされていた。Further, as shown in the schematic side sectional view of FIG. 10, the sapphire substrate 10 is curved into a spherical shape with a central concave portion. This sapphire substrate 10 has a thickness H1 of 300
[Μm] to 500 [μm], the degree of curvature, that is, the dent depth D1 shown in the figure at the center is the average.
It is often about 5 [μm] to 10 [μm]. In the conventional general molding technology, the thickness H1 is 300 [μm].
Was the limit.
【０００６】これは、サファイヤ基板10を平滑に研削研
磨していく研磨工程において、極薄厚に成形する際に
は、平行度が得られないという加工精度的な問題があ
り、さらに結晶素材内部の歪み及び外部からの加工歪み
などにより、板状表面が自然に湾曲形状となってくるた
めに生じる問題である。なお、サファイヤ基板10では、
前記厚さＨ１程度の仕上げでは板状表面が上下面共に比
較的精度よく研磨され、何れの部位においてもほぼ均一
の厚さを有するので、図に示す周辺部の浮き上がり高さ
Ｄ２も前記凹み深さＤ１とほぼ同等の5［μm］〜10［μ
m］程度である場合が多い。[0006] In the polishing step of grinding and polishing the sapphire substrate 10 smoothly, there is a problem in processing accuracy that parallelism cannot be obtained when forming the sapphire substrate 10 to an extremely thin thickness. This is a problem that occurs because the plate-shaped surface naturally becomes curved due to distortion and processing distortion from the outside. In the sapphire substrate 10,
In the finishing with the thickness H1, the plate-like surface is polished with relatively high accuracy on both the upper and lower surfaces, and the thickness is almost uniform at any part. 5 [μm] to 10 [μ]
m].
【０００７】次に、従来のサファイヤ基板10を用いてＧ
ａＮ等の半導体をエピタキシャル成長させた後の基板形
状について説明する。図１１は、前記図９及び図１０で
示した従来のサファイヤ基板10を用いて、ＧａＮを結晶
成長させた場合の図１０と同一方向から見たサファイヤ
基板10断面を示した模式図である。Next, using a conventional sapphire substrate 10, G
The substrate shape after epitaxially growing a semiconductor such as aN will be described. FIG. 11 is a schematic diagram showing a cross section of the sapphire substrate 10 when the GaN is grown using the conventional sapphire substrate 10 shown in FIGS. 9 and 10 and viewed from the same direction as FIG.
【０００８】同図において記号12は、サファイヤ基板10
の結晶成長面13表面上に結晶成長させた半導体層（Ｇａ
Ｎ層）を示し、この半導体層12とサファイヤ基板10とを
併せて成長後基板11と称することとする。In FIG. 1, reference numeral 12 denotes a sapphire substrate 10.
Semiconductor layer (Ga) on the crystal growth surface 13 of
N layer), and the semiconductor layer 12 and the sapphire substrate 10 are collectively referred to as a substrate 11 after growth.
【０００９】同図から明らかなように、成長後基板11
は、結晶成長させる前と逆向きの「反り返り」現象が発
生する。結晶成長面13に付加された半導体層12の厚さＨ
２は、ほぼ2［μm］〜5［μm］程度であるが、これによ
り基板形状は成膜後に大きく変化し、逆に中心部の浮き
上がり高さＤ３は20［μm］〜30［μm］程度にもなる。As is apparent from FIG.
In the case, a "warp" phenomenon occurs in a direction opposite to that before crystal growth. The thickness H of the semiconductor layer 12 added to the crystal growth surface 13
2 is about 2 [μm] to 5 [μm], whereby the substrate shape changes greatly after film formation, and conversely, the floating height D3 at the center is about 20 [μm] to 30 [μm]. Also.
【００１０】この反り返りの現象は、熱膨張率の違いに
よる歪みとサファイヤ基板の加工歪みに起因すると考え
られる。Ａl２Ｏ３（サファイヤ）のｃ軸に平行な方向
の熱膨張係数は、室温からエピタキシャル成長させる温
度である1000℃程度の区間では、ほぼ一定の5.3×10-6
［Ｋ-1］であり、一方、ＧａＮの熱膨張係数は、700℃
程度を臨界点として大きさが変化し、臨界点より高い温
度では7.75×10-6［Ｋ-1］、低い温度では3.17×10
-6［Ｋ-1］である。また、サファイヤ基板10の結晶成長
面13の反対の面（裏面）14は研削された素材面であり、
結晶成長面13と裏面14とは表面応力が大きく異なる。It is considered that this warping phenomenon is caused by distortion due to the difference in thermal expansion coefficient and processing distortion of the sapphire substrate. The coefficient of thermal expansion of Al 2 O 3 (sapphire) in the direction parallel to the c-axis is almost constant at 5.3 × 10 −6 in the section from room temperature to about 1000 ° C., which is the temperature for epitaxial growth.
[K −1 ], while the thermal expansion coefficient of GaN is 700 ° C.
The size changes with the degree as a critical point, and 7.75 × 10 -6 [K -1 ] at a temperature higher than the critical point and 3.17 × 10 at a lower temperature.
-6 [K -1 ]. The surface (back surface) 14 opposite to the crystal growth surface 13 of the sapphire substrate 10 is a ground material surface,
The crystal growth surface 13 and the back surface 14 have significantly different surface stresses.
【００１１】従って、ＧａＮの熱膨張係数の断続的な変
化、ＧａＮとＡl２Ｏ３との熱膨張係数の差、及び結晶
成長面13と裏面14との間の加工歪みにより、成長後基板
11の温度が1000℃程度から室温に降下する過程におい
て、基板に反り返りが発生することが知られていた。Therefore, the intermittent change in the thermal expansion coefficient of GaN, the difference in the thermal expansion coefficient between GaN and Al 2 O 3 , and the processing strain between the crystal growth surface 13 and the back surface 14 cause the growth of the substrate after growth.
It was known that the substrate was warped in the process of dropping the temperature of 11 from about 1000 ° C. to room temperature.
【００１２】このように従来では、前記湾曲形状のサフ
ァイヤ基板10を用いて、ＧａＮ系のIII族窒化物半導体
等をエピタキシャル成長させ、これにより青色発光素子
等の有用な半導体を得ていた。As described above, conventionally, a GaN-based group III nitride semiconductor or the like is epitaxially grown using the curved sapphire substrate 10, thereby obtaining a useful semiconductor such as a blue light emitting device.
【００１３】[0013]
【発明が解決しようとする課題】しかしながら、従来の
技術では以下の問題点があった。一般的に成長後基板11
は、その後、発光素子チップなどとして使用するため、
サファイヤ基板10の裏面14を研削して、その厚さを100
［μm］程度にまで二次加工研削する。この時、裏面14
の研削方法にもよるが、反り返りが発生した成長後基板
11の裏面を研削する際には、成長後基板11を一様に保持
することが非常に困難であるため、加工する際に保持部
分で半導体層12を傷つけてしまい、製品品質が著しく低
下してしまうという潜在的な問題点があった。However, the prior art has the following problems. Generally after growth substrate 11
After that, for use as a light emitting element chip, etc.
Grind the back surface 14 of the sapphire substrate 10 and reduce its thickness to 100
Secondary processing grinding to about [μm]. At this time, the back 14
Depends on the grinding method of the substrate
When grinding the back surface of 11, it is very difficult to hold the substrate 11 uniformly after growth, so that the semiconductor layer 12 is damaged at the holding portion during processing, and the product quality is significantly reduced. There was a potential problem that it would.
【００１４】また、成長後基板11は、その後、ペレタイ
ズなどの工程を経て製品となるが、成長後基板11に施す
加工工程数は可能な限り少ない方が好ましいのは言うま
でもない。特に、発光素子として使用する場合は、成長
後基板11を0.3［mm］×0.3［mm］程度の微少チップに分
離切断する必要があるが、この際、裏面14側に縦横0.3
［mm］間隔の溝を付けるスクライブ処理が必要であっ
た。After growth, the substrate 11 becomes a product through a process such as pelletizing. It goes without saying that the number of processing steps performed on the substrate 11 after growth is preferably as small as possible. In particular, when the substrate 11 is used as a light emitting element, it is necessary to separate the substrate 11 into small chips of about 0.3 [mm] × 0.3 [mm] after growth.
A scribe process for forming grooves at [mm] intervals was required.
【００１５】すなわち、従来ではサファイヤ基板10自体
が非常に厚く、半導体成長後に中間工程として必ず裏面
14側を研削除去する必要があり、さらに研削後に個々チ
ップに分離切断するためのスクライブ処理が必要とな
る。従って、作業工程において裏面研削などの二次加工
工数が多くなり、また保持部分で二次加工中に基板の半
導体層12を傷つける恐れもあり、取り扱いを誤ると製品
品質が著しく低下してしまう場合があるという大きな問
題点があった。That is, conventionally, the sapphire substrate 10 itself is very thick, and the back surface is always required as an intermediate step after semiconductor growth.
It is necessary to grind and remove the 14 side, and a scribing process for separating and cutting into individual chips after grinding is required. Therefore, the number of man-hours for secondary processing such as back grinding in the work process increases, and there is a possibility that the semiconductor layer 12 of the substrate may be damaged during the secondary processing at the holding portion, and if the handling is incorrect, the product quality is significantly reduced. There was a big problem that there is.
【００１６】本発明は上記問題に鑑みてなされたもので
あって、基板の精度と製品品質を向上することは勿論の
こと、二次研削加工を必要としないサファイヤ基板を提
供することを目的とする。The present invention has been made in view of the above problems, and has as its object to provide a sapphire substrate that does not require secondary grinding, as well as improving the accuracy and product quality of the substrate. I do.
【００１７】[0017]
【課題を解決するための手段】上記目的を達成するため
に、請求項１に係る発明は、半導体をエピタキシャル成
長させる際に用いるサファイヤ基板であって、当該基板
の厚さを、当該基板に積層させる半導体の積層厚さと同
程度の厚さに予め加工したことを特徴とする。According to one aspect of the present invention, there is provided a sapphire substrate used for epitaxially growing a semiconductor, wherein the thickness of the substrate is laminated on the substrate. It is characterized in that it has been processed in advance to a thickness approximately equal to the thickness of the semiconductor layer.
【００１８】この請求項１の発明によれば、エピタキシ
ャル成長させる半導体の最終的な成長厚さ（設計上の厚
さ）を見越して、素材のサファイヤ基板の厚さを予め加
工調整するので、各種の歪みを相殺することができ、結
晶成長後の反り返りを極力少なくできる。According to the first aspect of the present invention, the thickness of the sapphire substrate as a material is preliminarily processed and adjusted in anticipation of the final growth thickness (designed thickness) of the semiconductor to be epitaxially grown. Strain can be offset, and warpage after crystal growth can be minimized.
【００１９】また、請求項２に係る発明は、請求項１に
記載の発明において、直径を5cm以上、13cm以下、厚さ
を20μm以下の円盤形状に加工したことを特徴とする。The invention according to claim 2 is characterized in that, in the invention according to claim 1, the disk is processed into a disk shape having a diameter of 5 cm or more and 13 cm or less and a thickness of 20 μm or less.
【００２０】この請求項２の発明によれば、エピタキシ
ャル成長させる半導体結晶の厚さが数［μm］〜10数
［μm］程度である場合において、結晶成長後のサファ
イヤ基板の反り返りを極力少なくすることができる。According to the second aspect of the present invention, when the thickness of the semiconductor crystal to be epitaxially grown is several [μm] to several tens [μm], the warpage of the sapphire substrate after the crystal growth is minimized. Can be.
【００２１】また、請求項３に係る発明は、半導体をエ
ピタキシャル成長させる際に用いるサファイヤ基板であ
って、当該基板の厚さを10μm以上、150μm以下とし、
さらに、エピタキシャル成長させる面と反対側の面に予
めスクライブ溝を形成したことを特徴とする。According to a third aspect of the present invention, there is provided a sapphire substrate used for epitaxially growing a semiconductor, wherein the thickness of the substrate is 10 μm or more and 150 μm or less,
Furthermore, a scribe groove is formed in advance on a surface opposite to a surface on which epitaxial growth is performed.
【００２２】この請求項３の発明によれば、結晶成長後
のサファイヤ基板裏面の研削工程が不要となり、かつ、
予め格子状にスクライブ溝が形成されているので、ペレ
タイズ工程における基板結晶面に対する損傷を少なくす
ることができる。According to the third aspect of the present invention, the step of grinding the back surface of the sapphire substrate after the crystal growth becomes unnecessary, and
Since the scribe grooves are formed in a lattice shape in advance, damage to the crystal plane of the substrate in the pelletizing step can be reduced.
【００２３】また、請求項４に係る発明は、請求項１、
２または３に記載の発明において、前記半導体が、III
族窒化物半導体もしくは窒化ガリウム系化合物半導体で
あることを特徴とする。Further, the invention according to claim 4 is based on claim 1,
4. The invention according to 2 or 3, wherein the semiconductor is III
It is a group III nitride semiconductor or a gallium nitride compound semiconductor.
【００２４】この請求項４の発明によれば、サファイヤ
（Ａｌ２Ｏ３）と格子定数の近似するIII族窒化物半導
体もしくは窒化ガリウム系化合物半導体をエピタキシャ
ル成長させることができ、基板上に良好な半導体結晶を
得ることができる。According to the fourth aspect of the present invention, a group III nitride semiconductor or a gallium nitride-based compound semiconductor having a lattice constant similar to that of sapphire (Al 2 O 3 ) can be epitaxially grown, and a good semiconductor can be formed on a substrate. Crystals can be obtained.
【００２５】[0025]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照しながら詳細に説明する。 （実施の形態１）図１、図２は、本発明の本実施の形態
に係る薄型サファイヤ基板の一例を示す図であり、図１
は平面図を、同図２は図１のＡ−Ａ断面の概略を示して
いる。サファイヤ基板1は直径２インチ（5.08［cm］）
の円盤形状であり、その厚さＨ１は、ＧａＮ等の半導体
膜を、例えば７［μm］程度に積層（結晶成長）させる
際、その積層（結晶成長）厚みと同一の板厚に加工した
ものを用いるものである。Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIGS. 1 and 2 show an example of a thin sapphire substrate according to this embodiment of the present invention.
2 shows a plan view, and FIG. 2 shows a schematic cross section taken along the line AA in FIG. Sapphire substrate 1 is 2 inches in diameter (5.08 [cm])
The thickness H1 is obtained by processing a semiconductor film of GaN or the like to the same thickness as the thickness of the laminated (crystal growth) when, for example, laminating (crystal growing) about 7 [μm]. Is used.
【００２６】ここでは厚さＨ１＝20［μm］のサファイ
ヤ基板1を用い、半導体膜を約20［μm］とした。また、
サファイヤ基板1の外周部にはオリフラ2が設けられてお
り、結晶軸方向の目印となる基準線的な役割を担うの
と、各種加工機器の位置調整に使用される。Here, the sapphire substrate 1 having a thickness H1 = 20 [μm] was used, and the semiconductor film was set to about 20 [μm]. Also,
An orientation flat 2 is provided on the outer peripheral portion of the sapphire substrate 1, and serves as a reference line serving as a mark in the crystal axis direction, and is used for adjusting the position of various processing equipment.
【００２７】また図２に示すように、サファイヤ基板1
は、研磨加工工程等により、従来のサファイヤ基板10
（図１０参照）とほぼ同様に、薄板基板自体が均等厚な
中心凹球面状に湾曲面を形成している。すなわち、サフ
ァイヤ基板1は、結晶成長面3が中心凹球曲面となってお
り、反対の凸球曲面側の裏面4の浮き上がり高さＤ２と
同程度の凹み深さＤ１が形成された湾曲面形状となって
いる。As shown in FIG. 2, the sapphire substrate 1
The conventional sapphire substrate 10
In substantially the same manner as in FIG. 10, the thin plate substrate itself has a curved surface with a central concave spherical surface having a uniform thickness. That is, the sapphire substrate 1 has a crystal growth surface 3 having a central concave spherical surface, and a concave surface D1 having a concave depth D1 substantially equal to the floating height D2 of the back surface 4 on the opposite convex spherical surface. It has become.
【００２８】次に、この薄型のサファイヤ基板1を用い
て半導体層（ＧａＮ層）をエピタキシャル成長させた場
合での、従来例で示した「反り返り」現象の影響につい
て説明する。図３〜図６は、本実施の形態のサファイヤ
基板1を用いて、半導体層のＧａＮ層5を結晶成長させた
後の基板形状の状態を示す模式図である。Next, the effect of the "warping" phenomenon shown in the conventional example when a semiconductor layer (GaN layer) is epitaxially grown using this thin sapphire substrate 1 will be described. FIG. 3 to FIG. 6 are schematic diagrams showing the state of the substrate after crystal growth of the GaN layer 5 of the semiconductor layer using the sapphire substrate 1 of the present embodiment.
【００２９】図に示すＧａＮ層5は、サファイヤ基板1の
厚さＨ１と同程度の厚さＨ２を有することにより、結晶
成長後、ほぼ平坦なものとなる。サファイヤ基板1の加
工条件により多少のバラツキはあるが、もっとも良好な
結果としては、図３に示すように、成長後基板6は基板
全体として反りの全くない平坦なものとなる。The GaN layer 5 shown in the figure has a thickness H2 substantially equal to the thickness H1 of the sapphire substrate 1, so that it becomes substantially flat after crystal growth. Although there is some variation depending on the processing conditions of the sapphire substrate 1, the best result is that, as shown in FIG. 3, the substrate 6 after growth is flat without any warpage as a whole substrate.
【００３０】また、ＧａＮ層5の厚さＨ２やサファイヤ
基板1の厚さＨ１、およびサファイヤ基板1を薄く加工す
る加工工程において生じる歪み応力などのバラツキによ
り、図４に示す、反り返りまでには至らなかったほぼ平
坦な成長後基板6、もしくは図５に示すように、反り返
りが若干発生した、ほぼ平坦な成長後基板6のもが得ら
れた。Also, due to variations in the thickness H2 of the GaN layer 5, the thickness H1 of the sapphire substrate 1, and the strain stress generated in the processing step of processing the sapphire substrate 1 thinly, the warpage shown in FIG. A substantially flat post-growth substrate 6 was obtained, or a substantially flat post-growth substrate 6 was obtained as shown in FIG.
【００３１】さらにまた、図６に示すように、鞍型に反
った変形型の成長後基板6も一部で見受けられた。ここ
で付け加えて説明するが、図６の模式図は、説明のため
に形状が強調して描画されており、実際の反りは図４並
びに図５のように非常に小さいものであり、ほぼ平坦な
ものが得られた。Further, as shown in FIG. 6, a deformed type substrate 6 that is warped to a saddle shape was partially observed. As will be additionally described here, the schematic diagram of FIG. 6 is drawn with the shape emphasized for the sake of explanation, and the actual warpage is very small as shown in FIGS. Was obtained.
【００３２】成長後基板6は、図４、図５および図６の
何れの場合においても、反り返りの大きさ、すなわち、
中心部の凹み深さＥ１、周辺部の浮き上がり高さＥ２お
よび中心部の浮き上がり高さＥ３は、対応する結晶成長
前の凹み深さＤ１、周辺部の浮き上がり高さＤ２および
中心部の浮き上がり高さＤ３より確実に小さいものであ
った。The substrate 6 after the growth, in any case of FIG. 4, FIG. 5 and FIG.
The concave depth E1 at the center, the floating height E2 at the peripheral portion, and the floating height E3 at the central portion are the corresponding concave depth D1 before crystal growth, the floating height D2 at the peripheral portion, and the floating height at the central portion. It was definitely smaller than D3.
【００３３】成長後基板6は、反り返りの大きさが従来
品より極端に小さく、その後のペレタイズ工程などにお
いて、結晶成長させたＧａＮ層を傷つけてしまう場合が
従来より少なくなった。また、本実施の形態において使
用したサファイヤ基板1は、もともと薄い基板なので、
結晶成長後に裏面4（図１参照）を更に二次研削する必
要がなく、加工工程を少なくすることができた。The substrate 6 after the growth has a significantly smaller warpage than that of the conventional product, and the number of cases where the crystal-grown GaN layer is damaged in the subsequent pelletizing step or the like is smaller than in the conventional case. The sapphire substrate 1 used in the present embodiment is originally a thin substrate,
After crystal growth, the back surface 4 (see FIG. 1) does not need to be subjected to secondary grinding, and the number of processing steps can be reduced.
【００３４】すなわち、本発明では高精度な加工技術に
より得られた薄型のサファイヤ基板1を結晶成長基板に
用いることにより、加工工程を簡素化でき、製品品質を
安定させ、かつ、最終的に歩留りを向上させることが可
能となった。That is, in the present invention, by using a thin sapphire substrate 1 obtained by a high-precision processing technique as a crystal growth substrate, the processing steps can be simplified, the product quality can be stabilized, and finally the yield can be improved. Can be improved.
【００３５】（実施の形態２）次に、予めスクライブ溝
を備えた薄型サファイヤ基板について説明する。図７
は、本実施の形態に係るサファイヤ基板の一例を示す図
であり、同図７は基板の裏面側平面図を、同図８は同図
７のＡ−Ａ断面をそれぞれ示すものである。なお、実施
の形態２においては、実施の形態１と同様の部分につい
てはその説明を省略し、また、同一の構成を有する部位
に対しては同一の符号を付するものとする。(Embodiment 2) Next, a thin sapphire substrate having scribe grooves in advance will be described. FIG.
7 is a diagram showing an example of the sapphire substrate according to the present embodiment, FIG. 7 is a plan view of the back side of the substrate, and FIG. 8 is a cross-sectional view taken along the line AA of FIG. In the second embodiment, the description of the same parts as in the first embodiment is omitted, and the same reference numerals are given to parts having the same configuration.
【００３６】サファイヤ基板7は、直径３インチ（7.62
［cm］）の円盤形状であり、その厚さＨ１を100［μm］
程度にまで薄厚に加工したものを用いる。さらに、この
サファイヤ基板7には、結晶成長を行う前に、裏面4側全
域に間隔0.3［mm］、深さ5［μm］のスクライブ溝8を縦
横に格子状にダイサーで加工した。The sapphire substrate 7 has a diameter of 3 inches (7.62
[Cm]), and the thickness H1 is 100 [μm].
Use the one that has been processed to be thin to the extent. Further, in the sapphire substrate 7, scribe grooves 8 having an interval of 0.3 [mm] and a depth of 5 [μm] were formed in a vertical and horizontal lattice pattern by a dicer on the entire back surface 4 side before crystal growth.
【００３７】次に、このサファイヤ基板7を用いて厚さ1
0［μm］のＧａＮをエピタキシャル成長させ、その後、
最終的に青色発光素子を製造するための各種ウエハ処理
・ペレタイズを行った。Next, using this sapphire substrate 7,
0 [μm] GaN is epitaxially grown, and then
Finally, various kinds of wafer processing and pelletizing for manufacturing a blue light emitting element were performed.
【００３８】このとき、すでにサファイヤ基板７の裏面
4側にはスクライブ溝8を予め設けてあるので、薄厚なサ
ファイヤ基板7の片面に結晶成長させた前記基板の円盤
平面を、ローラー治具で加圧しながら押すだけで、基板
全体が細かに分割され、各チップを分離する作業工程を
容易におこなうことができた。At this time, the back surface of the sapphire substrate 7 has already been formed.
Since the scribe groove 8 is provided in advance on the 4 side, the disk plane of the substrate on which crystal growth has occurred on one side of the thin sapphire substrate 7 is simply pressed while pressing with a roller jig, and the entire substrate is finely divided. As a result, a work process for separating each chip could be easily performed.
【００３９】このように、スクライブ溝8を施した薄型
サファイヤ基板7を用いることにより、研削工程を無く
して加工工程を少なくし、さらにチップ製品の品質を向
上させ、かつ、量産性と歩留りの向上を図ることが可能
となった。As described above, the use of the thin sapphire substrate 7 provided with the scribe grooves 8 eliminates the grinding step, reduces the number of processing steps, further improves the quality of chip products, and improves the mass productivity and yield. It became possible to aim at.
【００４０】[0040]
【発明の効果】以上説明したように、本発明のサファイ
ヤ基板（請求項１）は、当該基板の厚さを、当該基板に
積層させる半導体の積層厚さと同程度の厚さに予め加工
してあるので、結晶成長後の反り返りを極端に少なくす
ることができ、これにより、製品品質を向上させること
が可能となる。As described above, the sapphire substrate of the present invention (Claim 1) is prepared by processing the thickness of the substrate in advance to the same thickness as the thickness of the semiconductor laminated on the substrate. As a result, warpage after crystal growth can be extremely reduced, thereby improving product quality.
【００４１】また、本発明のサファイヤ基板（請求項
２）は、直径を5cm以上、13cm以下、厚さを20μm以下の
円盤形状に加工してあるので、エピタキシャル成長させ
る結晶の厚さが数μm〜10数μm程度である場合に、結晶
成長後の基板の反り返りを少なくすることができ、これ
により、製品品質を向上させることが可能となる。The sapphire substrate of the present invention (claim 2) is processed into a disk shape having a diameter of 5 cm or more and 13 cm or less and a thickness of 20 μm or less. When the thickness is about 10 μm, the warpage of the substrate after the crystal growth can be reduced, thereby improving the product quality.
【００４２】また、本発明のサファイヤ基板（請求項
３）は、当該基板の厚さを10μm以上、150μm以下と
し、さらに、エピタキシャル成長させる面と反対側の面
に予めスクライブ溝を形成してあるので、結晶成長後の
裏面の研削工程が不要で、ペレタイズ工程における結晶
面に対する損傷を低減させることができ、これにより、
製品品質を向上と歩留り向上が可能となる。In the sapphire substrate of the present invention (claim 3), the thickness of the substrate is 10 μm or more and 150 μm or less, and scribe grooves are previously formed on the surface opposite to the surface on which epitaxial growth is performed. This eliminates the need for a back surface grinding step after crystal growth, and reduces damage to the crystal surface in the pelletizing step.
Product quality and yield can be improved.
【００４３】また、本発明のサファイヤ基板（請求項
４）は、請求項１、２または３に記載の発明において、
結晶成長させる半導体をIII族窒化物半導体もしくは窒
化ガリウム系化合物半導体としたので、サファイヤと格
子定数が近似し、結晶成長後基板においても良好な結晶
を得ることができ、これにより、高い製品品質を得るこ
とが可能となる。The sapphire substrate of the present invention (Claim 4) is characterized in that:
Since the semiconductor to be crystal-grown is a group III nitride semiconductor or a gallium nitride-based compound semiconductor, the lattice constant is close to that of sapphire, and a good crystal can be obtained even on the substrate after crystal growth. It is possible to obtain.
【図１】実施の形態１に係るサファイヤ基板の一例を示
す平面概略図である。FIG. 1 is a schematic plan view showing an example of a sapphire substrate according to a first embodiment.
【図２】実施の形態１に係るサファイヤ基板の一例を示
す側断面概略図である。FIG. 2 is a schematic side sectional view showing an example of the sapphire substrate according to the first embodiment.
【図３】実施の形態１に係るサファイヤ基板を用いてＧ
ａＮを結晶成長させた後の基板の状態を示す模式図であ
る。FIG. 3 is a diagram showing a G using the sapphire substrate according to the first embodiment;
It is a schematic diagram which shows the state of the board | substrate after crystal growth of aN.
【図４】実施の形態１に係るサファイヤ基板を用いてＧ
ａＮを結晶成長させた後の基板の状態を示す別の模式図
である。FIG. 4 is a diagram showing a structure of the sapphire substrate according to the first embodiment,
FIG. 4 is another schematic diagram showing a state of a substrate after aN is crystal-grown.
【図５】実施の形態１に係るサファイヤ基板を用いてＧ
ａＮを結晶成長させた後の基板の状態を示す別の模式図
である。FIG. 5 is a view showing a structure of a sapphire substrate according to the first embodiment,
FIG. 4 is another schematic diagram showing a state of a substrate after aN is crystal-grown.
【図６】実施の形態１に係るサファイヤ基板を用いてＧ
ａＮを結晶成長させた後の基板の状態を示す別の模式図
である。FIG. 6 is a diagram illustrating a method using the sapphire substrate according to the first embodiment;
FIG. 4 is another schematic diagram showing a state of a substrate after aN is crystal-grown.
【図７】実施の形態２に係るサファイヤ基板の一例を示
す平面概略図である。FIG. 7 is a schematic plan view showing an example of a sapphire substrate according to a second embodiment.
【図８】実施の形態２に係るサファイヤ基板の一例を示
す側断面概略図である。FIG. 8 is a schematic side sectional view showing an example of a sapphire substrate according to a second embodiment.
【図９】従来のサファイヤ基板の一例を示す平面概略図
である。FIG. 9 is a schematic plan view showing an example of a conventional sapphire substrate.
【図10】従来のサファイヤ基板の一例を示す側断面概略
図である。FIG. 10 is a schematic side sectional view showing an example of a conventional sapphire substrate.
【図11】従来のサファイヤ基板を用いてＧａＮを結晶成
長させた場合の基板側断面を示した模式図である。FIG. 11 is a schematic view showing a cross section on the substrate side when GaN is grown using a conventional sapphire substrate.
1、7、10 サファイヤ基板 2 オリフラ 3 結晶成長面 4、14 裏面 5 ＧａＮ層 6、11 成長後基板 8 スクライブ溝 12 半導体層 13 結晶成長面 1, 7, 10 Sapphire substrate 2 Oriflat 3 Crystal growth surface 4, 14 Back surface 5 GaN layer 6, 11 Substrate after growth 8 Scribe groove 12 Semiconductor layer 13 Crystal growth surface
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 次男 秋田県湯沢市愛宕町４丁目６番56号 並木 精密宝石株式会社秋田湯沢工場内 (72)発明者 戸嶋 博昭 秋田県湯沢市愛宕町４丁目６番56号 並木 精密宝石株式会社秋田湯沢工場内 Ｆターム(参考） 4G077 AA03 BE15 ED04 HA02 5F041 AA40 CA40 CA46 CA76 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Tsugio Sato 4-6-56, Atago-cho, Yuzawa-shi, Akita Namiki Precision Jewelry Co., Ltd. Inside the Akita-Yuzawa Plant (72) Inventor Hiroaki Tojima 4-chome, Atago-cho, Yuzawa-shi, Akita 6-56 Namiki Precision Jewelry Co., Ltd. F-term in the Akita Yuzawa Plant (reference) 4G077 AA03 BE15 ED04 HA02 5F041 AA40 CA40 CA46 CA76
Claims (4)
用いるサファイヤ基板であって、当該基板の厚さを、当
該基板上に積層させる半導体の積層厚さと同程度の厚さ
に予め加工したことを特徴とする薄型サファイヤ基板。1. A sapphire substrate used for epitaxially growing a semiconductor, characterized in that the thickness of the substrate has been previously processed to the same thickness as the thickness of a semiconductor to be laminated on the substrate. Thin sapphire substrate.
μm以下の円盤形状に加工したことを特徴とする請求項
１に記載の薄型サファイヤ基板。2. The diameter is not less than 5 cm and not more than 13 cm, and the thickness is not more than 20 cm.
2. The thin sapphire substrate according to claim 1, wherein the substrate is processed into a disk shape of not more than μm.
用いるサファイヤ基板であって、当該基板の厚さを10μ
m以上、150μm以下とし、さらに、エピタキシャル成長
させる面と反対側の面に予めスクライブ溝を格子状に形
成したことを特徴とする薄型サファイヤ基板。3. A sapphire substrate used for epitaxially growing a semiconductor, wherein the substrate has a thickness of 10 μm.
A thin sapphire substrate characterized in that scribe grooves are previously formed in a lattice shape on a surface opposite to a surface on which epitaxial growth is to be performed, in a range from m to 150 μm.
くは窒化ガリウム系化合物半導体であることを特徴とす
る請求項１、２または３に記載の薄型サファイヤ基板。4. The thin sapphire substrate according to claim 1, wherein the semiconductor is a group III nitride semiconductor or a gallium nitride compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000069422A JP2001253800A (en) | 2000-03-13 | 2000-03-13 | Thin sapphire substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000069422A JP2001253800A (en) | 2000-03-13 | 2000-03-13 | Thin sapphire substrate |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009197771A Division JP2010006700A (en) | 2009-08-28 | 2009-08-28 | Thin sapphire substrate |
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| Publication Number | Publication Date |
|---|---|
| JP2001253800A true JP2001253800A (en) | 2001-09-18 |
Family
ID=18588298
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000069422A Pending JP2001253800A (en) | 2000-03-13 | 2000-03-13 | Thin sapphire substrate |
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| Country | Link |
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| JP (1) | JP2001253800A (en) |
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| JP2006108202A (en) * | 2004-10-01 | 2006-04-20 | Sony Corp | Method of manufacturing light emitting element |
| JP2007184352A (en) * | 2006-01-05 | 2007-07-19 | Matsushita Electric Ind Co Ltd | Wafer for nitride-based compound semiconductor element and manufacturing method thereof |
| JP2009208991A (en) * | 2008-03-04 | 2009-09-17 | Hitachi Cable Ltd | Method for producing nitride semiconductor substrate |
| US7919815B1 (en) | 2005-02-24 | 2011-04-05 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel wafers and methods of preparation |
| WO2012118303A1 (en) * | 2011-03-03 | 2012-09-07 | 서울옵토디바이스주식회사 | Light-emitting diode chip |
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| JPS55153350A (en) * | 1979-05-18 | 1980-11-29 | Nec Corp | Manufacture of hybrid integrated circuit |
| JPH09129559A (en) * | 1995-10-30 | 1997-05-16 | Toshiba Corp | Manufacture of compound semiconductor |
| JPH10256200A (en) * | 1997-03-07 | 1998-09-25 | Nec Corp | Semiconductor substrate and its manufacture |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004018743A1 (en) * | 2002-08-26 | 2004-03-04 | National Institute For Materials Science | Diboride single crystal substrate, semiconductor device using this and its manufacturing method |
| US7297989B2 (en) | 2002-08-26 | 2007-11-20 | National Institute For Materials Science | Diboride single crystal substrate, semiconductor device using this and its manufacturing method |
| CN100415948C (en) * | 2002-08-26 | 2008-09-03 | 独立行政法人物质·材料研究机构 | Diboride single crystal substrate, semiconductor device using this and its manufacturing method |
| JP2006108202A (en) * | 2004-10-01 | 2006-04-20 | Sony Corp | Method of manufacturing light emitting element |
| JP4600743B2 (en) * | 2004-10-01 | 2010-12-15 | ソニー株式会社 | Method for manufacturing light emitting device |
| US7919815B1 (en) | 2005-02-24 | 2011-04-05 | Saint-Gobain Ceramics & Plastics, Inc. | Spinel wafers and methods of preparation |
| JP2007184352A (en) * | 2006-01-05 | 2007-07-19 | Matsushita Electric Ind Co Ltd | Wafer for nitride-based compound semiconductor element and manufacturing method thereof |
| JP2009208991A (en) * | 2008-03-04 | 2009-09-17 | Hitachi Cable Ltd | Method for producing nitride semiconductor substrate |
| WO2012118303A1 (en) * | 2011-03-03 | 2012-09-07 | 서울옵토디바이스주식회사 | Light-emitting diode chip |
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