JP2001244372A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2001244372A JP2001244372A JP2000055863A JP2000055863A JP2001244372A JP 2001244372 A JP2001244372 A JP 2001244372A JP 2000055863 A JP2000055863 A JP 2000055863A JP 2000055863 A JP2000055863 A JP 2000055863A JP 2001244372 A JP2001244372 A JP 2001244372A
- Authority
- JP
- Japan
- Prior art keywords
- post
- semiconductor device
- solder
- layer
- spherical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は高密度実装対応のウ
エーハレベルのＣＳＰ（チップサイズパッケージ）型の
半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer-level CSP (chip size package) type semiconductor device for high-density mounting and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、携帯電話や情報端末等の機器類の
小型化に伴い、搭載部品の小型，軽量化が要求され、Ｌ
ＳＩ等の半導体装置も、従来のウエーハ処理工程とパッ
ケージ組み立て工程を一本化したウエーハレベルのＣＳ
Ｐの供給が行われるようになった。ウエーハレベルのＣ
ＳＰの特徴は、従来の単チップから作られるＣＳＰに比
べ、インタポーザ等の部品点数や工程数の削減による製
造コストを抑え、パッケージトータルの低コスト化を図
るものである。この技術は、例えば１９９９年の日経マ
イクロデバイス２月号ｐ３８〜ｐ６７や電子材料９月号
ｐ２１〜ｐ８５にその構造や工程概要が記載されてい
る。2. Description of the Related Art In recent years, with the miniaturization of devices such as mobile phones and information terminals, smaller and lighter components have been required.
Semiconductor devices such as SI also have wafer-level CS that integrates the conventional wafer processing process and package assembly process.
P was supplied. Wafer level C
The SP is characterized in that, compared to a conventional CSP made from a single chip, the manufacturing cost is reduced by reducing the number of components and steps of the interposer and the like, and the total package cost is reduced. The structure and process outline of this technique are described in, for example, Nikkei Microdevice February 1999, p.38 to p67, and Electronic Material September, p21 to p85.
【０００３】これらの製造方法は、例えば図７及び図８
に示す。[0003] These manufacturing methods are described, for example, in FIGS.
Shown in
【０００４】まず、図７（Ａ）に示すように、半導体素
子が作り込まれたシリコン基板１１のＡｌ合金配線パッ
ド１２上のシリコン窒化膜等の保護絶縁層１３及びポリ
イミド層１４を開孔した後に、ＣｒやＴｉＷ等の密着層
１５上にＣｕをそれぞれスパッタしてシード層１６を形
成後、更にレジスト１７をマスクにＣｕを選択メッキし
て引き出し用の再配線層１８を形成する。次に、図７
（Ｂ）に示すように、新たなレジスト１９をマスクに１
００μｍ程度の厚いＣｕ層と、バリア層３１を選択メッ
キして、バリアが積層されたＣｕポスト３０を形成す
る。次に、図８（Ａ）に示すように、レジスト１９を剥
離した後、再配線層１８をマスクにシード層１６、密着
層１５をエッチング除去すると、各々分離した再配線が
形成される。更に、図８（Ｂ）に示すように、シリコン
基板１１全体の少なくとも表面を封止樹脂２１で密閉し
た後、該樹脂２１を研削もしくは機械研磨によってＣｕ
ポスト３０表面のバリア層３１を露出させる。更に自動
移載機によって各ポスト３０領域にハンダボールを搭載
し、ハンダボールがポストに溶着するように熱処理を施
し、外部端子２２を形成する。その後電気特性がチェッ
クされチップ毎にダイシングし、携帯機器類のマザーボ
ード等に装着される。First, as shown in FIG. 7A, a protective insulating layer 13 such as a silicon nitride film and a polyimide layer 14 on an Al alloy wiring pad 12 of a silicon substrate 11 in which a semiconductor element is formed are opened. Thereafter, Cu is sputtered on the adhesion layer 15 such as Cr or TiW to form a seed layer 16, and then Cu is selectively plated using the resist 17 as a mask to form a lead-out rewiring layer 18. Next, FIG.
As shown in (B), the new resist 19 is used as a mask for 1
A thick Cu layer of about 00 μm and a barrier layer 31 are selectively plated to form a Cu post 30 on which a barrier is laminated. Next, as shown in FIG. 8A, after the resist 19 is peeled off, the seed layer 16 and the adhesion layer 15 are removed by etching using the rewiring layer 18 as a mask, thereby forming separated rewiring. Further, as shown in FIG. 8B, at least the entire surface of the silicon substrate 11 is sealed with a sealing resin 21, and then the resin 21 is ground or mechanically polished to form a Cu substrate.
The barrier layer 31 on the surface of the post 30 is exposed. Further, solder balls are mounted on the areas of the posts 30 by an automatic transfer machine, and heat treatment is performed so that the solder balls are welded to the posts, thereby forming the external terminals 22. After that, the electrical characteristics are checked, and each chip is diced and mounted on a motherboard or the like of a portable device.
【０００５】しかしこの技術においては、以下のような
問題を有する。However, this technique has the following problems.
【０００６】厚いＣｕポスト３０をメッキで形成するこ
とや、Ｃｕの酸化等を防ぐバリア層３１を必要とし、異
種のメッキ浴槽と工程が必要で、コストと流動工数が問
題となる。更にポスト３０は垂直に形成されるため縦方
向の引っ張り応力には弱く、特にフレキシブルボードに
搭載した場合は再配線層１８との剥離が生ずる問題があ
る。又、ポスト３０にかかる圧縮応力をシリコン基板１
１表面の半導体素子に不具合を与えないように、厚み数
十〜１００μｍ前後のポリイミド層１４を敷いて弾力を
持たせているが、この結果パッド開孔部と再配線との接
触部に応力が集中し、樹脂封止や研削工程あるいはボー
ドへの装着等の後工程で、パッド１２領域周辺に断線や
クラックが生じ易い。又ポリイミド層１４のパッド開孔
段差によってパッド開孔部ではスパッタに依るシード層
１６等の付きまわりが厳しいため、結果的に再配線層１
８の成長も均一でなくエレクトロマイグレーションにか
かわる信頼性も問題となっていた。この他、薄いバリア
層３１を再現良く残すように研削しなくてはならず、封
止樹脂の厚み,研削量及びメッキ厚み等の管理項目が多
く量産性も問題である。A thick Cu post 30 needs to be formed by plating, and a barrier layer 31 for preventing oxidation of Cu and the like is required. Therefore, different types of plating baths and steps are required, and cost and flow man-hours become problems. Further, since the post 30 is formed vertically, the post 30 is weak against the tensile stress in the vertical direction. In particular, when the post 30 is mounted on a flexible board, there is a problem that the post 30 is separated from the rewiring layer 18. Further, the compressive stress applied to the post 30 is changed to the silicon substrate 1.
A polyimide layer 14 having a thickness of about several tens to 100 μm is laid so as to have elasticity so as not to cause a defect on one surface of the semiconductor element. As a result, stress is applied to a contact portion between the pad opening and the rewiring. Concentration is likely to cause disconnection and cracks around the pad 12 region in a post-process such as resin sealing, a grinding process, or mounting on a board. Also, due to the step difference in pad opening of the polyimide layer 14, the rotation of the seed layer 16 and the like due to sputtering is severe in the pad opening, and as a result, the rewiring layer 1
The growth of No. 8 was not uniform, and the reliability related to electromigration was also a problem. In addition, it is necessary to grind the thin barrier layer 31 so as to leave it with good reproducibility, and there are many management items such as the thickness of the sealing resin, the grinding amount, and the plating thickness, and mass productivity is also a problem.
【０００７】[0007]
【発明が解決しようとする課題】本発明の目的は、ウエ
ーハレベルのＣＳＰ型の半導体装置において、工程の増
加を伴うことなく、低コストで信頼性の高い半導体装置
及びその製造方法を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a low-cost and highly reliable semiconductor device and a method of manufacturing the same in a wafer-level CSP type semiconductor device without increasing the number of steps. It is in.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体装置の製造方法において、少なくとも
以下の工程（ａ）〜（ｅ）を含むことを特徴とする。A method for manufacturing a semiconductor device according to the present invention is characterized in that the method for manufacturing a semiconductor device includes at least the following steps (a) to (e).
【０００９】（ａ）最終配線パッドから電極引き出し用
の再配線層を施す工程 （ｂ）前記再配線層の所望領域にハンダポストをメッキ
形成する工程 （ｃ）熱処理によって、前記ハンダポストの少なくとも
側面を球状化する工程 （ｄ）樹脂にて封止を行った後に、前記樹脂の所望量を
除去し前記ポストの一部を露出させる工程、及び （ｅ）露出したポスト上に外部端子を形成する工程。(A) a step of applying a redistribution layer for leading out an electrode from a final wiring pad; (b) a step of plating a solder post in a desired region of the redistribution layer; and (c) at least a side surface of the solder post by heat treatment. (D) after sealing with a resin, removing a desired amount of the resin to expose a part of the post; and (e) forming an external terminal on the exposed post. Process.
【００１０】本発明の製造方法においては、ＬＳＩ等の
最終配線の外部取り出し用パッド、あるいはダミーパッ
ド等に再配線層を施し、その所望領域にハンダポストを
形成した後アニールによって球状化し、これを封止樹脂
で包み、研削もしくは機械研磨等によって一部を露出さ
せた後、更にハンダボールを搭載し溶着させることで外
部端子が形成される。In the manufacturing method of the present invention, a rewiring layer is applied to a pad for taking out the final wiring of an LSI or the like or a dummy pad, a solder post is formed in a desired region thereof, and the solder post is formed into a spherical shape by annealing. After wrapping with a sealing resin and exposing a part by grinding or mechanical polishing, solder balls are further mounted and welded to form external terminals.
【００１１】この製造方法によれば、側面が弓形をなし
引っ張り応力にも強いポストが形成できる。従って工数
を増加させることなく、又バリア層を必要としないポス
トが形成でき、簡易なプロセスによりコストの削減と量
産性及び信頼性の向上が図れる。According to this manufacturing method, a post having an arcuate side surface and having a high tensile stress can be formed. Therefore, a post that does not require a barrier layer can be formed without increasing the number of steps, and cost can be reduced and mass productivity and reliability can be improved by a simple process.
【００１２】なお、本発明に係る工程（ａ）〜（ｅ）
は、半導体ウエハーに対して行うことも、固片チップに
対して行うことも可能である。The steps (a) to (e) according to the present invention.
Can be performed on a semiconductor wafer or a solid chip.
【００１３】また、本発明の半導体装置の製造方法は、
前記工程（ｂ）において、前記ハンダポストは、パッド
開孔部上の再配線層引き出し領域にも選択メッキ形成さ
れていることを特徴とする。Further, a method of manufacturing a semiconductor device according to the present invention
In the step (b), the solder post is selectively plated also in a rewiring layer lead-out area on a pad opening.
【００１４】このように、ハンダポストを同一工程でパ
ッド開孔部にも形成することができるため、樹脂の封止
や研削工程でのストレスを回避できる。又、パッド開孔
内部にもハンダが充填されるので再配線の付きまわり不
良を補い断線を回避できる。As described above, since the solder post can be formed in the pad opening in the same step, stress in the resin sealing and grinding steps can be avoided. In addition, since the solder is also filled in the inside of the pad opening, it is possible to compensate for the poor re-wiring and to avoid disconnection.
【００１５】さらに、本発明の半導体装置の製造方法
は、前記工程（ｂ）において、前記ハンダポストは、フ
ォトレジストをマスクに再配線層金属とは異種の金属を
選択メッキした後に、続けてハンダ層を選択メッキして
形成されていることを特徴とする。Further, in the method of manufacturing a semiconductor device according to the present invention, in the step (b), the solder post may be formed by selectively plating a metal different from the rewiring layer metal using a photoresist as a mask, and then soldering. The layer is formed by selective plating.
【００１６】工程（ｃ）において、ハンダポストを熱処
理して球状にするが、温度が高いと再配線層上をハンダ
が流れやすくなる。ハンダを選択メッキする前に同じパ
ターンで再配線層と異なる金属をベース層としてメッキ
することでハンダ流れのストップガイドの役割を果た
し、厳しい温度管理をしなくても、ポスト形状の安定化
が図れる。例えば、Ｃｕの再配線層上にＮｉあるいは、
Ｎｉ再配線層上にＣｕ等，もしくはいずれの再配線上に
ＡｕＮｉ合金等の異種金属を配置することでハンダ流れ
を抑御できる。あるいは、本願発明の半導体装置の製造
方法は、前記工程（ｅ）において、前記外部端子は、ハ
ンダポストより融点の低い組成材料でなることを特徴と
する。In the step (c), the solder post is heat-treated to be spherical, but when the temperature is high, the solder easily flows on the rewiring layer. By performing plating with the same pattern and a different metal from the rewiring layer as the base layer before the selective plating of the solder, it plays the role of a stop guide for the solder flow and stabilizes the post shape without strict temperature control. . For example, Ni or Ni on the Cu rewiring layer
By disposing a dissimilar metal such as Cu on the Ni redistribution layer or an AuNi alloy on any of the redistribution layers, the solder flow can be suppressed. Alternatively, in the method of manufacturing a semiconductor device according to the present invention, in the step (e), the external terminal is made of a composition material having a melting point lower than that of a solder post.
【００１７】もしくは、本発明の半導体装置の製造方法
は、前記工程（ｅ）において、外部端子は、ハンダポス
トより融点の低い組成材料でなることを特徴とする。Alternatively, in the method of manufacturing a semiconductor device according to the present invention, in the step (e), the external terminal is made of a composition material having a lower melting point than the solder post.
【００１８】さらには、本発明の半導体装置の製造方法
は、前記工程（ｅ）の後に、ダイシングを施してチップ
毎に固片化する工程をさらに有することを特徴とする。Further, the method of manufacturing a semiconductor device according to the present invention is characterized in that the method further comprises, after the step (e), a step of performing dicing to solidify each chip.
【００１９】前記チップ毎に固片化する工程は、前記工
程（ａ）〜（ｅ）を半導体ウエハーに対して行った場合
に適用される工程であり、前記工程（ａ）〜（ｅ）を固
片チップに対して行った場合には適用されない。The step of solidifying for each chip is a step applied when the steps (a) to (e) are performed on a semiconductor wafer, and the steps (a) to (e) are performed. It does not apply when performed on solid chips.
【００２０】ここで、工程（ｅ）において、ハンダボー
ルを露出ポスト上に搭載し熱処理によって溶着させ外部
端子とさせるが、内部にＣｕやＮｉ等のハンダより融点
の高い核を持ったボールを適用することで、外部端子の
高さや形状がばらつきが少なくなる。したがってマザー
ボード等への装着時の歩留まりが改善され、更に核の浮
遊によって応力緩和の役割も果たし、素子への特性影響
と装着条件の制御が容易になる。Here, in step (e), solder balls are mounted on the exposed posts and welded by heat treatment to form external terminals. Balls having nuclei, such as Cu or Ni, having a higher melting point than solder are applied. By doing so, variations in the height and shape of the external terminals are reduced. Therefore, the yield at the time of mounting on a motherboard or the like is improved, and the floating of the nucleus also plays a role of relaxing the stress, thereby facilitating the control of the characteristics influence on the element and the mounting conditions.
【００２１】また、本発明の半導体装置は、チップサイ
ズパッケージ型の半導体装置であって、最終配線のパッ
ド開孔部から再配線層を施し、前記再配線層の所望領域
に封止樹脂で一部を囲まれた球状ポストを有し、前記球
状ポストの上に外部端子が形成されてなることを特徴と
する。Further, the semiconductor device of the present invention is a semiconductor device of a chip size package type, in which a rewiring layer is formed from a pad opening of a final wiring, and a desired area of the rewiring layer is sealed with a sealing resin. A spherical post surrounding the portion, wherein an external terminal is formed on the spherical post.
【００２２】本発明の半導体装置は、前記半導体装置
は、半導体ウエハーでもよいし、前記再配線層、前記球
状ポスト、及び前記外部端子が形成された後に半導体チ
ップ毎に固片化されてなるものでもよいし、半導体ウエ
ハーを半導体チップ毎に固片化した後に、前記再配線
層、前記球状ポスト、及び前記外部端子が形成されてな
るものでもよい。In the semiconductor device according to the present invention, the semiconductor device may be a semiconductor wafer, or may be solidified for each semiconductor chip after the rewiring layer, the spherical posts, and the external terminals are formed. Alternatively, after the semiconductor wafer is solidified for each semiconductor chip, the rewiring layer, the spherical posts, and the external terminals may be formed.
【００２３】このように、本発明の半導体装置は、半導
体ウエハー及び固片チップのいずれの態様であってもよ
い。As described above, the semiconductor device of the present invention may be in any form of a semiconductor wafer and a solid chip.
【００２４】あるいは、本発明の半導体装置は、前記球
状ポストは、メッキ法によるハンダで形成されているこ
とを特徴とする。Alternatively, the semiconductor device according to the present invention is characterized in that the spherical post is formed of solder by a plating method.
【００２５】さらには、本発明の半導体装置は、チップ
サイズパッケージ型の半導体装置であって、樹脂で覆わ
れるポスト側面の形状は、シリコン基板に対して少なく
とも一部が垂直でない領域を持つことを特徴とする。Further, the semiconductor device according to the present invention is a semiconductor device of a chip size package type, wherein the shape of the side surface of the post covered with resin has a region at least partially not perpendicular to the silicon substrate. Features.
【００２６】この半導体装置によれば、樹脂で覆われる
ポスト側面の形状は、シリコン基板に対して少なくとも
一部に垂直でない領域を持つことができ、ウエーハレベ
ルのＣＳＰとして、例えば携帯機器のマザーボードに装
着する場合の引っ張り応力に対して強度が確保され、歩
留まりや信頼性の向上が図れる。又、ポストが配置され
る領域における再配線層の少なくとも一部に、異種金属
層を設けることで、ポストの形状制御と密着強度の向上
が図れる。According to this semiconductor device, the shape of the post side surface covered with the resin can have a region that is not at least partially perpendicular to the silicon substrate, and is used as a wafer-level CSP, for example, on a motherboard of a portable device. The strength against the tensile stress in the case of mounting is secured, and the yield and reliability can be improved. Further, by providing a dissimilar metal layer on at least a part of the rewiring layer in a region where the post is arranged, it is possible to control the shape of the post and improve the adhesion strength.
【００２７】または、本発明の半導体装置は、チップサ
イズパッケージ型の半導体装置であって、外部端子を搭
載するポストが、中空形状となっていることを特徴とす
る。Alternatively, a semiconductor device according to the present invention is a semiconductor device of a chip size package type, wherein a post for mounting an external terminal has a hollow shape.
【００２８】さらには、本発明の半導体装置は、チップ
サイズパッケージ型の半導体装置であって、外部端子
は、表面がハンダ材で構成され、内部に前記ハンダ材よ
り融点の高い金属核を有することを特徴とする。Further, the semiconductor device of the present invention is a semiconductor device of a chip size package type, wherein the external terminal has a surface made of a solder material, and has a metal core having a melting point higher than that of the solder material inside. It is characterized by.
【００２９】このように、更にハンダ外部端子の内部
に、ハンダより融点の高い、例えばＣｕやＮｉあるいは
合金等の核を保有させることで、外部端子の形状ばらつ
きを抑え、ボード装着時に応力を緩和し条件マージンを
広くとることが可能になり、歩留まりや信頼性の向上が
図れる。As described above, the core having a higher melting point than that of the solder, such as Cu, Ni, or an alloy, is held inside the solder external terminal, thereby suppressing the variation in shape of the external terminal and relaxing the stress when the board is mounted. In this case, the condition margin can be widened, and the yield and reliability can be improved.
【００３０】[0030]
【発明の実施の形態】（第１の実施の形態）図１は、本
発明の第１の実施の形態に係る半導体装置の断面構造図
である。第１の実施の形態に係る半導体装置の構造を簡
単に説明する。シリコン基板１１にはＭＯＳトランジス
タ等の半導体素子が形成され、これらが層間絶縁膜を介
してＡｌ合金等の金属で配線され、シリコン酸化膜やシ
リコン窒化膜等でなる最終保護絶縁層１３で覆ってい
る。外部電極取り出しのために例えば最終配線の外部へ
の電極取り出し用のパッド１２を設け、該保護絶縁層１
３の必要領域を開孔し、その上層に開孔部を除いて例え
ば数十〜１００μｍ程度のポリイミド層１４が、素子へ
の応力緩和のため積層されている。パッド１２からはＴ
ｉＷでなる密着層１５とＣｕシード層１６、更に数μｍ
の厚みでＣｕをメッキ成膜した再配線層１８を有する。
再配線層１８上の所定領域にハンダメッキで成膜した
後、熱処理した球状ポスト２０が形成され、その周囲を
エポキシ等の封止樹脂２１で包み、表面はほぼ同一面で
研削され、結果的にポスト２０側面は弓形をなしてい
る。露出した頭部にハンダボールを搭載した外部端子２
２が、所望ポスト２０上に溶着形成されている。内部素
子からパッド１２、再配線層１８、球状ポスト２０等を
介して外部端子２２に電気的接続がなされる。(First Embodiment) FIG. 1 is a sectional structural view of a semiconductor device according to a first embodiment of the present invention. The structure of the semiconductor device according to the first embodiment will be briefly described. Semiconductor elements such as MOS transistors are formed on the silicon substrate 11 and are wired with a metal such as an Al alloy via an interlayer insulating film, and are covered with a final protective insulating layer 13 made of a silicon oxide film or a silicon nitride film. I have. In order to take out the external electrode, for example, a pad 12 for taking out the electrode to the outside of the final wiring is provided.
A required region of No. 3 is opened, and a polyimide layer 14 of, for example, about several tens to 100 μm is laminated on the upper layer excluding the opening to reduce stress on the element. T from the pad 12
iW adhesion layer 15 and Cu seed layer 16 and several μm
Has a re-wiring layer 18 formed by plating Cu with a thickness of 3 mm.
After a film is formed on a predetermined region on the rewiring layer 18 by solder plating, a heat-treated spherical post 20 is formed, the periphery of which is wrapped with a sealing resin 21 such as epoxy, and the surface is ground on substantially the same surface. The post 20 has an arcuate side surface. External terminals 2 with solder balls mounted on the exposed head
2 is formed by welding on the desired post 20. The internal elements are electrically connected to the external terminals 22 via the pads 12, the redistribution layer 18, the spherical posts 20, and the like.
【００３１】次に、第１の実施の形態に係る半導体装置
の製造方法を説明する。図２及び図３は、これを工程順
に説明するための概略断面図である。Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. FIG. 2 and FIG. 3 are schematic cross-sectional views for explaining this in the order of steps.
【００３２】図２（Ａ）に示すように、まず半導体素子
等が形成されたシリコン基板１１にパッド１２を含むＡ
ｌ合金の最終配線と、プラズマＣＶＤによってシリコン
窒化膜等の保護絶縁層１３を１０００ｎｍ程度成膜し、
所望領域の該絶縁層１３を選択エッチングして開孔す
る。更に応力緩和のため厚みが数十〜１００μｍ程度の
ポリイミド層１４を成膜しパッド開孔部を選択除去す
る。保護絶縁層１３とポリイミド層１４は同一フォトマ
スクで選択開孔すると、パッド１２までの段差形状が厳
しくなり、テーパー化しても後述する再配線工程での段
切れを生ずるので、別工程で行なうのが良く、更に感光
性ポリイミドを用いると工程が簡略化される。次いで、
数十〜１００ｎｍ程度のＴｉＷ，１００〜１０００ｎｍ
程度のＣｕを連続スパッタして密着層１５及びシード層
１６を形成した後、フォトレジスト１７をパターニング
しここに数百〜数千ｎｍ程度の厚みのＣｕを選択電界メ
ッキし再配線層１８を形成する。密着層１５は、ＴｉＷ
の他にＣｒ，Ｎｉ，Ｔｉ，ＴｉＣｕ,Ｐｔ等高融点金属
やその合金を適用しても良い。またシード層１６にはＣ
ｕの他にＮｉ、ＡｇやＡｕもしくはこれらの合金も適用
できる。As shown in FIG. 2A, a silicon substrate 11 on which semiconductor elements and the like are formed is
l-alloy final wiring and a protective insulating layer 13 such as a silicon nitride film by plasma CVD with a thickness of about 1000 nm,
The insulating layer 13 in a desired region is selectively etched to form a hole. Further, a polyimide layer 14 having a thickness of about several tens to 100 μm is formed for stress relaxation, and the pad opening is selectively removed. When the protective insulating layer 13 and the polyimide layer 14 are selectively opened with the same photomask, the step shape up to the pad 12 becomes severe, and even if the taper is formed, a step break occurs in a rewiring step described later. The use of a photosensitive polyimide simplifies the process. Then
TiW of several tens to 100 nm, 100 to 1000 nm
After forming the adhesion layer 15 and the seed layer 16 by continuous sputtering of about Cu, the photoresist 17 is patterned, and Cu having a thickness of about several hundreds to several thousand nm is selectively electroplated thereon to form the rewiring layer 18. I do. The adhesion layer 15 is made of TiW
Alternatively, a high melting point metal such as Cr, Ni, Ti, TiCu, Pt or an alloy thereof may be applied. The seed layer 16 has C
In addition to u, Ni, Ag, Au, or an alloy thereof can be applied.
【００３３】次に、図２（Ｂ）に示すように、新らたに
フォト工程でパターニングしたレジスト１９をマスク
に、再配線層１８の所望領域に数十〜１００μｍ程度の
厚みで選択メッキしたハンダポスト２００を成長させ
る。選択メッキは電界法でＰｂ８５〜９７ｗｔ％／Ｓｎ
の組成でなる高温ハンダを成長させた。Ｃｕをポストを
用いる場合には表面酸化皮膜等ができないようにＮｉや
Ａｕやその合金あるいはハンダ等をバリア層として再メ
ッキが必要であったが、ハンダポスト２００の場合は不
要である。その後レシスト１９を剥離し、再配線層１８
をマスクにイオンミーリングを用いて不要領域のシード
層１６と密着層１５を選択除去することで、図２（Ｃ）
に示すように、再配線が各々分離される。この除去工程
には、王水、硝酸第二セリウムアンモニウムや水酸化カ
リウムの水溶液等のウエットエッチでも良いが、再配線
を構成する各金属層のサイドエッチやハンダポスト２０
０の厚み減少を考慮するとドライエッチャーやミーリン
グ等によるエッチバックが好ましい。Next, as shown in FIG. 2B, a desired region of the rewiring layer 18 is selectively plated with a thickness of several tens to 100 μm using a resist 19 newly patterned in a photo process as a mask. The solder post 200 is grown. Selective plating is Pb 85-97 wt% / Sn by electric field method.
A high-temperature solder having the following composition was grown. When Cu is used as a post, replating is required using Ni, Au, an alloy thereof, solder, or the like as a barrier layer so that a surface oxide film or the like cannot be formed. However, the solder post 200 does not require replating. Thereafter, the resist 19 is peeled off, and the rewiring layer 18 is removed.
2C by selectively removing the seed layer 16 and the adhesion layer 15 in unnecessary regions by using ion milling with the mask shown in FIG.
As shown in FIG. This removal step may be a wet etch of aqua regia, an aqueous solution of ceric ammonium nitrate or potassium hydroxide, but may be a side etch of each metal layer constituting the rewiring or a solder post.
Considering the thickness reduction of 0, etch back by dry etcher, milling or the like is preferable.
【００３４】続いて、図３（Ａ）に示すように、必要に
応じてフラックスを塗布し、１８０〜２３０℃程度の窒
素雰囲気中で数〜１０分ほど熱処理をするとハンダポス
ト２００がフローされて球状ポスト２０が形成される。
この時の形状や大きさは、パターン寸法，膜厚と組成及
び温度と時間に依存する。ハンダポスト２００のパター
ンの幅は数十〜数百μｍで選択したが、平面形状は、正
方形に限らず長方形や多角形等、パッド１２と同様に多
様化出来る。更に、図３（Ｂ）に示すように、モールド
装置によって、エポキシ等の封止樹脂２１で球状ポスト
を覆い、続いてグラインダーで球状ポスト２０が露出す
るように研削する。この時の研削量の管理は、球状ポス
ト２０の頂点から最大径に達するまでの距離の１／５〜
４／５の範囲として、研削量のマージンは従来のＣｕを
ポストを用いる場合より十分に大きくできた。ここで
は、球状ポスト２０が封止樹脂２１で上面から包まれる
かたちとすることがポイントである。尚、樹脂の研削に
はグラインダーを用いたがウエーハ状のシリコン基板全
面を一括機械研磨する方式あるいは、酸素やＣＦ4ある
いはＮＦ3もしくはこれらの混合ガスを用いたドライエ
ッチャーによるエッチバックも応用可能である。Subsequently, as shown in FIG. 3 (A), a flux is applied as required, and a heat treatment is performed for several to 10 minutes in a nitrogen atmosphere at about 180 to 230 ° C., so that the solder post 200 flows. A spherical post 20 is formed.
The shape and size at this time depend on the pattern dimensions, film thickness and composition, and temperature and time. The width of the pattern of the solder post 200 is selected in the range of several tens to several hundreds μm, but the planar shape can be diversified similarly to the pad 12 such as not only a square but also a rectangle and a polygon. Further, as shown in FIG. 3B, the spherical post is covered with a sealing resin 21 such as epoxy by a molding device, and then ground by a grinder so that the spherical post 20 is exposed. At this time, the grinding amount is controlled by １ ／ of the distance from the top of the spherical post 20 to the maximum diameter.
With a range of 4/5, the margin of the grinding amount could be made sufficiently larger than in the case where the conventional Cu post was used. The point here is that the spherical post 20 is wrapped from the upper surface with the sealing resin 21. Although a grinder is used for grinding the resin, a method of mechanically polishing the entire surface of a wafer-shaped silicon substrate at a time, or an etch-back by a dry etcher using oxygen, CF4, NF3, or a mixed gas thereof can also be applied.
【００３５】次に、図３（Ｃ）に示すように、必要に応
じフラックスを塗布し、Ｐｂ／Ｓｎ６０〜７０ｗｔ％ハ
ンダボール２２０を自動移載機で必要なポスト２０上に
配置し、１７０〜２００℃程度の熱処理でリフローさせ
ると、図１に示すような球状ポスト２０と溶着した外部
端子２２が形成される。ハンダボール２２０の大きさ
は、ＢＧＡ（Boll Grid Array）用に１５０〜３００μ
ｍ径を用いたが、用途によって特に限定されない。外部
端子２２用のハンダは、ポスト２０に用いるハンダより
融点の低い材料を用いた方が、リフロー時のポストの変
形が少なく、その結果外部端子形状のばらつきが少な
い。又ハンダボール２２０を搭載する代わりに、印刷
法、メッキ法やメタルジェット法による外部端子用のハ
ンダ層の形成も考えられるが、工数やコスト、形状再現
性はボール搭載法に劣る。Next, as shown in FIG. 3 (C), a flux is applied as required, and a Pb / Sn 60 to 70 wt% solder ball 220 is placed on the necessary post 20 by an automatic transfer machine. When reflow is performed by heat treatment at about 200 ° C., the external terminals 22 welded to the spherical posts 20 as shown in FIG. 1 are formed. The size of the solder ball 220 is 150 to 300 μm for BGA (Boll Grid Array).
Although the m diameter was used, it is not particularly limited depending on the application. When the solder for the external terminals 22 is made of a material having a lower melting point than the solder used for the posts 20, deformation of the posts at the time of reflow is small, and as a result, variations in the shapes of the external terminals are small. Instead of mounting the solder balls 220, a solder layer for external terminals may be formed by a printing method, a plating method, or a metal jet method, but the man-hour, cost, and shape reproducibility are inferior to those of the ball mounting method.
【００３６】第１の実施の形態によれば、ポスト２０の
側面は弓形を保って封止樹脂２１で包み込まれるように
固定されている。従って後工程で生ずる各方向からの応
力に対しても、ポスト２０の密着力が確保され、特に従
来に比べ引っ張り方向の応力に対する密着力は大幅に改
善され、歩留まりや信頼性の向上が図れた。又、ポスト
２０の形成においては、厚いＣｕ層やバリア層のメッキ
やフォト工程を必要とせず、スループットやコストの改
善がなされる。又、バリア層がないので、樹脂封止後の
研削量の制御管理が容易となり歩留まりと量産性の向上
が図れた。更に外部端子２２を構成する材料の融点をポ
スト２０の構成材料のそれより低くし、外部端子の形状
安定化も含めマザーボード等へのＣＳＰ装着歩留まりと
信頼性が確保される。According to the first embodiment, the side surface of the post 20 is fixed so as to be wrapped with the sealing resin 21 while maintaining the bow shape. Accordingly, the adhesion of the post 20 is ensured even with respect to stresses from various directions generated in the post-process, and the adhesion with respect to the stress in the pulling direction is greatly improved, and the yield and reliability are improved. . Further, in forming the post 20, the plating and the photo step of the thick Cu layer and the barrier layer are not required, and the throughput and the cost are improved. In addition, since there is no barrier layer, control and control of the grinding amount after resin sealing are facilitated, and the yield and mass productivity are improved. Further, the melting point of the material forming the external terminal 22 is made lower than that of the material forming the post 20, and the yield and reliability of CSP mounting on a motherboard or the like, including the stabilization of the shape of the external terminal, are secured.
【００３７】この他、図２（Ｂ）におけるハンダポスト
２００の形成工程において、パッド１２領域の再配線層
１８上にも、ポストパターンを同時に形成した半導体装
置も製造したが、後工程で生じるパッド１２周辺領域で
の再配線の密着不良やクラック等が低減した。又パッド
１２からの再配線を構成する各スパッタ層の厳しいステ
ップカバレージをポスト材で補うことができ、段切れ不
良を低減することができた。ここのポストは外部端子を
搭載する必要はないので、他の部署のポストより面積の
小さなパターンを一括フォトリソで形成し、第１の熱処
理でパッド開孔部に沈むような形態にすると封止樹脂を
研削する際に、表面が露出しない状態のポストとでき
る。又、フォトパターンの大きさを調整してここのポス
トに外部端子を搭載し、補強用端子もしくは機能チェッ
ク用端子として活用しても良い。In addition, in the step of forming the solder post 200 in FIG. 2B, a semiconductor device in which a post pattern is simultaneously formed on the redistribution layer 18 in the region of the pad 12 is also manufactured. In the area around No. 12, poor re-wiring adhesion and cracks were reduced. In addition, the severe step coverage of each sputter layer constituting the rewiring from the pad 12 could be compensated for by the post material, and the disconnection failure could be reduced. Since there is no need to mount external terminals on the posts here, a pattern smaller in area than posts in other departments is formed by collective photolithography, and when the first heat treatment is performed to sink into the pad opening, the sealing resin When grinding, a post whose surface is not exposed can be formed. Alternatively, the size of the photo pattern may be adjusted to mount an external terminal on the post, and the post may be used as a reinforcing terminal or a function checking terminal.
【００３８】（他の実施の形態）熱処理でハンダポスト
２００を球状化する際に、フラックスの塗布条件や材料
あるいは再配線層１８の表面状態によって、該再配線層
上１８をハンダが流れて、結果的に球状ポスト２０の高
さがばらつく場合がまれにあった。これを防ぐ方法とし
て、図４に示すように、ハンダポスト２００を成長する
前に、予め再配線層１８と異なるＮｉやＡｕ等の異種金
属を、数十ｎｍ程度の厚みで薄くメッキしたベース層２
３を施した。その結果、従来のようなハンダ流れが皆無
になりポスト２０形状の安定化が図れた。(Other Embodiments) When the solder post 200 is spheroidized by heat treatment, the solder flows on the rewiring layer 18 depending on the conditions of application of the flux, the material, or the surface condition of the rewiring layer 18. As a result, the height of the spherical post 20 sometimes varies. As a method for preventing this, as shown in FIG. 4, before growing the solder post 200, a different layer metal such as Ni or Au, which is different from the redistribution layer 18, is thinly plated to a thickness of about several tens of nm beforehand. 2
3 was given. As a result, the conventional solder flow is eliminated, and the shape of the post 20 is stabilized.
【００３９】又、第１の実施の形態では外部端子となる
Ｐｂ／Ｓｎ６０ｗｔ％程度でなるハンダボールを用いた
が、これに代えて、図５に示すように、内部に融点の高
いＮｉ核５０を含み、外周が従来のハンダ材で覆われた
ボールを試作適用した結果、従来の場合に比べ外部端子
２２の形状の安定化が図れた。ＣＳＰを装着する工程に
おいては、ハンダ溶着の際に核の浮遊運動によって、相
手マザーボードの配線高さがばらついても確実な接触と
固定が確保され、その結果溶着圧力や温度制御マージン
が広がり、ボードへの装着歩留まりの向上が図れた。In the first embodiment, a solder ball of about 60 wt% of Pb / Sn used as an external terminal is used. However, instead of this, as shown in FIG. As a result of trial application of a ball whose outer periphery is covered with a conventional solder material, the shape of the external terminal 22 was stabilized as compared with the conventional case. In the process of mounting the CSP, the floating movement of the nucleus during solder welding ensures secure contact and fixation even if the wiring height of the mating motherboard varies, resulting in a wider welding pressure and temperature control margin, The mounting yield on the device was improved.
【００４０】この他、再配線層１８を形成後、図６
（Ａ）に示すように、フォト工程で、ハンダポスト２０
０を形成する領域の更に内部にパターンレジスト１９０
を形成しておき、従来法と同じようにＣｕポスト３０と
Ｎｉのバリア層３１を選択メッキし、中空ポストを形成
する。その後レシスト１９及び１９０を剥離し、再配線
層１８をマスクにイオンミーリングを用いて不要領域の
シード層１６と密着層１５を選択除去して再配線を各々
分離した。その後、必要に応じフラックスを塗布してか
ら、ハンダボール２２０を自動移載機で所望する中空ポ
スト上に配置し、１７０〜２００でリフローさせると、
図６（Ｂ）に示すように、中空ポストと溶着した外部端
子２２が形成される。次にエポキシ等の封止樹脂２１を
塗布した後、酸素やＣＦ4の混合ガスを用いたドライエ
ッチャーでエッチバックし、外部端子２２を露出し、図
６（Ｃ）に示すような半導体装置を製造した。この結果
ポストが中空形状でメッキコストの更る低減が図れ、且
つ外部端子とポストとの密着面積が増し強度が大きくな
った。又、内部へ流れるハンダ量を調整することや、中
空ポストを構成する板厚４０を調整することでポストに
柔軟性を持たせ封止樹脂が硬化する際の応力を緩和し、
ポスト直下の半導体素子への影響を防ぎ、ＣＳＰ型の半
導体装置の信頼性が確保できる効果もある。In addition, after the rewiring layer 18 is formed,
As shown in (A), in the photo process, the solder post 20
Pattern resist 190 further inside the region where
Is formed, and the Cu post 30 and the Ni barrier layer 31 are selectively plated as in the conventional method to form a hollow post. Thereafter, the resists 19 and 190 were peeled off, and the seed layer 16 and the adhesion layer 15 in the unnecessary area were selectively removed by ion milling using the rewiring layer 18 as a mask to separate the rewiring from each other. After that, if necessary, after applying a flux, the solder balls 220 are arranged on a desired hollow post by an automatic transfer machine, and reflowed at 170 to 200,
As shown in FIG. 6B, an external terminal 22 welded to the hollow post is formed. Next, after a sealing resin 21 such as epoxy is applied, it is etched back with a dry etcher using a mixed gas of oxygen and CF4 to expose the external terminals 22, thereby manufacturing a semiconductor device as shown in FIG. did. As a result, the post was hollow and the plating cost was further reduced, and the contact area between the external terminal and the post was increased to increase the strength. Also, by adjusting the amount of solder flowing into the inside, or by adjusting the plate thickness 40 constituting the hollow post, the post is given flexibility to reduce stress when the sealing resin is cured,
There is also an effect that the influence on the semiconductor element immediately below the post is prevented and the reliability of the CSP type semiconductor device can be secured.
【００４１】尚、再配線層１８，球状ポスト２０や外部
端子は、電極取り出し用のパッドだけに限らず、各種ダ
ミーパッド上に形成して、装着補強端子等に用いてもさ
しつかえない。The rewiring layer 18, the spherical posts 20, and the external terminals are not limited to the pads for taking out the electrodes, but may be formed on various dummy pads and used as mounting reinforcing terminals.
【００４２】又、これまで説明した実施の形態において
は、半導体装置の配線がＡｌ合金で構成されたものにつ
いて説明したが、Ｃｕや高融点金属材料もしくはそれら
の積層や合金配線層で形成されたものでも可能で、さら
に配線層の形成がダマシン法で行われる半導体装置にも
適用できる。特にＣｕを用いたダマシン配線にＣｕやＮ
ｉの再配線を形成する場合は、平坦性やパッド材との密
着相性が良好である。Further, in the above-described embodiments, the case where the wiring of the semiconductor device is made of an Al alloy has been described, but the wiring of the semiconductor device is made of Cu, a high melting point metal material, or a laminate or alloy wiring layer thereof. The present invention is also applicable to a semiconductor device in which a wiring layer is formed by a damascene method. In particular, Cu or N is used for damascene wiring using Cu.
In the case of forming the rewiring of i, the flatness and the close contact compatibility with the pad material are good.
【００４３】更に、実施例での、Ｐｂ／Ｓｎ系ハンダの
ほかに、Ｐｂを含まないハンダ材としてＳｎにＡｇ、Ｃ
ｕやＢｉ等を含む組成のハンダの適用も可能である。Further, in addition to the Pb / Sn-based solder in the embodiment, Sn, Ag, C
It is also possible to apply solder having a composition containing u, Bi, or the like.
【００４４】[0044]
【発明の効果】以上のように、本発明によれば、ウエー
ハレベルのＣＳＰにおて外部端子を搭載するポストをハ
ンダで形成してから球状化処理を行ない、更に該ポスト
を封止樹脂で包むかたちとして、再配線からポストおよ
び外部端子強度を大きくし信頼性の高い半導体装置を、
低コストで供給することができる。更にハンダ外部端子
内部に、該ハンダ材より高い融点の金属核を保有させる
ことやハンダポスト直下に再配線材と異種金属のベース
層を挟むこと等により、各構成部材の形状ばらつきを抑
え、ＣＳＰをマザーボードへ搭載する際の歩留まり向上
や、半導体素子へ加わる応力緩和が図れ、量産性に富ん
だ微細ＣＳＰ型の半導体装置を供給できる。As described above, according to the present invention, a post for mounting an external terminal is formed on a wafer-level CSP by soldering, and then a spheroidizing process is performed. As a form of wrapping, a highly reliable semiconductor device that increases the strength of posts and external terminals from rewiring,
It can be supplied at low cost. Further, by holding a metal nucleus having a higher melting point than the solder material inside the solder external terminal or by sandwiching a rewiring material and a base layer of a dissimilar metal immediately below the solder post, the shape variation of each component is suppressed, and the CSP It is possible to improve the yield when mounting the semiconductor device on a motherboard and relieve the stress applied to the semiconductor element, thereby providing a fine CSP type semiconductor device with high mass productivity.
【図１】本発明の第１の実施の形態に係わる半導体装置
の断面構造面である。FIG. 1 is a sectional structural view of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施の形態に係わる半導体装置
の製造方法の一例を工程順に示す断面構造図である。FIG. 2 is a sectional structural view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.
【図３】図２に示す工程に続いて行われる本発明の第１
の実施の形態に係わる半導体装置の製造方法の一例を工
程順に示す断面構造図である。FIG. 3 shows a first embodiment of the present invention performed after the step shown in FIG. 2;
FIG. 13 is a cross-sectional structure diagram illustrating an example of a method for manufacturing a semiconductor device according to the embodiment in the order of steps.
【図４】本発明の他の実施の形態に係わる半導体装置の
製造方法の一例を示す断面構造図である。FIG. 4 is a sectional view showing an example of a method for manufacturing a semiconductor device according to another embodiment of the present invention.
【図５】本発明の更に他の実施の形態に係わる半導体装
置の製造方法の一例を断面構造図である。FIG. 5 is a sectional view showing an example of a method for manufacturing a semiconductor device according to still another embodiment of the present invention.
【図６】本発明の更に他の実施の形態に係わる半導体装
置の製造方法の一例の工程順を示す断面構造図である。FIG. 6 is a cross-sectional structure diagram showing a process order of an example of a method for manufacturing a semiconductor device according to still another embodiment of the present invention.
【図７】従来の半導体装置の製造方法の一例を工程順に
示す断面構造図である。FIG. 7 is a sectional structural view showing an example of a conventional method for manufacturing a semiconductor device in the order of steps.
【図８】図７に示す工程に続いて行われる従来の半導体
装置の製造方法の一例を工程順に示す断面構造図であ
る。8 is a cross-sectional structure view showing an example of a conventional method for manufacturing a semiconductor device performed after the step shown in FIG. 7 in the order of steps;
１１ シリコン基板 １２ パッド １３ 保護絶縁層 １４ ポリイミド層 １５ 密着層 １６ シード層 １７、１９，１９０ レシスト １８ 再配線層 ２０ 球状ポスト ２１ 封止樹脂 ２２ 外部端子 ２３ ベース層 ３０ Ｃｕポスト ３１ バリア層 ４０ 板厚 ５０ 核 ２００ ハンダポスト ２２０ ハンダボール Reference Signs List 11 silicon substrate 12 pad 13 protective insulating layer 14 polyimide layer 15 adhesion layer 16 seed layer 17, 19, 190 resist 18 redistribution layer 20 spherical post 21 sealing resin 22 external terminal 23 base layer 30 Cu post 31 barrier layer 40 plate thickness 50 core 200 solder post 220 solder ball
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/92 ６０３Ｄ ６０４Ｈ Ｆターム(参考） 5F033 HH07 HH11 HH12 HH13 HH14 HH17 HH18 HH23 JJ07 JJ11 JJ12 JJ13 JJ14 JJ17 JJ18 JJ23 KK07 KK08 KK11 KK12 KK13 KK14 KK17 KK18 KK23 MM08 MM17 NN30 PP15 PP27 QQ09 QQ11 QQ14 QQ19 QQ27 QQ30 QQ31 QQ37 QQ46 QQ73 QQ75 RR06 RR21 RR22 RR27 SS15 VV07 XX14 XX33 XX34 5F061 AA01 BA07 CA21 CB13 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (reference) H01L 21/92 603D 604H F term (reference) 5F033 HH07 HH11 HH12 HH13 HH14 HH17 HH18 HH23 JJ07 JJ11 JJ12 JJ13 JJ14 JJ17 JJ18 KK08 KK11 KK12 KK13 KK14 KK17 KK18 KK23 MM08 MM17 NN30 PP15 PP27 QQ09 QQ11 QQ14 QQ19 QQ27 QQ30 QQ31 QQ37 QQ46 QQ73 QQ75 RR06 RR21 RR22 RR27 SS15 VV07 XX14 XX33 CB34A21A
Claims (14)
も以下の工程（ａ）〜（ｅ）を含むことを特徴とする半
導体装置の製造方法。 （ａ）最終配線パッドから電極引き出し用の再配線層を
施す工程 （ｂ）前記再配線層の所望領域にハンダポストをメッキ
形成する工程 （ｃ）熱処理によって、前記ハンダポストの少なくとも
側面を球状化する工程 （ｄ）樹脂にて封止を行った後に、前記樹脂の所望量を
除去し前記ポストの一部を露出させる工程、及び （ｅ）露出したポスト上に外部端子を形成する工程。1. A method of manufacturing a semiconductor device, comprising at least the following steps (a) to (e). (A) a step of applying a redistribution layer for leading an electrode from the final wiring pad; (b) a step of plating a solder post in a desired area of the redistribution layer; and (c) at least a side surface of the solder post is made spherical by heat treatment. (D) a step of removing a desired amount of the resin and exposing a part of the post after sealing with a resin; and (e) forming an external terminal on the exposed post.
開孔部上の再配線層引き出し領域にも選択メッキ形成さ
れていることを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (b), the solder post is selectively plated also in a rewiring layer lead-out area on a pad opening. Method.
レジストをマスクに再配線層金属とは異種の金属を選択
メッキした後に、続けてハンダ層を選択メッキして形成
されていることを特徴とする半導体装置の製造方法。3. The solder post according to claim 1, wherein in the step (b), the solder post is formed by selectively plating a metal different from the rewiring layer metal using a photoresist as a mask, and then selectively plating the solder layer. A method for manufacturing a semiconductor device, comprising:
ら球状ハンダポストの最大径に達するまでとすることを
特徴とする半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), the amount of the resin removed is from the upper surface to the maximum diameter of the spherical solder post.
トより融点の低い組成材料でなることを特徴とする半導
体装置の製造方法。5. The method according to claim 1, wherein in the step (e), the external terminal is made of a composition material having a lower melting point than a solder post.
固片化する工程をさらに有することを特徴とする半導体
装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 1, further comprising, after the step (e), a step of performing dicing to singulate chips.
あって、最終配線のパッド開孔部から再配線層を施し、
前記再配線層の所望領域に封止樹脂で一部を囲まれた球
状ポストを有し、前記球状ポストの上に外部端子が形成
されてなることを特徴とする半導体装置。7. A semiconductor device of a chip size package type, wherein a rewiring layer is formed from a pad opening of a final wiring,
A semiconductor device having a spherical post partially surrounded by a sealing resin in a desired region of the rewiring layer, and external terminals formed on the spherical post.
する半導体装置。8. The semiconductor device according to claim 7, wherein said semiconductor device is a semiconductor wafer.
成された後に半導体チップ毎に固片化されてなることを
特徴とする半導体装置。9. The semiconductor device according to claim 7, wherein the semiconductor device is solidified for each semiconductor chip after the rewiring layer, the spherical posts, and the external terminals are formed.
記再配線層、前記球状ポスト、及び前記外部端子が形成
されてなることを特徴とする半導体装置。10. The semiconductor device according to claim 7, wherein the rewiring layer, the spherical posts, and the external terminals are formed after solidifying the semiconductor wafer for each semiconductor chip.
いることを特徴とする半導体装置。11. The semiconductor device according to claim 7, wherein said spherical post is formed of solder by a plating method.
であって、樹脂で覆われるポスト側面の形状は、シリコ
ン基板に対して少なくとも一部が垂直でない領域を持つ
ことを特徴とする半導体装置。12. A semiconductor device of a chip size package type, wherein a shape of a side surface of a post covered with a resin has a region at least partly not perpendicular to a silicon substrate.
であって、外部端子を搭載するポストが、中空形状とな
っていることを特徴とする半導体装置。13. A semiconductor device of a chip size package type, wherein a post for mounting an external terminal has a hollow shape.
であって、外部端子は、表面がハンダ材で構成され、内
部に前記ハンダ材より融点の高い金属核を有することを
特徴とする半導体装置。14. A semiconductor device of a chip size package type, wherein an external terminal has a surface made of a solder material and a metal core having a melting point higher than that of the solder material inside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000055863A JP2001244372A (en) | 2000-03-01 | 2000-03-01 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000055863A JP2001244372A (en) | 2000-03-01 | 2000-03-01 | Semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001244372A true JP2001244372A (en) | 2001-09-07 |
Family
ID=18576913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000055863A Pending JP2001244372A (en) | 2000-03-01 | 2000-03-01 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001244372A (en) |
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| CN115693101A (en) * | 2022-12-30 | 2023-02-03 | 中国电子科技集团公司信息科学研究院 | W-band transmit-receive integrated phased array packaged antenna and manufacturing process |
| CN115693101B (en) * | 2022-12-30 | 2023-03-28 | 中国电子科技集团公司信息科学研究院 | W-band transmit-receive integrated phased array packaged antenna and manufacturing process |
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