JP2001230547A - Method for manufacturing wiring board - Google Patents
Method for manufacturing wiring boardInfo
- Publication number
- JP2001230547A JP2001230547A JP2000036066A JP2000036066A JP2001230547A JP 2001230547 A JP2001230547 A JP 2001230547A JP 2000036066 A JP2000036066 A JP 2000036066A JP 2000036066 A JP2000036066 A JP 2000036066A JP 2001230547 A JP2001230547 A JP 2001230547A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- holding plate
- manufacturing
- conductor layer
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は，導体層と絶縁層と
を積層してなる配線板を製造する方法に関するものであ
る。さらに詳細には，導体層のパターン等の位置および
寸法精度の向上を図った配線板の製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board formed by laminating a conductor layer and an insulating layer. More specifically, the present invention relates to a method for manufacturing a wiring board which improves the position and dimensional accuracy of a pattern and the like of a conductor layer.
【０００２】[0002]
【従来の技術】従来より，多層構造の配線板がビルドア
ップによって製造されている。すなわち，樹脂の両面に
導体層を有するコア基板を用意し，導体層をパターニン
グする。そして，その外側に順次，層間絶縁層及び導体
層を積層していくのである。また，必要に応じて導体層
と他の導体層の間にビアホール等を適宜設ける。しかし
ながら，上記のような配線板の製造方法では，導体層の
パターンやビアホールの位置精度が低いという問題点が
ある。コア基板の材料が樹脂であるため，コア基板に対
してプレス等の熱的な処理を行うと，コア基板が熱膨張
により伸縮し，その状態で導体層のパターン形成や，層
間絶縁層のビアホールの形成がなされてしまうからであ
る。2. Description of the Related Art Hitherto, a wiring board having a multilayer structure has been manufactured by build-up. That is, a core substrate having a conductor layer on both surfaces of a resin is prepared, and the conductor layer is patterned. Then, an interlayer insulating layer and a conductor layer are sequentially laminated on the outside thereof. Also, a via hole or the like is appropriately provided between the conductor layer and another conductor layer as needed. However, the method for manufacturing a wiring board as described above has a problem that the positional accuracy of the pattern of the conductor layer and the via hole is low. Since the core substrate is made of resin, if the core substrate is subjected to thermal treatment such as pressing, the core substrate expands and contracts due to thermal expansion. Is formed.
【０００３】[0003]
【発明が解決しようとする課題】そこで本発明は，位置
および寸法精度よく導体層のパターン等を形成できる配
線板の製造方法を提供することを課題とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a wiring board which can form a pattern of a conductor layer with high accuracy in position and dimensions.
【０００４】[0004]
【課題を解決するための手段】この課題の解決を目的と
してなされた本発明は，導体パターンと層間絶縁層とを
交互に積層する配線板の製造方法であって，剛性のある
材質の保持板の上に加熱加圧プロセスを用いて導体パタ
ーンおよび層間絶縁層を積層する工程（１）と，工程
（１）より後で保持板と積層物とを分離する工程（２）
とを含んでいる。ここで剛性のある材質のものとは，樹
脂等と比較して機械的強度に優れた材料を指す。具体的
には，ステンレス鋼や普通鋼等の金属系の材料が該当す
る。この種の材料は一般的に，樹脂材と比較して機械的
強度に優れるだけでなく熱膨張率も小さく，寸法の安定
性に優れている。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a wiring board in which conductor patterns and interlayer insulating layers are alternately laminated, and wherein a holding plate made of a rigid material is provided. (1) laminating a conductor pattern and an interlayer insulating layer on the substrate by using a heating and pressing process, and (2) separating a holding plate and a laminate after the step (1)
And Here, a material having rigidity refers to a material having a higher mechanical strength than a resin or the like. Specifically, a metallic material such as stainless steel or ordinary steel corresponds to this. This type of material generally has not only excellent mechanical strength but also a low coefficient of thermal expansion and excellent dimensional stability as compared with resin material.
【０００５】この方法では，導体パターンや層間絶縁層
の積層が，剛性のある保持板上で行われるので，ホット
プレスのような加熱加圧プロセスを経ても寸法精度が安
定している。よって，導体パターンや層間接続構造の位
置および寸法精度が高い配線板が製造される。なお，保
持板自体は配線板の一部をなすものではないので，後に
除去される。In this method, since the lamination of the conductor pattern and the interlayer insulating layer is performed on a rigid holding plate, the dimensional accuracy is stable even after a heating and pressing process such as a hot press. Therefore, a wiring board having a high position and dimensional accuracy of the conductor pattern and the interlayer connection structure is manufactured. Since the holding plate itself does not form a part of the wiring board, it is removed later.
【０００６】さらに本発明の配線板の製造方法において
は，工程（１）を，２枚の剛性のある保持板上にそれぞ
れ固定的に保持された導体パターンを，層間絶縁層を間
に挟んで対面させて行うことが望ましい。このようにす
ると，各導体パターンは，保持板上に位置精度よく形成
され，さらに加熱加圧プロセスにおいてもその位置精度
の高さが保持される。Further, in the method for manufacturing a wiring board according to the present invention, the step (1) is performed by sandwiching a conductive pattern fixedly held on two rigid holding plates with an interlayer insulating layer interposed therebetween. It is desirable to perform it face-to-face. By doing so, each conductor pattern is formed with high positional accuracy on the holding plate, and the high positional accuracy is maintained even in the heating and pressing process.
【０００７】さらに本発明の配線板の製造方法において
は，保持板として導電体を用い，積層された層間絶縁層
にホールを形成するとともに，保持板を電流供給経路と
する電気めっきによりホールを充填して層間接続構造を
形成する工程を含むことが好ましい。このようにする
と，ホールの充填の際，保持板全体を経由して各めっき
箇所に電流が供給される。このため，めっき厚の均一性
がよく，平坦性に優れるめっき結果が得られる。Further, in the method of manufacturing a wiring board according to the present invention, a conductor is used as a holding plate, holes are formed in a laminated interlayer insulating layer, and holes are filled by electroplating using the holding plate as a current supply path. To form an interlayer connection structure. In this way, when filling the holes, a current is supplied to each plating portion via the entire holding plate. For this reason, a plating result with good uniformity of plating thickness and excellent flatness can be obtained.
【０００８】[0008]
【発明の実施の形態】以下，本発明の配線板の製造方法
を具体化した実施の形態について，添付図面を参照しつ
つ詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying a method for manufacturing a wiring board according to the present invention will be described below in detail with reference to the accompanying drawings.
【０００９】まず，ステンレス鋼によって形成された厚
さ１ｍｍの保持板１を用意する。この保持板１には，図
１中両端の位置にガイド穴１Ａ，１Ａ（５ｍｍφ）が開
けられている。さらに，図中左のガイド穴１Ａよりやや
内側の位置に吸気口１Ｂが開けられている。この保持板
１のガイド穴１Ａ，１Ａにガイドピン１２，１２（５ｍ
ｍφ，ステンレス鋼）を通し，保持板１の上にアルミ箔
４（２０μｍ厚）を配置する。もちろんアルミ箔４にも
ガイド穴１Ａ，１Ａと同じ位置にあらかじめ穴が開けら
れている。そして，吸気口１Ｂから吸気する。すると，
アルミ箔４は保持板１に密着して固定される。First, a 1 mm thick holding plate 1 made of stainless steel is prepared. The holding plate 1 is provided with guide holes 1A, 1A (5 mmφ) at both ends in FIG. Further, an intake port 1B is opened at a position slightly inside the guide hole 1A on the left side in the figure. The guide pins 12, 12 (5 m) are inserted into the guide holes 1 A, 1 A of the holding plate 1.
mφ, stainless steel), and an aluminum foil 4 (20 μm thick) is arranged on the holding plate 1. Of course, holes are also formed in the aluminum foil 4 in advance at the same positions as the guide holes 1A. Then, the air is sucked from the air inlet 1B. Then
The aluminum foil 4 is fixed in close contact with the holding plate 1.
【００１０】次に，アルミ箔４の上に導体層６を積層す
る。この積層は次のように行う。すなわち，アルミ箔４
の表面上にめっきレジスト６Ｅ（２０μｍ厚）を形成し
てから，電気銅めっきを施す。このとき，保持板１およ
びアルミ箔４により通電をとる。すると，めっきレジス
ト６Ｅが形成されていない部分に銅パターン６Ａ，６Ｂ
（２０μｍ厚）が形成される。かくして，図１に示すよ
うに，アルミ箔４の上に導体層６が積層される。かくし
て形成された銅パターン６Ａ，６Ｂは，実質的に保持板
１に固定された状態であり，位置および寸法の精度に優
れている。また，広く保持板１およびアルミ箔４の全体
を電流供給経路として用いるので，めっき速度の速い条
件でめっきしたとしても厚さの均一性に優れている。Next, a conductor layer 6 is laminated on the aluminum foil 4. This lamination is performed as follows. That is, aluminum foil 4
After a plating resist 6E (20 μm thick) is formed on the surface of the substrate, electrolytic copper plating is performed. At this time, electricity is supplied by the holding plate 1 and the aluminum foil 4. Then, the copper patterns 6A and 6B are formed on the portions where the plating resist 6E is not formed.
(Thickness of 20 μm) is formed. Thus, the conductor layer 6 is laminated on the aluminum foil 4 as shown in FIG. The copper patterns 6A and 6B thus formed are substantially fixed to the holding plate 1, and have excellent positional and dimensional accuracy. In addition, since the entire holding plate 1 and the entire aluminum foil 4 are used as a current supply path, even when plating is performed under a condition of a high plating speed, the thickness uniformity is excellent.
【００１１】そして，図１に示したものと同じ（導体層
のパターンを除く）ものをもう１つ用意する。そして図
２に示すように，エポキシ樹脂の層間接着絶縁シート１
０（１００μｍ厚）を間に挟み込みつつ両者の導体層
６，９同士を対面させてホットプレスする。このとき，
導体層６，９がそれぞれ保持板１，７に固定された状態
であるため，プレス時の加熱・加圧にかかわらず位置お
よび寸法の精度が保持される。その後上側の保持板７と
アルミ箔５とを除去すると，図３の状態が得られる。こ
のとき，導体層９中のブランク９Ｃが，導体層６中のパ
ターン６Ａの上方に位置している。Then, another one identical to that shown in FIG. 1 (excluding the pattern of the conductor layer) is prepared. Then, as shown in FIG.
Hot pressing is performed with the two conductor layers 6 and 9 facing each other while sandwiching 0 (100 μm thickness) therebetween. At this time,
Since the conductor layers 6 and 9 are fixed to the holding plates 1 and 7, respectively, the positional and dimensional accuracy is maintained irrespective of heating / pressing at the time of pressing. Thereafter, when the upper holding plate 7 and the aluminum foil 5 are removed, the state of FIG. 3 is obtained. At this time, the blank 9C in the conductor layer 9 is located above the pattern 6A in the conductor layer 6.
【００１２】次に，パターン６Ａとパターン９Ａとの電
気的接続をとるビアホールを形成する。これは次のよう
にして行う。すなわち，ブランク９Ｃをコンフォーマル
マスクとするレーザ加工（ＣＯ2 レーザ等）により層間
絶縁層１０に穴を開け，その穴を電気めっきにより銅で
充填する。このとき，保持板１およびアルミ箔４を電流
供給経路とする。かくして，図４に示すようにビアホー
ル１２が形成される。ここにおいて，保持板１およびア
ルミ箔４の全体を経由して電流が均等に供給されるた
め，高速でめっきできかつめっき厚の面内均一性が高
い。このため，ビアホール１２が複数個ある場合でも場
所による凹凸の問題が生じにくい。また，電気めっき前
に化学めっきを行う必要がない。Next, a via hole for making an electrical connection between the pattern 6A and the pattern 9A is formed. This is performed as follows. That is, holes are formed in the interlayer insulating layer 10 by laser processing (CO 2 laser or the like) using the blank 9C as a conformal mask, and the holes are filled with copper by electroplating. At this time, the holding plate 1 and the aluminum foil 4 are used as a current supply path. Thus, a via hole 12 is formed as shown in FIG. Here, since the current is uniformly supplied through the entire holding plate 1 and the aluminum foil 4, plating can be performed at a high speed and plating uniformity in the surface is high. For this reason, even if there are a plurality of via holes 12, the problem of unevenness depending on the location hardly occurs. Also, there is no need to perform chemical plating before electroplating.
【００１３】なお，ビアホール１２の形成のための穴開
けは，コンフォーマルマスク法に限らずラージウィンド
ウ法でもよいし，銅ダイレクト法でもよい。さらには，
レーザを使わないエッチング法でもよい。また，めっき
の際には，パターン９Ａをめっき液による腐食から保護
する皮膜を穴開け前にあらかじめ形成しておくことが望
ましい。The holes for forming the via holes 12 are not limited to the conformal mask method but may be a large window method or a copper direct method. Moreover,
An etching method that does not use a laser may be used. Further, at the time of plating, it is desirable that a film for protecting the pattern 9A from corrosion by the plating solution is formed before drilling.
【００１４】次に，導体層９の上に層間絶縁層１１およ
び導体層１４を積層する（図５）。この積層は，導体層
６の上に層間絶縁層１０および導体層９を積層したとき
と同様に，図１に示したものと同じものをホットプレス
することにより行う。図５の状態では，導体層９の銅パ
ターン９Ａの上方に導体層１４の銅パターン１４Ａが位
置し，導体層６の銅パターン６Ｂの上方に導体層１４の
銅パターン１４Ｂが位置している。さらに，銅パターン
１４Ａの中にブランク１４Ｃが，銅パターン１４Ｂの中
にブランク１４Ｄが設けられている。Next, an interlayer insulating layer 11 and a conductor layer 14 are laminated on the conductor layer 9 (FIG. 5). This lamination is performed by hot-pressing the same one as shown in FIG. 1, similarly to the case where the interlayer insulating layer 10 and the conductor layer 9 are laminated on the conductor layer 6. In the state of FIG. 5, the copper pattern 14A of the conductor layer 14 is located above the copper pattern 9A of the conductor layer 9, and the copper pattern 14B of the conductor layer 14 is located above the copper pattern 6B of the conductor layer 6. Further, a blank 14C is provided in the copper pattern 14A, and a blank 14D is provided in the copper pattern 14B.
【００１５】次に，銅パターン９Ａと銅パターン１４Ａ
とを電気的に接続するビアホール１６と，銅パターン６
Ｂと銅パターン１４Ｂとを電気的に接続するビアホール
１７とを形成する（図６）。ビアホール１６，１７は，
ビアホール１２を形成したときと同様にレーザ加工と電
気めっきとにより形成する。最後に，ガイドピン１２，
１２を抜いて保持板１から取り外し，さらにアルミ箔４
を導体層６から剥がす。かくして，図７に示す配線板が
製造される。Next, copper pattern 9A and copper pattern 14A
Via hole 16 for electrically connecting the copper pattern 6
A via hole 17 for electrically connecting B and the copper pattern 14B is formed (FIG. 6). Via holes 16 and 17
It is formed by laser processing and electroplating in the same manner as when the via hole 12 is formed. Finally, guide pins 12,
12 and remove it from the holding plate 1 and further remove the aluminum foil 4
Is peeled off from the conductor layer 6. Thus, the wiring board shown in FIG. 7 is manufactured.
【００１６】以上詳細に説明したように本実施の形態で
は，各導体層を，ステンレス鋼の保持板上に固定した状
態で形成するとともに，保持板上に固定された状態のま
まホットプレスして積層している。このため，保持板の
剛性および低熱膨張性により，各導体層における銅パタ
ーンや各ビアホールの位置精度が高い配線板が製造され
ている。また，銅パターンの形成やビアホールの充填の
際に保持板全体を電流供給経路としてめっきするので，
高速めっきが可能でありかつ厚さの均一性にも優れてい
る。かくして，位置および寸法精度よく導体層のパター
ン等を形成できる配線板の製造方法が実現されている。As described in detail above, in the present embodiment, each conductor layer is formed while being fixed on a stainless steel holding plate, and hot pressed while being fixed on the holding plate. Laminated. For this reason, due to the rigidity and low thermal expansion of the holding plate, a wiring board with high positional accuracy of the copper pattern and each via hole in each conductor layer has been manufactured. Also, when forming copper patterns and filling via holes, the entire holding plate is plated as a current supply path.
It is capable of high-speed plating and has excellent thickness uniformity. Thus, a method for manufacturing a wiring board that can form a conductor layer pattern and the like with high positional and dimensional accuracy has been realized.
【００１７】なお，本実施の形態は単なる例示にすぎ
ず，本発明を何ら限定するものではない。したがって本
発明は当然に，その要旨を逸脱しない範囲内で種々の改
良，変形が可能である。The present embodiment is merely an example, and does not limit the present invention. Therefore, naturally, the present invention can be variously modified and modified without departing from the gist thereof.
【００１８】例えば，使用する各部の材料は目的に沿う
ものであれば別のものでも良い。特に，本形態でステン
レス鋼を用いた保持板については，必要な機械的強度と
ある程度の低熱膨張性を持つものなら他の素材でもよ
い。普通鋼も候補の１つであるが，繰り返し使用する場
合の耐食性を考えるとステンレス鋼の方がよい。また，
低熱膨張性に着目すればアンバー合金（インバー，イン
バルともいう）も有力な候補だが，供給の安定性という
点ではステンレス鋼の方が優れる。For example, the material of each part to be used may be different as long as it meets the purpose. In particular, the holding plate made of stainless steel in the present embodiment may be made of another material as long as it has the necessary mechanical strength and a certain degree of low thermal expansion. Plain steel is one of the candidates, but stainless steel is better in terms of corrosion resistance when used repeatedly. Also,
Focusing on low thermal expansion, invar alloys (also known as invar and invar) are promising candidates, but stainless steel is superior in terms of supply stability.
【００１９】また，積層の段数は異なってもよい。積層
の方法は，２段目以上（図６中の導体層９，１４）につ
いては通常のビルドアップ法でもよい。また，保持板上
に最初に貼るアルミ箔に替えて銅箔を用い，これを配線
板における導体層として用いることも考えられる。その
場合，最後に保持板から外してから最初の銅箔をパター
ニングすればよい。Further, the number of layers in the lamination may be different. The stacking method may be an ordinary build-up method for the second and higher layers (the conductor layers 9 and 14 in FIG. 6). It is also conceivable to use a copper foil instead of the aluminum foil to be attached first on the holding plate and use this as a conductor layer in the wiring board. In that case, the first copper foil may be patterned after it is finally removed from the holding plate.
【００２０】さらに，本形態では平板状の保持板を利用
するバッチ処理方式の製造方法を説明したが，reel to
reel法による連続処理も可能である。すなわち，各材料
としてロール状の長尺材を用い，プレスの際にはロール
プレス法を用いるのである。その場合の保持板として
は，厚さ０．１ｍｍ程度のステンレス鋼帯を用いればよ
い。Further, in this embodiment, the manufacturing method of the batch processing method using the flat holding plate has been described.
Continuous processing by the reel method is also possible. That is, a long roll material is used as each material, and a roll press method is used for pressing. In this case, a stainless steel strip having a thickness of about 0.1 mm may be used as the holding plate.
【００２１】[0021]
【発明の効果】以上の説明から明らかなように本発明に
よれば，位置および寸法精度よく導体層のパターン等を
形成できる配線板の製造方法が提供されている。As is apparent from the above description, according to the present invention, there is provided a method of manufacturing a wiring board capable of forming a conductor layer pattern and the like with high accuracy in position and dimensions.
【図１】保持板の上に導体層を形成した状態を示す断面
図である。FIG. 1 is a cross-sectional view showing a state where a conductor layer is formed on a holding plate.
【図２】図１に示すものを２組向き合わせてプレスする
状況を説明する断面図である。FIG. 2 is a cross-sectional view for explaining a situation in which two sets shown in FIG. 1 are pressed together.
【図３】２層目の導体層を積層した状態を示す断面図で
ある。FIG. 3 is a cross-sectional view showing a state in which a second conductive layer is stacked.
【図４】層間絶縁層にビアホールを形成した状態を示す
断面図である。FIG. 4 is a cross-sectional view showing a state where a via hole is formed in an interlayer insulating layer.
【図５】３層目の導体層を積層した状態を示す断面図で
ある。FIG. 5 is a cross-sectional view showing a state where a third conductor layer is stacked.
【図６】層間絶縁層にビアホールを形成した状態を示す
断面図である。FIG. 6 is a cross-sectional view showing a state where a via hole is formed in an interlayer insulating layer.
【図７】製造した配線板を保持板から取り外した状態を
示す断面図である。FIG. 7 is a cross-sectional view showing a state in which the manufactured wiring board is removed from the holding plate.
１，７ 保持板 ６，９，１４ 導体層 １０，１１ 層間絶縁層 １２，１６，１７ ビアホール 1,7 Holding plate 6,9,14 Conductive layer 10,11 Interlayer insulating layer 12,16,17 Via hole
Claims (3)
層する配線板の製造方法において，剛性のある材質の保
持板の上に加熱加圧プロセスを用いて導体パターンおよ
び層間絶縁層を積層する工程（１）と，工程（１）より
後で前記保持板と積層物とを分離する工程（２）とを含
むことを特徴とする配線板の製造方法。In a method of manufacturing a wiring board in which conductive patterns and interlayer insulating layers are alternately stacked, a conductive pattern and an interlayer insulating layer are stacked on a holding plate made of a rigid material using a heating and pressing process. A method for manufacturing a wiring board, comprising: a step (1); and a step (2) of separating the holding plate and the laminate after the step (1).
おいて，前記工程（１）を，２枚の剛性のある保持板上
にそれぞれ固定的に保持された導体パターンを，層間絶
縁層を間に挟んで対面させて行うことを特徴とする配線
板の製造方法。2. The method for manufacturing a wiring board according to claim 1, wherein the step (1) comprises the steps of: forming a conductive pattern fixedly held on two rigid holding plates; A method for manufacturing a wiring board, wherein the method is performed by sandwiching and facing each other.
板の製造方法において，前記保持板として導電体を用
い，積層された層間絶縁層にホールを形成するととも
に，前記保持板を電流供給経路とする電気めっきにより
前記ホールを充填して層間接続構造を形成する工程を含
むことを特徴とする配線板の製造方法。3. The method for manufacturing a wiring board according to claim 1, wherein a conductor is used as the holding plate, a hole is formed in the laminated interlayer insulating layer, and a current is supplied to the holding plate. A method for manufacturing a wiring board, comprising a step of forming an interlayer connection structure by filling the holes by electroplating as a path.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000036066A JP2001230547A (en) | 2000-02-15 | 2000-02-15 | Method for manufacturing wiring board |
| PCT/JP2001/000776 WO2001062055A1 (en) | 2000-02-15 | 2001-02-02 | Method of manufacturing wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000036066A JP2001230547A (en) | 2000-02-15 | 2000-02-15 | Method for manufacturing wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001230547A true JP2001230547A (en) | 2001-08-24 |
Family
ID=18560160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000036066A Pending JP2001230547A (en) | 2000-02-15 | 2000-02-15 | Method for manufacturing wiring board |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2001230547A (en) |
| WO (1) | WO2001062055A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012009839A1 (en) * | 2010-07-20 | 2012-01-26 | Wang Dingfeng | Single-sided circuit board and manufacturing method thereof |
| JP2014225493A (en) * | 2013-05-15 | 2014-12-04 | 矢崎総業株式会社 | Method of manufacturing thick film circuit board |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56155587A (en) * | 1980-05-02 | 1981-12-01 | Fujitsu Ltd | Printed circuit board |
| JPS63150991A (en) * | 1986-12-15 | 1988-06-23 | 松下電工株式会社 | Manufacture of circuit board |
| JPH01246897A (en) * | 1988-03-29 | 1989-10-02 | Sumitomo Bakelite Co Ltd | Manufacture of multilayer printed circuit board |
| JPH06177277A (en) * | 1992-12-08 | 1994-06-24 | Toppan Printing Co Ltd | Manufacture of semiconductor device |
| JPH08139450A (en) * | 1994-11-07 | 1996-05-31 | Toshiba Corp | Manufacturing method of printed-wiring board |
| JPH08204333A (en) * | 1995-01-31 | 1996-08-09 | Toshiba Corp | Manufacture of printed wiring board |
| JPH1070363A (en) * | 1996-08-27 | 1998-03-10 | Toshiba Corp | Method for manufacturing printed wiring board |
-
2000
- 2000-02-15 JP JP2000036066A patent/JP2001230547A/en active Pending
-
2001
- 2001-02-02 WO PCT/JP2001/000776 patent/WO2001062055A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56155587A (en) * | 1980-05-02 | 1981-12-01 | Fujitsu Ltd | Printed circuit board |
| JPS63150991A (en) * | 1986-12-15 | 1988-06-23 | 松下電工株式会社 | Manufacture of circuit board |
| JPH01246897A (en) * | 1988-03-29 | 1989-10-02 | Sumitomo Bakelite Co Ltd | Manufacture of multilayer printed circuit board |
| JPH06177277A (en) * | 1992-12-08 | 1994-06-24 | Toppan Printing Co Ltd | Manufacture of semiconductor device |
| JPH08139450A (en) * | 1994-11-07 | 1996-05-31 | Toshiba Corp | Manufacturing method of printed-wiring board |
| JPH08204333A (en) * | 1995-01-31 | 1996-08-09 | Toshiba Corp | Manufacture of printed wiring board |
| JPH1070363A (en) * | 1996-08-27 | 1998-03-10 | Toshiba Corp | Method for manufacturing printed wiring board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012009839A1 (en) * | 2010-07-20 | 2012-01-26 | Wang Dingfeng | Single-sided circuit board and manufacturing method thereof |
| JP2014225493A (en) * | 2013-05-15 | 2014-12-04 | 矢崎総業株式会社 | Method of manufacturing thick film circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001062055A1 (en) | 2001-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100863091B1 (en) | Hinge board and method for producing the same | |
| US6841738B2 (en) | Printed wiring board having rigid portion and flexible portion, and method of fabricating the board | |
| TWI233765B (en) | Method for manufacturing printed wiring substrates, metal plate for use in manufacturing printed wiring substrates, and multi-printed-wiring-substrate panel | |
| KR100615382B1 (en) | Clad board for printed-circuit board, multilayered printed-circuit board, and method of manufacture thereof | |
| EP2563105B1 (en) | Printed substrate manufacturing method and printed substrate employing same | |
| CN114554712A (en) | Circuit board and manufacturing method thereof | |
| US20140318834A1 (en) | Wiring board and method for manufacturing the same | |
| JP2001230547A (en) | Method for manufacturing wiring board | |
| CN110650597B (en) | Circuit board, manufacturing method thereof and electronic equipment | |
| JP2001326458A (en) | Printed wiring board and its manufacturing method | |
| JP2758603B2 (en) | Manufacturing method of ceramic multilayer wiring board | |
| KR101987378B1 (en) | Method of manufacturing printed circuit board | |
| JPS6223198A (en) | Making of multilayer interconnection board | |
| JP2004158671A (en) | Multilayer board and its producing process | |
| WO2006016474A1 (en) | Method for manufacturing multilayer flex rigid wiring board | |
| JP2007081274A (en) | Flexible circuit substrate | |
| JPS6247199A (en) | Manufacture of inner layer circuit board for multilayer circuit board | |
| JP2000133943A (en) | Manufacture of multilayered board | |
| JP4599745B2 (en) | Method for producing metal-clad laminate | |
| CN113133214A (en) | Method for manufacturing asymmetric copper thick multilayer board | |
| JP6320788B2 (en) | Method for manufacturing flexible printed circuit board and intermediate product used for manufacturing flexible printed circuit board | |
| JP2002314229A (en) | Method for manufacturing flexible printed circuit board | |
| KR20130104507A (en) | The flexible printed circuit board and the method for manufacturing the same | |
| JPH06169172A (en) | Method for manufacturing multilayer printed board | |
| KR20140008184A (en) | Manufacturing method for printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Effective date: 20070115 Free format text: JAPANESE INTERMEDIATE CODE: A621 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091117 |
|
| A521 | Written amendment |
Effective date: 20100113 Free format text: JAPANESE INTERMEDIATE CODE: A523 |
|
| A131 | Notification of reasons for refusal |
Effective date: 20100223 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
| A521 | Written amendment |
Effective date: 20100409 Free format text: JAPANESE INTERMEDIATE CODE: A523 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100511 |