JP2001217275A - Flip-chip mounting structure for semiconductor device - Google Patents

Flip-chip mounting structure for semiconductor device

Info

Publication number
JP2001217275A
JP2001217275A JP2000026275A JP2000026275A JP2001217275A JP 2001217275 A JP2001217275 A JP 2001217275A JP 2000026275 A JP2000026275 A JP 2000026275A JP 2000026275 A JP2000026275 A JP 2000026275A JP 2001217275 A JP2001217275 A JP 2001217275A
Authority
JP
Japan
Prior art keywords
solder
layer
flip
semiconductor device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000026275A
Other languages
Japanese (ja)
Inventor
Kazunari Kuzuhara
一功 葛原
Yasushi Tanaka
恭史 田中
Shigenari Takami
茂成 高見
Ryoko Toyoda
陵子 豊田
Atsushi Makino
篤 牧野
Mitsuo Isagawa
光男 去来川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2000026275A priority Critical patent/JP2001217275A/en
Publication of JP2001217275A publication Critical patent/JP2001217275A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

PROBLEM TO BE SOLVED: To provide a flip-chip mounting structure for a semiconductor device in which the life of a solder bump bonding part under a high-temperature envi ronment is made long. SOLUTION: In the semiconductor device, solder bumps are formed in such a way that barrier layers 3 composed of Cr/Ni/Cu, Cu core layers 4 and layers of solder 5 composed of 20% of Sn and 80% of Pb are laminated sequentially on Al electrodes 2 of a chip 1. The semiconductor device is flip-chip-mounted on a ceramic substrate 9 on which electrodes 80 composed of a tungsten thin film are formed in position facing the solder bumps. By constitution, the movement (diffusion) of Sn to the side of the electrodes 80 on the ceramic substrate 9 from the solder 5 is eliminated. A drop in the concentration of the Sn in the solder 5 is delayed. As a result, the formation of a void due to a shortage of Sn can be delayed, and the life of the solder bump bonding part can be extended as compared with conventional case.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半田バンプを用い
たＩＣのような半導体装置のフリップチップ実装構造に
関するものである。The present invention relates to a flip-chip mounting structure of a semiconductor device such as an IC using solder bumps.

【０００２】[0002]

【従来の技術】半導体装置（半導体素子）と回路基板と
を電気的接続する手段として、ワイヤボンディングが一
般的である。しかしながら近年ではより高密度に実装で
き、更に電気信号の高速処理が可能となるフリップチッ
プボンディング（ＦＣＢ）や、テープオートメイテッド
ボンディング（ＴＡＢ）が注目されている。 一方近
年、車載用の半導体装置の分野では高耐熱化(１５０℃
以上)が求められており、特に半導体装置と回路基板と
の接合部の高温での信頼性確保が課題である。2. Description of the Related Art Wire bonding is generally used as means for electrically connecting a semiconductor device (semiconductor element) to a circuit board. However, in recent years, attention has been focused on flip chip bonding (FCB) and tape automated bonding (TAB), which can be mounted at a higher density and can further process electric signals at high speed. On the other hand, in recent years, in the field of in-vehicle semiconductor devices, high heat resistance (150 ° C.
Above), and in particular, ensuring the reliability of the junction between the semiconductor device and the circuit board at high temperatures is an issue.

【０００３】このような課題に答えるものとして高温対
応のＦＣＢが採用される場合がある。As a solution to such a problem, there is a case where a high-temperature-compatible FCB is adopted.

【０００４】以下に従来の高温対応のフリップチップ実
装の工程を図７に示す工程順によって説明する。 （バンプ形成工程＜図７の（ａ）＞）フリップチップ実
装に関して、メッキ法等によるウェハプロセスを応用し
たメッキバンプがある。これは、ＩＣを構成する半導体
装置のチップ１のＡｌ電極（組成がＡｌ９９％、Ｓｉ１
％のもので、以下Ａｌ電極と言う）２上に半田との接合
性を向上させるため、ＵＢＭと呼ばれるバリア層３を形
成する。このバリア層３は主にＣｒ／Ｎｉ／Ｃｕにより
構成されている。さらに、チップ１の接合時にギャップ
が狭くならないように、ＣｕメッキをしてＣｕコア層４
とする。A conventional high-temperature compatible flip-chip mounting process will be described below with reference to a process sequence shown in FIG. (Bump Forming Step <FIG. 7A>) Regarding flip chip mounting, there is a plated bump to which a wafer process such as a plating method is applied. This is because the Al electrode of the chip 1 of the semiconductor device constituting the IC (composition: Al 99%, Si 1
%, Hereinafter referred to as an Al electrode) 2 to form a barrier layer 3 called UBM in order to improve the bondability with solder. This barrier layer 3 is mainly composed of Cr / Ni / Cu. Further, Cu plating is performed so that the gap does not become narrow when the chip 1 is joined.
And

【０００５】その後、半田５をメッキにて形成する。半
田５の組成としては、ＳｎＰｂ系が用いられ、高温対応
として、例えばＳｎ２０％、Ｐｂ８０％のものがある。After that, the solder 5 is formed by plating. As the composition of the solder 5, SnPb-based is used, and for high-temperature compatibility, there are, for example, Sn20% and Pb80%.

【０００６】このようにしてチップ１に半田バンプが形
成される。このとき半田５の層とＣｕコア層４との界面
に極々薄いＣｕ6Ｓｎ5の合金層６が形成される。 （フリップチップ実装工程＜図７の（ｂ）＞）次に、チ
ップ１に半田バンプを上記方法で形成した後、チップ１
を反転させて半田バンプにフラックス７を転写し、Ａｇ
Ｐｔ厚膜ペーストにて回路の電極８を形成したセラミッ
ク基板９の実装位置に搭載する。[0006] In this manner, solder bumps are formed on the chip 1. At this time, an extremely thin Cu 6 Sn 5 alloy layer 6 is formed at the interface between the layer of the solder 5 and the Cu core layer 4. (Flip Chip Mounting Step <FIG. 7B>) Next, after forming solder bumps on the chip 1 by the above-described method,
Is reversed to transfer flux 7 to the solder bumps, and Ag
The Pt thick film paste is mounted on the mounting position of the ceramic substrate 9 on which the circuit electrodes 8 are formed.

【０００７】この時フラックス７の粘性を利用して、チ
ップ１を仮止めする。 （リフロー工程＜図７の（ｃ）＞）次に、空気又は窒素
雰囲気で、半田（半田バンプ）溶融温度以上になるよう
に加熱する。なお、窒素雰囲気の場合、半田５の酸化防
止効果により、半田濡れ性が向上する。 （フラックス洗浄工程）更に、フラックス７が洗浄タイ
プであれば、超音波やジェット洗浄法で、フラックス７
を除去する。＜無洗浄タイプの場合は省略＞ （樹脂封止工程＜図７の（ｄ）＞）次に、チップ１とセ
ラミック基板９の外的保護、及び接着強度を向上させる
ために、チップ１とセラミック基板９の間隙に、封止樹
脂１０を流し込んで硬化させる。この時用いる封止樹脂
１０は高温対応の為、Ｔｇが高い物を用いる。例えば１
５０℃以上での使用を考え、温度マージンを見てＴｇ１
８０℃のエポキシ系樹脂等を採用する。At this time, the chip 1 is temporarily fixed by utilizing the viscosity of the flux 7. (Reflow Step <(c) of FIG. 7>) Next, the solder (solder bump) is heated in an air or nitrogen atmosphere to a temperature equal to or higher than a melting temperature of solder (solder bump). In the case of a nitrogen atmosphere, the solder wettability is improved by the effect of preventing the solder 5 from being oxidized. (Flux cleaning step) Further, if the flux 7 is a cleaning type, the flux 7 is ultrasonically or jet-cleaned.
Is removed. <Omitted in case of no cleaning type> (Resin sealing step <(d) of FIG. 7)) Next, in order to externally protect the chip 1 and the ceramic substrate 9 and improve the adhesive strength, the chip 1 and the ceramic The sealing resin 10 is poured into the gap between the substrates 9 and cured. At this time, a sealing resin 10 having a high Tg is used to cope with high temperatures. For example, 1
Considering use at 50 ° C or higher, Tg1
80 ° C. epoxy resin or the like is employed.

【０００８】以上の工程を経て得られたフリップチップ
実装構造の半導体装置を図８に示す。この図に示すよう
に半田５と電極８との界面には半田５中のＳｎが拡散し
てＳｎＡｇの合金層１１が形成されている。FIG. 8 shows a semiconductor device having a flip-chip mounting structure obtained through the above steps. As shown in this figure, Sn in the solder 5 is diffused at the interface between the solder 5 and the electrode 8 to form a SnAg alloy layer 11.

【０００９】[0009]

【発明が解決しようとする課題】ところで上記の従来例
のフリップチップ実装構造では、高温環境下における信
頼性確保が難しい。However, it is difficult for the above-described conventional flip-chip mounting structure to ensure reliability in a high-temperature environment.

【００１０】つまり、従来例ではフリップチップ実装前
（図９（ａ））からフリップチップ実装後（図９
（ｂ））に、半田５とＣｕコア層４との界面に形成され
たＣｕ6Ｓｎ5の合金層６が成長してその厚さを増し、ま
た、半田５とＡｇＰｔ厚膜ペーストからなる電極８との
界面に上述のようにＳｎＡｇの合金層１１が形成され
る。That is, in the conventional example, before the flip chip mounting (FIG. 9A), after the flip chip mounting (FIG. 9A).
(B)), an alloy layer 6 of Cu 6 Sn 5 formed at the interface between the solder 5 and the Cu core layer 4 grows to increase its thickness, and an electrode made of the solder 5 and AgPt thick film paste As described above, the SnAg alloy layer 11 is formed at the interface with the substrate 8.

【００１１】この従来例のサンプルを１８０℃で１００
０時間の放置試験を行ったところ、図９（ｃ）に示すよ
うに時間の経過とともに半田５とＣＵコア層４との界面
に形成されているＣｕ6Ｓｎ5の合金層６が成長し、更に
ＣＵコア層４とＣｕ6Ｓｎ5の合金層６との界面にはＣｕ
3Ｓｎの合金層１２が形成され、成長している。一方、
半田５とＡｇＰｔの電極８との界面に形成されたＳｎＡ
ｇの合金層１１も成長している。図１０（ａ）はこの１
０００時間の放置試験を行った半導体装置を示す。The sample of this prior art was heated at 180 ° C. for 100
As a result of a 0-hour standing test, as shown in FIG. 9C, the Cu 6 Sn 5 alloy layer 6 formed at the interface between the solder 5 and the CU core layer 4 grew over time, Further, at the interface between the CU core layer 4 and the Cu 6 Sn 5 alloy layer 6, Cu
A 3 Sn alloy layer 12 is formed and growing. on the other hand,
SnA formed at the interface between the solder 5 and the AgPt electrode 8
g alloy layer 11 is also growing. FIG. 10A shows this 1
1 shows a semiconductor device that has been subjected to a standing test for 000 hours.

【００１２】試験を更に３０００時間まで行うと、図１
０（ｂ）に示すように半田５とＣｕコア層４の界面には
Ｃｕ3Ｓｎの合金層１２のみとなり、更にその界面付近
にボイドやクラック１３が発生して断線した。尚セラミ
ック基板９側の電極もＳｎＡｇの合金層１１のみとな
る。When the test is further performed for up to 3000 hours, FIG.
As shown in FIG. 0 (b), only the Cu 3 Sn alloy layer 12 was formed at the interface between the solder 5 and the Cu core layer 4, and voids and cracks 13 were generated near the interface, resulting in disconnection. The electrode on the ceramic substrate 9 side is also only the SnAg alloy layer 11.

【００１３】これは、半田５中のＳｎが図９（ｃ）に示
すように高温放置においてＣｕコア層４、及びＡｇＰｔ
電極８にそれぞれ拡散し、合金層１２、１１を形成して
成長させるために、半田５中のＳｎ濃度が低下し、やが
て合金層１２，１１へのＳｎの移動（拡散）が少なくな
り、そのためＣｕ6Ｓｎ5の合金層６はＳｎ濃度が次第に
低下し、Ｃｕ3Ｓｎの合金層１２へと変化し、さらに半
田５中のＳｎの濃度が下がると、半田５中よりＳｎの補
充がされなくなって、図９（ｄ）に示すように半田５に
ボイド１４が形成され、その数が増えることで合金層１
２と半田５との界面の強度が弱くなって、封止樹脂１０
の熱膨張により半田バンプにかかっている引っ張り応力
に耐えきれず破断したためと考えられる。This is because the Sn in the solder 5 has the Cu core layer 4 and the AgPt when left at high temperature as shown in FIG.
Since the Sn diffuses into the electrode 8 and forms and grows the alloy layers 12 and 11, the Sn concentration in the solder 5 decreases, and the movement (diffusion) of Sn to the alloy layers 12 and 11 decreases soon. The Sn concentration in the Cu 6 Sn 5 alloy layer 6 gradually decreases and changes to the Cu 3 Sn alloy layer 12, and when the Sn concentration in the solder 5 further decreases, the Sn is not replenished from the solder 5. As shown in FIG. 9D, voids 14 are formed in the solder 5, and the number of voids 14 is increased.
The strength of the interface between the solder 2 and the solder 5 becomes weak, and the sealing resin 10
This is considered to be due to the fact that the material failed to withstand the tensile stress applied to the solder bumps due to the thermal expansion and thus broke.

【００１４】本発明は、上記の点に鑑みて為されたもの
で、その目的とするところは、高温環境下における、半
田バンプ接合部の長寿命化を図った半導体装置のフリッ
プチップ実装構造を提供することにある。The present invention has been made in view of the above points, and an object of the present invention is to provide a flip-chip mounting structure of a semiconductor device in which a long life of a solder bump joint is achieved in a high temperature environment. To provide.

【００１５】[0015]

【課題を解決するための手段】上記目的を達成するため
に、請求項１の発明では、チップに設けられＡｌの電極
にＣｕ層を介してＳｎを含んだ半田の層を積層すること
により半田バンプを形成した半導体装置を用いて絶縁材
料からなる基板上に設けられた電極上へフリップチップ
実装する半導体装置のフリップチップ実装構造におい
て、上記半田のＳｎの濃度低下を遅らせる手段を備えた
ことを特徴とする。In order to achieve the above object, according to the first aspect of the present invention, a solder layer containing Sn is laminated on an Al electrode provided on a chip via a Cu layer. In a flip-chip mounting structure of a semiconductor device in which flip-chip mounting is performed on an electrode provided on a substrate made of an insulating material using a semiconductor device on which bumps are formed, a means for delaying a decrease in the concentration of Sn in the solder is provided. Features.

【００１６】請求項２の発明では、チップに設けられＡ
ｌの電極にＣｕ層を介してＳｎを含んだ半田の層を積層
することにより半田バンプを形成した半導体装置を用い
て絶縁材料からなる基板上に設けられた電極上へフリッ
プチップ実装する半導体装置のフリップチップ実装構造
において、上記Ｃｕ層と上記半田の層との間に、上記Ｃ
ｕ層への上記半田のＳｎの拡散によるＣｕとＳｎによる
合金層の形成を遅らせる金属層をＳｎの拡散がＡｇより
も小さい金属で形成したことを特徴とする。According to the second aspect of the present invention, A
A semiconductor device that is flip-chip mounted on an electrode provided on a substrate made of an insulating material using a semiconductor device in which a solder bump is formed by laminating a solder layer containing Sn on an electrode 1 via a Cu layer In the flip-chip mounting structure of the above, between the Cu layer and the solder layer, the C
The metal layer for delaying the formation of an alloy layer of Cu and Sn by the diffusion of Sn of the solder into the u layer is formed of a metal having a Sn diffusion smaller than Ag.

【００１７】請求項３の発明では、請求項１の発明にお
いて、上記半田のＳｎの濃度低下を遅らせる手段とし
て、Ｓｎの濃度が高濃度な半田で上記半田の層を形成し
たことを特徴とする。According to a third aspect of the present invention, in the first aspect of the present invention, as a means for delaying a decrease in the Sn concentration of the solder, the solder layer is formed of a solder having a high Sn concentration. .

【００１８】請求項４の発明では、請求項１の発明にお
いて、上記半田のＳｎの濃度低下を遅らせる手段とし
て、上記基板上に形成せる上記電極をＡｇよりもＳｎの
拡散が小さい金属により形成したことを特徴とする。According to a fourth aspect of the present invention, in the first aspect of the present invention, the electrode formed on the substrate is formed of a metal having a smaller Sn diffusion than Ag, as means for delaying a decrease in the Sn concentration of the solder. It is characterized by the following.

【００１９】請求項５の発明では、請求項１の発明にお
いて、上記基板上の電極がＡｇを含んだ電極であって、
上記半田のＳｎの濃度低下を遅延させる手段として、上
記基板上の上記電極上にＳｎの拡散がＡｇよりも小さい
金属の層を形成したことを特徴とする。According to a fifth aspect of the present invention, in the first aspect of the present invention, the electrode on the substrate is an electrode containing Ag,
As means for delaying a decrease in the Sn concentration of the solder, a metal layer having a Sn diffusion smaller than Ag is formed on the electrode on the substrate.

【００２０】請求項６の発明では、請求項１の発明にお
いて、請求項４又は５の発明において、上記Ｃｕ層と上
記半田の層との間にＳｎの拡散がＡｇよりも小さい金属
の層を形成したことを特徴とする。According to a sixth aspect of the present invention, in the first aspect of the present invention, in the fourth or fifth aspect of the present invention, a metal layer in which Sn diffusion is smaller than Ag is provided between the Cu layer and the solder layer. It is characterized by having been formed.

【００２１】請求項７の発明では、請求項４乃至６の何
れかの発明において、Ｓｎの濃度が高濃度な半田で上記
半田の層を形成したことを特徴とする。According to a seventh aspect of the present invention, in any one of the fourth to sixth aspects, the solder layer is formed of solder having a high Sn concentration.

【００２２】[0022]

【発明の実施の形態】以下本発明を実施形態により説明
する。尚各実施形態において、従来例と共通する部分に
ついては同一の符号を付して説明を省略し、実施形態の
特徴となる部分についてのみ詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. In each of the embodiments, portions common to the conventional example are denoted by the same reference numerals, and description thereof will be omitted. Only the features that are characteristic of the embodiments will be described in detail.

【００２３】（実施形態１）本実施形態は、図１に示す
ようにチップ１のＡ１電極２上にＣｒ／Ｎｉ／Ｃｕから
なるバリア層３，Ｃｕコア層４、従来例と同様の組成が
Ｓｎ２０％、ＰＢ８０％の半田５の層を順次積層するこ
とにより従来と同様に半田バンプを形成した半導体装置
を、半田バンプと対向する位置にＳｎとの拡散がＡｇよ
りも小さい金属であるタングステンの薄膜よりなる電極
８０を形成したセラミック基板９上ヘフリップチップ実
装する。(Embodiment 1) In this embodiment, as shown in FIG. 1, a barrier layer 3 made of Cr / Ni / Cu and a Cu core layer 4 are formed on an A1 electrode 2 of a chip 1 and have the same composition as a conventional example. A semiconductor device in which solder bumps are formed in the same manner as in the related art by sequentially laminating solder 5 layers of 20% Sn and 80% PB is used to form a semiconductor device having tungsten, which is a metal whose diffusion with Sn is smaller than Ag, at a position facing the solder bump. Flip chip mounting is performed on the ceramic substrate 9 on which the electrode 80 made of a thin film is formed.

【００２４】このように構成した本実施形態のフリップ
チップ実装構造によれば、半田５からセラミック基板９
の電極８０側へのＳｎの移動（拡散）が無くなり、半田
５中のＳｎ濃度が下がるのが遅くなるため、Ｓｎ不足に
よるボイド形成を遅らせることができ、結果従来に比べ
て寿命が延びることになる。 （実施形態２）本実施形態は、図２に示すようにチップ
１のＡ１電極２上にＣｒ／Ｎｉ／Ｃｕからなるバリア層
３、組成がＳｎ９０％、Ｐｂ１０％よりなる半田５の層
を順次積層することにより半田バンプを形成した半導体
装置を、その半田バンプと対向する位置にＡｇＰｔの電
極８を形成したセラミック基板９上ヘフリップチップ実
装する。According to the flip-chip mounting structure of this embodiment configured as described above, the ceramic 5
The movement (diffusion) of Sn to the electrode 80 side is eliminated, and the decrease in the Sn concentration in the solder 5 is slowed, so that void formation due to Sn shortage can be delayed, and as a result, the life is extended as compared with the conventional case. Become. (Embodiment 2) In this embodiment, as shown in FIG. 2, a barrier layer 3 made of Cr / Ni / Cu and a solder layer 5 made of 90% Sn and 10% Pb are sequentially formed on an A1 electrode 2 of a chip 1. The semiconductor device having the solder bumps formed by lamination is flip-chip mounted on the ceramic substrate 9 having the AgPt electrode 8 formed at a position facing the solder bump.

【００２５】このように構成した本実施形態のフリップ
チップ実装構造によれば、構造的には従来とかわらず、
半田５と電極８との間にＳｎＡｇによる合金層１１が形
成され、またＣｕコア層４と半田５との間にＣｕ6Ｓｎ5
の合金層が形成され、更に経時的にはこの合金層とＣｕ
コア層４との間にＣｕ3Ｓｎの合金層が形成されること
になるが、半田５中のＳｎの濃度が９０％と高くなって
いるため、電極８側へのＳｎの移動（拡散）があっても
半田５中のＳｎ濃度がなかなか下がらず、結果Ｓｎ不足
によるボイド形成を遅らせることができ、従来に比べて
寿命が延びることになる。 （実施形態３）本実施形態は、図３に示すようにチップ
１のＡ１電極２上にバリア層３，Ｃｕコア層４を積層す
るとともに、このＣｕコア層４の上にＮｉ層１５、Ａｕ
層１６を介してＳｎ２０％Ｐｂ８０％よりなる半田５の
層を積層することにより半田バンプを形成した半導体装
置を、その半田バンプと対向する位置にＡｇＰｔの電極
１２を形成したセラミック基板９上ヘフリップチップ実
装する。According to the flip-chip mounting structure of this embodiment configured as described above, the structure is not the conventional one,
An alloy layer 11 of SnAg is formed between the solder 5 and the electrode 8, and Cu 6 Sn 5 is formed between the Cu core layer 4 and the solder 5.
Alloy layer is formed, and over time, this alloy layer and Cu
An alloy layer of Cu 3 Sn is formed between itself and the core layer 4. However, since the concentration of Sn in the solder 5 is as high as 90%, the movement (diffusion) of Sn to the electrode 8 side. Even if there is, the Sn concentration in the solder 5 does not readily decrease, and as a result, void formation due to Sn deficiency can be delayed, and the life is extended as compared with the conventional case. (Embodiment 3) In this embodiment, as shown in FIG. 3, a barrier layer 3 and a Cu core layer 4 are laminated on the A1 electrode 2 of the chip 1, and a Ni layer 15 and Au are formed on the Cu core layer 4.
A semiconductor device having a solder bump formed by laminating a layer of solder 20 made of Sn20% Pb80% via a layer 16 is flipped over a ceramic substrate 9 having an AgPt electrode 12 formed at a position facing the solder bump. Chip mounting.

【００２６】このように構成した本実施形態のフリップ
チップ実装構造によれば、Ａｕ層１６，Ｎｉ層１５によ
り半田５からのＳｎのＣｕコア層４への移動（拡散）を
妨げ、半田５中のＳｎ濃度が下がるのが遅くなり、結果
Ｓｎ不足によるボイド形成を遅らせることができ、従来
に比べて寿命が延びることになる。 （実施形態４）本実施形態は、図４に示すようにチップ
１のＡ１電極２上にバリア層３、Ｃｕコア層４、Ｓｎ２
０％Ｐｂ８０％の半田５の層を順次積層することにより
半田バンプを形成した半導体装置を、その半田バンプと
対向する位置にＡｇＰｔによる電極８を形成するととも
に、その電極８の上にＮｉ層１７、Ａｕ層１８を形成し
たセラミック基板９上ヘフリップチップ実装する。According to the flip-chip mounting structure of the present embodiment configured as described above, the movement (diffusion) of Sn from the solder 5 to the Cu core layer 4 is prevented by the Au layer 16 and the Ni layer 15, and the solder 5 Is slowed down, and as a result, void formation due to Sn deficiency can be delayed, and the life is extended as compared with the conventional case. (Embodiment 4) In this embodiment, as shown in FIG. 4, a barrier layer 3, a Cu core layer 4, a Sn2
A semiconductor device in which solder bumps are formed by sequentially laminating layers of solder 5 of 0% Pb 80% is formed. An electrode 8 of AgPt is formed at a position facing the solder bump, and a Ni layer 17 is formed on the electrode 8. And flip chip mounting on the ceramic substrate 9 on which the Au layer 18 is formed.

【００２７】このように構成した本実施形態のフリップ
チップ実装構造によれば、Ａｕ層１８、Ｎｉ層１７によ
り半田５からのＳｎのＣｕコア層４への移動（拡散）を
妨げ、半田５中のＳｎ濃度が下がるのが遅くなり、結果
Ｓｎ不足によるボイド形成を遅らせることができ、従来
に比べて寿命が延びることになる。 （実施形態５）本実施形態は、図５に示すようにチップ
１のＡ１電極２上にＣｒ／Ｎｉ／Ｃｕからなるバリア層
３，Ｃｕコア層４、そして実施形態３と同様にＮｉ層１
５、Ａｕ層１６を介して、Ｓｎ２０％Ｐｂ８０％の半田
５の層を順次積層することにより半田バンプを形成した
半導体装置を、半田バンプと対向する位置にＳｎの拡散
がＡｇよりも小さい金属であるタングステンの薄膜より
なる電極８０を形成したセラミック基板９上ヘフリップ
チップ実装する。According to the flip-chip mounting structure of this embodiment configured as described above, the Au layer 18 and the Ni layer 17 prevent the movement (diffusion) of Sn from the solder 5 to the Cu core layer 4, and Is slowed down, and as a result, void formation due to Sn deficiency can be delayed, and the life is extended as compared with the conventional case. (Embodiment 5) In this embodiment, as shown in FIG. 5, a barrier layer 3 made of Cr / Ni / Cu and a Cu core layer 4 are formed on an A1 electrode 2 of a chip 1;
5. A semiconductor device in which solder bumps are formed by sequentially laminating layers of solder 20 of Sn 20% Pb 80% via an Au layer 16 is formed by using a metal in which Sn diffusion is smaller than Ag at a position facing the solder bump. Flip chip mounting is performed on the ceramic substrate 9 on which the electrode 80 made of a certain tungsten thin film is formed.

【００２８】このように構成した本実施形態のフリップ
チップ実装構造によれば、半田５からセラミック基板９
の電極８０側へのＳｎの移動（拡散）が無くなる上に、
Ｎｉ層１５、Ａｕ層１６により半田５からのＳｎのＣｕ
コア層４への移動（拡散）を妨げ、実施形態１，３に比
べて半田５中のＳｎ濃度が下がるのが一層遅くなり、結
果Ｓｎ不足によるボイド形成を一層遅らせることがで
き、一層寿命が延びることになる。 （実施形態６）本実施形態は、図６に示すようにチップ
１のＡ１電極２上にＣｒ／Ｎｉ／Ｃｕからなるバリア層
３，Ｃｕコア層４、そして実施形態３と同様にＮｉ層１
５、Ａｕ層１６を介して、Ｓｎ２０％Ｐｂ８０％の半田
５の層を順次積層することにより半田バンプを形成した
半導体装置を、実施形態４と同様に半田バンプと対向す
る位置にＡｇＰｔによる電極８を形成するとともに、そ
の電極８の上にＮｉ層１７、Ａｕ層１８を形成したセラ
ミック基板９上ヘフリップチップ実装する。According to the flip-chip mounting structure of this embodiment configured as described above, the ceramic 5
In addition to eliminating the movement (diffusion) of Sn to the electrode 80 side,
Cu of Sn from solder 5 by Ni layer 15 and Au layer 16
Movement (diffusion) to the core layer 4 is hindered, and the Sn concentration in the solder 5 decreases more slowly than in the first and third embodiments. As a result, void formation due to lack of Sn can be further delayed, and the life is further improved. Will be extended. (Embodiment 6) In this embodiment, as shown in FIG. 6, a barrier layer 3 made of Cr / Ni / Cu and a Cu core layer 4 are formed on an A1 electrode 2 of a chip 1.
5, a semiconductor device in which solder bumps are formed by sequentially laminating layers of solder 20 of Sn 20% Pb 80% via an Au layer 16 is mounted on the electrode 8 of AgPt at a position facing the solder bumps as in the fourth embodiment. And a flip-chip mounting on the ceramic substrate 9 on which the Ni layer 17 and the Au layer 18 are formed on the electrodes 8.

【００２９】このように構成した本実施形態のフリップ
チップ実装構造によれば、Ａｕ層１６、Ｎｉ層１５によ
り半田５からのＳｎのＣｕコア層４への移動（拡散）を
妨げ、また電極８上に形成したＮｉ層１５、Ａｕ層１６
によって、半田５中のＳｎの電極８への拡散するのを防
げ、実施形態３，４に比べ半田５中のＳｎ濃度が下がる
のが一層遅くなり、結果Ｓｎ不足によるボイド形成を一
層遅らせることができ、寿命が一層延びることになる。According to the flip-chip mounting structure of this embodiment configured as described above, the Au layer 16 and the Ni layer 15 prevent the movement (diffusion) of Sn from the solder 5 to the Cu core layer 4 and prevent the electrode 8 Ni layer 15 and Au layer 16 formed thereon
Accordingly, the diffusion of Sn in the solder 5 to the electrode 8 can be prevented, and the Sn concentration in the solder 5 decreases more slowly than in the third and fourth embodiments. As a result, the formation of voids due to lack of Sn can be further delayed. And the service life is further extended.

【００３０】尚実施形態１，３〜６における半田５とし
て、実施形態２の組成がＳｎ９０％、Ｐｂ１０％の半田
５のようにＳｎの濃度が高い半田を用いれば一層長寿命
化が図れるのは勿論である。If the solder 5 in the first and third to sixth embodiments is a solder having a high Sn concentration, such as the solder 5 in which the composition of the second embodiment is Sn 90% and Pb 10%, the service life can be further extended. Of course.

【００３１】またＳｎの濃度を高くすることで、ボイド
形成を遅らせる場合、半田５としての融点が所望の温度
が確保でき且つ、寿命の延命効果が評価できる程度にボ
イド形成を遅らせることができるＳｎの濃度であれば、
実施形態２の半田５のＳｎ９０％、Ｐｂ１０％の組成に
特に限定されるものではない。When the formation of voids is delayed by increasing the concentration of Sn, the formation of Sn can be delayed such that the melting point of the solder 5 can secure a desired temperature and the effect of extending the life can be evaluated. If the concentration is
The composition of the solder 5 of the second embodiment is not particularly limited to the composition of Sn 90% and Pb 10%.

【００３２】[0032]

【発明の効果】請求項１の発明は、チップに設けられＡ
ｌの電極にＣｕ層を介してＳｎを含んだ半田の層を積層
することにより半田バンプを形成した半導体装置を用い
て絶縁材料からなる基板上に設けられた電極上へフリッ
プチップ実装する半導体装置のフリップチップ実装構造
において、上記半田のＳｎの濃度低下を遅らせる手段を
備えたので、半田中のＳｎ濃度が下がるのが遅くなり、
結果Ｓｎ不足によるボイド形成を遅らせることができる
ため、高温環境下においてボイド形成によるクラック発
生が遅くなって、半田バンプの接合部位の寿命を延ばす
ことができるという効果がある。According to the first aspect of the present invention, an A
A semiconductor device that is flip-chip mounted on an electrode provided on a substrate made of an insulating material using a semiconductor device in which a solder bump is formed by laminating a solder layer containing Sn on an electrode 1 via a Cu layer In the flip-chip mounting structure of (1), the means for delaying the decrease in the Sn concentration of the solder is provided, so that the decrease in the Sn concentration in the solder is delayed,
As a result, void formation due to Sn deficiency can be delayed, so that crack generation due to void formation is delayed in a high-temperature environment, and there is an effect that the life of the joint portion of the solder bump can be extended.

【００３３】請求項２の発明は、チップに設けられＡｌ
の電極にＣｕ層を介してＳｎを含んだ半田の層を積層す
ることにより半田バンプを形成した半導体装置を用いて
絶縁材料からなる基板上に設けられた電極上へフリップ
チップ実装する半導体装置のフリップチップ実装構造に
おいて、上記Ｃｕ層と上記半田の層との間に、上記Ｃｕ
層への上記半田のＳｎの拡散によるＣｕとＳｎによる合
金層の形成を遅らせる金属層をＳｎの拡散がＡｇよりも
小さい金属で形成したので、半田からのＳｎのＣｕ層へ
の拡散を妨げてＣｕと、Ｓｎによる合金層の形成を遅ら
せることができ、結果Ｓｎ不足によるボイド形成を遅ら
せることができるため、高温環境下においてボイド形成
によるクラック発生が遅くなって、半田バンプの接合部
位の寿命を延ばすことができるという効果がある。According to a second aspect of the present invention, an Al
Of a semiconductor device that is flip-chip mounted on an electrode provided on a substrate made of an insulating material using a semiconductor device in which a solder bump is formed by laminating a solder layer containing Sn via a Cu layer on the electrode of In the flip-chip mounting structure, the Cu layer is provided between the Cu layer and the solder layer.
Since the metal layer that delays the formation of an alloy layer of Cu and Sn due to the diffusion of Sn of the solder into the layer is formed of a metal in which the diffusion of Sn is smaller than Ag, the diffusion of Sn from the solder to the Cu layer is prevented. The formation of an alloy layer by Cu and Sn can be delayed, and as a result, void formation due to Sn deficiency can be delayed, so that crack generation due to void formation is delayed in a high-temperature environment, and the life of the joint portion of the solder bump is reduced. There is an effect that it can be extended.

【００３４】請求項３の発明は、請求項１の発明におい
て、上記半田のＳｎの濃度低下を遅らせる手段として、
Ｓｎの濃度が高濃度な半田で上記半田の層を形成したの
で、基板側の電極へのＳｎの拡散があっても、半田中の
Ｓｎの濃度低下が遅く、その結果Ｓｎ不足によるボイド
形成を遅らせることができるため、高温環境下において
ボイド形成によるクラック発生が遅くなって、半田バン
プの接合部位の寿命を延ばすことができるという効果が
ある。According to a third aspect of the present invention, in the first aspect of the present invention, as means for delaying the decrease in the Sn concentration of the solder,
Since the solder layer is formed of a solder having a high Sn concentration, the Sn concentration in the solder decreases slowly even if Sn diffuses to the electrode on the substrate side, and as a result, void formation due to Sn shortage occurs. Since the delay can be delayed, the generation of cracks due to the formation of voids in a high-temperature environment is delayed, and there is an effect that the life of the joint portion of the solder bump can be extended.

【００３５】請求項４の発明は、請求項１の発明におい
て、上記半田のＳｎの濃度低下を遅らせる手段として、
上記基板上に形成せる上記電極をＡｇよりもＳｎの拡散
が小さい金属により形成してあるので、半田中のＳｎの
基板の電極への拡散が少なく或いは無く、そのため半田
中のＳｎの濃度低下が遅く、結果Ｓｎ不足によるボイド
形成を遅らせることができるため、高温環境下において
ボイド形成によるクラック発生が遅くなって、半田バン
プの接合部位の寿命を延ばすことができるという効果が
ある。According to a fourth aspect of the present invention, in the first aspect of the present invention, the means for delaying the decrease in the Sn concentration of the solder includes:
Since the electrode formed on the substrate is formed of a metal in which the diffusion of Sn is smaller than that of Ag, the diffusion of Sn in the solder to the electrode of the substrate is small or not, and therefore, the concentration of Sn in the solder is reduced. As a result, void formation due to Sn deficiency can be delayed, so that crack generation due to void formation is delayed in a high-temperature environment, and there is an effect that the life of the joint portion of the solder bump can be extended.

【００３６】請求項５の発明は、請求項１の発明におい
て、上記基板上の電極がＡｇを含んだ電極であって、上
記半田のＳｎの濃度低下を遅延させる手段として、上記
基板上の上記電極上にＳｎの拡散がＡｇよりも小さい金
属の層を形成したので、該金属層により半田中のＳｎの
基板の電極への拡散を妨げ、そのため半田中のＳｎの濃
度低下が遅く、結果Ｓｎ不足によるボイド形成を遅らせ
ることができるため、高温環境下においてボイド形成に
よるクラック発生が遅くなって、半田バンプの接合部位
の寿命を延ばすことができるという効果がある。According to a fifth aspect of the present invention, in the first aspect of the present invention, the electrode on the substrate is an electrode containing Ag, and the electrode on the substrate serves as a means for delaying a decrease in the concentration of Sn in the solder. Since a metal layer in which the diffusion of Sn was smaller than that of Ag was formed on the electrodes, the diffusion of Sn in the solder to the electrodes of the substrate was prevented by the metal layer, so that the decrease in the concentration of Sn in the solder was slow. Since void formation due to shortage can be delayed, crack generation due to void formation in a high-temperature environment is delayed, so that there is an effect that the life of a joint portion of a solder bump can be extended.

【００３７】請求項６の発明は、請求項１の発明におい
て、請求項４又は５の発明において、上記Ｃｕ層と上記
半田の層との間にＳｎの拡散がＡｇよりも小さい金属の
層を形成したので、Ｓｎ不足によるボイド形成を一層遅
らせることができ、そのため高温環境下においてボイド
形成によるクラック発生が更に遅くなって、半田バンプ
の接合部位の寿命を一層延ばすことができるという効果
がある。According to a sixth aspect of the present invention, in the first aspect of the present invention, in the fourth or fifth aspect of the present invention, a metal layer in which Sn diffusion is smaller than Ag is provided between the Cu layer and the solder layer. Since it is formed, void formation due to Sn deficiency can be further delayed, so that crack generation due to void formation can be further delayed in a high-temperature environment, and the life of the joint portion of the solder bump can be further extended.

【００３８】請求項７の発明は、請求項４乃至６の何れ
かの発明において、Ｓｎの濃度が高濃度な半田で上記半
田の層を形成したので、Ｓｎ不足によるボイド形成をよ
り一層遅らせることができ、そのため高温環境下におい
てボイド形成によるクラック発生が一層遅くなって、半
田バンプの接合部位の寿命をより一層延ばすことができ
るという効果がある。According to a seventh aspect of the present invention, in any one of the fourth to sixth aspects, since the solder layer is formed of solder having a high Sn concentration, the formation of voids due to Sn shortage is further delayed. Therefore, the generation of cracks due to the formation of voids in a high-temperature environment is further delayed, so that the life of the joint portion of the solder bump can be further extended.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態１の断面図である。FIG. 1 is a cross-sectional view of Embodiment 1 of the present invention.

【図２】本発明の実施形態２の断面図である。FIG. 2 is a cross-sectional view of Embodiment 2 of the present invention.

【図３】本発明の実施形態３の断面図である。FIG. 3 is a sectional view of Embodiment 3 of the present invention.

【図４】本発明の実施形態４の断面図である。FIG. 4 is a sectional view of Embodiment 4 of the present invention.

【図５】本発明の実施形態５の断面図である。FIG. 5 is a sectional view of Embodiment 5 of the present invention.

【図６】本発明の実施形態６の断面図である。FIG. 6 is a cross-sectional view of Embodiment 6 of the present invention.

【図７】従来例の実装工程の説明図である。FIG. 7 is an explanatory diagram of a mounting process of a conventional example.

【図８】同上の断面図である。FIG. 8 is a sectional view of the same.

【図９】同上の半田のＳｎの移動（拡散）の説明図であ
る。FIG. 9 is an explanatory diagram of movement (diffusion) of Sn in the above solder.

【図１０】同上を１８０℃の雰囲気で放置した実験にお
ける経時的な変化を示す図であって、（ａ）は１０００
時間経過時、（ｂ）は３０００時間経過時の夫々の断面
図である。FIG. 10 is a diagram showing a change over time in an experiment in which the same was left in an atmosphere at 180 ° C.
FIG. 3B is a cross-sectional view of a lapse of time, and FIG.

【符号の説明】[Explanation of symbols]

１ チップ ２ Ａｌの電極 ３ バリア層 ４ Ｃｕコア層 ５ 半田 ６ Ｃｕ6Ｓｎ5の合金層 ９ セラミック基板 ８０ タングステン薄膜の電極Reference Signs List 1 chip 2 electrode of Al 3 barrier layer 4 Cu core layer 5 solder 6 alloy layer of Cu 6 Sn 5 9 ceramic substrate 80 electrode of tungsten thin film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高見 茂成 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 豊田 陵子 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 牧野 篤 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 去来川 光男 大阪府門真市大字門真1048番地松下電工株 式会社内 Ｆターム(参考） 5F044 KK04 LL04 QQ03 QQ04  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Shigenari Takami 1048, Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor: Reiko Toyoda 1048, Kadoma, Kazuma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor Makino Atsushi 1048, Kazuma, Kadoma, Osaka Prefecture, Matsushita Electric Works, Ltd. KK04 LL04 QQ03 QQ04

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 チップに設けられたＡｌの電極にＣｕ層
を介してＳｎを含んだ半田の層を積層することにより半
田バンプを形成した半導体装置を用いて絶縁材料からな
る基板上に設けられた電極上へフリップチップ実装する
半導体装置のフリップチップ実装構造において、上記半
田のＳｎの濃度低下を遅らせる手段を備えたことを特徴
とする半導体装置のフリップチップ実装構造。1. A semiconductor device having solder bumps formed by laminating a solder layer containing Sn on an Al electrode provided on a chip via a Cu layer and provided on a substrate made of an insulating material. A flip-chip mounting structure for a semiconductor device, wherein the flip-chip mounting structure of the semiconductor device is flip-chip mounted on an electrode, the flip-chip mounting structure including means for delaying a decrease in the concentration of Sn in the solder. 【請求項２】 チップに設けられＡｌの電極にＣｕ層を
介してＳｎを含んだ半田の層を積層することにより半田
バンプを形成した半導体装置を用いて絶縁材料からなる
基板上に設けられた電極上へフリップチップ実装する半
導体装置のフリップチップ実装構造において、上記Ｃｕ
層と上記半田の層との間に、上記Ｃｕ層への上記半田の
Ｓｎの拡散によるＣｕとＳｎによる合金層の形成を遅ら
せる金属層をＳｎの拡散がＡｇよりも小さい金属で形成
したことを特徴とする半導体装置のフリップチップ実装
構造。2. A semiconductor device in which a solder bump is formed by laminating a solder layer containing Sn on an Al electrode provided on a chip via a Cu layer and provided on a substrate made of an insulating material. In a flip-chip mounting structure of a semiconductor device to be flip-chip mounted on an electrode, the above Cu
A metal layer that delays the formation of an alloy layer of Cu and Sn by diffusion of Sn of the solder into the Cu layer between the layer and the layer of the solder is formed of a metal in which the diffusion of Sn is smaller than Ag. Features flip-chip mounting structure of semiconductor device. 【請求項３】 上記半田のＳｎの濃度低下を遅らせる手
段として、Ｓｎの濃度が高濃度な半田で上記半田の層を
形成したことを特徴とする請求項１記載の半導体装置の
フリップチップ実装構造。3. The flip-chip mounting structure of a semiconductor device according to claim 1, wherein said solder layer is formed of a solder having a high Sn concentration as means for delaying a decrease in the Sn concentration of said solder. . 【請求項４】 上記半田のＳｎの濃度低下を遅らせる手
段として、上記基板上に形成せる上記電極をＡｇよりも
Ｓｎの拡散が小さい金属により形成して成ることを特徴
とする請求項１記載の半導体装置のフリップチップ実装
構造。4. The method according to claim 1, wherein said electrode formed on said substrate is formed of a metal having a smaller Sn diffusion than Ag, as means for delaying the decrease in the Sn concentration of said solder. Flip chip mounting structure of semiconductor device. 【請求項５】 上記基板上の電極がＡｇを含んだ電極で
あって、上記半田のＳｎの濃度低下を遅延させる手段と
して、上記基板上の上記電極上にＳｎの拡散がＡｇより
も小さい金属の層を形成したことを特徴とする請求項１
記載の半導体装置のフリップチップ実装構造。5. The method according to claim 1, wherein the electrode on the substrate is an electrode containing Ag, and the diffusion of Sn on the electrode on the substrate is smaller than that of Ag. 2. The layer of claim 1 wherein:
A flip-chip mounting structure of the semiconductor device described in the above. 【請求項６】 上記Ｃｕ層と上記半田の層との間にＳｎ
の拡散がＡｇよりも小さい金属の層を形成したことを特
徴とする請求項４又は５記載の半導体装置のフリップチ
ップ実装構造。6. An Sn film between the Cu layer and the solder layer.
6. A flip-chip mounting structure for a semiconductor device according to claim 4, wherein a metal layer having a diffusion of less than Ag is formed. 【請求項７】 Ｓｎの濃度が高濃度な半田で上記半田の
層を形成したことを特徴とする請求項４乃至６の何れか
記載の半導体装置のフリップチップ実装構造。7. The flip-chip mounting structure for a semiconductor device according to claim 4, wherein said solder layer is formed of solder having a high Sn concentration.
JP2000026275A 2000-02-03 2000-02-03 Flip-chip mounting structure for semiconductor device Withdrawn JP2001217275A (en)

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Application Number Priority Date Filing Date Title
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Publication Number Publication Date
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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2403173A (en) * 2003-06-25 2004-12-29 King S College London Soldering refractory metal surfaces
US8836145B2 (en) 2004-06-03 2014-09-16 International Rectifier Corporation Power semiconductor device with reduced contact resistance
JP2017130823A (en) * 2016-01-21 2017-07-27 京セラ株式会社 Piezoelectric oscillator and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2403173A (en) * 2003-06-25 2004-12-29 King S College London Soldering refractory metal surfaces
US8836145B2 (en) 2004-06-03 2014-09-16 International Rectifier Corporation Power semiconductor device with reduced contact resistance
JP2017130823A (en) * 2016-01-21 2017-07-27 京セラ株式会社 Piezoelectric oscillator and manufacturing method of the same

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