JP2001185440A - Laminated ceramic capacitor - Google Patents
Laminated ceramic capacitorInfo
- Publication number
- JP2001185440A JP2001185440A JP36788399A JP36788399A JP2001185440A JP 2001185440 A JP2001185440 A JP 2001185440A JP 36788399 A JP36788399 A JP 36788399A JP 36788399 A JP36788399 A JP 36788399A JP 2001185440 A JP2001185440 A JP 2001185440A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- internal
- internal electrodes
- ceramic capacitor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は複数の誘電体層が積
層され、その誘電体層間に互いに対向する内部電極を形
成してなる積層セラミックコンデンサの構造に関し、特
に、複数のコンデンサが直列に接続された構造を備える
ものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a multilayer ceramic capacitor in which a plurality of dielectric layers are laminated, and internal electrodes facing each other are formed between the dielectric layers, and in particular, a plurality of capacitors are connected in series. To a device having a structured structure.
【０００２】[0002]
【従来の技術】積層セラミックコンデンサは、小型でか
つ高容量を得ることができ、また基板への実装が容易で
あることから、電子機器の小型化に大きく貢献してい
る。また、近年、装置の小型化、機能の向上等に伴っ
て、装置内に用いる積層セラミックコンデンサは小型か
つ高容量化が必要となっており、この要望は、積層セラ
ミックコンデンサを例えば１０００〜９０００Ｖという
比較的高い電圧領域（中圧ないし高圧領域）での使用を
可能とすることにより実現しようとしている。2. Description of the Related Art Multilayer ceramic capacitors are small and have a high capacity and are easy to mount on a substrate, which greatly contributes to miniaturization of electronic equipment. In recent years, with the miniaturization and improvement of functions of the device, the multilayer ceramic capacitor used in the device has been required to have a small size and a high capacity. It is intended to be realized by enabling use in a relatively high voltage range (medium pressure to high pressure range).
【０００３】図４には、比較的高い電圧領域に使用が可
能とされた、即ち、耐圧性が向上された従来の積層セラ
ミックコンデンサを説明する図を示し、（ａ）は積層セ
ラミックコンデンサの長さ方向横断面図であり、（ｂ）
が水平方向の断面図を示している。FIG. 4 is a view for explaining a conventional multilayer ceramic capacitor which can be used in a relatively high voltage range, that is, has improved withstand voltage. FIG. (B)
Shows a cross-sectional view in the horizontal direction.
【０００４】図４によれば、複数の誘電体層が積層され
た積層体４１と、積層体４１の互いに対向する端面４２
ａ、４２ｂにそれぞれ形成される第１および第２の外部
電極４５、４６と、第１の外部電極４５に接続されて積
層状に形成された複数の第１の内部電極４３と、第２の
外部電極４６に接続され、第１の内部電極４４と同一の
誘電体層に第１の内部電極４４と対向して形成された第
２の内部電極４４と、第１，第２の内部電極（以下、引
き出し電極）４３、４４と誘電体層を介して一部が重な
り合う第３の内部電極（以下、浮き電極）４７とから構
成されている。特に、引き出し電極４３，４４と浮き電
極４７とでコンデンサユニット４８を形成しており、コ
ンデンサユニット４８が複数積層方向に整列してなる。According to FIG. 4, a laminate 41 in which a plurality of dielectric layers are laminated, and end faces 42 of the laminate 41 facing each other.
a and 42b respectively formed on the first and second external electrodes 45 and 46; a plurality of first internal electrodes 43 connected to the first external electrode 45 and formed in a stacked state; A second internal electrode 44 connected to the external electrode 46 and formed on the same dielectric layer as the first internal electrode 44 so as to face the first internal electrode 44; Hereinafter, extraction electrodes 43 and 44 and a third internal electrode (hereinafter referred to as a floating electrode) 47 that partially overlaps with a dielectric layer interposed therebetween. In particular, the capacitor units 48 are formed by the extraction electrodes 43 and 44 and the floating electrodes 47, and a plurality of capacitor units 48 are arranged in the laminating direction.
【０００５】[0005]
【発明が解決しようとする課題】上述の積層セラミック
コンデンサにおいては、積層体４１の一体焼成時に、誘
電体層と引き出し電極４３，４４と浮き電極４７の収縮
率が異なることにより起こる誘電体層間のデラミネーシ
ョンや熱衝撃試験により積層体４１のクラックを低減さ
せなければならない。このためには、引き出し電極４
３，４４と浮き電極４７の厚みは薄い方が望ましい。し
かしながら、引き出し電極４３，４４と浮き電極４７の
厚みを単に薄くすると、外部電極４５，４６との接続性
が阻害され、高周波でのＥＳＲ（等価直列抵抗）が大き
くなるという問題点があった。In the above-described multilayer ceramic capacitor, when the laminated body 41 is integrally fired, the dielectric layer and the lead electrodes 43 and 44 and the floating electrode 47 have different shrinkage ratios and cause a difference between the dielectric layers. Cracks in the laminate 41 must be reduced by delamination or thermal shock tests. For this purpose, the extraction electrode 4
It is desirable that the thickness of the floating electrodes 47 is small. However, when the thicknesses of the lead electrodes 43 and 44 and the floating electrode 47 are simply reduced, the connectivity between the external electrodes 45 and 46 is hindered, and the ESR (equivalent series resistance) at a high frequency increases.
【０００６】特に、耐電圧を維持しようとすると、内部
電極間によりはさまれた誘電体の厚みを大きくすること
が必要になり、配設可能な内部電極の層数（枚数）が減
少するため、ＥＳＲ（等価直列抵抗）が大きくなる傾向
がある。Particularly, in order to maintain the withstand voltage, it is necessary to increase the thickness of the dielectric sandwiched between the internal electrodes, and the number (number of layers) of the internal electrodes that can be arranged is reduced. , ESR (equivalent series resistance) tends to increase.
【０００７】一方、未焼成状態の誘電体層となるグリー
ンシートを介して引き出し電極４３，４４と浮き電極４
７とを交互に積層した場合、引き出し電極４３，４４と
浮き電極４７との重なる領域が盛り上がってしまい、切
断後に端部となる領域がへこんでしまうという問題点を
有していた。従って、積層体４１の主面における平面平
行度が保てなくなり、積層時に積層体４１を圧着しても
段差が大きいために圧力が均一にかからず各誘電体層の
密着不良が起こり、その結果、切断した際に剥離，密着
不良の不具合が生じる問題点を有していた。On the other hand, the lead electrodes 43 and 44 and the floating electrode 4 are interposed via a green sheet to be an unfired dielectric layer.
In the case where layers 7 and 7 are alternately stacked, there is a problem that the region where the extraction electrodes 43 and 44 and the floating electrode 47 overlap is raised, and the region that becomes the end after cutting is dented. Therefore, the plane parallelism on the main surface of the laminated body 41 cannot be maintained, and even when the laminated body 41 is pressed during lamination, the pressure is not uniformly applied due to a large step, and poor adhesion between the dielectric layers occurs. As a result, there is a problem that peeling and poor adhesion may occur when cut.
【０００８】また、低背化，小型化で、かつ、高容量を
実現する積層セラミックコンデンサを構成するために
は、コンデンサユニット４８の数を積層方向に増やすた
め、積層体４１の主面から一番近い電極までの距離（ト
ップマージン）を薄くせざるを得ず、このように薄くし
た場合には、積層体４１の角部の肉厚が薄くなることが
あった。この理由は、外部電極４５，４６の形成をディ
ップ法、即ち、導電性ペーストの入った槽に積層体４１
の端面４２ａ，４２ｂを漬けて形成されるが、この方法
では、積層体４１の端面中央部の外部電極４５，４６に
比べて角部の外部電極４５，４６の肉厚が導電性ペース
トの表面張力によって薄く形成されるからである。In order to form a multilayer ceramic capacitor having a low profile, a small size and a high capacitance, the number of capacitor units 48 is increased in the stacking direction. The distance (top margin) to the nearest electrode has to be reduced, and in such a case, the thickness of the corners of the stacked body 41 may be reduced. The reason for this is that the external electrodes 45 and 46 are formed by a dipping method, that is, the laminate 41 is placed in a tank containing a conductive paste.
In this method, the thickness of the outer electrodes 45 and 46 at the corners is larger than that at the center of the end surfaces of the conductive paste. This is because it is formed thin by tension.
【０００９】従って、このように、積層体４１の角部が
薄い場合には、次の外部電極４５，４６にメッキ処理を
行う工程において、以下の原因で外部電極４５，４６か
らメッキ液が積層体４１に浸入する問題点を有してい
た。即ち、（１）積層体４１と外部電極４５，４６が接
触する４つの面の間、特に、積層体４１の端面に近い主
面と外部電極４５，４６との境界部位から入る場合、
（２）端面４２ａ，４２ｂに直接形成する外部電極４
５，４６に存在する微少な中空孔からメッキ液が直接浸
入する。外部電極４５，４６の厚みが薄ければ入りやす
くなる。Therefore, when the corners of the laminate 41 are thin, a plating solution is laminated from the external electrodes 45 and 46 in the next step of plating the external electrodes 45 and 46 for the following reasons. There was a problem of infiltration into the body 41. That is, (1) between the four surfaces where the laminated body 41 and the external electrodes 45 and 46 are in contact with each other, particularly when entering from the boundary between the main surface near the end face of the laminated body 41 and the external electrodes 45 and 46,
(2) External electrodes 4 directly formed on end faces 42a and 42b
The plating solution directly penetrates through the minute hollow holes existing in 5, 46. When the thickness of the external electrodes 45 and 46 is small, it becomes easy to enter.
【００１０】従って、積層体４１の主面に一番近い引き
出し電極４３，４４は、その両端部で覆われる外部電極
４５，４６の肉厚が薄くなっているので、メッキ液が入
りやすくなっており、この引き出し電極４３，４４にメ
ッキ液が入り込むと、高温環境化で内部電極が膨張しデ
ラミネーションやクラックの原因となるという問題点が
あった。Therefore, the extraction electrodes 43 and 44 closest to the main surface of the laminated body 41 are thinner in the external electrodes 45 and 46 which are covered at both ends, so that the plating solution can easily enter. When the plating solution enters the extraction electrodes 43 and 44, the internal electrode expands in a high-temperature environment and causes delamination and cracks.
【００１１】本発明は、上述の問題点に鑑みて案出され
たものであり、その目的は、外部電極との接続性を向上
させるとともに、積層体の焼成時のデラミネーション
や、熱衝撃試験によりクラックが発生することがなく、
積層体の平面平行度を得ることができ、また、外部電極
の表面をメッキする工程においてもメッキ液の浸入を防
止して高温環境化で内部電極が膨張しデラミネーション
やクラックを防止することができる積層セラミックコン
デンサを提供することにある。The present invention has been devised in view of the above-mentioned problems, and has as its object to improve the connectivity with external electrodes, and to perform delamination at the time of firing a laminate and a thermal shock test. Cracks do not occur,
The plane parallelism of the laminate can be obtained, and the plating solution can be prevented from penetrating even in the step of plating the surface of the external electrode, and the internal electrode can be expanded in a high temperature environment to prevent delamination and cracking. It is an object of the present invention to provide a multilayer ceramic capacitor that can be used.
【００１２】[0012]
【課題を解決するための手段】上述の課題を解決するた
めに本発明は、誘電体層を複数積層して成る積層体の対
向する両端面から内部に向かって延び、かつ、互いの先
端が所定間隔隔てるように突き合わせて配置した第１及
び第２の内部電極と、前記第１，第２の内部電極の双方
と前記誘電体層を介して一部が重なり合う第３の内部電
極と、前記積層体の両端面に形成し、前記第１、第２の
内部電極と接続した第１、第２の外部電極とからなる積
層セラミックコンデンサにおいて、前記第１、第２の内
部電極のうち、前記第３の内部電極と重なり合わない内
部電極の領域の層厚が、重なり合う領域の層厚に比べて
厚いことを特徴とする積層セラミックコンデンサを提供
する。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to a laminated body formed by laminating a plurality of dielectric layers, extending inward from opposing both end faces, and having the tips of each other. A first and a second internal electrode arranged in abutting manner at a predetermined interval, a third internal electrode partially overlapping with both the first and the second internal electrodes via the dielectric layer, In a multilayer ceramic capacitor formed on both end surfaces of a multilayer body and including first and second external electrodes connected to the first and second internal electrodes, the first and second internal electrodes may include: A multilayer ceramic capacitor characterized in that the layer thickness of the region of the internal electrode that does not overlap with the third internal electrode is thicker than the layer thickness of the region that overlaps.
【００１３】本発明の構成によれば、第１、第２の内部
電極のうち、前記第３の内部電極と重なり合わない内部
電極の領域の層厚が、重なり合う領域の層厚に比べて厚
いために未焼成状態で積層体の両端部が第１、第２の内
部電極の厚みによりへこみを防止することができ、これ
により、積層体の平面平行度を維持させることができ
る。その結果、誘電体層間の剥離・密着不良を大幅に減
少させると共に、第１，第２の外部電極との接続性を向
上させることができる。According to the structure of the present invention, of the first and second internal electrodes, the layer thickness of the region of the internal electrode which does not overlap with the third internal electrode is larger than the layer thickness of the overlapping region. Therefore, dents can be prevented at both ends of the laminate in the unfired state due to the thicknesses of the first and second internal electrodes, whereby the plane parallelism of the laminate can be maintained. As a result, peeling and poor adhesion between the dielectric layers can be significantly reduced, and the connectivity with the first and second external electrodes can be improved.
【００１４】また、前記積層体の両主面に近い内部電極
を前記第３の内部電極としてもよい。即ち、メッキ工程
において外部電極からメッキ液が浸入した場合に、肉厚
を厚く形成した第１、第２の内部電極の部位はメッキ液
と接触しやすいが、第３の内部電極が積層体の両主面と
第１、第２の内部電極の間に介在されているので、積層
体の角部である外部電極の肉厚が薄く形成されている部
位から第１，第２の内部電極を遠ざけることができ、こ
れにより、メッキ液の浸入による高温環境化で内部電極
が膨張してデラミネーションの発生やクラックの発生を
防止することができる。Further, an internal electrode near both main surfaces of the laminate may be used as the third internal electrode. That is, when the plating solution infiltrates from the external electrode in the plating step, the first and second internal electrodes formed to have a large thickness are easily in contact with the plating solution, but the third internal electrode is formed of the laminated body. Since the first and second internal electrodes are interposed between the two main surfaces and the first and second internal electrodes, the first and second internal electrodes are formed from a portion where the thickness of the external electrode, which is a corner of the laminated body, is thin. This can prevent the internal electrodes from expanding due to a high-temperature environment caused by the infiltration of the plating solution, thereby preventing the occurrence of delamination and cracks.
【００１５】[0015]
【発明の実施の形態】以下、本発明の積層セラミックコ
ンデンサを図面に基づいて詳説する。図１は本発明に係
る積層セラミックコンデンサの外観斜視図であり、図２
は図１の積層セラミックコンデンサの断面図であり、図
３は図１の積層セラミックコンデンサの透視平面図であ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer ceramic capacitor according to the present invention will be described in detail with reference to the drawings. FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to the present invention, and FIG.
FIG. 3 is a sectional view of the multilayer ceramic capacitor of FIG. 1, and FIG. 3 is a perspective plan view of the multilayer ceramic capacitor of FIG.
【００１６】この積層セラミックコンデンサ１０におい
ては、チタン酸バリウム、チタン酸ストロンチウムなど
の誘電体からなる直方体形状の積層体１と、積層体１の
相対向する一対の端面に夫々形成した外部電極５、６と
からなっている。外部電極５，６は積層体１の端面に直
接形成する厚膜下地導体層５ａ，６ａ及びその表面にメ
ッキ層５ｂ，６ｂがそれぞれ形成されている。In this multilayer ceramic capacitor 10, a rectangular parallelepiped laminate 1 made of a dielectric material such as barium titanate or strontium titanate, and external electrodes 5 formed on a pair of opposed end surfaces of the laminate 1, respectively. It consists of six. The external electrodes 5 and 6 have thick film underlying conductor layers 5a and 6a formed directly on the end face of the multilayer body 1 and plating layers 5b and 6b formed on the surfaces thereof.
【００１７】積層体１は、複数の誘電体層１ａ〜１ｆが
積層してなる。各誘電体層１間には、ＰｄまたはＡｇ−
Ｐｄ合金などの貴金属材料あるいはＮｉなどの卑金属材
料からなる第１、第２の内部電極３、４及び第３内部電
極７とが交互に配置されている。The laminate 1 is formed by laminating a plurality of dielectric layers 1a to 1f. Between each dielectric layer 1, Pd or Ag-
First and second internal electrodes 3 and 4 and third internal electrodes 7 made of a noble metal material such as a Pd alloy or a base metal material such as Ni are alternately arranged.
【００１８】なお、第１の内部電極３の一端部は外部電
極５に、また、内部電極４の一端部は外部電極６にそれ
ぞれ接続され、内部電極３，４の他端部は互いの先端が
所定間隔隔てて突き合わせて配置されている。また、内
部電極３は浮き電極であり、第１，第２の内部電極３，
４の多端部で互いに重なるように配置されている。One end of the first internal electrode 3 is connected to the external electrode 5, one end of the internal electrode 4 is connected to the external electrode 6, and the other ends of the internal electrodes 3 and 4 are connected to each other. Are arranged facing each other at a predetermined interval. The internal electrode 3 is a floating electrode, and the first and second internal electrodes 3
4 are arranged so as to overlap each other at multiple ends.
【００１９】さらに、積層体１の主面に近い内部電極を
第３の電極７が配置されており、第３の内部電極７にお
ける上部側のトップマージン層となる誘電体層１ａと、
下部側のトップマージン層となる誘電体層１ｆとが介在
されている。ここで、前記第１、第２内部電極３、４と
第３の内部電極７が重なりあう領域の厚さは、重ならな
い領域の厚さに比べて厚く形成されている。さらに第
１、第２の内部電極３、４の両端部が積層体１の端面に
剥き出して、外部電極５及び外部電極６に厚み領域で接
続される。Further, a third electrode 7 is disposed as an internal electrode close to the main surface of the multilayer body 1, and a dielectric layer 1a serving as a top margin layer on the upper side of the third internal electrode 7;
A dielectric layer 1f serving as a lower top margin layer is interposed. Here, the thickness of the region where the first and second internal electrodes 3 and 4 and the third internal electrode 7 overlap is formed to be thicker than the thickness of the non-overlapping region. Furthermore, both ends of the first and second internal electrodes 3 and 4 are exposed on the end surface of the multilayer body 1 and are connected to the external electrodes 5 and 6 in the thickness region.
【００２０】上記構成の積層セラミックコンデンサ１０
はつぎのように作製する。第１，第２の内部電極３、４
の導電層パターンと第３の内部電極７の導電層パターン
が同一のスクリーン上に１層おきに形成されている。そ
して、誘電体層となるグリーンシート上に第１、第２の
内部電極３，４、第３の内部電極７を印刷する。このと
き、第３の内部電極７と重なり合わない部分の第１，第
２の内部電極を厚くするために、第１，第２の内部電極
３，４を印刷する際に、スクリーンパターンのメッシュ
の開きを第３の内部電極と重なり合う第１，第２の内部
電極３，４の領域は薄くし、それに比べて重なり合わな
い部分を厚くしたスクリーンを用いて印刷する。The multilayer ceramic capacitor 10 having the above structure
Is prepared as follows. First and second internal electrodes 3 and 4
And the conductive layer pattern of the third internal electrode 7 are formed every other layer on the same screen. Then, the first and second internal electrodes 3 and 4 and the third internal electrode 7 are printed on the green sheet serving as the dielectric layer. At this time, when printing the first and second internal electrodes 3 and 4 to increase the thickness of the first and second internal electrodes in a portion that does not overlap with the third internal electrode 7, a mesh of a screen pattern is used. The area of the first and second internal electrodes 3 and 4 overlapping the third internal electrode is made thinner, and printing is performed using a screen in which the non-overlapping parts are made thicker.
【００２１】この印刷後、各内部電極が形成されたグリ
ーンシートを交互に積層し、この積層したグリーンシー
トを仮プレスする。そして、これを、形状に応じて寸法
に切断してチップ材を形成する。ついで、このチップ材
を所定の雰囲気、温度で焼成し、内部電極を一体的に焼
結する。これにより、積層体１を作製する。After this printing, the green sheets on which the internal electrodes are formed are alternately laminated, and the laminated green sheets are temporarily pressed. Then, this is cut into dimensions according to the shape to form a chip material. Next, the chip material is fired in a predetermined atmosphere and temperature, and the internal electrodes are integrally sintered. Thus, the laminate 1 is manufactured.
【００２２】次に積層体１の端面に、外部電極５、６を
形成する。具体的には、厚膜下地導体層５ａ，６ａの形
成をディップ法、即ち、導電性ペーストの入った槽に積
層体１の端面を漬けて塗布形成する。この場合の導体ペ
ーストはＡｇまたはＡｇ−Ｐｄ合金からなる。この塗布
形成した厚膜下地導体層５ａ，６ａの表面にＮｉやＮｉ
−Ｓｎ等でメッキ処理をおこなうことで積層セラミック
コンデンサが製造される。Next, external electrodes 5 and 6 are formed on the end surfaces of the laminate 1. Specifically, the formation of the thick film underlying conductor layers 5a and 6a is performed by dipping, that is, by applying the end face of the laminate 1 in a bath containing a conductive paste. In this case, the conductor paste is made of Ag or an Ag-Pd alloy. Ni or Ni is coated on the surfaces of the thick base conductor layers 5a and 6a formed by coating.
By performing plating with -Sn or the like, a multilayer ceramic capacitor is manufactured.
【００２３】ここで、図５（ｂ）のように、積層体１の
主面に近い内部電極を第１、第２の内部電極３，４とし
た場合には、第３の内部電極３を配置した場合に比べ
て、その端部から積層体１の角部における膜厚下地導体
膜５ａの膜厚の長さｄ2がｄ１に比べて短くなってい
る。これによって、この膜厚の長さｄ2が短いためにメ
ッキ処理の工程でメッキ液が浸入しやすくなってしま
い、その結果、絶縁抵抗特性が劣化し、湿中耐圧試験で
の信頼性が大きく低下する。Here, as shown in FIG. 5B, when the internal electrodes near the main surface of the laminate 1 are the first and second internal electrodes 3 and 4, the third internal electrode 3 is The thickness d2 of the film thickness of the base conductor film 5a from the end to the corner of the laminate 1 from the end is shorter than d1. As a result, the plating solution easily penetrates in the plating process because the length d2 of the film thickness is short, and as a result, the insulation resistance characteristics are deteriorated, and the reliability in the humidity and pressure resistance test is greatly reduced. I do.
【００２４】しかし、図５（ａ）に示すように積層体１
の主面に近い内部電極を第３の内部電極７とした場合
は、次にくる第１，第２の内部電極３，４の距離が外部
電極５の薄くなっている積層体１の角部から距離ｄ２分
まで遠ざけることができ、メッキ液浸入による不具合を
防止することができる。However, as shown in FIG.
In the case where the internal electrode close to the main surface is the third internal electrode 7, the distance between the next first and second internal electrodes 3, 4 is the corner of the laminated body 1 where the external electrode 5 is thin. , And a distance d2 from the plating solution, thereby preventing problems caused by infiltration of the plating solution.
【００２５】かくして、本発明の積層セラミックコンデ
ンサによれば、第１、第２の内部電極３，４のうち、第
３の内部電極７と重なり合わない内部電極の領域の層厚
が、重なり合う領域の層厚に比べて厚いために、未焼成
状態で積層体１の両端部が各第１，第２の内部電極３，
４の厚みによりへこみを防止することができ、これによ
り、積層体１の平面平行度を維持させることができる。
その結果、誘電体層間の剥離・密着不良を大幅に減少さ
せると共に、第１，第２の外部電極３，４との接続性を
向上させることができる。Thus, according to the multilayer ceramic capacitor of the present invention, the layer thickness of the first and second internal electrodes 3 and 4 which are not overlapped with the third internal electrode 7 are limited to the overlapped area. Since the thickness is larger than the thickness of each of the first and second internal electrodes 3 in the unfired state,
Depression can be prevented by the thickness of 4, whereby the plane parallelism of the laminate 1 can be maintained.
As a result, peeling and poor adhesion between the dielectric layers can be significantly reduced, and the connectivity with the first and second external electrodes 3 and 4 can be improved.
【００２６】また、積層体１の両主面に近い内部電極を
第３の内部電極７とすることにより、メッキ工程におい
て外部電極５，６からメッキ液が浸入した場合に、肉厚
を厚く形成した第１、第２の内部電極３，４の部位はメ
ッキ液と接触しやすいが、第３の内部電極７が積層体１
の両主面と第１、第２の内部電極３，４の間に介在され
ているので、積層体１の角部である外部電極５，６の肉
厚が薄く形成されている部位から第１，第２の内部電極
３，４を遠ざけることができ、これにより、メッキ液の
浸入によるメッキ液の浸入による高温環境化で内部電極
が膨張してデラミネーションの発生やクラックの発生を
防止することができる。Further, by using the internal electrodes near both main surfaces of the laminated body 1 as the third internal electrodes 7, when the plating solution penetrates from the external electrodes 5 and 6 in the plating step, the internal electrodes are formed to be thick. Although the portions of the first and second internal electrodes 3 and 4 that have been formed easily come into contact with the plating solution, the third internal electrode 7 is
Between the two main surfaces and the first and second internal electrodes 3 and 4, the outer electrodes 5 and 6, which are the corners of the multilayer body 1, are formed from the thinner portions to the first and second inner electrodes 3 and 4. The first and second internal electrodes 3 and 4 can be kept away from each other, thereby preventing the occurrence of delamination and cracks due to the expansion of the internal electrodes due to the high temperature environment caused by the infiltration of the plating solution by the infiltration of the plating solution. be able to.
【００２７】なお、本発明は上記の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲内
での種々の変更や改良等は何ら差し支えない。It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.
【００２８】[0028]
【発明の効果】以上のように、本発明によれば、第１、
第２の内部電極のうち、前記第３の内部電極と重なり合
わない内部電極の領域の層厚が、重なり合う領域の層厚
に比べて厚いために未焼成状態で積層体の両端部が第
１、第２の内部電極の厚みによりへこみを防止すること
ができ、これにより、積層体の平面平行度を維持させる
ことができる。その結果、誘電体層間の剥離・密着不良
を大幅に減少させると共に、第１，第２の外部電極との
接続性を向上させることができる。As described above, according to the present invention, the first,
In the second internal electrode, since the layer thickness of the region of the internal electrode that does not overlap with the third internal electrode is larger than the layer thickness of the overlapping region, both ends of the stacked body are unfired in the first state. In addition, dents can be prevented by the thickness of the second internal electrode, whereby the plane parallelism of the stacked body can be maintained. As a result, peeling and poor adhesion between the dielectric layers can be significantly reduced, and the connectivity with the first and second external electrodes can be improved.
【００２９】また、前記積層体の両主面に近い内部電極
を前記第３の内部電極とすることで、メッキ工程におい
て外部電極からメッキ液が浸入した場合に、肉厚を厚く
形成した第１、第２の内部電極の部位はメッキ液と接触
しやすいが、第３の内部電極が積層体の両主面と第１、
第２の内部電極の間に介在されているので、積層体の角
部である外部電極の肉厚が薄く形成されている部位から
第１，第２の内部電極を遠ざけることができ、これによ
り、メッキ液の浸入によるメッキ液の浸入による高温環
境化で内部電極が膨張してデラミネーションの発生やク
ラックの発生を防止することができる。Further, by using the internal electrodes close to both main surfaces of the laminated body as the third internal electrodes, when the plating solution infiltrates from the external electrodes in the plating step, the first electrode is formed to have a large thickness. , The second internal electrode is likely to come into contact with the plating solution, but the third internal electrode is in contact with both main surfaces of the laminate and the first and second internal electrodes.
Since it is interposed between the second internal electrodes, the first and second internal electrodes can be kept away from the corners of the laminate where the thickness of the external electrodes is reduced. In addition, it is possible to prevent the occurrence of delamination and cracks due to expansion of the internal electrodes due to a high-temperature environment caused by intrusion of the plating solution due to intrusion of the plating solution.
【図１】本発明の積層セラミックコンデンサの外観斜視
図である。FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to the present invention.
【図２】本発明の積層セラミックコンデンサの断面図で
ある。FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor of the present invention.
【図３】図２の積層セラミックコンデンサの透視平面図
である。FIG. 3 is a perspective plan view of the multilayer ceramic capacitor of FIG. 2;
【図４】従来の積層セラミックコンデンサの断面図であ
る。FIG. 4 is a cross-sectional view of a conventional multilayer ceramic capacitor.
【図５】積層セラミックコンデンサの部分説明図であ
る。FIG. 5 is a partial explanatory view of the multilayer ceramic capacitor.
１０・・・・・・・・積層セラミックコンデンサ １・・・・・・・・・積層体 ２、４２・・・・・・誘電体層 ３、４３・・・・・・第１内部電極 ４、４４・・・・・・第２内部電極 ５、４５・・・・・・第１外部電極 ６、４６・・・・・・第２外部電極 ７、４７・・・・・・第３内部電極 10 Multilayer ceramic capacitor 1 Multilayer body 2, 42 Dielectric layer 3, 43 First internal electrode 4 , 44... Second internal electrode 5, 45... First external electrode 6, 46... Second external electrode 7, 47. electrode
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E001 AB03 AC03 AC04 AC06 AC09 AC10 AE01 AE02 AE03 AF00 AF06 AH01 AH05 AH06 AH09 AJ01 AZ01 5E082 AA01 AB03 BC33 CC03 CC12 CC13 EE04 EE12 EE17 EE23 EE35 FG06 FG26 FG27 FG54 GG10 GG11 GG26 GG28 JJ03 JJ05 JJ12 JJ21 JJ23 LL02 LL03 MM22 PP09 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) JJ03 JJ05 JJ12 JJ21 JJ23 LL02 LL03 MM22 PP09
Claims (2)
向する両端面から内部に向かって延び、かつ、互いの先
端が所定間隔隔てるように突き合わせて配置した第１及
び第２の内部電極と、前記第１，第２の内部電極の双方
と前記誘電体層を介して一部が重なり合う第３の内部電
極と、前記積層体の両端面に形成し、前記第１、第２の
内部電極と接続した第１，第２の外部電極とからなる積
層セラミックコンデンサにおいて、 前記第１、第２の内部電極のうち、前記第３の内部電極
と重なり合わない内部電極の領域の層厚が、重なり合う
領域の層厚に比べて厚いことを特徴とする積層セラミッ
クコンデンサ。1. A first and a second inner part which extend inward from opposing end faces of a laminated body formed by laminating a plurality of dielectric layers, and which are arranged so that their tips are spaced apart by a predetermined distance. An electrode, a third internal electrode that partially overlaps both the first and second internal electrodes via the dielectric layer, and a first internal electrode formed on both end surfaces of the multilayer body; In the multilayer ceramic capacitor including the first and second external electrodes connected to the internal electrode, a layer thickness of a region of the first and second internal electrodes that does not overlap with the third internal electrode However, the multilayer ceramic capacitor is characterized in that it is thicker than the layer thickness of the overlapping area.
記第３の内部電極とすることを特徴とする請求項１記載
の積層セラミックコンデンサ。2. The multilayer ceramic capacitor according to claim 1, wherein internal electrodes near both main surfaces of the multilayer body are used as the third internal electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36788399A JP2001185440A (en) | 1999-12-24 | 1999-12-24 | Laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36788399A JP2001185440A (en) | 1999-12-24 | 1999-12-24 | Laminated ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001185440A true JP2001185440A (en) | 2001-07-06 |
Family
ID=18490445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36788399A Pending JP2001185440A (en) | 1999-12-24 | 1999-12-24 | Laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001185440A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7329976B2 (en) * | 2005-04-27 | 2008-02-12 | Kyocera Corporation | Laminated electronic component |
| US8508911B2 (en) | 2011-01-28 | 2013-08-13 | Murata Manufacturing Co., Ltd. | Electronic component and substrate module |
| JP2013536989A (en) * | 2010-09-03 | 2013-09-26 | エプコス アーゲー | Ceramic device and manufacturing method thereof |
| US8576538B2 (en) | 2011-01-28 | 2013-11-05 | Murata Manuacturing Co., Ltd. | Electronic component and substrate module |
| US8587920B2 (en) | 2011-05-31 | 2013-11-19 | Samsung Electr-Mechanics Co., Ltd. | Multilayer ceramic electronic component and method for manufacturing the same |
| JP2020126914A (en) * | 2019-02-04 | 2020-08-20 | 株式会社村田製作所 | Coil component |
-
1999
- 1999-12-24 JP JP36788399A patent/JP2001185440A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7329976B2 (en) * | 2005-04-27 | 2008-02-12 | Kyocera Corporation | Laminated electronic component |
| JP2013536989A (en) * | 2010-09-03 | 2013-09-26 | エプコス アーゲー | Ceramic device and manufacturing method thereof |
| US8508911B2 (en) | 2011-01-28 | 2013-08-13 | Murata Manufacturing Co., Ltd. | Electronic component and substrate module |
| US8576538B2 (en) | 2011-01-28 | 2013-11-05 | Murata Manuacturing Co., Ltd. | Electronic component and substrate module |
| US8587920B2 (en) | 2011-05-31 | 2013-11-19 | Samsung Electr-Mechanics Co., Ltd. | Multilayer ceramic electronic component and method for manufacturing the same |
| JP2020126914A (en) * | 2019-02-04 | 2020-08-20 | 株式会社村田製作所 | Coil component |
| JP7099345B2 (en) | 2019-02-04 | 2022-07-12 | 株式会社村田製作所 | Coil parts |
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