JP2001177253A - Manufacturing method for multilayer printed board - Google Patents
Manufacturing method for multilayer printed boardInfo
- Publication number
- JP2001177253A JP2001177253A JP36221499A JP36221499A JP2001177253A JP 2001177253 A JP2001177253 A JP 2001177253A JP 36221499 A JP36221499 A JP 36221499A JP 36221499 A JP36221499 A JP 36221499A JP 2001177253 A JP2001177253 A JP 2001177253A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- resin
- wiring
- via hole
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は多層プリント基板の
製造方法に関し、特にビルドアップ方式で多層化するプ
リント基板の絶縁層を平坦化して、配線形成を容易にす
るための製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer printed circuit board, and more particularly to a method of manufacturing a multilayer printed circuit board by flattening an insulating layer of a printed circuit board to facilitate wiring formation.
【０００２】[0002]
【従来の技術】多層プリント基板の製造方法としては、
従来、導体回路が形成された複数の配線板を接着樹脂層
であるプリプレグを介して積層プレスすることで多層化
し、次いでスルーホール穴あけをしたのち、このスルー
ホール内を銅メッキすることで層間の導通をとる方法が
主流であった（積層接着法）。しかしながら、この方法
ではエッチング法により回路を形成するため微細配線の
形成に限界があり、また、配線板にガラス繊維入りの絶
縁樹脂が用いられるため相関の導通確保用のスルーホー
ルがドリルを用いなければ加工できず、穴径とピッチの
限界から高密度化が難しいという問題がある。2. Description of the Related Art A method of manufacturing a multilayer printed circuit board includes:
Conventionally, a plurality of wiring boards on which conductive circuits are formed are laminated by pressing through a prepreg, which is an adhesive resin layer, to form a multilayer, and then a through-hole is drilled, and then the inside of the through-hole is plated with copper to form an interlayer. The method of establishing conduction was the mainstream (lamination bonding method). However, in this method, there is a limit in forming fine wiring because a circuit is formed by an etching method, and a through hole for securing conduction of correlation must be used with a drill because an insulating resin containing glass fiber is used for a wiring board. However, there is a problem that it is difficult to process the material, and it is difficult to increase the density due to the limitations of the hole diameter and pitch.
【０００３】この問題を解決するため、表面に回路を形
成した通常のプリント基板をコア基板として、その上に
絶縁樹脂層と配線層を交互に積み重ね、バイアホールに
よって相関の導通を確保する、いわゆるビルドアップ基
板の開発が進められている。In order to solve this problem, a so-called normal printed circuit board having a circuit formed on its surface is used as a core board, and insulating resin layers and wiring layers are alternately stacked on the printed circuit board, and the conduction of correlation is secured by via holes. Build-up boards are being developed.
【０００４】このビルドアップ基板における配線層の形
成には二種類あり、ひとつは全面に銅メッキしたところ
を従来と同じエッチング法でパターニングするサブトラ
クティブ方式であり、他のひとつはレジストで作ったガ
イドの間にメッキで銅を積み上げるアディティブ方式で
ある。ビルドアップ基板ではレーザ加工や写真法を応用
した露光現像プロセスで作製した微細ビア穴によって相
関の導通確保を行うため（それぞれ、レーザビア方式お
よびフォトビア方式と呼ぶ）、サブトラクティブ方式で
回路を形成しても従来の積層接着法に比べればかなり高
密度化が図れる。There are two types of wiring layers formed on this build-up substrate. One is a subtractive method in which copper plating is performed on the entire surface by the same etching method as before, and the other is a guide made of resist. This is an additive method in which copper is accumulated by plating between the two. On the build-up substrate, the circuit is formed by the subtractive method in order to secure the continuity of the correlation by the fine via hole made by the exposure and development process using laser processing and photographic method (referred to as laser via method and photo via method, respectively). Also, the density can be considerably increased as compared with the conventional laminating method.
【０００５】しかしながら、化学エッチングではサイド
エッチングがあるため微細幅で高アスペクト比の配線を
形成するのは難しく、いっそうの高密度化を図るにはア
ディティブ方式が必須である。このビルドアップ基板で
は銅メッキで微細な配線層を積み上げるため、レーザビ
ア方式とフォトビア方式を問わず配線層と絶縁樹脂層と
の密着力確保と微細配線形成時の断線不良防止が重要な
課題で、そのためほとんどの場合、絶縁層の平坦化と表
面粗化が行われる。そして、この目的のため各種のプロ
セスが考案されている。However, it is difficult to form a wiring having a fine width and a high aspect ratio due to side etching in chemical etching, and an additive method is indispensable for further increasing the density. In this build-up board, since the fine wiring layer is built up by copper plating, it is important to ensure the adhesion between the wiring layer and the insulating resin layer and prevent disconnection failure at the time of forming fine wiring regardless of the laser via method and the photo via method. Therefore, in most cases, planarization and surface roughening of the insulating layer are performed. Various processes have been devised for this purpose.
【０００６】図３は従来工程のひとつを示したもので、
公開特許公報の特開平１１−１８６７３７号において開
示されているものである。まず、外層に配線２が形成さ
れ、スルーホールが樹脂３によって穴埋めされたコア基
板１（ａ）の表面に感光性絶縁樹脂４を塗布しプリベー
クする（ｂ）。次いで、写真法を用いたパターン露光と
現像によりビア穴７を形成したのち加熱硬化させる
（ｃ）。さらに、この絶縁樹脂４の表面を機械的に研磨
することによりその表面を平坦化し（ｄ）、アルカリ溶
液を用いた化学エッチングによって絶縁樹脂４の表面を
粗化する。次いで、この粗化した絶縁樹脂４の表面に感
光性のメッキレジスト８を塗布した後、同じく紫外光を
用いたパターン露光と現像によりパターニングし、配線
部並びにビア穴部に相当する部分のメッキレジストを除
去する（ｅ）。最後に、このメッキレジストが除去され
た部分に銅メッキ９を施して導体層を形成する（ｆ）。FIG. 3 shows one of the conventional processes.
This is disclosed in Japanese Patent Application Laid-Open No. 11-186737. First, the wiring 2 is formed in the outer layer, and the photosensitive insulating resin 4 is applied to the surface of the core substrate 1 (a) in which the through holes are filled with the resin 3 and prebaked (b). Next, a via hole 7 is formed by pattern exposure and development using a photographic method, followed by heat curing (c). Further, the surface of the insulating resin 4 is flattened by mechanically polishing the surface (d), and the surface of the insulating resin 4 is roughened by chemical etching using an alkaline solution. Next, a photosensitive plating resist 8 is applied to the surface of the roughened insulating resin 4 and then patterned by pattern exposure and development using ultraviolet light to form a plating resist corresponding to wiring portions and via holes. (E). Finally, copper plating 9 is applied to the portion where the plating resist has been removed to form a conductor layer (f).
【０００７】また、図４は別の公知例を示したものであ
り、公開特許公報の特開平１０−５６２６７号において
開示されている。なお、図４のコア基板の形状は公知例
と若干異なっているが、基本的なプロセスは公知例と同
じである。FIG. 4 shows another known example, which is disclosed in Japanese Patent Application Laid-Open No. H10-56267. Although the shape of the core substrate in FIG. 4 is slightly different from that of the known example, the basic process is the same as that of the known example.
【０００８】このプロセスでは、まずコア基板１の表面
にある配線間スペースにエポキシ等の樹脂４’を埋め込
んで配線段差を補正することで基板表面をほぼ平らにす
る（ｂ）。次いで、この上に絶縁樹脂層４を塗布したの
ち（ｃ）、ビア穴７を形成する（ｄ）。その後、ビア穴
内部を含めた表面全体に導体１０をメッキし（ｅ）、サ
ブトラクティブ法によって不要な部分の導体を除去する
ことによってビルドアップ回路が形成される（ｆ）。In this process, first, a resin surface 4 'such as epoxy is buried in a space between wirings on the surface of the core substrate 1 to correct wiring level differences, thereby making the substrate surface almost flat (b). Next, after applying an insulating resin layer 4 thereon, a via hole 7 is formed (d). Thereafter, the conductor 10 is plated on the entire surface including the inside of the via hole (e), and an unnecessary portion of the conductor is removed by a subtractive method to form a build-up circuit (f).
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、前記し
た第一の公知例においては、絶縁層樹脂４がコア基板表
面の導体配線の上に直接塗布されるため、配線の有無に
よって塗布樹脂厚に差が生じる。つまり表面に配線厚に
ほぼ相当する凹凸ができる。さらに、通常コア基板のス
ルーホールメッキの際にはコア基板外表面にもメッキが
付着するため、コア基板の配線厚はメッキ分だけさらに
厚くなっている。このため、配線上の樹脂高さと配線間
の樹脂高さの差はますます大きくなる。後工程の機械研
磨によってこの段差を除去した後に所定の絶縁層厚さを
確保するためには、塗布厚はかなり大きくする必要があ
る。この結果、写真法でビア穴パターンを露光し、現像
によってビア穴部の材料を溶解除去する際に、樹脂厚が
厚すぎるため穴底まで露光光が到達せず、小径のビア穴
形成が難しいという問題がある。さらに、表面に大きな
うねりや段差があると微細配線を形成する際に断線が生
じやすい。つまり、ビルドアップ基板においては絶縁層
の平坦性を確保するのが極めて重要な課題である。However, in the first known example, since the insulating layer resin 4 is applied directly on the conductor wiring on the surface of the core substrate, the thickness of the applied resin differs depending on the presence or absence of the wiring. Occurs. That is, irregularities substantially corresponding to the wiring thickness are formed on the surface. Further, when plating the through hole of the core substrate, the plating also adheres to the outer surface of the core substrate, so that the wiring thickness of the core substrate is further increased by the amount of the plating. For this reason, the difference between the resin height on the wiring and the resin height between the wirings is further increased. In order to secure a predetermined thickness of the insulating layer after removing the step by mechanical polishing in a later step, the coating thickness needs to be considerably large. As a result, when exposing the via hole pattern by photographic method and dissolving and removing the material of the via hole portion by development, the exposure light does not reach the hole bottom because the resin thickness is too thick, and it is difficult to form a small diameter via hole. There is a problem. Further, if there are large undulations or steps on the surface, disconnection is likely to occur when forming fine wiring. That is, it is extremely important to secure the flatness of the insulating layer in the build-up substrate.
【００１０】また、第二の公知例では、配線段差を樹脂
４’であらかじめ埋めておいた後で、絶縁層樹脂を塗布
するため全般的に平坦性は良くなるが、余分な塗布と乾
燥・硬化工程を必要とするためスループットが落ち、製
造コストも高くなる。塗布・硬化は両面同時にはできな
いためこれを両面に渡って行うと、さらに時間がかかる
ことになる。また、樹脂の塗布をスクリーン印刷法など
で行うと、大きな段差は無くなるが、印刷時のメッシュ
後などによる５μｍ程度の段差は残ることになる。In the second known example, after the wiring step is filled in advance with the resin 4 ', the insulating layer resin is applied to improve the overall flatness. The need for a curing step lowers throughput and increases manufacturing costs. Since application and curing cannot be performed simultaneously on both sides, if this is performed over both sides, it will take more time. Further, when the resin is applied by a screen printing method or the like, a large step is eliminated, but a step of about 5 μm due to a mesh after printing or the like remains.
【００１１】[0011]
【課題を解決するための手段】前記した従来技術の課題
を解決するため、新たに発明した平坦化方法の基本的プ
ロセスは以下の通りである。To solve the above-mentioned problems of the prior art, a basic process of a flattening method newly invented is as follows.
【００１２】まず、コア基板の表面に感光性の絶縁層樹
脂を塗布し、プリベークする。次に、加圧板を絶縁層表
面に押し付けて背面からほぼ一様な分布を持つ荷重で加
圧する。First, a photosensitive insulating layer resin is applied to the surface of the core substrate and prebaked. Next, a pressure plate is pressed against the surface of the insulating layer and pressed from the back with a load having a substantially uniform distribution.
【００１３】この際、プリベーク状態では樹脂の流動性
は残っているため、加圧により凸の部分の樹脂が塑性流
動し近傍の凹の部分に流れ込む。そして表面全体がほぼ
平らになったところで加圧力と樹脂の流動抵抗がバラン
スし、自動的に平坦化工程が停止する。この方法により
絶縁層樹脂の表面を平坦化すると同時に、絶縁層樹脂が
コア基板表面の配線段差に完全に充填されるようにする
ものである。At this time, since the fluidity of the resin remains in the pre-baked state, the resin in the convex portion plastically flows by pressure and flows into the concave portion in the vicinity. Then, when the entire surface is substantially flat, the pressing force and the flow resistance of the resin are balanced, and the flattening process automatically stops. By this method, the surface of the insulating layer resin is flattened, and at the same time, the insulating layer resin is completely filled in the wiring steps on the surface of the core substrate.
【００１４】[0014]
【発明の実施の形態】以下、本発明の具体的な実施例に
ついて図面を用いて詳述する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.
【００１５】《実施例１》図１は本発明の第一の実施例
を示すもので、フォトビア方式のビルドアップ基板の製
造工程を示したものである。Embodiment 1 FIG. 1 shows a first embodiment of the present invention and shows a manufacturing process of a photo-via type build-up substrate.
【００１６】図において、１はコア基板、２はコア基板
の表面配線、３はスルーホールに充填された樹脂、４は
感光性絶縁樹脂、５は加圧板、６は加圧力、７はビア
穴、８はメッキレジスト、９は銅メッキ配線、をそれぞ
れ意味する。In the figure, 1 is a core substrate, 2 is a surface wiring of the core substrate, 3 is a resin filled in a through hole, 4 is a photosensitive insulating resin, 5 is a pressing plate, 6 is a pressing force, and 7 is a via hole. , 8 indicate a plating resist, and 9 indicates a copper plating wiring.
【００１７】まず、スルーホールが樹脂３で充填され、
かつ外層に配線２が形成されたコア基板１を準備する
（ａ）。次にこのコア基板１の両面に感光性樹脂４を塗
布し、１００℃でプリベークする工程を両面に渡って行
う（ｂ）。なお、ここでは絶縁樹脂としてネガ型の感光
性エポキシ樹脂を用いた。First, the through holes are filled with the resin 3,
Further, a core substrate 1 having a wiring 2 formed on an outer layer is prepared (a). Next, the photosensitive resin 4 is applied to both sides of the core substrate 1 and prebaked at 100 ° C. on both sides (b). Here, a negative photosensitive epoxy resin was used as the insulating resin.
【００１８】次に、（ｂ）で形成された感光性樹脂４の
表面に加圧板５を当接し、室温状態で均等な加圧力６を
加えることによってその表面を平坦化する（ｃ）。そし
て、この平坦化した感光性絶縁樹脂４を写真法により紫
外光を用いて露光したのち現像することによって未露光
部分を溶解除去し、ビア穴７を形成した（ｄ）。次に、
この上にフィルム状の感光性メッキレジスト８を載置
し、絶縁樹脂４上に形成するビア穴と配線に相当する部
分をやはり写真法によりパターン状に除去した後
（ｅ）、その除去部分に化学銅メッキを析出させること
によって配線層９を形成する（ｆ）。Next, the pressure plate 5 is brought into contact with the surface of the photosensitive resin 4 formed in (b), and the surface is flattened by applying a uniform pressing force 6 at room temperature (c). Then, the flattened photosensitive insulating resin 4 was exposed to ultraviolet light by a photographic method and then developed to dissolve and remove unexposed portions, thereby forming via holes 7 (d). next,
A photosensitive plating resist 8 in the form of a film is placed on this, and portions corresponding to via holes and wiring formed on the insulating resin 4 are also removed in a pattern by a photographic method (e). The wiring layer 9 is formed by depositing chemical copper plating (f).
【００１９】この方法は、平板状の加圧板を用いて樹脂
表面を加圧し、樹脂の高い部分を押して余分な樹脂を低
い部分に流動させる方法であるため、本質的に樹脂厚が
均一化される方法である。つまり、従来の研磨法では表
面基準で研磨するため、表面は平坦になっても膜厚は均
一化できないが、この方法では面内の樹脂厚分布の均一
性に優れ、また、加圧板表面を高精度に仕上げておけ
ば、従来の研磨法でしばしば見られるようなスクラッチ
も生じない。In this method, the resin surface is pressurized using a flat pressing plate, and a high resin portion is pushed to flow excess resin to a low portion, so that the resin thickness is essentially uniform. It is a method. In other words, in the conventional polishing method, since the surface is polished on the basis of the surface, the film thickness cannot be made uniform even if the surface becomes flat. When finished with high precision, scratches, which are often seen in the conventional polishing method, do not occur.
【００２０】さらに、ドライプロセスであるため、従来
のウエット状態で行う機械研磨に比べて表面の汚染やビ
ア穴内への異物の充填なども生じることがなく、スクラ
ッチが生じないということと合わせて、製造歩留まりも
良くなる。Further, since this is a dry process, there is no occurrence of contamination of the surface and no filling of foreign matter into the via holes, as compared with the conventional mechanical polishing performed in a wet state. The production yield is also improved.
【００２１】なお、以上の説明では発明の要点をわかり
やすくするため、基本の工程だけを示したが、実際には
ビア穴形成後の絶縁樹脂の加熱硬化、銅メッキの密着力
をより上げるため、ビアあ穴形成後にアルカリ溶液によ
って絶縁樹脂４の表面を粗化する工程、メッキの前処理
等々が行われる。In the above description, only the basic steps are shown to make the gist of the invention easy to understand. However, in practice, it is necessary to heat-harden the insulating resin after the formation of the via holes and to increase the adhesion of the copper plating. After the formation of the via holes, a step of roughening the surface of the insulating resin 4 with an alkaline solution, a pretreatment for plating, and the like are performed.
【００２２】《実施例２》図２は本発明の第一の実施例
を示すもので、図１の変形例である。Embodiment 2 FIG. 2 shows a first embodiment of the present invention and is a modification of FIG.
【００２３】図において、１１は加圧板の粗化面、１２
は絶縁樹脂の粗化面、をそれぞれ意味する。In the figure, reference numeral 11 denotes a roughened surface of a pressure plate;
Means a roughened surface of the insulating resin.
【００２４】この実施例では、加圧板５に粗化面１１を
設けておき（ｃ）、この面で絶縁樹脂４を平坦化する際
に、平坦化と同時に樹脂４の表面に細かい凹凸１２を形
成する（ｄ）。この結果、工程（ｇ）で銅メッキを行っ
た際に、銅メッキと絶縁樹脂４の密着力の向上を図るこ
とができる。なお、加圧板の表面を粗化する方法として
は、化学的なエッチング法やサンドブラスト法などの機
械的な粗化法など、いかなる手段でも良い。また、粗化
面粗さは大き過ぎても小さ過ぎても好ましくなく、およ
そ２〜１０μｍＲｔの範囲が好ましい。さらに、線状に
連続して粗化された面も好ましくなく、できれば独立し
たクレータ状に粗化された面が好適である。さらに、プ
リベークされた感光性絶縁樹脂表面にはタック性（粘着
性）が残る場合があるが、このような場合には、加圧板
の粗化面にフッ素樹脂処理することで粘着を防止しても
良い。In this embodiment, a roughened surface 11 is provided on the pressure plate 5 (c), and when the insulating resin 4 is flattened on this surface, fine irregularities 12 are formed on the surface of the resin 4 simultaneously with the flattening. (D). As a result, when the copper plating is performed in the step (g), the adhesion between the copper plating and the insulating resin 4 can be improved. As a method for roughening the surface of the pressure plate, any means such as a mechanical etching method such as a chemical etching method or a sand blast method may be used. Further, it is not preferable that the roughened surface roughness is too large or too small, and a range of about 2 to 10 μmRt is preferable. Further, a surface which is continuously roughened linearly is not preferable, and a surface which is roughened into an independent crater is preferable if possible. Further, tackiness (adhesion) may remain on the pre-baked photosensitive insulating resin surface. In such a case, the roughened surface of the pressure plate is treated with a fluororesin to prevent adhesion. Is also good.
【００２５】[0025]
【発明の効果】以上説明したように、本発明は、フォト
ビアビルドアップ基板の絶縁層表面をドライ状態で、簡
便にかつ高精度に平坦化でき、さらに粗化まで同時にで
きるため、従来の方法に比べてビルドアップ基板の製造
工程を簡略化でき、かつ歩留まりも向上するという効果
がある。また、本平坦化法は絶縁層樹脂凸部の余分な樹
脂を加圧により凹の部分に流動させる方式であり、本質
的に樹脂厚を均一化する手法であることから、本法で製
作した基板は層間絶縁性にも優れているという利点があ
る。As described above, according to the present invention, the insulating layer surface of a photo-via build-up substrate can be easily and accurately flattened in a dry state, and can be simultaneously roughened. This has the effect of simplifying the manufacturing process of the build-up substrate and improving the yield as compared with the above. In addition, this flattening method is a method in which excess resin in the insulating layer resin convex portion is caused to flow to the concave portion by pressurization, and is essentially a method of making the resin thickness uniform. The substrate has an advantage that it has excellent interlayer insulating properties.
【図１】本発明の第１の実施例である製造工程を示す説
明図である。FIG. 1 is an explanatory view showing a manufacturing process according to a first embodiment of the present invention.
【図２】本発明の第２の実施例である製造工程を示す説
明図である。FIG. 2 is an explanatory view showing a manufacturing process according to a second embodiment of the present invention.
【図３】従来の製造工程を示す説明図である。FIG. 3 is an explanatory view showing a conventional manufacturing process.
【図４】従来の製造工程を示す説明図である。FIG. 4 is an explanatory view showing a conventional manufacturing process.
１…コア基板、２…コア基板の表面配線、３…スルーホ
ールに充填された樹脂、４…感光性絶縁樹脂、５…加圧
板、６…加圧力、７…ビア穴、８…メッキレジスト、９
…導体配線、１０…コア表面導体、１１…加圧板の粗化
面、１２…平坦化された樹脂の粗化面。DESCRIPTION OF SYMBOLS 1 ... Core board, 2 ... Surface wiring of core board, 3 ... Resin filled in through hole, 4 ... Photosensitive insulating resin, 5 ... Pressing plate, 6 ... Pressing force, 7 ... Via hole, 8 ... Plating resist, 9
... conductor wiring, 10 ... core surface conductor, 11 ... roughened surface of pressure plate, 12 ... roughened surface of flattened resin.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 宮崎 政志 神奈川県秦野市堀山下１番地 株式会社日 立製作所エンタープライズサーバ事業部内 Ｆターム(参考） 5E343 BB24 BB67 BB71 CC62 DD33 EE33 EE37 ER16 ER18 ER35 FF30 GG04 GG11 5E346 AA04 AA12 AA26 AA32 AA43 AA53 AA54 BB01 CC02 CC08 CC32 DD03 DD23 DD33 DD44 DD47 EE06 EE33 EE38 EE39 FF07 FF13 GG15 GG17 GG18 GG19 GG27 GG40 HH32 HH33 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masashi Miyazaki 1 Horiyamashita, Hadano-shi, Kanagawa F-term in Enterprise Server Division, Hitachi, Ltd. 5E343 BB24 BB67 BB71 CC62 DD33 EE33 EE37 ER16 ER18 ER35 FF30 GG04 GG11 5E346 AA04 AA12 AA26 AA32 AA43 AA53 AA54 BB01 CC02 CC08 CC32 DD03 DD23 DD33 DD44 DD47 EE06 EE33 EE38 EE39 FF07 FF13 GG15 GG17 GG18 GG19 GG27 GG40 HH32 HH33
Claims (3)
ア基板の表面に感光性樹脂からなる絶縁層を形成したの
ちプリベークする工程と、当該プリベークした絶縁層に
加圧板を当接し、加圧することでその表面を平坦化する
工程と、当該平坦化した絶縁層に紫外光による写真法を
用いて穴パターンを露光し、現像によってその部分を除
去することでバイアホールを形成する工程と、このバイ
アホールを形成した絶縁層を加熱硬化させる工程と、当
該加熱硬化させた絶縁層表面を化学的に粗化する工程
と、当該粗化した絶縁層表面に感光性樹脂からなるメッ
キレジスト層を形成し、このメッキレジスト層の、前記
絶縁層のバイアホールに当たる部分並びに前記絶縁層表
面に形成する配線ラインに相当する部分を写真法により
パターン露光したのち現像して除去する工程と、当該現
像により部分的に除去されたメッキレジスト層の除去さ
れた部分に銅メッキを施すことによりバイアホール内部
と絶縁層表面に導体層を形成する工程とからなる多層プ
リント基板の製造方法。1. A step of forming an insulating layer made of a photosensitive resin on the surface of a core substrate having a circuit pattern formed on an outer conductor layer and prebaking, and pressing a pressure plate against the prebaked insulating layer to apply pressure. Forming a via hole by exposing a hole pattern to the flattened insulating layer by photolithography with ultraviolet light and removing the portion by development, and forming the via hole. A step of heating and curing the insulating layer in which the holes are formed; a step of chemically roughening the surface of the insulating layer that has been heated and cured; and forming a plating resist layer made of a photosensitive resin on the surface of the roughened insulating layer. After pattern exposure of a portion of the plating resist layer corresponding to a via hole of the insulating layer and a portion corresponding to a wiring line formed on the surface of the insulating layer by photographic method, A multi-layer process comprising a step of developing and removing, and a step of forming a conductor layer on the inside of the via hole and on the surface of the insulating layer by applying copper plating to the removed portion of the plating resist layer partially removed by the development. Manufacturing method of printed circuit board.
る絶縁層に当接する加圧板の表面を粗化しておくこと
で、加圧後の絶縁層の表面に加圧板の表面凹凸を転写す
ることを特徴とする特許請求項１記載の多層プリント基
板の製造方法。2. The roughening of the surface of the pressure plate in contact with the insulating layer made of the prebaked photosensitive resin makes it possible to transfer the surface irregularities of the pressure plate to the surface of the insulating layer after pressing. 2. The method for manufacturing a multilayer printed circuit board according to claim 1, wherein:
絶縁層の表面を平坦化するに際して、加圧プレスを用い
て行うことを特徴とする特許請求項１に記載の多層プリ
ント基板の製造方法。3. The method for manufacturing a multilayer printed circuit board according to claim 1, wherein the flattening of the surface of the insulating layer made of the prebaked photosensitive resin is performed using a pressure press.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36221499A JP2001177253A (en) | 1999-12-21 | 1999-12-21 | Manufacturing method for multilayer printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36221499A JP2001177253A (en) | 1999-12-21 | 1999-12-21 | Manufacturing method for multilayer printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001177253A true JP2001177253A (en) | 2001-06-29 |
Family
ID=18476285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36221499A Pending JP2001177253A (en) | 1999-12-21 | 1999-12-21 | Manufacturing method for multilayer printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001177253A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100790350B1 (en) * | 2006-04-04 | 2008-01-02 | 엘지전자 주식회사 | Making method of printed circuit board |
| KR100948641B1 (en) * | 2007-10-02 | 2010-03-24 | 삼성전기주식회사 | Method for manufacturing printed circuit board |
| CN106304612A (en) * | 2015-06-29 | 2017-01-04 | 三星电机株式会社 | Printed circuit board and manufacturing methods |
-
1999
- 1999-12-21 JP JP36221499A patent/JP2001177253A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100790350B1 (en) * | 2006-04-04 | 2008-01-02 | 엘지전자 주식회사 | Making method of printed circuit board |
| KR100948641B1 (en) * | 2007-10-02 | 2010-03-24 | 삼성전기주식회사 | Method for manufacturing printed circuit board |
| CN106304612A (en) * | 2015-06-29 | 2017-01-04 | 三星电机株式会社 | Printed circuit board and manufacturing methods |
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