JP2001144448A - Flexible multilayer circuit board - Google Patents
Flexible multilayer circuit boardInfo
- Publication number
- JP2001144448A JP2001144448A JP32648399A JP32648399A JP2001144448A JP 2001144448 A JP2001144448 A JP 2001144448A JP 32648399 A JP32648399 A JP 32648399A JP 32648399 A JP32648399 A JP 32648399A JP 2001144448 A JP2001144448 A JP 2001144448A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- circuit board
- multilayer circuit
- insulating layer
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層化構造の可撓
性回路基板に於いて、絶縁層のアウトガスによる導体パ
タ−ンの膨れを解消できる可撓性多層回路基板に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flexible multi-layer circuit board having a multi-layer structure and capable of eliminating a swelling of a conductor pattern due to outgassing of an insulating layer.
【０００２】[0002]
【従来の技術】この種の可撓性多層回路基板は、絶縁層
を介して複数層に所要の導体パタ−ンを形成するもので
あるが、通常は先ず一層目の所要の導体パタ−ンを適当
な絶縁層上に形成し、次いでその導体パタ−ン上に例え
ば感光性の絶縁層を形成し、このような工程を繰り返し
て多層化構造の可撓性回路基板を構成する。2. Description of the Related Art In a flexible multi-layer circuit board of this kind, a required conductor pattern is formed in a plurality of layers via an insulating layer. Is formed on a suitable insulating layer, and then, for example, a photosensitive insulating layer is formed on the conductor pattern, and such steps are repeated to form a flexible circuit board having a multilayer structure.
【０００３】ここで、各層の導体パタ−ンは、接続の為
のパッド等を含めてその占める面積が大小種々に形成さ
れる。Here, the conductor pattern of each layer has variously large and small areas including pads for connection.
【０００４】[0004]
【発明が解決しようとする課題】ところで、多層回路基
板を構成する上でしばしば発生する問題の一つに加熱処
理工程時に絶縁層等からのアウトガスによる導体パタ−
ンの膨れが生ずるという問題がある。One of the problems that often arises when constructing a multilayer circuit board is that a conductor pattern due to outgas from an insulating layer or the like during a heat treatment step.
There is a problem that swelling occurs.
【０００５】即ち、図５の如く絶縁層１０に例えば加熱
時にアウトガスを発生するような感光性ポリイミド樹脂
等の絶縁材料を用いた場合、多層化していくと最下層の
絶縁層１０は複数回加熱処理され、最初の加熱処理での
未反応物質或いはその後の工程で吸収した水分等のアウ
トガスが矢印のように次の絶縁層１２を含めて導体パタ
−ン１１を膨らませてしまう。That is, as shown in FIG. 5, when an insulating material such as a photosensitive polyimide resin which generates outgas when heated is used for the insulating layer 10, the lowermost insulating layer 10 is heated a plurality of times as the number of layers increases. The unreacted material in the first heat treatment or the outgas such as moisture absorbed in the subsequent process causes the conductor pattern 11 including the next insulating layer 12 to expand as shown by the arrow.
【０００６】しかし、このような膨れは必ずしも生じる
ものではなく、その膨れが生じるか否かはアウトガスの
拡散速度と導体パタ−ンの面積に大きく依存することが
考えられる。However, such swelling does not always occur, and it is considered that whether or not such swelling occurs depends largely on the diffusion rate of outgas and the area of the conductor pattern.
【０００７】そこで、本発明では導体パタ−ンの大きさ
或いは面積を所定値以下に制限するように形成すること
により、絶縁層からのアウトガスによる導体パタ−ンの
膨れを解消できるようにした可撓性多層回路基板を提供
するものである。Therefore, in the present invention, the size or area of the conductor pattern is limited to a predetermined value or less, so that swelling of the conductor pattern due to outgas from the insulating layer can be eliminated. A flexible multilayer circuit board is provided.
【０００８】[0008]
【課題を解決するための手段】その為に本発明に係る可
撓性多層回路基板では、感光性ポリイミド樹脂などの感
光性樹脂材料からなる絶縁層を介して複数層に所要の導
体パタ−ンを形成した可撓性多層回路基板に於いて、前
記導体パタ−ンの大きさ又は面積を所定値以下に制限す
るように構成したものである。For this purpose, in the flexible multilayer circuit board according to the present invention, a required conductor pattern is formed in a plurality of layers via an insulating layer made of a photosensitive resin material such as a photosensitive polyimide resin. Wherein the size or area of the conductor pattern is limited to a predetermined value or less.
【０００９】ここで、前記導体パタ−ンが接続の為のパ
ッドのような大きな面積となるものではその導体パタ−
ンに多数のピンホ−ルを形成することができる。In the case where the conductor pattern has a large area such as a pad for connection, the conductor pattern is
A large number of pinholes can be formed on a pin.
【００１０】[0010]
【発明の実施の形態】以下、図示の実施例を参照しなが
ら本発明を更に詳述する。図１は本発明による可撓性多
層回路基板に於ける導体パタ−ンの膨れの限界を調べる
為の断面説明図であって、図２はその平面説明図であ
る。両図に於いて、絶縁層１は感光性ポリイミド樹脂等
の感光性樹脂材料を用い、その上面には銅等で比較的面
積の小さな導体パタ−ン２と比較的面積の大きな導体パ
タ−ン３とを混在させてアディティブ法等の手段で形成
し、これらの導体パタ−ン２，３上には上記と同様な材
料で他の絶縁層４を形成したものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in further detail with reference to the illustrated embodiments. FIG. 1 is a sectional explanatory view for examining the limit of swelling of a conductor pattern in a flexible multilayer circuit board according to the present invention, and FIG. 2 is a plan explanatory view thereof. In both figures, the insulating layer 1 is made of a photosensitive resin material such as a photosensitive polyimide resin, and has a conductor pattern 2 of relatively small area and a conductor pattern of relatively large area made of copper or the like on its upper surface. 3 is formed by means of the additive method or the like, and another insulating layer 4 is formed on these conductor patterns 2 and 3 with the same material as described above.
【００１１】上記で得られた回路基板を加熱処理した場
合、二度目の加熱時に比較的面積の小さな導体パタ−ン
２は絶縁層１からのアウトガスにより膨れを生じない
が、他の比較的面積の大きな導体パタ−ン３がそのアウ
トガスにより膨れを生じる確率が高かったという場合に
は、現実に所要の導体パタ−ンを形成する際には上記の
如く膨れが生じた導体パタ−ン３の面積よりも下回る配
線幅で所要の導体パタ−ンを形成することにより、可撓
性多層回路基板の加熱処理時に於ける絶縁層からの未反
応物質や水分等のアウトガスによる導体パタ−ンの膨れ
を実質的に軽減することができる。When the circuit board obtained above is subjected to a heat treatment, the conductor pattern 2 having a relatively small area does not swell due to outgas from the insulating layer 1 during the second heating, but the other relatively large area. If the probability that the conductor pattern 3 having a large size of the conductor pattern 3 causes swelling due to the outgassing is high, the conductor pattern 3 having the swelling as described above is actually formed when a required conductor pattern is formed. By forming a required conductor pattern with a wiring width smaller than the area, the conductor pattern swells due to outgas such as unreacted substances and moisture from the insulating layer during the heat treatment of the flexible multilayer circuit board. Can be substantially reduced.
【００１２】このように、導体パタ−ンの大きさ又は面
積を所定値以下に制限できる導体パタ−ンの場合には上
記の手法で絶縁層のアウトガスによる導体パタ−ンの膨
れを実質的に解消できるが、図３の如く、接続の為のパ
ッドのようにどうしても大きな面積を要する導体パタ−
ン５の場合には、その導体パタ−ン５に多数の小さなピ
ンホ−ル６を形成するものである。As described above, in the case of a conductor pattern in which the size or area of the conductor pattern can be limited to a predetermined value or less, the swelling of the conductor pattern due to the outgassing of the insulating layer can be substantially reduced by the above-described method. However, as shown in FIG. 3, a conductor pattern requiring a large area like a pad for connection is inevitable.
In the case of the pin 5, a large number of small pinholes 6 are formed on the conductor pattern 5.
【００１３】上記ピンホ−ル６を有する大きな導体パタ
−ン５を形成した多層回路基板の場合でも、加熱処理時
に発生する絶縁層１からのアウトガスは図４の矢印のよ
うに各ピンホ−ル６から好適に逃げることができるの
で、この導体パタ−ン５の膨れを回避することができ
る。Even in the case of a multilayer circuit board on which a large conductor pattern 5 having the above-mentioned pinholes 6 is formed, outgas from the insulating layer 1 generated at the time of the heat treatment is generated as shown by arrows in FIG. Therefore, the conductor pattern 5 can be prevented from swelling.
【００１４】[0014]
【発明の効果】本発明に係る可撓性多層回路基板では、
絶縁層を介して複数層に所要の導体パタ−ンを形成する
場合、前記導体パタ−ンの大きさ又は面積を所定値以下
に制限するように構成したので、絶縁層に対する加熱処
理時に絶縁層からの未反応物質や水分等によるアウトガ
スによっても導体パタ−ンに膨れの生じない品質の良好
な多層回路基板を提供することができる。According to the flexible multilayer circuit board of the present invention,
When a required conductor pattern is formed in a plurality of layers via an insulating layer, the size or area of the conductor pattern is limited to a predetermined value or less. It is possible to provide a high-quality multilayer circuit board in which the conductor pattern does not swell even by an outgas due to unreacted substances or moisture from the substrate.
【００１５】また、接続の為のパッドのように大きな面
積を要する導体パタ−ンの場合は、その導体パタ−ンに
多数の小さなピンホ−ルを形成するので、この場合でも
上記の如きアウトガスをそのピンホ−ルから好適に逃が
して該導体パタ−ンの膨れを回避でき、従って安定的に
可撓性多層回路基板を製作することができる。In the case of a conductor pattern requiring a large area, such as a pad for connection, a large number of small pinholes are formed in the conductor pattern. The conductor pattern can be suitably escaped from the pinhole to avoid swelling of the conductor pattern, so that a flexible multilayer circuit board can be stably manufactured.
【図１】本発明による可撓性多層回路基板に於ける導体
パタ−ンの膨れの限界を調べる為の断面説明図。FIG. 1 is an explanatory sectional view for examining the limit of swelling of a conductor pattern in a flexible multilayer circuit board according to the present invention.
【図２】その平面説明図。FIG. 2 is an explanatory plan view thereof.
【図３】大きな導体パタ−ンにはピンホ−ルを設けた例
の平面説明図。FIG. 3 is an explanatory plan view of an example in which a pinhole is provided on a large conductor pattern.
【図４】その断面説明図。FIG. 4 is an explanatory sectional view of the same.
【図５】従来例による導体パタ−ンの膨れの問題を説明
する為の図。FIG. 5 is a view for explaining a problem of swelling of a conductor pattern according to a conventional example.
１ 絶縁層 ２ 小さな導体パタ−ン ３ 比較的大きな導体パタ−ン ４ 他の絶縁層 ５ 大きな導体パタ−ン ６ ピンホ−ル DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Small conductor pattern 3 Relatively large conductor pattern 4 Other insulating layers 5 Large conductor pattern 6 Pinhole
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E338 AA00 AA01 AA12 AA16 CC01 CD22 CD40 EE27 5E346 AA02 AA12 AA15 AA26 AA29 AA32 BB15 BB16 BB20 CC08 CC10 CC32 DD33 EE33 EE42 GG01 HH11 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E338 AA00 AA01 AA12 AA16 CC01 CD22 CD40 EE27 5E346 AA02 AA12 AA15 AA26 AA29 AA32 BB15 BB16 BB20 CC08 CC10 CC32 DD33 EE33 EE42 GG01 HH11
Claims (3)
パタ−ンを形成した可撓性多層回路基板に於いて、前記
導体パタ−ンの大きさ又は面積を所定値以下に制限する
ように構成した可撓性多層回路基板。In a flexible multilayer circuit board having a required conductor pattern formed in a plurality of layers via a required insulating layer, the size or area of the conductor pattern is limited to a predetermined value or less. Flexible multi-layer circuit board configured to:
項１の可撓性多層回路基板。2. The flexible multilayer circuit board according to claim 1, wherein said insulating layer is made of a photosensitive resin material.
うな大きな面積となるものではその導体パタ−ンに多数
のピンホ−ルを形成した請求項１又は２の可撓性多層回
路基板。3. A flexible multi-layer circuit according to claim 1, wherein said conductive pattern has a large area such as a pad for connection, and a large number of pinholes are formed on said conductive pattern. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32648399A JP2001144448A (en) | 1999-11-17 | 1999-11-17 | Flexible multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32648399A JP2001144448A (en) | 1999-11-17 | 1999-11-17 | Flexible multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001144448A true JP2001144448A (en) | 2001-05-25 |
Family
ID=18188332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32648399A Pending JP2001144448A (en) | 1999-11-17 | 1999-11-17 | Flexible multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001144448A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006013188A (en) * | 2004-06-28 | 2006-01-12 | Toppan Printing Co Ltd | Multilayer wiring board |
| JP2007043110A (en) * | 2005-08-01 | 2007-02-15 | Samsung Electronics Co Ltd | Flexible printed circuit and its manufacturing method |
| JP2008060413A (en) * | 2006-08-31 | 2008-03-13 | Toshiba Corp | Printed wiring board with built-in component, and electronic apparatus |
| WO2019159521A1 (en) * | 2018-02-15 | 2019-08-22 | 株式会社村田製作所 | Multilayer substrate and electric element |
-
1999
- 1999-11-17 JP JP32648399A patent/JP2001144448A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006013188A (en) * | 2004-06-28 | 2006-01-12 | Toppan Printing Co Ltd | Multilayer wiring board |
| JP2007043110A (en) * | 2005-08-01 | 2007-02-15 | Samsung Electronics Co Ltd | Flexible printed circuit and its manufacturing method |
| JP2008060413A (en) * | 2006-08-31 | 2008-03-13 | Toshiba Corp | Printed wiring board with built-in component, and electronic apparatus |
| WO2019159521A1 (en) * | 2018-02-15 | 2019-08-22 | 株式会社村田製作所 | Multilayer substrate and electric element |
| JPWO2019159521A1 (en) * | 2018-02-15 | 2020-08-27 | 株式会社村田製作所 | Multilayer substrate and electric element |
| US11064606B2 (en) | 2018-02-15 | 2021-07-13 | Murata Manufacturing Co., Ltd. | Multilayer substrate and electric element |
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